Technique for performing store-to-load forwarding - Patent Application 20070122997

Abstract

A technique for performing store-to-load forwarding is provided, which includes determining a virtual address of data to be loaded for a load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual address-based compare value of the load instruction with one or more virtual address-based compare values ​​of one or more store instructions, determining a physical address of the load instruction, and validating the load instruction based on a comparison of the physical address of the load instruction with the physical address of the matching store instruction.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of U.S. Patent Application No. 16 / 698,808, filed on November 27, 2019, entitled "TECHNIQUES FOR PERFORMING STORE - TO - LOAD FORWARDING", which is hereby incorporated by reference in its entirety.

Background Art

[0002] Out - of - order processors execute instructions out of order but follow certain constraints to ensure that they are executed as specified in the program. In particular, a young load that is executed on the same address as an older store may be executed out of order and may be temporally close. If the value stored by the store instruction has not been committed to the memory system (including caches backed up by, for example, higher - level caches and system memory) by the time the load instruction is executed, a store - to - load transfer is performed. In this case, the instruction pipeline directly provides the data stored by the store instruction to the load instruction.

[0003] A more detailed understanding can be obtained from the following description given as an example together with the accompanying drawings.

Brief Description of the Drawings

[0004]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4

[0005] Techniques are provided for performing a store-to-load transfer. The techniques include determining a virtual address of data to be loaded for a load instruction, identifying a matching store instruction from one or more store instruction memories by comparing a virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values of one or more store instructions, determining a physical address of the load instruction, and verifying the load instruction based on a comparison of the physical address of the load instruction with the physical address of the matching store instruction. A processing unit and a load / store subsystem are also provided.

[0006] FIG. 1 is a block diagram of an exemplary device 100 in which aspects of the present disclosure are implemented. Device 100 includes, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a cellular phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 optionally also includes an input driver 112 and an output driver 114. In certain embodiments, device 100 includes additional components not shown in FIG. 1.

[0007] In one example, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, where each processor core is a CPU or a GPU. In various examples, the memory 104 is located on the same die as the processor 102 or is located separately from the processor 102. The memory 104 includes volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0008] In various examples, the storage device 106 includes, but is not limited to, a fixed storage device or a removable storage device (e.g., hard disk drive, solid state drive, optical disk, flash drive). In various examples, the input device 108 includes, but is not limited to, a keyboard, keypad, touch screen, touch pad, detector, microphone, accelerometer, gyroscope, biometrics scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE802 signals). In various examples, the output device 110 includes, but is not limited to, a display, speaker, printer, tactile feedback device, one or more lights, antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE802 signals).

[0009] The input driver 112 communicates with the processor 102 and the input device 108 and enables the processor 102 to receive inputs from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110 and enables the processor 102 to send outputs to the output device 110. Note that the input driver 112 and the output driver 114 are optional components and that the device 100 operates similarly when the input driver 112 and the output driver 114 are absent.

[0010] FIG. 2 is a block diagram of an instruction execution pipeline 200 located within the processor 102 of FIG. 1, according to an example. The instruction execution pipeline 200 fetches instructions from memory and executes the instructions, such as outputting data to memory and modifying the states of elements within the instruction execution pipeline 200, such as registers within the register file 218.

[0011] The instruction execution pipeline 200 includes an instruction fetch unit 204 that fetches instructions from the system memory (such as memory 104) via the instruction cache 202, a decoder 208 that decodes the fetched instructions, a functional unit 216 that executes calculations to process the instructions, a load / store unit 214 that loads data from the system memory or stores data in the system memory via the memory system 220, and a register file 218 that includes registers for storing working data for the instructions. The memory system 220 includes memories of one or more memory hierarchies, such as, for example, a data cache (e.g., level 0), other caches, memory, and other memories. The reorder buffer 210 tracks instructions that are currently in flight and guarantees in-order retirement of the instructions while permitting out-of-order execution during flight. An “in-flight” instruction refers to an instruction that has been received by the reorder buffer 210 but has not committed its result to the processor's architectural state (e.g., non-speculative results written to the register file, etc.). The reservation station 212 holds instructions waiting to be executed in the functional unit 216 and tracks the instruction operands. When all operands are ready for the execution of a particular instruction, the reservation station 212 sends the instruction to the functional unit 216 or the load / store unit 214 for execution. Completed instructions are marked for retirement to the reorder buffer 210 and are retired when they are at the head of the reorder buffer queue 210. Retirement refers to the act of committing the result of an instruction to the processor's architectural state. For example, writing the addition result to the youngest non-speculative copy of an architectural register by an add instruction, writing the loaded value to the youngest non-speculative copy of an architectural register by a load instruction, or non-speculatively jumping the instruction flow to a new location by a branch instruction are all examples of instruction retirement.

[0012] The various elements of the instruction execution pipeline 200 communicate via a common data bus 222. For example, the functional unit 216 and the load / store unit 214 write results to the common data bus 222, and the results may be read by the reservation station 212 for the execution of dependent instructions and by the reorder buffer 210 as the final processing result of the in-flight instructions that have completed execution. Also, the load / store unit 214 reads data from the common data bus 222. For example, the load / store unit 214 reads results from the common data bus 222 from completed instructions and writes the results to memory via the memory system 220 to store the instructions.

[0013] The instruction execution pipeline 200 can execute load instructions and store instructions (among other instructions). A load instruction is an instruction that loads data from memory and places that data in a register of the register file 218. A store instruction is an instruction that stores data from a register to a memory location. In either case of a store or a load, often the specified address (the address where the data is to be stored or from which the data is to be loaded) is calculated based on the contents of one or more registers and / or one or more values specified in the instruction itself. Further, in the case of a load or a store that specifies a virtual memory address, those addresses are translated to physical addresses.

[0014] More specifically, the store instruction is executed as follows. The instruction fetch unit 204 fetches the store instruction. The decoder 208 decodes the store instruction and sends the store instruction to the reorder buffer 210, and the reorder buffer 210 provides the store instruction to the load / store unit 214. The reservation station 212 issues the store instruction to the functional unit 216 to generate a virtual address (e.g., calculating a virtual address in the manner specified by the store instruction, e.g., by adding the content of one register to the content of another register). Subsequently, the functional unit 216 sends the virtual address to the load / store unit 214, and the load / store unit 214 executes the store instruction. The load / store unit 214 converts the virtual address to a physical address via the translation lookaside buffer (TLB) 226 and internally buffers the data to be stored by the store instruction in the load / store unit 214 to execute the store instruction. The reorder buffer 210 retires the store instruction, which means that the store instruction is not executed speculatively and is ultimately committed to the memory system 220. The load / store unit 214 sends the store instruction to the store commit queue 230. Next, the load / store unit 214 commits the store to the memory system 220 and deletes the store instruction from the store commit queue 230 in response to receiving a notification that the data specified by the store instruction has actually been written to the memory system 220. In certain embodiments, the store commit queue 230 is not used.

[0015] More specifically, the load instruction is executed as follows. The instruction fetch unit 204 fetches the load instruction. The decoder 208 decodes the load instruction, sends the load instruction to the reorder buffer 210, and the reorder buffer 210 provides the load instruction to the load / store unit 214. The reservation station 212 issues the load instruction to the functional unit 216 to generate a virtual address for the load instruction (e.g., calculate the virtual address in the manner specified by the load instruction, such as by adding the content of one register to the content of another register). Subsequently, the functional unit 216 sends the virtual address to the load / store unit 214, and the load / store unit 214 executes the load instruction. The load / store unit 214 executes the load instruction by converting the virtual address to a physical address via the data TLB 226 and loading the data specified by the physical address from the memory system 220.

[0016] For performance reasons, the load / store unit 214 performs a transfer from store to load for stores and loads that access the same address and are executed during at least partially overlapping periods. More specifically, in certain situations, a load instruction and a store instruction occur at the same address, and the load instruction is a younger instruction than the store instruction. The load instruction executed by the load / store unit 214 attempts to load the requested data. If the store instruction has not yet committed that data to the memory system 220, reading from the memory system by the load instruction is not possible and will result in old data. Therefore, the load / store unit 214 transfers the data from the store instruction to the load instruction.

[0017] As described above, the transfer from store to load occurs when the physical addresses of the load instruction and the store instruction older than it are the same. If the physical addresses are different, the transfer from store to load does not occur. Therefore, in one technique, when a load instruction is executed, the load / store unit 214 checks whether the physical address of the load instruction is the same as that of a store instruction whose physical address has not been committed. However, in this technique, depending on the situation, a potential delay associated with the fact that either or both of the physical addresses of the store instruction or the load instruction are unknown at the time when this check is performed occurs. Therefore, in this technique, a delay occurs in order to successfully execute the load instruction until such a physical address becomes available.

[0018] Therefore, in one technique, the load / store unit 214 uses a virtual address-based comparison value (which may also be simply referred to as a "comparison value" in this specification) based on the virtual address of the data loaded by the load instruction to check for a match between the load instruction and a store instruction whose commit has not occurred. In one embodiment, the virtual address-based comparison value is the entire virtual address. In other embodiments, the virtual address-based comparison value is a part of the entire virtual address. In still other embodiments, the virtual address-based comparison value is a value derived from the entire virtual address through a conversion function (in one embodiment, the conversion function is a hash function). In still other embodiments, the virtual address-based comparison value is a value derived from a part of the virtual address through a conversion function (in one embodiment, the conversion function is a hash function). The virtual address-based comparison value is calculated for both the load instruction and the store instruction so that these values can be compared. In one embodiment, "match" means that the virtual address-based comparison value of the store instruction is the same as the virtual address-based comparison value of the load instruction. In other embodiments, match means that a part of the comparison values is the same.

[0019] Note that even if the virtual address-based comparison value of the load instruction matches the virtual address-based comparison value of the store instruction, the physical addresses of the load instruction and the store instruction do not necessarily match. Instead, the match of the comparison values indicates that it is likely that these physical addresses are the same. Therefore, the execution of the load instruction, including obtaining data from the store instruction whose comparison value matches, is considered speculative. For this reason, after obtaining data based on the match of the comparison values, the load / store unit 214 verifies after a while that the load has been executed correctly. The event that triggers this verification of the load instruction is referred to as a "verification trigger event" in this specification. In one example, the verification trigger event is the successful completion of the load instruction. That is, the load instruction completes all other steps that are considered to have completed the load instruction, such as address translation and actual reception of the loaded data. In another example, the verification trigger event is the successful completion of the store instruction after the load instruction has already completed. When the verification is successfully completed, the data loaded by the load instruction is considered correct, and the load instruction is no longer considered to be executed speculatively for the purpose of verifying the transfer from store to load (in some situations, the load instruction may still be executed speculatively for other reasons). If the verification is not successfully completed, the load instruction is flushed from the instruction execution pipeline 200. That is, the load instruction (and, in one example, potential other instructions such as instructions younger than the load instruction) is removed from the pipeline, and the flushed load instruction does not affect the architectural state of the pipeline, and the load instruction (and, in some cases, other instructions) is replayed.

[0020] Verification of the transfer from store to load occurring based on a virtual address-based comparison value is performed in the following manner. At the time of verification, the store instruction may already have successfully completed the conversion from the virtual address of the address storing the data to the physical address. In that case, the verification includes checking whether the physical address of the store instruction is the same as the physical address from which the load instruction read the data being loaded. The load instruction is successfully verified if the physical addresses are the same and is not verified if the physical addresses are different. It should be noted that this verification is performed at a later point in time when the load instruction is executed and hides the delay in obtaining the physical addresses of both the load instruction and the store instruction.

[0021] At the time of verification of the load instruction, the store instruction may not yet have successfully completed the conversion from the virtual address of the address where the data is stored to the physical address. In that case, in response to the load / store unit 214 completing the load instruction, the load / store unit 214 places the load instruction in the load wait buffer 228. When the load / store unit 214 obtains the physical address of the store instruction whose comparison value matches the load instruction through address translation, it compares that physical address with the physical address of the load instruction. If the physical addresses are the same, the verification is considered to have been successfully completed. If the physical addresses are not the same, the verification is considered not to have been successfully completed.

[0022] In one embodiment, the load wait buffer 228 is an out-of-order buffer that is also used to verify the memory ordering rules for store-to-load. More specifically, the ordering from store to load is a memory ordering rule that requires all loads to receive data from the store operation as defined by the program order (i.e., the order in which the instructions are to be executed according to the control flow of the software executing these instructions). Since the instruction execution pipeline 200 can execute instructions including load instructions and store instructions out of order, the ordering from store to load is enforced between instructions of the same thread to prevent load instructions from consuming old data.

[0023] In one example, violations of the store-to-load ordering are checked in the following manner. In response to a load instruction completing and the load instruction being eligible for placement into the out-of-order buffer, the load / store unit 214 places the load instruction into the out-of-order buffer. The load instruction is eligible for placement into the out-of-order buffer if the load instruction may violate the store-to-load ordering rule. Such a violation is possible if there is at least one store instruction older than the load instruction and the load / store unit 214 has not yet determined the physical address of the older store instruction. If the load instruction is not eligible for placement into the out-of-order buffer, the load / store unit 214 does not place the load instruction into the out-of-order buffer.

[0024] While in the out-of-order buffer, the load / store unit 214 checks for violations of the store-to-load ordering rule in the following manner. When the physical address of a store instruction older than the load instruction is determined, the load / store unit 214 compares that physical address to the physical address of the load instruction. If there is a match, the load / store unit 214 determines that a violation has occurred, and if there is no match, the load / store unit 214 determines that no violation has occurred for that store instruction. In response to there being no further store instructions older than the load instruction whose physical address has not yet been determined, the load / store unit 214 determines that a violation for the load instruction is no longer possible and, if there is no other reason to hold the load instruction in the out-of-order buffer, removes the load instruction from the out-of-order buffer.

[0025] Accordingly, the load-wait buffer 228 is used in one embodiment to perform store-to-load transfer verification and to perform checks for violations of the store-to-load ordering rule. If both checks are required, the load / store unit 214 removes the load instruction from the load-wait buffer 228 in response to both checks being complete.

[0026] In one embodiment, the load / store unit 214 implements a technique that includes selection of a first candidate store instruction based on a portion of the virtual address of the load instruction, subsequent comparison value-based preliminary verification, and subsequently physical address-based final verification. More specifically, during the process of executing the load instruction, the load / store unit 214 selects candidates for uncommitted store instructions based on the least significant X bits (in one example, X is 12) of the virtual address of the store instruction and the least significant X bits of the virtual address of the load instruction. More specifically, the load / store unit 214 identifies an uncommitted store instruction whose least significant X bits are the same as the least significant X bits of the load instruction as a candidate for the uncommitted store instruction. Next, the load / store unit 214 attempts to pre-verify that the store instruction is the correct instruction for obtaining the data of the load instruction by comparing the comparison value based on the virtual address of the store instruction with the comparison value based on the virtual address of the load instruction. If they match, the load / store unit 214 enables the load instruction to be executed using the data from the matching store instruction.

[0027] Subsequently, the load / store unit 214 performs a final verification using the physical addresses of matching store and load instructions. This is described elsewhere in this specification. After identifying candidates for uncommitted store instructions, if the virtual address-based comparison values do not match, there are two possibilities: a false miss or a true miss. A false miss occurs when the candidates for uncommitted store instructions and the virtual address of the load instruction have the same least significant bits of X, but the virtual addresses themselves are different (and thus have different comparison values, e.g., the hashes of different virtual addresses are different), yet the different virtual addresses refer to the same physical address. A true miss occurs when the least significant bits of X match, but the remaining virtual addresses do not match and the physical addresses also do not match. Therefore, after identifying candidates for uncommitted store instructions as described elsewhere in this specification (e.g., as described with respect to step 408 of FIG. 4), if the virtual address-based comparison values do not match, the load / store unit 214 determines whether this failure of match indicates a true miss or a false miss by comparing the physical addresses.

[0028] If the physical addresses are different, a true miss occurs. If the physical addresses are the same, a false miss has occurred. In either case, the load instruction is replayed. If a true miss occurs, the candidate store instruction does not hold the correct data for the load instruction, and the load instruction does not receive data from that store instruction in subsequent replays. If a false miss occurs, the candidate store instruction holds the correct data for the load instruction, and the load instruction receives data from that store instruction in subsequent replays.

[0029] In one embodiment, a false miss is detected after a match with a candidate store instruction has been pre-invalidated. More specifically, as described elsewhere herein, a preliminary verification based on a virtual address-based comparison value is performed at a relatively early stage of the execution of the load instruction, and the physical address of either or both of the load instruction and the store instruction is not available. A subsequent final verification is performed when the physical address becomes available. In the case of a true miss, the load / store unit 214 stores that the store instruction did not match and restarts the load instruction. Using this stored information, the load / store unit 214 excludes the store instruction from the initial candidate selection, and the load instruction does not receive data from that store instruction. In the case of a false miss, the load / store unit 214 stores that the store matched and restarts the load. Using this stored information, the load / store unit 214 causes a verification that would have failed due to a mismatch in the comparison value to succeed instead. Since the physical addresses are the same, the final verification also succeeds.

[0030] FIG. 3A is a diagram showing operations for performing a transfer from a store to a load according to an example. In FIG. 3A, a load instruction that loads from an address is executed when a store instruction that writes to the same address has been at least partially executed but the result has not yet been committed.

[0031] In operation 320, the reservation station 212 that receives a load instruction from the reorder buffer 210 sends the load instruction to the load / store unit 214 for execution through the decoder 208 and the instruction fetch unit 204. In operation 322, the reservation station 212 sends the load instruction to the functional unit 216 to determine the virtual address of the load instruction. Since many load instructions include virtual addresses that are specified indirectly (e.g., as the sum of two or more values such as a base address and an offset), operation 322 includes performing an operation in the functional unit 216 to obtain the virtual address of the source from which data is to be loaded as specified by the load instruction.

[0032] In operation 324, load / store unit 214 performs the following sub-operations. The load / store unit determines a virtual address-based comparison value based on the virtual address obtained in operation 322. In various examples, this determination is made by performing a hash on all or part of the virtual address obtained in operation 322, or by performing an operation other than a hash on all or part of the virtual address obtained in operation 322. Finding a match involves finding a store operation in the memory system that has a virtual address-based comparison value that matches the virtual address-based comparison value of the load instruction and for which the result has not yet been committed. In one example, two virtual address-based comparison values matching means the two values are the same. In another example, two virtual address-based comparison values matching means that part of the two values is the same. In yet another example, a match means that a function applied to the two values results in the same value. Operation 326 indicates searching for a match in store queue 304 and store commit queue 230, but it is possible to alternatively or additionally search other structures that store data for store instructions that have not yet been committed to memory. Store queue 304 is a memory that stores store instructions that are pending from when the load / store unit 214 receives a store instruction until the store instruction retires and is placed in store commit queue 230. Store commit queue 230 is a memory that stores store instructions from when the store instruction is received from store queue 304 until the data stored by the store instruction is committed (i.e., stored) to memory system 220.

[0033] Further, in operation 324, the load / store unit 214 provides the address of the load instruction to the address translation system (i.e., the data TLB 226 that attempts to translate the address through the contents of the TLB cache memory and, if necessary, with the assistance of the upper levels of the memory hierarchy), and the address translation system returns the translated address. In operation 324, in some situations, the match discovery and address translation occur during at least partially overlapping periods. In some situations, the load / store unit 214 issues the operations for discovering a match and for translating the virtual address to a physical address almost simultaneously. In one example, "almost simultaneously" means in the same clock cycle. In another example, "almost simultaneously" means that both start in response to the acquisition of the virtual address. Generally, in operation 324, each operation is started without waiting for the other operations to complete.

[0034] Note that since finding a match between the comparison values is started before waiting for the physical address to complete, the load instruction can obtain the loaded data earlier than when waiting for the physical address to complete. However, since the match that occurs in operation 324 is not based on the physical address, a verification operation (operation 326) occurs to verify the loaded data. Further, in FIG. 3A, at the time when verification is performed, the matching store instruction has not yet received the translated address (the term "matching store instruction" means, in operation 324, the store instruction in which the virtual address-based comparison value is found to match the virtual address-based comparison value of the load instruction). More specifically, the process of executing a store instruction older than the load instruction also includes obtaining an address translation. However, the address translation of the load instruction may be obtained before the address translation of the matching store instruction. Also in this case, as shown in FIG. 3A, in operation 326, the load / store unit 214 places the load instruction in the load-wait buffer 228. In operation 328, in response to the physical address translation being obtained for the store instruction, the load / store unit applies that physical address to the load-wait buffer 228 to verify the speculatively executed load instruction. If the physical address of the load instruction does not match the physical address of the store instruction, the load / store unit 214 determines that the speculative execution of the load instruction has failed, and the load / store unit 214 flushes the load instruction from the instruction execution pipeline 200 and re-executes the load instruction. If the physical address of the load instruction matches the physical address of the store instruction, the load / store unit 214 determines that the speculative execution has completed successfully.

[0035] Figure 3B is a diagram showing operations for performing a transfer from store to load according to another example. This example is the same as the example of Figure 3A, except that the load instruction is not placed in the load wait buffer 228 because the physical address of the store instruction is already available when verifying the load instruction. More specifically, in operation 342, the reservation station 212 dispatches the load instruction to the load / store unit 214 in the same way as in operation 322. In operation 344, the reservation station 212 determines the virtual address of the load instruction in the same way as in operation 324. In operation 346, the load / store unit finds a match of the comparison value between the load instruction and the store instruction in the same way as in operation 326. In operation 348, the load / store unit 214 compares the physical address of the store instruction with the physical address of the load instruction. If the addresses are the same, the load instruction is verified. If the addresses are not the same, the load instruction is not verified and is flushed and replayed.

[0036] Figure 4 is a flowchart of a method 400 for performing a transfer from store to load for a load instruction according to an example. Although described with respect to the systems of FIGS. 1 - 3B, those skilled in the art will understand that any system configured to perform the steps of method 400 in any technically feasible order is within the scope of the present disclosure.

[0037] In step 402, the load / store unit determines the virtual address of the data to be loaded for the load instruction. As described elsewhere herein, the load instruction specifies the address from which the data is to be loaded. The address is often specified indirectly based on an offset added to a base address or in another way. Step 402 includes performing any steps necessary to determine the virtual address from the information specified by the load instruction.

[0038] In step 404, the load / store unit 214 identifies a matching store instruction by comparing the virtual address-based comparison value of the load instruction with the virtual address-based comparison values of one or more store instructions. The store instructions whose comparison values are being compared are store instructions that have started execution but have not yet committed the result to memory because they are store instructions that can be used for the comparison. When a store instruction commits the store value to memory, the value becomes directly usable in memory. In one embodiment, the load / store unit 214 attempts to identify the matching store instruction from among the store instructions in the store queue 304 and the store commit queue 230, both of which are described elsewhere in this specification. Note that if no matching store instruction is found, the store-to-load transfer is not executed and method 400 ends.

[0039] In step 406, the load / store unit 214 determines the physical address of the load instruction via address translation. In various embodiments, step 406 is executed during a period that at least partially overlaps with step 404. More specifically, in these embodiments, the load / store unit 214 identifies the matching store without waiting to receive the physical address translation, resulting in a speedup compared to techniques where the load / store unit 214 uses the physical address to execute the store-to-load transfer.

[0040] In step 408, the load / store unit 214 verifies the load instruction based on a comparison between the physical address of the load instruction and the physical address of the store instruction that matches it. In certain situations, the load instruction completes and the store instruction has not yet received a physical address. In this situation, the load / store unit 214 places the load instruction in the load wait buffer 228. When the store instruction receives a physical address, the load / store unit 214 applies that physical address to the load instruction in the load wait buffer 228 for verification. In other situations, the load instruction completes and the store instruction has received a physical address. In this situation, the load / store unit 214 compares the physical address of the load instruction and the physical address of the store instruction for verification. Regardless of whether the load wait buffer 228 is used, if there is a match between the physical addresses, the load / store unit 214 successfully verifies the load instruction, and if there is no match between the physical addresses, the load / store unit 214 fails to verify the load instruction and the load / store unit 214 flushes and restarts the load instruction.

[0041] In an alternative of the above technique, when trying to find a store instruction with a virtual address-based comparison value that matches the load instruction, if the store instruction with the matching comparison value already has a translated physical address, the load instruction can be executed and completed, but if such a matching store instruction does not yet have a translated physical address, the load instruction does not complete and is restarted.

[0042] Of course, based on the disclosure of this specification, many variations are possible. Although the features and elements have been described in specific combinations above, each feature or element may be used alone without other features and elements, or in various combinations with other features and elements or in various combinations without other features and elements.

[0043] The various elements described herein are implemented as circuitry configured to perform the functions described herein, as software executed on a processor, or as a combination thereof. In FIG. 1, processor 102 is a computer processor configured to perform the operations described herein. Input driver 112, output driver 114, input device 108, and output device 110 are software executed on one or more processors, hardware, or a combination thereof. The various elements of instruction execution pipeline 200 are hardware circuits.

[0044] The methods provided may be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, by way of example, general-purpose processors, dedicated processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of other intermediate data (such instructions that may be stored on a computer-readable medium), including hardware description language (HDL) instructions and netlists, to be processed. The results of such processing may be a mask work used in a semiconductor manufacturing process to manufacture a processor that implements aspects of the embodiments.

[0045] The methods or flowcharts provided herein may be implemented in a computer program, software, or firmware incorporated into a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include magnetic media such as read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, internal hard disks, and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

Claim 1 A method for performing a transfer from a store to a load in response to a load instruction, comprising: determining a virtual address of data to be loaded in response to the load instruction; identifying a matching store instruction from one or more store instruction memories by comparing a virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values of one or more store instructions; placing the load instruction in a load-wait buffer in response to detecting that the matching store instruction has not yet received address translation when starting verification of the load instruction; verifying the load instruction based on a comparison between a physical address of the load instruction and a physical address of the matching store instruction. A method. Claim 2 Determining a virtual address of data to be loaded in response to the load instruction includes: executing one or more calculations on an address value specified by the load instruction to obtain the virtual address. The method of claim 1. Claim 3 The one or more store instruction memories include at least one of: a store queue configured to store store instructions that are in execution and have not yet retired; and a store commit queue configured to store store instructions that have retired and whose store data has not yet been committed to the memory system. The method of claim 1. Claim 4 The method of claim 1 further comprising determining a physical address of the load instruction by performing address translation to convert the virtual address of the data to be loaded in response to the load instruction to the physical address of the load instruction. The method of claim 1. Claim 5 The method of claim 1 further comprising applying the physical address of the store instruction to the load-wait buffer in response to receiving the physical address of the store instruction to determine whether the physical address of the store instruction matches the physical address of the load instruction. The method of claim 1. Claim 6 Verifying the load instruction includes: detecting that the matching store instruction has received address translation at the start of the verification; and comparing the physical address of the load instruction with the physical address of the matching store instruction. The method of claim 1. Claim 7 The virtual address-based comparison value of the load instruction based on the virtual address of the data of the load instruction is a hash of a part of the virtual address of the load instruction, and a hash of the entire virtual address of the load instruction, and a part of the virtual address of the load instruction, and the entire virtual address of the load instruction, and includes any one of The method of claim 1.

8. completing the execution of the load instruction without flushing the load instruction in response to successfully verifying the load instruction, or further including flushing the load instruction and replaying the load instruction in response to failing to verify the load instruction, The method of claim 1.

9. A load / store subsystem for performing a store-to-load transfer for a load instruction, comprising: the load / store subsystem, one or more store instruction memories, a load / store unit, and the load / store unit, determining a virtual address of data to be loaded for the load instruction, identifying a matching store instruction from the one or more store instruction memories by comparing a virtual address-based comparison value of the load instruction with virtual address-based comparison values of one or more store instructions, placing the load instruction in a load wait buffer in response to detecting that the matching store instruction has not yet received address translation when starting verification of the load instruction, verifying the load instruction based on a comparison between a physical address of the load instruction and a physical address of the matching store instruction, is configured to perform Load / store subsystem.

10. Determining a virtual address of data to be loaded for the load instruction includes performing one or more calculations on an address value specified by the load instruction to obtain the virtual address, The load / store subsystem of claim 9.

11. The one or more store instruction memories a store queue configured to store store instructions that are in execution and have not yet retired, a store commit queue configured to store store instructions that have been retired and whose store data has not been committed to the memory system, includes at least one of The load / store subsystem of claim 9.

12. The load / store unit is further configured to determine the physical address of the load instruction by performing address translation to convert the virtual address of the data loaded for the load instruction into the physical address of the load instruction. The load / store subsystem of claim 9.

13. The load / store unit is further configured to apply the physical address of the store instruction to the load waiting buffer in response to receiving the physical address of the store instruction, and to determine whether the physical address of the store instruction matches the physical address of the load instruction. The load / store subsystem of claim 9.

14. Verifying the load instruction includes detecting that the matching store instruction has received address translation at the start of the verification, and comparing the physical address of the load instruction with the physical address of the matching store instruction. The load / store subsystem of claim 9.

15. The virtual address-based comparison value of the load instruction based on the virtual address of the data of the load instruction includes any one of a hash of a part of the virtual address of the load instruction, a hash of the entire virtual address of the load instruction, a part of the virtual address of the load instruction, and the entire virtual address of the load instruction. The load / store subsystem of claim 9.

16. The load / store unit is further configured to complete the execution of the load instruction without flushing the load instruction in response to successfully verifying the load instruction, or to flush the load instruction and replay the load instruction in response to failing to verify the load instruction. The load / store subsystem of claim 9.

17. A processing unit for performing a store-to-load transfer for a load instruction, wherein the processing unit comprises one or more store instruction memories, a load / store unit, and a data translation lookaside buffer, and the load / store unit is configured to determine the virtual address of the data loaded for the load instruction. Identifying a matching store instruction from the one or more store instruction memories by comparing a virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values of one or more store instructions; Placing the load instruction in a load-wait buffer in response to detecting that the matching store instruction has not yet received address translation when starting verification of the load instruction; Verifying the load instruction based on a comparison between a physical address of the load instruction and a physical address of the matching store instruction; is configured to perform; The data translation lookaside buffer is configured to convert the virtual address of the load instruction to the physical address of the load instruction. Processing unit.

18. Determining a virtual address of data to be loaded for the load instruction includes performing one or more calculations on an address value specified by the load instruction to obtain the virtual address. The processing unit of claim 17.

19. The one or more store instruction memories include at least one of a store queue configured to store store instructions that are in execution and have not yet retired, and a store commit queue configured to store store instructions that have been retired and whose store data has not been committed to the memory system. The processing unit of claim 17. including at least one of The processing unit of claim 17.

20. The load / store unit is further configured to determine the physical address of the load instruction by performing address translation to convert the virtual address of the data to be loaded for the load instruction to the physical address of the load instruction. The processing unit of claim 17.

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