Mirroring of Data into the Write Cache of the Controller of the Non-Volatile Memory

Abstract

A data storage system provides persistent storage in a large capacity non-volatile memory. A controller of the data storage system receives host write commands and buffers associated host write data in both a first write cache in the non-volatile memory and a mirrored second write cache in the volatile memory. The controller destages the host write data from the second write cache to the large capacity non-volatile memory, but not from the first write cache. The controller responds to a relocation write command that requests data relocation in the large capacity non-volatile memory with reference to the second write cache. Responding to the relocation write command includes buffering the relocation write data in the second write cache, but not from the first write cache, and destaging the relocation write data from the second write cache to the large capacity non-volatile memory.

Description

Technical Field

[0001] The present disclosure generally relates to data storage, and more particularly to non-volatile memory systems. Even more particularly, the present disclosure relates to non-volatile memory systems that include a mirrored write cache for buffering host-written data within both volatile and non-volatile memories.

Background Art

[0002] NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more data bits per memory cell as charge on a floating gate of a transistor, or a similar charge trap structure. In a typical implementation, a NAND flash memory array is organized into physical blocks of memory (also referred to as "erase blocks"), each of which contains a plurality of physical pages, each of which in turn contains a number of memory cells. Due to the arrangement of word and bit lines used to access the memory cells, a flash memory array can generally be programmed on a page-by-page basis, but erased on a block-by-block basis.

[0003] As is well known in the art, blocks of NAND flash memory must be erased before new data can be programmed. Blocks of NAND flash memory cells are erased by applying a high positive erase voltage pulse to the p-well bulk region of the selected block and biasing all of the word lines of the memory cells to be erased to ground. The application of the erase pulse facilitates the tunneling of electrons from the floating gates of the memory cells biased to ground, giving them a net positive charge and thus shifting the voltage threshold of the memory cells towards the erased state. After each erase pulse, an erase verification operation is generally performed to determine whether the erase operation was successful by reading the erased block and, for example, confirming that the memory cells within the erased block that did not successfully erase have a threshold count below a certain number. Generally, erase pulses are continuously applied to the erase block until the erase verification operation is successful or a predetermined number of erase pulses have been used (i.e., until the erase pulse budget is exhausted).

[0004] NAND flash memory cells can be programmed by applying a high positive program voltage to the word lines of the memory cells to be programmed and applying an intermediate pass voltage to the memory cells within the same string that should be prohibited from programming. The application of the program voltage causes tunneling of electrons onto the floating gates, changing the state from the initial erased state to a programmed state with a net negative charge. After programming, the programmed page is typically read in a read verification operation to ensure that the programming operation was successful, for example, by confirming that the memory cells within the programmed page that contain bit errors have a threshold count below a certain number. Generally, the program and read verification operations are applied to the page until the read verification operation is successful or a predetermined number of programming pulses have been used (i.e., until the programming pulse budget is exhausted).

[0005] Data is written to the NAND flash memory in the form of logical pages, each containing, for example, 4 kB or 16 kB of data. A given physical page of the memory can store one or more logical pages of data. As the data is updated, the logical pages storing the old data become invalid, leaving a mixture of physical pages containing valid and invalid data in the physical block. Eventually, the controller of the NAND flash memory recovers the storage capacity consumed by the physical pages holding the invalid data through a process called garbage collection. In garbage collection, the data that is still valid is rewritten from the first physical block into one or more previously erased physical blocks. Thereafter, the first physical block can be erased in preparation for reprogramming.

[0006] In enterprise-class NAND flash-based memory systems, for example, it is extremely important to prevent data loss in the event of a power failure. Therefore, in such data storage systems, the flash controller can only respond positively to a host write command after the host write data associated with the host write command has been permanently stored in non-volatile storage. In a first prior art design, the flash controller first buffers incoming host write data in a write cache implemented with a low-cost volatile memory technology such as dynamic random access memory (DRAM). Next, the flash controller destages the host write data from the DRAM write cache into the NAND flash memory. When all the write data associated with the host write command has become permanent in the NAND flash memory (and thus is protected from data loss in the event of a power loss), the flash controller sends a positive response to the host and releases the resources within the host allocated to track the completion of the host write command. Relocation writes performed in conjunction with garbage collection in the NAND flash memory are similarly buffered in the DRAM write cache before being destaged back into the NAND flash memory. This first architecture has the advantage of a simple and relatively low-cost design, but has the disadvantage of relatively low write performance in that the positive response to the host is delayed until the host write data has been permanently stored in the NAND flash memory.

[0007] To provide improved write performance compared to this first prior art design, a second prior art design implements a non-volatile write cache, for example, in the form of battery-backed DRAM, magnetoresistive RAM (MRAM), ferroresistive RAM (FRAM), phase change memory (PCM), or other non-volatile memory technologies. Using this design, as soon as the associated host write data is written into the write cache and thus before the host write data is fully destaged from the non-volatile write cache to the NAND flash memory, the flash controller can send an affirmative response to the host write command to the host, resulting in significantly improved write performance. Relocation writes performed in conjunction with garbage collection are likewise first written into the non-volatile write cache before being destaged to the NAND flash memory. This second prior art architecture provides significantly better write performance than the first prior art architecture, but does so at the trade-off of higher complexity and higher cost due to the price difference between implementing the write cache in volatile memory (e.g., DRAM) versus non-volatile memory (e.g., MRAM).

[0008] In view of the prior art, it is recognized that it would be useful and desirable for the present application to provide an improved data storage system that implements a non-volatile write cache that enables an affirmative response to a host write command before destaging associated host write data to the NAND flash memory, while also reducing the cost of the memory utilized to implement the non-volatile write cache for a given write performance level. SUMMARY OF THE INVENTION

[0009] In at least one embodiment, a method for managing a data storage system that provides persistent storage within a large-capacity non-volatile memory is provided. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in the non-volatile memory and a mirrored second write cache in the volatile memory. The controller destages the host write data from the second write cache, rather than the first write cache, to the large-capacity non-volatile memory. The controller responds to a rearrangement write command that requests a data rearrangement in the large-capacity non-volatile memory by referencing the second write cache. Responding to the rearrangement write command includes buffering the rearrangement write data in the second write cache, rather than the first write cache, and destaging the rearrangement write data from the second write cache to the large-capacity non-volatile memory.

[0010] In at least one embodiment, a data storage system includes a controller of a large-capacity non-volatile memory. The controller is configured to receive a host write command and buffer associated host write data in both a first write cache in the non-volatile memory and a mirrored second write cache in the volatile memory. The controller destages the host write data from the second write cache, rather than the first write cache, to the large-capacity non-volatile memory. The controller responds to a rearrangement write command that requests a data rearrangement in the large-capacity non-volatile memory by referencing the second write cache. Responding to the rearrangement write command includes buffering the rearrangement write data in the second write cache, rather than the first write cache, and destaging the rearrangement write data from the second write cache to the large-capacity non-volatile memory.

[0011] In at least one embodiment, a program product includes a storage device and program code stored in the storage device that is executable by a controller of a mass non-volatile memory. When executed, the program code causes the controller to receive a host write command and buffer associated host write data in both a first write cache in the non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data from the second write cache, rather than the first write cache, to the mass non-volatile memory. The controller responds to a relocation write command that requests data relocation in the mass non-volatile memory by referencing the second write cache. Responding to the relocation write command includes buffering the relocation write data in the second write cache, rather than the first write cache, and destaging the relocation write data from the second write cache to the mass non-volatile memory.

[0012] In at least one embodiment, before completion of destaging host write data to the mass non-volatile memory, the controller transmits an affirmative response to the host write command to the host based on the host write data being buffered in the first write cache.

[0013] In at least one embodiment, the mass non-volatile memory includes flash memory and the controller generates at least some of the relocation write commands during garbage collection in the flash memory.

[0014] In at least one embodiment, the controller releases the host write data of the host write command in the first write cache based on completion of destaging host write data to the mass non-volatile memory.

[0015] In at least one embodiment, the controller records at least a first location of host write data in a first write cache within an entry of a logical-physical conversion data structure. Based on the destination of the host write data to the mass non-volatile memory, the controller updates the entry to indicate a different second location within the mass non-volatile memory.

[0016] In at least one embodiment, the controller additionally records a third location of host write data in a second write cache within an entry of a logical-physical conversion data structure.

[0017] In at least one embodiment, the mass non-volatile memory includes a first write cache.

[0018] In at least one embodiment, the controller maintains a plurality of buffers in the first write cache and in the second write cache, each corresponding to a respective one of a plurality of different write heats. BRIEF DESCRIPTION OF THE DRAWINGS

[0019]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

DETAILED DESCRIPTION OF THE INVENTION

[0020] Referring to the figures, and particularly to FIG. 1A, a high-level block diagram of an exemplary data processing environment 100 is shown that includes a data storage system 120 having a mirroring write cache as further described herein. As shown, data processing environment 100 includes one or more hosts, such as a processor system 102 having one or more processors 104 that process instructions and data. Processor system 102 may further include local storage 106 (e.g., DRAM or disk) that may store program code, operands, or the execution results of processing performed by processor 104, or combinations thereof. In various embodiments, processor system 102 can be, for example, a mobile computing device (such as a smartphone or tablet), a laptop or desktop personal computer system, a server computer system (such as one of the POWER(R) series available from International Business Machines Corporation), or a mainframe computer system. Processor system 102 can also be an embedded processor system using various processors such as ARM(R), POWER(R), Intel x86, or any other processor, combined with a memory cache, memory controller, local storage, I / O bus hub, etc.

[0021] Each processor system 102 further includes an input / output (I / O) adapter 108 coupled directly (i.e., without any intervening devices) or indirectly (i.e., through at least one intermediate device) to a data storage system 120 via an I / O channel 110. In various embodiments, the I / O channel 110 may employ any one or combination of well-known or future-developed communication protocols, including, for example, Fibre Channel (FC), FC over Ethernet (FCoE), Internet Small Computer System Interface (iSCSI), InfiniBand®, Transport Control Protocol / Internet Protocol (TCP / IP), Peripheral Component Interconnect Express® (PCIe®), Non-volatile Memory Express® (NVMe®), NVMe over Fabrics® (NVMe-oF®), etc. I / O commands communicated via the I / O channel 110 include host read commands in which the processor system 102 requests data from the data storage system 120, and host write commands in which the processor system 102 requests storage of data into the data storage system 120.

[0022] In the illustrated embodiment, the data storage system 120 includes a plurality of interface nodes 122 through which the data storage system 120 receives and responds to I / O commands via the I / O channel 110. Each interface node 122 is coupled to each of a plurality of redundant array of inexpensive disks (RAID) controllers 124 to facilitate fault tolerance and load balancing. Each of the RAID controllers 124 is in turn coupled (e.g., by a PCIe bus) to each of a plurality of flash cards 126, which in this example include NAND flash memory media. In other embodiments, other volatile memory media may be employed.

[0023] FIG. 1B shows a more detailed block diagram of the flash card 126 of the data storage system 120 of FIG. 1A according to the first embodiment. In this embodiment, the flash card 126 includes a gateway 130 that serves as an interface between the flash card 126 and the RAID controller 124. The gateway 130 is coupled to a general-purpose processor (GPP) 132 that can be configured (e.g., by program code) to perform various management functions such as preprocessing I / O commands received by the gateway 130, scheduling responses to the I / O commands by the flash card 126, performing other management functions, or combinations thereof. The GPP 132 is coupled to a GPP memory 134 (e.g., DRAM) that can conveniently buffer data created, referenced, modified, or combined by the GPP 132 during its processing.

[0024] The gateway 130 is further coupled to at least one flash controller 140 that controls a mass storage non-volatile memory system, such as the NAND flash memory system 150. The flash controller (FC) 140 accesses the NAND flash memory system 150 and responds to I / O commands by, for example, reading requested data from or writing data into the NAND flash memory system 150, as further described below. In various embodiments, the flash controller 140 may be implemented, for example, by an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). In an embodiment where the flash controller 140 is implemented using an FPGA, the GPP 132 may program and configure the flash controller 140 during startup of the data storage system 120.

[0025] In this embodiment, the flash controller 140 is coupled to a flash controller memory that includes both a flash controller non-volatile memory 142 and a flash controller volatile memory 144. The flash controller non-volatile memory 142 may be implemented using, for example, MRAM, FRAM, PCM, DRAM with battery backup, or other non-volatile memory technologies, and the flash controller volatile memory 144 may be implemented using a relatively inexpensive volatile memory technology such as DRAM. As further indicated in FIG. 1B, the flash controller non-volatile memory 142 includes a first host write cache 146a for buffering host write data associated with a host write command received from a host such as the processor system 102. The contents of the host write cache 146a are mirrored by the flash controller 140 into a second host write cache 146b implemented within the flash controller volatile memory 144. The host write caches 146a and 146b may further be attached to the same memory bus to allow mirrored data to be written into the two write caches 146a, 146b using a single command, as will be understood by those skilled in the art upon reading this description.

[0026] The flash controller 140 implements a flash translation layer (FTL) that provides logical-to-physical address translation to enable access to specific storage locations within the NAND flash memory system 150. Generally, an I / O command received by the flash controller 140 from a host device, such as the processor system 102, includes a logical block address (LBA) at which data is to be accessed (read or written), and, in the case of a host write command, the host write data to be written to the data storage system 120. The I / O command may also specify the amount (or size) of data to be accessed. Other information may also be communicated depending on the protocol and features supported by the data storage system 120. As is well known to those skilled in the art, depending on the implementation form of the NAND flash memory, the minimum data granularity that can be accessed by a host read or host write command is fixed to the size of a single physical page, for example, 16 kilobytes (kB). The LBA provided by the host device corresponds to a logical page within the logical address space, which may have a size of, for example, 4 kB or 16 kB. This logical page can be further compressed by the flash controller 140 so that each physical page can store one or more logical pages. The FTL converts the LBA assigned to the corresponding physical location within the NAND flash memory system 150 into a physical address. The flash controller 140 can store the association between the logical address and the physical address in a logical-to-physical translation data structure, such as a logical-to-physical translation (LPT) table 152, which can be conveniently stored in the flash controller volatile memory 144.

[0027] As further shown in FIG. 1B, in the illustrated embodiment, the flash controller volatile memory 144 further includes a relocation write buffer 148 for buffering data collected by a garbage collection process that will be relocated within the NAND flash memory system 150. Additionally, the flash controller volatile memory 144 may optionally include a read cache 156 for buffering data from the NAND flash memory system 150 that has been recently, frequently, or both requested by host read commands. The flash controller 140 may also store threshold voltage (Vth) shift data 154 utilized to calibrate the read threshold voltages of various subsets (e.g., page groups) of the NAND flash memory system 150, as well as other management data structures 158 that store management data such as bit error rate (BER) and other statistics, program / erase (P / E) cycle counters, journaling information, etc. within the flash controller volatile memory 144.

[0028] The NAND flash memory system 150 may take many forms in various embodiments. Referring now to FIGS. 2 - 5, an exemplary arrangement of the physical memory within the NAND flash memory system 150 according to one embodiment is shown.

[0029] As shown in FIG. 2, the NAND flash memory system 150 can be formed from 40 individually addressable NAND flash memory storage devices. In the illustrated example, each of the flash memory storage devices M0a-M19b takes the form of a board-mounted flash memory module having the ability to store two or more bits per cell. In one particular embodiment, the memory module is implemented using a QLC NAND flash memory configured to operate in a hybrid hierarchical arrangement that includes a first pool of physical blocks operating in quad level cell (QLC) mode and a second pool of physical blocks operating in single level cell (SLC) mode. The 40 NAND flash memory modules are arranged in the form of 20 groups of two, (M0a, M0b)-(M19a, M19b). For the purpose of the physical address assignment scheme, each group of two modules forms a "lane", sometimes also referred to as a "channel", whereby the NAND flash memory system 150 includes 20 channels or lanes (Lane0-Lane19).

[0030] In a preferred embodiment, each of the individual lanes has its own associated bus that couples it to the associated flash controller 140. Therefore, by directing its communication to one of the specific communication buses, the flash controller 140 can direct its communication to one of the lanes of the memory module. Since each communication bus for a given lane is independent of the communication buses for other lanes, the flash controller 140 can issue commands simultaneously and transmit or receive data through the various communication buses, enabling the flash controller 140 to access the flash memory modules corresponding to the individual lanes simultaneously or almost simultaneously.

[0031] Next, referring to FIG. 3, an exemplary embodiment of a flash memory module 300 that can be used to implement any of the flash memory modules M0a to M19b of FIG. 2 is shown. As shown in FIG. 3, the physical memory locations provided by the flash memory module 300 are further subdivided into physical locations that can be addressed or identified, or both, through Chip Enable (CE). In the example of FIG. 3, the physical memory of each flash memory chip 300 is divided into four Chip Enables (CE0, CE1, CE2, and CE3), each having a respective CE line asserted by the flash controller 140 to enable access to or from the physical memory locations within the corresponding CE. Each CE is in turn subdivided into a plurality of dies (e.g., Die0 and Die1), each having two or four planes (e.g., Plane0 and Plane1). Each plane is physically associated with the others due to the physical layout of the flash memory chip and represents a set of physical blocks that utilize a common circuit (e.g., an I / O buffer) for performing various operations, such as read and write operations.

[0032] As further shown in FIGS. 4-5, an exemplary plane 400 that can be utilized to implement any of the planes within the flash memory module 300 of FIG. 3 includes, for example, 512, 2048, or 4096 blocks of physical memory. Because some blocks may fail early due to manufacturing defects, some manufacturers include additional blocks to this nominal block count. Generally, a block is a set of physical pages that are typically associated with each other in a physical manner. This association is defined such that a block becomes the smallest granularity of physical storage location that can be erased within the NAND flash memory system 150. In the embodiment of FIG. 5, each block 500 includes hundreds or thousands of pages, for example, 512, 1024, or 4096 physical pages. Here, a physical page is defined to be the smallest individually addressable data unit for read and write access. In an exemplary system, each physical page of data has a common capacity (e.g., 16 kB) for additional storage for page metadata in addition to data storage. Therefore, data is typically written to or read from the NAND flash memory system 150 in page units, but erased in block units.

[0033] The FTL implemented by the data storage system 120 decouples the logical address space made available to the host device from the physical memory within the NAND flash memory system 150, so the size of the NAND flash memory system 150 need not be equal to the size of the logical address space provided to the host device. In most embodiments, it is beneficial to provide a logical address space that is smaller in size than the total available physical memory (i.e., it is beneficial to over-provision the NAND flash memory system 150). Over-provisioning in this way ensures that physical memory resources are available when the logical address space is fully utilized, even given the presence of a certain amount of invalid data as described above. In addition to invalid data that has not yet been reclaimed, the over-provisioned space can be used to ensure that there is sufficient logical space, even given the presence of memory failures and memory overhead associated with the use of data protection schemes such as error correcting code (ECC), cyclic redundancy check (CRC), and parity.

[0034] In some embodiments, data is written to the NAND flash memory system 150 one physical page at a time. In other embodiments where more robust error recovery is desired, data is written to a group of associated physical pages of the NAND flash memory system 150 referred to herein as a "page stripe". In one embodiment, all pages of a page stripe are associated with different lanes to achieve a high write bandwidth. In many implementations, since the minimum erase unit is a block, as shown in FIG. 6A, a plurality of page stripes can be grouped into a block stripe, where each block within the block stripe is associated with a different lane. When constructing a block stripe, any free block of a lane can be selected, but preferably all blocks within the same block stripe have the same or similar health. Note that the selection of blocks can be further limited to be from the same plane, die, or chip enable, or a combination thereof. The length of the block stripe can vary, but in one embodiment where the NAND flash memory system 150 includes 20 lanes, each block stripe includes 2 to 20 blocks where each block is from a different lane.

[0035] Once blocks from each lane are selected and a block stripe is formed, the page stripe is preferably formed from physical pages having the same page number from all the blocks within the block stripe. The lengths of the various page stripes stored within the NAND flash memory system 150 can vary, but in one embodiment, each page stripe includes from one to twenty data pages of write data (typically provided by a host device). In another embodiment, the page stripe includes from one to nineteen data pages of write data and one additional page (a "data protection page") used to store data protection information for the write data. For example, FIG. 6B shows an exemplary page stripe 610 that includes N data pages (i.e., Dpage00 through DpageN-1) and one data protection page (i.e., PpageN). The data protection page can be placed on any lane of a page stripe that includes non-retired pages, but is typically on the same lane for all page stripes of the same block stripe in order to minimize metadata information. The addition of the data protection page as shown requires that garbage collection be performed simultaneously for all page stripes of the same block stripe. After the garbage collection of the block stripe is complete, the block stripe can be dissolved and each block can be placed into a ready-to-use (RTU) queue as described below.

[0036] Having described the overall physical structure and operation of an exemplary embodiment of the data storage system 120, reference is now made to FIG. 7 to describe certain operational aspects of the data storage system 120. FIG. 7 is a high-level data flow diagram showing flash management functions and data structures employed by the GPP 132 or the flash controller 140 or both, according to one embodiment.

[0037] As described above, data storage system 120 generally does not allow an external device (e.g., a host) to directly address, access, or both access and address physical storage locations within NAND flash memory system 150. Instead, data storage system 120 is generally configured to present one or more logical volumes, each having a contiguous logical address space, to the host device, and thus to allow the host device to read data from and write data to logical block addresses (LBAs) within the logical address space, while one or more of various levels of controllers (e.g., RAID controller 124, flash controller 140, and GPP 132) are able to control where data associated with the various LBAs actually resides within the physical storage locations that make up NAND flash memory system 150. In this way, the performance and lifespan of NAND flash memory system 150 can be intelligently managed and optimized. In the illustrated embodiment, each flash controller 140 performs logical-physical address translation for a related set of LBAs using a logical-physical address translation data structure, such as logical-physical translation (LPT) table 152, which may be stored in the associated flash controller volatile memory 144. Note that since various components within data storage system 120 may perform the address translation operation between the external device and flash controller 140, the logical address supplied to flash controller 140 may be different from the logical address originally supplied to data storage system 120.

[0038] As will be appreciated, the implementation of the mirrored host write cache 146b within the flash controller volatile memory 144 reduces the available capacity within the flash controller volatile memory 144 for other metadata, such as LPT 152. In at least some embodiments, the flash controller 140 may reduce the footprint of the LPT 152 within the flash controller volatile memory 144 by implementing a paging mechanism. In such embodiments, the backing store for the LPT entries is maintained within the NAND flash memory system 150, and the flash controller 140 pages LPT entries to and from the backing store as needed.

[0039] The flash management code running on the GPP 132 tracks the erased blocks of the NAND flash memory system 150 that are ready for use within the ready-to-use (RTU) queue 700, which may be stored, for example, within the GPP memory 134. In the illustrated embodiment, the flash management code running on the GPP 132 preferably maintains one or more RTU queues 700 per plane or channel, and the identifier of each erased block that is to be reused is placed into one of the RTU queues 700 corresponding to that channel. For example, in one embodiment, the RTU queue 700 includes a respective RTU queue 700 for each of a plurality of block healths per channel. In various implementations, it has been found that two to eight RTU queues 700 (and corresponding numbers of block healths) per plane are sufficient.

[0040] (For example, performed by flash management code running on GPP132) The build block stripes function 702 constructs new block stripes from the erased blocks placed in the RTU queue 700. As described above with reference to FIG. 6A, the block stripes are preferably formed by blocks of the same or similar soundness (i.e., predicted remaining useful life) that exist in different channels. That is, the block stripes can be conveniently constructed by the block stripe construction function 702 by pulling out each block of the new block stripe from the corresponding RTU queues 700 of different planes or channels. Next, the new block stripes are queued to the flash controller 140 for data placement by the data placement function 704.

[0041] The data placement function 704 includes an open block queue 706 that tracks the identifiers of the non-fully programmed blocks within the block stripes constructed by the block stripe construction function 702. As further shown in FIG. 7, the data placement function 704 further includes a caching engine 714 for writing host write data into the mirrored host write caches 146a, 146b and for writing relocatable write data into the relocatable write buffer 148. The data placement function 704 also includes a destaging engine 716 for writing data from the host write cache 146b and the relocatable write buffer 148 into the open blocks of the NAND flash memory system 150 identified within the open block queue 706.

[0042] In response to a host write command received from a host such as processor system 102, data placement function 704 of flash controller 140 refers to LPT table 152 to determine whether the target LBA indicated in the host write command is currently associated with a physical page within NAND flash memory system 150. If so, it changes the status of each data page currently associated with the target LBA to indicate that it is no longer valid. Caching engine 714 preferably uses a single operation to write the host write data of the host write command into both host write caches 146a, 146b in parallel (e.g., the host write data crosses the memory bus only once). When the update of host write cache 146a is complete, caching engine 714 can immediately provide an acknowledgement message ("Ack") to the issuing host via I / O channel 110. Caching engine 714 also updates the entry in LPT 704 for the LBA indicated by the host write command to indicate the location of the host write data within host write cache 146a or host write cache 146b or both.

[0043] To respond to a host write command, the data placement function 702, if necessary, additionally allocates page stripes to store the write data of the host write command and, if present, any unupdated data (i.e., data that is still valid and needs to be processed in a read-modify-write manner if the write request is smaller than the logical page) from the existing page stripes targeted by the host write command, or stores the write data of the host write command and, if present, any unupdated (i.e., still valid) data from the existing page stripes targeted by the host write command in an already allocated page stripe having remaining free space, or does both. The page stripes can be allocated from block stripes that have already been allocated to hold data or from new block stripes. In a preferred embodiment, the allocation of page stripes can be based on the health of the blocks available for allocation and the "heat" (i.e., the estimated or measured write access frequency) of the LBAs of the write data. Next, the destaging engine 716 of the data placement function 704 writes the host write data and associated metadata (e.g., CRC and ECC values) word by word from the host write cache 146b into the pages of the allocated page stripes identified within the open block queue 706, and additionally, if required, writes parity information into the data protection pages of the allocated page stripes. The destaging engine 716 also updates the LPT table 152 to associate the LBA of the host write data with the address of the physical pages in the NAND flash memory 150 used to store the write data. Thereafter, the flash controller 140 can access the data from the NAND flash memory 150 by referring to the LPT table 152 and respond to host read commands.

[0044] When all pages within a block stripe have been written or the block stripe is otherwise closed, the flash controller 140 places the identifier of the block stripe on one of the occupied block queues 708, and the flash management code running on the GPP 132 uses this to track the block for garbage collection and other management functions. As described above, through the write process, pages are invalidated, and thus portions of the NAND flash memory system 150 become unused. The associated flash controller 140 (or the GPP 132 or both) will ultimately need to reclaim this space through garbage collection performed by the garbage collector 720. The garbage collector 720 selects a particular block stripe for garbage collection based on a number of factors, including, for example, the health of the physical blocks within the block stripe and how much of the data within the physical blocks is invalid. In at least one embodiment, garbage collection is performed on the entire block stripe, and the garbage collector 720 issues a relocation write command to the caching engine 714 of the data placement function 704 to relocate still valid data within the garbage collected block stripe to another block stripe. In a NAND flash memory system 150 implementing a hybrid hierarchical arrangement that includes a first pool of physical blocks operating in a higher storage density mode (e.g., QLC mode) and a second pool of physical blocks operating in a lower storage density mode (e.g., SLC mode), it is desirable to enable the garbage collected data to be written from old blocks operating in either mode to new blocks operating in either mode. Therefore, the relocation write command issued by the garbage collector 720 may specify the desired operating mode of the target block stripe, for example, to support QLC-QLC, SLC-QLC, SLC-SLC, or QLC-SLC garbage collection.

[0045] As further indicated in FIG. 7, the flash management function performed by GPP132 or the flash controller 140 or both further includes a wear leveler 722 that requests rearrangement of data held within a block stripe in the occupied block queue 708 to equalize wear across blocks, and a pool balancer 724 that requests rearrangement of data held within a particular block stripe to enable some or all of the constituent blocks to be reconfigured to operate in different operating modes (e.g., QLC or SLC).

[0046] Based on the relocation write commands received from the garbage collector 720, wear-leveler 722, and pool balancer 724, the caching engine 714 stores the relocation write data from the old block stripe in the relocation write buffer 148 within the flash controller volatile memory 144. Additionally, the caching engine 714 may update the LPT table 152 to additionally indicate the location within the relocation write buffer 148. When all still-valid data has been moved from the old block stripe and written to the new pages of the allocated page stripe identified within the open block queue 706, the destaging engine 716 updates the LPT table 152 to remove the current association between the logical and physical addresses of the data and to associate the LBA of the relocated data with the address of the physical page within the NAND flash memory 150 used to store the relocated data. Next, the old block stripe is disassembled, thus disassociating the blocks and placing the block identifiers into the erase queue 710, which may include one erase queue 710 per channel. Next, the block erase function 712 of the flash controller 140 erases each of the blocks that previously formed the disassembled block stripe and increments the associated program / erase (P / E) cycle count for the blocks within the management data structure 158. Based on the health metric of each erased block, each erased block is either retired (i.e., no longer used to store user data) or, instead, prepared for reuse by placing the block identifier on the appropriate ready-to-use (RTU) queue 700 within the associated GPP memory 134.

[0047] Next, referring to FIG. 8, a high-level logic flowchart of an exemplary method in which a controller responds to a host write command in a non-volatile memory system according to one embodiment is shown. The illustrated process may be performed by a controller (e.g., GPP 132 or flash controller 140 or both) in the form of hardware, firmware, software, or a combination thereof, for example, during operation of data storage system 120. Unless otherwise specifically stated, the operations are presented in a logical order rather than a strictly chronological order, and in some embodiments, the operations may be performed in an order different from that presented or simultaneously.

[0048] The process of FIG. 8 begins at block 800 and then proceeds to block 802. Block 802 indicates that the controller monitors for receipt of a host write command from a host, such as processor system 102. The host write command includes or associates the LBA to be written and the host write data. In response to detection of the host write command, the controller invalidates the entry for the LBA in LPT 152, if it exists. The process preferably proceeds in parallel from block 804 to blocks 806 and 808. Block 806 indicates that the controller buffers the host write data of the host write in host write cache 146a within flash controller non-volatile memory 142. Block 808 indicates that the controller additionally mirrors the host write data of the host write in host write cache 146b within flash controller volatile memory 144.

[0049] The minimum sizes of the host write caches 146a, 146b required to buffer host write data increase with the internal parallelism and number of supported write streams, as well as the supported write bandwidth and average write latency. For a controller with given write bandwidth and latency characteristics, the minimum size can be calculated as a function of the physical page size, number of lanes and planes, maximum number of outstanding page stripes, and number of supported write streams and bins. For example, for a NAND flash memory system 150 implementing 16 kB pages, 20 lanes with 4 planes grouped into stripes, and 4 outstanding word lines (i.e., 16 page stripes), the minimum size of the host write caches 146a, 146b can be determined to be 16 kB × 20 × 4 × 16 = 20 MB per stream / bin.

[0050] Referring to FIG. 9, there is shown a diagram of an exemplary data structure in accordance with one embodiment in which a controller supports both the separation of host write data and reallocation write data into different write streams and the separation of read heat within the write streams. In this exemplary embodiment, flash controller 140 implements one write stream for host write data and two write streams for relocation write data. Each write stream includes five write bins, including one write bin for SLC data and four write bins for QLC data. The four write bins for QLC data include respective bins for each QLC page type, namely, lower page (LP), upper page (UP), special page (XP), and top page (TP). Flash controller 140 directs data to the various QLC write bins based on relative read heat. For example, the coolest QLC write data is buffered in the QLC TP buffer, then the next warmer QLC write data is buffered in the QLC XP buffer, then the next warmer QLC write data is buffered in the QLC UP buffer, and the warmest QLC write data is buffered in the QLC LP buffer. Implementing the various heat bins increases the minimum size of host write caches 146a, 146b, but reducing the number of write streams or heat bins or both to reduce the footprint of host write caches 146a, 146b is not preferred because the overall write amplification will increase or the read heat separation efficiency will significantly degrade.

[0051] Returning to block 806 in FIG. 8, based on the host write data of the host write command being buffered in host write cache 146a, the controller starts transmitting an affirmative response to the host write command to the initiating host via I / O channel 110 (block 810). As described above, the affirmative response message implies the persistent storage of the host write data and, therefore, notifies the host that the resources allocated to the host write command can be freed for reuse. The process of FIG. 8 proceeds from blocks 810 and 808 and rejoins at block 812. Block 812 indicates that the controller updates the entry in LPT 152 for the LBA of the host write command to point to the location of the host write data within one or both of write caches 146a, 146b. As a result, in at least some embodiments, the controller can start responding to host read commands that request host write data from write cache 146b.

[0052] In block 814, the controller initiates the destaging of host write data from write cache 146b (rather than from write cache 146a) into the NAND flash memory system 150, in accordance with the allocation of data to the buffers within host write cache 146b. By avoiding destaging host write data from write cache 146a, access to the flash controller non-volatile memory 142 is typically constrained to a single write per host write command. In a preferred embodiment, the destaging of host write data is performed "in the background" while the controller is not busy responding to other host I / O commands or performing other management functions. The controller monitors for the completion of the destaging of host write data from write cache 146b into the NAND flash memory system 150 (block 816). In response to detecting that the destaging of host write data has completed, the controller can free (invalidate) the copy of the host write data that exists within host write cache 146a, since the host write data is now permanently stored within the NAND flash memory system 150 (block 818). Note that a copy of the host write data can be retained within host write cache 146b to respond to future host reads of the data. This can be beneficial, for example, when the size of host write cache 146b is larger than that of host write cache 146a. Alternatively, the host write data within host write cache 146b could be freed at the same time as the copy within host write cache 146a. The decision to free or retain the host write data within host write cache 146b can depend on, for example, the implemented caching policy, the likelihood that the host write data will be read in the future, or the available size of host write cache 146b, or a combination thereof. The process of FIG. 8 then ends at block 820.

[0053] Although not explicitly shown in FIG. 8, those skilled in the art will understand that data loss will be avoided if a power loss occurs to the flash card 126 or the data storage system 120 while a host write command is being responded to. In that case, the host write data can be recovered from the host queue by the host or from the persistent copy buffered in the write cache 146a by the controller. However, in the normal operation without power loss, the process of the present disclosure includes the following four internal data movements within the flash card 126: 1. One write into the non-volatile write cache 146a, 2. One write into the mirrored volatile write cache 146b, 3. One read from the mirrored volatile write cache 146b, and 4. One write into the NAND flash memory system 150. As will be appreciated, restricting access to the non-volatile write cache 146a to one write access per host write command significantly reduces the required bandwidth to the non-volatile write cache 146a compared to prior art solutions, and thus reduces the minimum required size (and cost) of the non-volatile write cache 146a. Alternatively, the saved space in the non-volatile write cache could be used to increase the number of write streams and thus improve thermal isolation.

[0054] Next, referring to FIG. 10, a high-level logical flow chart of an exemplary method in which a controller in a non-volatile memory system responds to a relocation write command according to one embodiment is shown. The illustrated process may be performed by a controller (e.g., GPP 132 or flash controller 140 or both) in the form of hardware, firmware, software, or a combination thereof, for example, during operation of the data storage system 120. Also in this case, as before, the operations are presented in a logical order rather than a strictly chronological order, and in some embodiments, the operations may be performed in an order different from that presented or simultaneously.

[0055] The process of FIG. 10 starts at block 1000 and then proceeds to block 1002. Block 1002 indicates that the controller monitors for receipt of a relocation write command, for example, from the garbage collector 720, wear-leveler 722, or pool balancer 724. The relocation write command specifies one or more physical blocks (e.g., block stripes) within the NAND flash memory 150 to which the relocation write data is to be relocated. In response to detection of the relocation write command, the controller reads one or more still-valid data pages (referred to herein as "relocation write data") from the physical blocks into the relocation write buffer 148 within the flash controller volatile memory 144 from the NAND flash memory 150 (block 1004). Note that the controller avoids buffering any of the relocation write data in the flash controller non-volatile memory 142.

[0056] In block 1006, the controller begins the destage of relocation write data from the relocation write buffer 148 into a block stripe within the NAND flash memory system 150 identified within the open block queue 706. In a preferred embodiment, the destage of the relocation write data is performed "in the background" while the controller is not busy in response to other host I / O commands or performing other management functions. The controller monitors for completion of the destage of the relocation write data from the relocation write buffer 148 to the NAND flash memory system 150 (block 1008). In response to detecting that the destage of the relocation write data is complete, the controller checks whether all still valid pages have been relocated from the relocated block or block stripe (block 1010). If there are additional pages to be relocated, the controller returns to block 1004 and reads the next one or more still valid pages as described above. When there are no remaining still valid pages, the controller can place the identifier of the source block from which the relocation write data was read into the erase queue 710 and free (invalidate) the copy of the relocation write data that exists within the relocation write buffer 148 (block 1012). In block 1012, the controller additionally updates the relevant entry within the LPT 152 to point to the new storage location within the NAND flash memory 150. Thereafter, the process of FIG. 10 ends in block 1014.

[0057] In normal operation (i.e., in the absence of a power loss), the process of the present disclosure for processing a relocation write command includes the following four internal data movements within the flash card 126: 1. One read from the NAND flash memory system 150, 2. One write into the relocation write buffer 148 within the flash controller volatile memory 148, 3. One read from the relocation write buffer 148, and 4. One write into the NAND flash memory system 150. As will be appreciated, eliminating any access to the non-volatile write cache 146a during response to the relocation write command greatly reduces the required bandwidth to the non-volatile write cache 146a compared to prior art solutions, and thus reduces the minimum required size (and cost) of the non-volatile write cache 146a. Alternatively, the saved space in the non-volatile write cache could be used to increase the number of write streams and thus improve heat separation.

[0058] Referring now to FIG. 11, a block diagram of an exemplary flash card of the data storage system of FIG. 1A according to the second embodiment is shown. As indicated by like reference numerals, the illustrated flash card 126’ includes mirrored host write caches 146a, 146b employed as previously described with reference to FIGS. 8 and 10. However, the flash card 126’ omits the separate flash controller non-volatile memory 142 and, instead, implements the host write cache 146a within the mass non-volatile memory within the NAND flash memory system 150. This second embodiment can be provided at a lower cost due to the omission of the flash controller non-volatile memory, but typically exhibits lower write performance due to the longer latency of writes to the NAND flash memory system 150. This longer write latency can be partially improved by implementing the host write cache 146a exclusively within a faster SLC storage tier (i.e., either within a QLC block configured to operate in SLC mode or within dedicated SLC flash memory).

[0059] As described above, in at least one embodiment, a data storage system provides persistent storage within a large-capacity non-volatile memory. A controller of the data storage system receives a host write command and buffers the associated host write data in both a first write cache within the non-volatile memory and a mirrored second write cache within the volatile memory. The controller destages the host write data from the second write cache, rather than the first write cache, to the large-capacity non-volatile memory. The controller responds to a relocation write command that requests data relocation within the large-capacity non-volatile memory by referencing the second write cache. Responding to the relocation write command includes buffering the relocation write data in the second write cache, rather than the first write cache, and destaging the relocation write data from the second write cache to the large-capacity non-volatile memory.

[0060] In at least one embodiment, before completion of destaging host write data to the large-capacity non-volatile memory, the controller sends an affirmative response to the host write command to the host based on the host write data being buffered in the first write cache.

[0061] In at least one embodiment, the large-capacity non-volatile memory includes flash memory, and the controller generates at least a portion of the relocation write commands during garbage collection within the flash memory.

[0062] In at least one embodiment, the controller releases the host write data of the host write command based on completion of destaging host write data to the large-capacity non-volatile memory within the first write cache.

[0063] In at least one embodiment, the controller records at least a first location of host write data in the first write cache within an entry of a logical-physical conversion data structure. Based on the destination of the host write data to the mass non-volatile memory, the controller updates the entry to indicate a different second location within the mass non-volatile memory.

[0064] In at least one embodiment, the controller additionally records a third location of host write data in the second write cache within an entry of a logical-physical conversion data structure.

[0065] In at least one embodiment, the mass non-volatile memory includes a first write cache.

[0066] In at least one embodiment, the controller maintains a plurality of buffers, each corresponding to a respective one of a plurality of different write heats, within the first write cache and within the second write cache.

[0067] In normal circumstances, by reducing the bandwidth requirements of the non-volatile write cache to a single write per host write command, embodiments of the present disclosure improve the design trade-off between the size of the flash controller non-volatile memory and its contribution to the cost of the data storage system. Specifically, in some embodiments, embodiments of the present disclosure make it possible to maintain a given number of write streams and sufficient write bandwidth while reducing the size (and thus the cost) of the non-volatile write cache. Alternatively, in other embodiments, it is possible to implement additional write streams that provide better performance at the same cost using a non-volatile write cache of a given size. In still other embodiments, some cost reduction can be achieved while implementing a larger number of write streams with the same overall write bandwidth.

[0068] The present invention can be a system, a method, or a computer program product, or a combination thereof. The computer program product can include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0069] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves in which instructions are recorded, and any suitable combination of the foregoing. A computer-readable storage medium should not be construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0070] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or to an external computer or external storage device via a network, such as, for example, the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each respective computing / processing device.

[0071] Computer-readable program instructions for carrying out the operation of the present invention can be in any combination of one or more programming languages, including assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object-oriented programming languages such as Smalltalk(R), C++, or the like, and conventional procedural programming languages such as the "C" programming language or similar programming languages, and can be either source code or object code. The computer-readable program instructions can be executed entirely on the user's computer, partly on the user's computer, executed as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection to an external computer can be made (e.g., through the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to customize the electronic circuit for performing aspects of the present invention.

[0072] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0073] These computer readable program instructions may be provided to the processor of a computer, other programmable data processing apparatus, or other device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer readable program instructions may be stored in a computer readable storage medium that includes instructions for causing a computer, programmable data processing apparatus, or other device to function in a particular manner, such that the computer readable storage medium comprises a product including instructions for implementing the aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0074] These computer readable program instructions may be loaded onto a computer, other programmable data processing apparatus, or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0075] Flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram can represent a module, segment, or portion of one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the drawings. For example, two blocks shown in succession may, in fact, be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order depending on the functionality involved. It should also be noted that each block of a block diagram or flowchart diagram, or both, and combinations of blocks in a block diagram or flowchart diagram, or both, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or by a combination of dedicated hardware and computer instructions.

[0076] Although the present invention has been specifically shown as described with reference to one or more preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. For example, although aspects have been described with respect to a data storage system including a flash controller that directs a particular function, it should be understood that the present invention can alternatively be implemented as a program product including a storage device storing program code that is processed by a processor to perform such a function or cause such a function to be performed. As used herein, "storage device" is specifically defined to include only statutory manufactured articles, excluding forms of transmission media themselves, transient propagated signals themselves, and energy itself.

[0077] In addition, although embodiments including the use of NAND flash memory have been described, it should be understood that embodiments of the present invention may also be used with other types of non-volatile random access memory (NVRAM), such as, for example, phase change memory (PCM) and combinations thereof.

[0078] The above-described figures, as well as the following written description of specific structures and functions, are not presented to limit the scope of what the applicant has invented or the scope of the appended claims. Rather, the figures and the written description are provided to teach any person skilled in the art to make and use the invention for which patent protection is sought. One skilled in the art will understand that not all features of the commercial embodiments of the invention are described or illustrated for clarity and understanding. Also, one skilled in the art will understand that the development of actual commercial embodiments incorporating aspects of the present invention will require numerous implementation-specific decisions to achieve the ultimate goal of the developer for the commercial embodiment. Such implementation-specific decisions may include, and perhaps be limited to, compliance with system-related, business-related, government-related, and other constraints that vary by particular implementation, location, and time. The efforts of the developer can be, in the absolute sense, complex and time-consuming, but nevertheless, such efforts would be routine for one skilled in the art having the benefit of this disclosure. It should be understood that the invention disclosed and taught herein is capable of accepting numerous various modifications and alternative forms. Finally, but not limiting, the use of singular terms such as "a" is not intended to limit the number of items.

Claims

1. A method in a data storage system for providing storage into a large-capacity non-volatile memory, comprising: receiving, by a controller of the data storage system, a host write command and buffering associated host write data into both a first write cache in the non-volatile memory and a mirrored second write cache in the volatile memory; destaging, by the controller, the host write data from the second write cache, rather than the first write cache, to the large-capacity non-volatile memory; responding, by the controller, to a relocation write command that requests data relocation in the large-capacity non-volatile memory by referencing the second write cache, including buffering relocation write data associated with the relocation write command into the second write cache, rather than the first write cache, and destaging the relocation write data from the second write cache to the large-capacity non-volatile memory; A method comprising the above steps.

2. The method according to claim 1, further comprising transmitting, by the controller, an affirmative response to the host write command to the host based on the host write data being buffered in the first write cache before completion of the destaging of the host write data to the large-capacity non-volatile memory.

3. The large-capacity non-volatile memory includes a flash memory, The method according to claim 1, further comprising generating, by the controller, at least some of a plurality of the relocation write commands during garbage collection in the flash memory. The method according to claim 1.

4. The method according to claim 1, further comprising releasing, by the controller, the host write data of the host write command based on completion of the destaging of the host write data to the large-capacity non-volatile memory in the first write cache. The method according to claim 1.

5. recording, by the controller, at least a first location of host write data in the first write cache into an entry of a logical-physical conversion data structure. The controller updates the entry to indicate a different second location within the mass non-volatile memory based on the destination of the host write data to the mass non-volatile memory. The method according to claim 1, further comprising.

6. The method according to claim 5, wherein recording in the entry includes recording in the entry a third location of the host write data in the second write cache.

7. The method according to claim 1, wherein the mass non-volatile memory includes the first write cache.

8. The controller maintains in the first write cache and the second write cache a plurality of buffers each corresponding to a respective one of a plurality of different write heats. The method according to claim 1, further comprising.

9. A data storage system, Comprising a controller for a mass non-volatile memory, the controller Receives a host write command and buffers the associated host write data in both a first write cache in the non-volatile memory and a mirrored second write cache in the volatile memory. Desaging the host write data from the second write cache to the mass non-volatile memory instead of the first write cache. Responding to a relocation write command that requests data relocation in the mass non-volatile memory by referring to the second write cache, buffering the relocation write data associated with the relocation write command in the second write cache instead of the first write cache, and desaging the relocation write data from the second write cache to the mass non-volatile memory. A data storage system configured to perform.

10. The controller Before completion of the desaging of the host write data to the mass non-volatile memory, transmits an affirmative response to the host write command to the host based on the fact that the host write data is buffered in the first write cache. The data storage system according to claim 9, further configured to perform.

11. The large-capacity non-volatile memory includes a flash memory, The controller is further configured to perform generating at least some of the plurality of relocation write commands during garbage collection in the flash memory. The data storage system according to claim 9.

12. The controller, releasing the host write data of the host write command in the first write cache based on completion of a destination stage of the host write data to the large-capacity non-volatile memory. The data storage system according to claim 9, further configured to perform the above.

13. The controller, recording at least a first location of host write data in the first write cache in an entry of a logical-physical conversion data structure; and updating the entry to indicate a different second location in the large-capacity non-volatile memory based on a destination stage of the host write data to the large-capacity non-volatile memory. The data storage system according to claim 9, further configured to perform the above.

14. The data storage system according to claim 13, wherein recording in the entry includes recording a third location of host write data in a second write cache in the entry.

15. The data storage system according to claim 9, further comprising the large-capacity non-volatile memory, and the large-capacity non-volatile memory includes the first write cache.

16. The controller, maintaining a plurality of buffers corresponding to respective ones of a plurality of different write heats in the first write cache and in the second write cache. The data storage system according to claim 9, further configured to perform the above.

17. A program for causing the controller to execute the method according to any one of claims 1 to 8.

Images