Memory System and Information Processing System

Abstract

To provide a memory system capable of reducing a cost of processing a data map that manages validity of data written in a non-volatile memory.SOLUTION: According to the embodiment, a memory system includes a non-volatile memory and a controller. The controller controls the non-volatile memory according to a command from a host. The controller uses a data map to manage validity of data in the non-volatile memory. The data map includes a plurality of first fragment tables. Each of the plurality of first fragment tables holds first information indicating validity of each piece of data of a predetermined size written in a range of a physical address in the non-volatile memory assigned to the first fragment tables, and second information indicating validity of a plurality of predetermined size data in each of a predetermined number of entries. The controller selects a block of a writing destination according to size of write data of the host.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and an information processing system.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories have become widespread. As an example of such a memory system, for example, a solid state drive (SSD) equipped with a NAND type flash memory is known.

[0003] By the way, the validity of data written in the above non-volatile memory (that is, whether the data is valid or invalid) is managed using a data map, and it is desired to efficiently manage the validity of the data. In addition, it is desired to reduce the processing cost of the data map.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment of the present invention provides a memory system and an information processing system capable of reducing the processing cost of a data map for managing the validity of data written in a non-volatile memory.

Means for Solving the Problems

[0006] According to the embodiment, the memory system is connectable to a host. The memory system includes a non-volatile memory and a controller. The non-volatile memory is including at least a first block and a second blockIt includes a plurality of blocks. The controller controls the writing of data to the non-volatile memory or the reading of data from the non-volatile memory in response to commands from the host. The controller manages the validity of the data written in the non-volatile memory using a data map. The data map includes a plurality of first fragment tables. Each of the plurality of first fragment tables holds first information indicating the validity of each of the data of a predetermined size written in the range of physical addresses in the non-volatile memory assigned to the first fragment table, and second information indicating the validity of the data of a plurality of predetermined sizes in a predetermined number of each entry. When the size of the write data for which the host's write command requests writing to the non-volatile memory is an integer multiple of the total amount of data whose validity is indicated by the second information, the controller selects the first block as the write destination block, and when it is not an integer multiple, the controller selects the second block as the write destination block. The controller selects a write destination block so that write data whose size is an integer multiple of the total data amount whose validity is indicated by the second information and write data whose size is not an integer multiple of the total data amount whose validity is indicated by the second information are not mixed in any of the plurality of blocks.

Brief Description of the Drawings

[0007]

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DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of an information processing system including the memory system according to the present embodiment.

[0009] In the present embodiment, the memory system is a semiconductor storage device configured to write data (user data) to a non-volatile memory and read data from the non-volatile memory. This memory system may be realized as, for example, a solid state drive (SSD), or may be realized as other storage devices such as a memory card. In the present embodiment, it is assumed that the memory system is realized as an SSD.

[0010] As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3. The host 2 is an information processing device that operates as a host device with respect to the memory system 3, and can be realized, for example, as a personal computer, a server device, a mobile phone, an imaging device, a mobile terminal (such as a tablet computer or a smartphone), a game device, or an in-vehicle terminal (such as a car navigation system).

[0011] The memory system 3 is configured to be connectable to the host 2, and includes a non-volatile memory 4 and a controller 5 (control circuit) that controls writing and reading of data to and from the non-volatile memory 4. Note that the non-volatile memory 4 may be configured to be detachable from the controller 5. According to this, the memory capacity of the memory system 3 can be freely expanded.

[0012] When the memory system 3 is realized as an SSD as described above, the non-volatile memory 4 is, for example, a NAND-type flash memory. In this case, the non-volatile memory 4 (NAND-type flash memory) includes a plurality of memory cells (memory cell array) arranged in a matrix. Note that the non-volatile memory 4 may be a two-dimensional NAND-type flash memory or a three-dimensional NAND-type flash memory.

[0013] Also, the memory cell array of the non-volatile memory 4 includes a plurality of blocks, and each of the blocks is composed of a number of pages. In the memory system 3 (SSD), each of the blocks functions as a data erasure unit. Also, each of the pages is a unit of data writing operation and data reading operation.

[0014] In addition, various data are written to the non-volatile memory 4, and the non-volatile memory 4 further stores an address conversion table called a LUT (Look Up Table) (hereinafter simply referred to as the LUT) 41. Note that the LUT 41 is also referred to as L2P (Logical address to Physical address). The LUT 41 corresponds to data for managing the correspondence between the logical address used when the host 2 accesses the memory system 3 (writing data to the non-volatile memory 4 or reading data from the non-volatile memory 4) and the physical address indicating the physical position where the data in the non-volatile memory 4 is written. In other words, the LUT 41 stores the physical address corresponding to each logical address in association with the logical address.

[0015] When the non-volatile memory 4 is a NAND type flash memory, the logical address managed in the LUT 41 is a logical block address (LBA: Logical Block Address), and the physical address is a physical block address (PBA: Physical Block Address). In the following description, the logical address will be described as LBA and the physical address as PBA.

[0016] In addition, the non-volatile memory 4 further stores a data map called a VDM (Valid Data Map) (hereinafter simply referred to as the VDM) 42. The VDM 42 corresponds to data for managing the validity of the data written to the physical address in the non-volatile memory 4 (that is, whether the data is valid or invalid).

[0017] Note that at least one of the LUT 41 and the VDM 42 may be stored in a non-volatile memory other than the non-volatile memory 4, for example. Also, the non-volatile memory 4 may be configured to divide the memory (area) for storing the data, the LUT 41, and the VDM 42.

[0018] The controller 5 includes a communication interface control unit 51, a write buffer memory 52, a read buffer memory 53, a non-volatile memory controller 54, a memory 55, and a processor 56. Note that the communication interface control unit 51, the write buffer memory 52, the read buffer memory 53, the non-volatile memory controller 54, the memory 55, and the processor 56 are electrically connected by an internal bus IB.

[0019] The communication interface control unit 51 controls the communication between an external device (for example, the host 2) and the memory system 3. Specifically, the communication interface control unit 51 receives various commands from the host 2. The various commands from the host 2 include, for example, a write command (write request) and a read command (read request).

[0020] Note that the write command received by the communication interface control unit 51 includes the data to be written to the non-volatile memory 4 based on the write command and the LBA used by the host 2 when accessing the data. Further, the read command received by the communication interface control unit 51 includes the LBA (that is, the LBA corresponding to the data) used by the host 2 when accessing the data read based on the read command.

[0021] Here, when a write command is received by the communication interface control unit 51, data is written to the non-volatile memory 4 based on the write command, and the write buffer memory 52 temporarily stores the data to be written to the non-volatile memory 4. Note that the data stored in the write buffer memory 52 is written to the non-volatile memory 4 via the non-volatile memory controller 54.

[0022] On the one hand, when a read command is received by the communication interface control unit 51, data is read from the non-volatile memory 4 based on the read command. The read buffer memory 53 temporarily stores the data read from the non-volatile memory 4 by the non-volatile memory controller 54. Note that the data stored in the read buffer memory 53 is transmitted to the host 2 via the communication interface control unit 51.

[0023] The non-volatile memory controller 54 controls the writing of data to the non-volatile memory 4 and the reading of data from the non-volatile memory 4. Although detailed description is omitted, the non-volatile memory controller 54 may be configured to include a DMAC (Direct Memory Access Controller), an error correction unit, a randomizer (or scrambler), etc.

[0024] The memory 55 is a main memory device used as a working memory for the processor 56. The memory 55 is, for example, a DRAM (Dynamic Random Access Memory), but may be other semiconductor memories such as SRAM (Static Random Access Memory).

[0025] Note that the memory 55 can be written to and read from at a higher speed compared to the non-volatile memory 4 and includes a cache memory 551 (the area used as such). The cache memory 551 stores cache data such as the LUT 41 and VDM 42 stored in the non-volatile memory 4.

[0026] The processor 56 controls the operation of the entire controller 5 via the internal bus IB. The processor 56 executes various processes (such as processes for various commands received from the host 2) by executing a control program (firmware) stored in, for example, a ROM (Read Only Memory) not shown in the figure.

[0027] In this embodiment, the controller 5 functions as a flash translation layer (FTL) configured to execute data management and block management of the non-volatile memory 4 (NAND type flash memory) by such a processor 56.

[0028] Note that the processor 56 may be, for example, a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), a DSP (Digital Signal Processor), or the like.

[0029] By executing the above-described control program, the processor 56 realizes functional units such as a write control unit 561, a read control unit 562, a garbage collection control unit 563, an address conversion unit 564, a management unit 565, and a cache memory control unit 566.

[0030] Note that each of these units 561 to 566 is realized by the above-described control program (that is, software), but may be realized by hardware or a combination of software and hardware.

[0031] When a write command is received by the communication interface control unit 51, the write control unit 561 controls the communication interface control unit 51, the write buffer memory 52, and the non-volatile memory controller 54, and executes a process of writing the data included in the write command to the non-volatile memory 4.

[0032] When a read command is received by the communication interface control unit 51, the read control unit 562 controls the communication interface control unit 51, the read buffer memory 53, and the non-volatile memory controller 54, and executes a process of reading the data corresponding to the LBA included in the read command from the non-volatile memory 4.

[0033] The garbage collection control unit 563 executes garbage collection (GC) on the non-volatile memory 4 with reference to the above-described VDM 42, for example, in cooperation with the write control unit 561, the read control unit 562, and the non-volatile memory controller 54. Garbage collection is a process of releasing unnecessary storage areas (memory areas) of the non-volatile memory 4. Note that compaction for eliminating fragmentation of the storage areas of the non-volatile memory 4 may be performed together with garbage collection.

[0034] When the above-described read command is received by the communication interface control unit 51, the address conversion unit 564 executes a process of converting the LBA included in the read command into a PBA (physical address) using the LUT 41 stored in the non-volatile memory 4. In the memory system 3, data (data corresponding to the LBA) can be read from the non-volatile memory 4 based on the PBA converted from the LBA by the address conversion unit 564 in this way.

[0035] When the above-described write command is received by the communication interface control unit 51 and data is written to the non-volatile memory 4 based on the write command, the management unit 565 executes a process of updating the LUT 41 and the VDM 42.

[0036] The cache memory control unit 566 reads the LUT 41 (a part thereof) or the VDM 42 (a part thereof) from the non-volatile memory 4, for example, via the read control unit 562, and stores the LUT 41 or the VDM 42 in the cache memory 551. Further, the cache memory control unit 566 reads the LUT 41 (a part thereof) or the VDM 42 (a part thereof) stored in the cache memory 551, and writes (writes back) the LUT 41 or the VDM 42 to the non-volatile memory 4 via the write control unit 561.

[0037] In FIG. 1, an example in which the memory system 3 is provided outside the host 2 has been described. However, as an interface between the host 2 and the memory system 3, for example, MVMe over Fabrics or the like may be used. Further, the memory system 3 may be built in the host 2. Furthermore, the memory system 3 may be connected to a plurality of hosts 2, or a plurality of memory systems 3 may be connected to one or more hosts 2.

[0038] Here, in the above-described LUT 41, the correspondence relationship between the LBA (logical address) and the PBA (physical address) is managed. For example, when a write command from the host 2 is received by the communication interface control unit 51 and data is written to the non-volatile memory 4 based on the write command, the management unit 565 updates (that is, registers the correspondence relationship in the LUT 41) the correspondence relationship between the LBA included in the write command and the PBA in the non-volatile memory 4 where the data is written in the LUT 41.

[0039] However, when a wide range of LBAs are specified in the above-described write command, it takes time to update the correspondence relationship between the LBA and the PBA in the LUT 41.

[0040] Therefore, the LUT 41 in the present embodiment is configured to have a hierarchical structure composed of a plurality of layers and include a plurality of tables (hereinafter referred to as LUT fragment tables) corresponding to the plurality of layers. The hierarchical structure of the LUT 41 is determined based on, for example, the setting information of the memory system 3 including the capacity of the non-volatile memory 4.

[0041] In such a LUT41, each of the plurality of LUT fragment tables shall be of the same size, for example. Although details will be described later, the LUT fragment table corresponding to the upper layer among the plurality of LUT fragment tables corresponding to a plurality of hierarchies stores an LBA (range) and reference destination information (hereinafter referred to as an LUT pointer) for referring to the LUT fragment table corresponding to a layer lower than the LUT fragment table. Note that the LUT pointer includes, for example, a PBA in the nonvolatile memory 4 in which the reference destination LUT fragment table is stored. Further, the LUT fragment table corresponding to the lowest layer in the hierarchical structure of the LUT41 stores PBAs corresponding to each of the LBAs assigned to the LUT fragment table.

[0042] That is, in the present embodiment, the LUT41 has a hierarchical structure in which the LUT fragment table corresponding to the lower layer can be sequentially referred to from the LUT fragment table corresponding to the upper layer, and the correspondence between the LBA and the PBA is managed in the hierarchical structure.

[0043] Hereinafter, with reference to FIG. 2, the LUT41 having a hierarchical structure will be conceptually described. In the example shown in FIG. 2, it is assumed that the LUT41 has a hierarchical structure composed of four layers. In this case, the LUT41 includes a plurality of first LUT fragment tables T411 to fourth LUT fragment tables T414.

[0044] As shown in FIG. 2, the first LUT fragment table T411 is a LUT fragment table corresponding to the lowest layer (hereinafter referred to as the first layer) in the hierarchical structure of the LUT41. The second LUT fragment table T412 is a LUT fragment table corresponding to the layer above the first LUT fragment table T411 (hereinafter referred to as the second layer) in the hierarchical structure of the LUT41. The third LUT fragment table T413 is a LUT fragment table corresponding to the layer above the second LUT fragment table T412 (hereinafter referred to as the third layer) in the hierarchical structure of the LUT41. The fourth LUT fragment table T414 is a LUT fragment table corresponding to the layer above the third LUT fragment table T413 (hereinafter referred to as the fourth layer) in the hierarchical structure of the LUT41. In the example shown in FIG. 2, the fourth layer is the top layer in the hierarchical structure of the LUT41.

[0045] Hereinafter, each of the above-described first LUT fragment table T411 to fourth LUT fragment table T414 will be described in detail.

[0046] First, a range of consecutive LBAs is assigned to each of the plurality of first LUT fragment tables T411, and the first LUT fragment table T411 includes a plurality of entries C411. Also, to each of the plurality of entries C411 included in the first LUT fragment table T411, a different one of the LBAs within the range of LBAs assigned to the first LUT fragment table T411 is assigned, and the PBA corresponding to the LBA (that is, the PBA in which the data corresponding to the LBA is written) is stored.

[0047] In this embodiment, the entire range of LBAs used when the host 2 accesses the memory system 3 is divided into the number of first LUT fragment tables T411, and the divided range of LBAs is assigned to each of the first LUT fragment tables T411. Thereby, in the plurality of first LUT fragment tables T411, the PBAs corresponding to each of the entire range of LBAs used when the host 2 accesses the memory system 3 can be managed.

[0048] Next, a range of LBAs wider than the above-described first LUT fragment table T411 is assigned to each of the plurality of second LUT fragment tables T412, and the second LUT fragment table T412 includes a plurality of entries C412. In addition, a range of LBAs assigned to the first LUT fragment table T411 corresponding to the lower layer of the second LUT fragment table T412 is assigned to each of the plurality of entries C412 included in the second LUT fragment table T412, and a LUT pointer indicating the position of the first LUT fragment table T411 is stored. In this case, the range of LBAs assigned to each of the second LUT fragment tables T412 corresponds to the ranges of LBAs assigned to all the first LUT fragment tables T411 indicated by the LUT pointers stored in each of the plurality of entries C412 included in the second LUT fragment table T412.

[0049] Also, a range of LBAs wider than the above-described second LUT fragment table T412 is assigned to each of the plurality of third LUT fragment tables T413, and the third LUT fragment table T413 includes a plurality of entries C413. In addition, a range of LBAs assigned to the second LUT fragment table T412 corresponding to the lower layer of the third LUT fragment table T413 is assigned to each of the plurality of entries C413 included in the third LUT fragment table T413, and a LUT pointer indicating the position of the second LUT fragment table T412 is stored. In this case, the range of LBAs assigned to each of the third LUT fragment tables T413 corresponds to the ranges of LBAs assigned to all the second LUT fragment tables T412 indicated by the LUT pointers stored in each of the plurality of entries C413 included in the third LUT fragment table T413.

[0050] Furthermore, a range of LBAs wider than the above-described third LUT fragment table T413 is assigned to each of the plurality of fourth LUT fragment tables T414, and the fourth LUT fragment table T414 includes a plurality of entries C414. Also, a range of LBAs assigned to the third LUT fragment table T413 for the lower layer of the fourth LUT fragment table T414 is assigned to each of the plurality of entries C414 included in the fourth LUT fragment table T414, and a LUT pointer indicating the position of the third LUT fragment table T413 is stored. In this case, the range of LBAs assigned to each of the fourth LUT fragment tables T414 corresponds to the ranges of LBAs assigned to all the third LUT fragment tables T413 indicated by the LUT pointers stored in each of the plurality of entries C414 included in the fourth LUT fragment table T414.

[0051] Here, each of the plurality of fourth LUT fragment tables T414 corresponding to the fourth layer (i.e., the top layer in the hierarchical structure) corresponds to each of the plurality of namespaces. A namespace is an area obtained by logically partitioning a storage area (a plurality of blocks) provided in the non-volatile memory 4. By assigning a namespace to each predetermined range of the storage area, for example, even when LBAs overlap in two or more storage areas, access to appropriate data can be achieved using the namespace ID (identification information for identifying the namespace) and the LBA. According to this, access to different namespaces can be treated in the same way as access to different devices.

[0052] In FIG. 2, the plurality of fourth LUT fragment tables T414 correspond to namespaces NS1 to NSn (n is a natural number of 2 or more). In this case, the number of the plurality of fourth LUT fragment tables T414 is n.

[0053] Note that, as shown in FIG. 2, in the LUT41, each of the namespace NS1 to NSn (the corresponding fourth LUT fragment table T414) has a hierarchical structure, and the number of hierarchical levels for each of the namespaces NS1 to NSn is determined according to the storage area (size) allocated to the namespaces NS1 to NSn. For example, when the size of the storage area allocated to a namespace is small, the number of hierarchical levels of the namespace is small. On the other hand, for example, when the size of the storage area allocated to a namespace is large, the number of hierarchical levels of the namespace is large. Note that in the example shown in FIG. 2, the case where the number of hierarchical levels of each of the namespaces NS1 to NSn is the same is shown.

[0054] In the LUT41 having the hierarchical structure shown in FIG. 2 described above, the LUT pointer stored in each of the entries C414 included in the fourth LUT fragment table T414 corresponding to the fourth layer (the topmost layer) indicates the third LUT fragment table T413 corresponding to the third layer, and the LUT pointer stored in each of the entries C413 included in the third LUT fragment table T413 indicates the second LUT fragment table T412 corresponding to the second layer, and the LUT pointer stored in each of the entries C412 included in the second LUT fragment table T412 indicates the first LUT fragment table T411 corresponding to the first layer (the bottommost layer), and the entry C411 included in the first LUT fragment table T411 is configured to store the PBA corresponding to one LBA.

[0055] According to such a LUT41, for example, based on the LBA specified in various commands (the LBA included in various commands), by sequentially referring to the fourth LUT fragment table T414, the third LUT fragment table T413, the second LUT fragment table T412, and the first LUT fragment table T411, the PBA corresponding to the LBA can be specified.

[0056] Here, in the example shown in FIG. 2, the first LUT fragment table T411 is a LUT fragment table corresponding to the lowest layer in the hierarchical structure of the LUT41, and for each entry C411 included in the first LUT fragment table T411, a PBA corresponding to one LBA is stored. In this case, assuming that the size of the data written to one PBA is 4 KiB and one first LUT fragment table T411 contains 32 entries C411, one first LUT fragment table T411 corresponding to the first layer is assigned a range of 32 LBAs (that is, the LBAs for accessing 128 KiB of data).

[0057] Similarly, assuming that one second LUT fragment table T412 contains 32 entries C412 and a LUT pointer indicating the first LUT fragment table T411 to which 32 LBAs for accessing 128 KiB of data are assigned is stored in each of the entries C412 (that is, each entry C412 is assigned the range of 32 LBAs assigned to the first LUT fragment table T411), one second LUT fragment table T412 corresponding to the second layer is assigned a range of 32×32 = 1,024 LBAs (that is, the LBAs for accessing 4 MiB of data).

[0058] Furthermore, assuming that one third LUT fragment table T413 contains 32 entries C413 and a LUT pointer indicating the second LUT fragment table T412 to which 1,024 LBAs for accessing 4 MiB of data are assigned is stored in each of the entries C413 (that is, each entry C413 is assigned the range of 1,024 LBAs assigned to the second LUT fragment table T412), one third LUT fragment table T413 corresponding to the third layer is assigned a range of 1,024×32 = 32,768 LBAs (that is, the LBAs for accessing 128 MiB of data).

[0059] Also, assume that one fourth LUT fragment table T414 contains 32 entries C414, and a LUT pointer indicating a third LUT fragment table T413 to which 32,768 LBAs for accessing 128 MiB of data are assigned is stored in each of the entries C414 (that is, a range of 32,768 LBAs assigned to the third LUT fragment table T413 is assigned to each entry C414). Then, a range of 32,768×32 = 1,048,576 LBAs (that is, LBAs for accessing 4 GiB of data) is assigned to one fourth LUT fragment table T414 corresponding to the fourth layer.

[0060] That is, in the example of LUT41 shown in FIG. 2, each of the first LUT fragment tables T411 manages a range of LBAs for accessing 128 KiB of data, each of the second LUT fragment tables T412 manages a range of LBAs for accessing 4 MiB of data, each of the third LUT fragment tables T413 manages a range of LBAs for accessing 128 MiB of data, and each of the fourth LUT fragment tables T414 manages a range of LBAs for accessing 4 GiB of data.

[0061] Although it has been described that LUT pointers are stored in each of a plurality of entries C414 included in the fourth LUT fragment table T414 in FIG. 2, when a plurality of third LUT fragment tables T413 indicated by each of the LUT pointers are arranged continuously in the nonvolatile memory 4, the fourth LUT fragment table T414 may be configured to store only a LUT pointer indicating the first third LUT fragment table T413 among the plurality of third LUT fragment tables T413 (that is, omit LUT pointers indicating third LUT fragment tables T413 that are not the first). According to this, it is possible to reduce the size of LUT41. Although the fourth LUT fragment table T414 has been described here, the same applies to other LUT fragment tables.

[0062] Also, for example, when the continuity of the PBAs in the non-volatile memory 4 in which data corresponding to the range of LBAs assigned to one LUT fragment table is written is ensured, it is also possible to omit the LUT fragment table corresponding to the lower layer than the said LUT fragment table (that is, indicated by the LUT pointers stored in the entries included in the said LUT fragment table).

[0063] Specifically, for example, the second LUT fragment table T412 manages the range of LBAs for accessing 4 MiB of data. However, when the 4 MiB of data accessed by the LBAs managed in the second LUT fragment table T412 is written to consecutive PBAs, the entry C413 included in the third LUT fragment table T413 may store the head PBA to which the 4 MiB of data is written instead of the LUT pointer indicating the second LUT fragment table T412. According to this, since it becomes unnecessary to refer to the second LUT fragment table T412 and the first LUT fragment table T411 lower than this third LUT fragment table T413, the LUT41 can be efficiently referred to, and it becomes possible to improve the access speed to the data written in the non-volatile memory 4.

[0064] FIG. 3 shows an example of the data structure of the LUT fragment tables included in the LUT41 in the present embodiment. Here, the data structure of the first LUT fragment table T411 will be mainly described.

[0065] The first LUT fragment table T411 includes, for example, a plurality of PBA storage units 41a, an LBA storage unit 41b, and a management data storage unit 41c.

[0066] The PBA storage unit 41a corresponds to the entry C411 included in the first LUT fragment table T411 described in FIG. 2. That is, the number of PBA storage units 41a is, for example, 32. The PBA storage unit 41a stores a PBA corresponding to one LBA assigned to the PBA storage unit 41a (entry C411) (that is, the PBA in which data corresponding to the LBA is written). When data corresponding to one LBA assigned to the PBA storage unit 41a is stored in the cache memory 551, the PBA storage unit 41a stores address information (PBA) in the cache memory 551. The size of the PBA stored in the PBA storage unit 41a is, for example, 32 bits.

[0067] In addition, for example, 8-bit management data MD1 is attached to the PBA stored in the PBA storage unit 41a, and the management data MD1 is stored in the PBA storage unit 41a together with the PBA. The management data MD1 attached to the PBA in this way includes data for managing, for example, whether the PBA is a PBA in the non-volatile memory 4 or address information in the cache memory 551.

[0068] In this case, the size of each of the PBA storage units 41a is 40 bits obtained by adding the size of the PBA (32 bits) and the size of the management data MD1 (8 bits), and the total size of the 32 PBA storage units 41a is 160 bytes.

[0069] The LBA storage unit 41b stores the first LBA in the range of LBAs assigned to the first LUT fragment table T411.

[0070] The management data storage unit 41c stores a namespace ID for identifying the namespace to which the first LUT fragment table T411 belongs and a Grain corresponding to the range of LBAs assigned to the first LUT fragment table T411 (the range of LBAs managed by the first LUT fragment table T411).

[0071] Note that other information may be stored in the management data storage unit 41c. Specifically, identification information (hierarchical ID) for identifying the hierarchy (first hierarchy) corresponding to the first LUT fragment table T411 and the like may be stored in the management data storage unit 41c.

[0072] Here, for example, when the LUT 41 is updated in the present embodiment, a part of the LUT 41 (the LUT fragment table to be updated) is stored in the cache memory 551. In this case, a part of the LUT 41 is stored in cache line units. Further, a part of the LUT 41 updated in the cache memory 551 is written back to the non-volatile memory 4 in cache line units.

[0073] Assume a case where the first LUT fragment table T411 is stored in the cache memory 551 in cache line units as described above. When the first LUT fragment table T411 stored in the cache memory 551 in this way is used as LUT cache data, the LUT cache data further includes, in addition to the PBA storage unit 41a, the LBA storage unit 41b, and the management data storage unit 41c described above, for example, a pointer indicating LUT cache data to be associated with each other in the cache memory 551.

[0074] Specifically, the LUT cache data includes a previous pointer storage unit 41d that stores a pointer indicating LUT cache data referred to before the LUT cache data, and a next pointer storage unit 41e that stores a pointer indicating other LUT cache data referred to after the LUT cache data.

[0075] As the pointers stored in the previous pointer storage unit 41d and the next pointer storage unit 41e described above, for example, a PBA in which other LUT cache data is stored is used, but other forms of addresses may be used.

[0076] By using pointers to the LUT cache data before and after the LUT cache data to be referenced, access to the cache memory 551 can be accelerated, and continuous access can be realized. Note that the LUT cache data may further include other management data.

[0077] In FIG. 3, the data structure of one first LUT fragment table T411 has been described, but all of the plurality of first LUT fragment tables T411 included in the LUT41 have the same data structure.

[0078] Also, the data structures of other LUT fragment tables (second LUT fragment table T412 to fourth LUT fragment table T414) other than the first LUT fragment table T411 are the same as that of the first LUT fragment table T411. However, in each of the PBA storage units 41a included in the second LUT fragment table T412 to the fourth LUT fragment table T414, a PBA (32 bits) in the non-volatile memory 4 in which the LUT fragment table is stored is stored as a LUT pointer indicating the LUT fragment table corresponding to the lower layer. Note that when the LUT fragment table corresponding to the lower layer is stored in the cache memory 551, the address information in the cache memory 551 is stored in the PBA storage unit 41a.

[0079] Also, even in the PBA storage unit 41a included in the second LUT fragment table T412 to the fourth LUT fragment table T414, there may be a case where the leading PBA in which the data corresponding to the range of the LBA assigned to the PBA storage unit 41a (entry C412, C413, or C424) is written is stored.

[0080] In the example shown in FIG. 3, the size of each of the first LUT fragment table T411 to the fourth LUT fragment table T414 is a fixed length of, for example, 168 bytes, and the size of each of the LUT cache data stored in the cache memory 551 is a fixed length of, for example, 188 bytes. However, in the present embodiment, it is assumed that the first LUT fragment table T411 to the fourth LUT fragment table T414 (that is, a plurality of LUT fragment tables included in the LUT41) are configured to have the same data structure.

[0081] Here, although the LUT41 has been described as having a hierarchical structure composed of a plurality of layers, in the present embodiment, the VDM42 also has a hierarchical structure similar to that of the LUT41.

[0082] Hereinafter, the VDM42 in the present embodiment will be described. First, with reference to FIG. 4, the VDM in the comparative example of the present embodiment will be described. The VDM in the comparative example of the present embodiment is configured to manage the validity of data written at a physical address in the non-volatile memory 4 in a single layer.

[0083] As shown in FIG. 4, the VDM42' in the comparative example of the present embodiment includes a plurality of VDM fragment tables T421' corresponding to a single layer. Different ranges of PBA (physical addresses) are assigned to the plurality of VDM fragment tables T421'. In each of the VDM fragment tables T421', the validity of the data stored in the range of the PBA assigned to the VDM fragment table T421' (that is, whether the data is valid or invalid) is managed.

[0084] In this case, for example, the entire range of the PBA in the non-volatile memory 4 that can write data based on a write command from the host 2 is divided into the number of VDM fragment tables T421', and the divided PBA ranges are assigned to each of the first VDM fragment tables T421'. As a result, in a plurality of VDM fragment tables T421', it is possible to manage the validity of the data written in the entire range of the PBA in the non-volatile memory 4 that can write data based on a write command from the host 2. Note that in each of the plurality of VDM fragment tables T421', the validity of the data written in the PBA range assigned to the VDM fragment table T421' is managed using a bitmap (BMP) described later.

[0085] Here, for example, when data is written to the PBA in the non-volatile memory 4 based on a write command from the host 2, it is necessary to refer to the VDM fragment table T421' to which the PBA is assigned in order to update the validity of the data written to the PBA. However, in order to refer to the VDM fragment table T421', it is necessary to hold (expand) pointers indicating the positions of each of the above-described plurality of VDM fragment tables T421' on the memory 55. The pointers held on the memory 55 in this way include, for example, the PBA in the non-volatile memory 4 in which each of the plurality of VDM fragment tables T421' is stored.

[0086] For example, assume that the size of the storage area of the non-volatile memory 4 in which the validity of data is managed is 2 PiB, and the size of the data written to one PBA (that is, the unit of data for which validity is managed) is 4 KiB. Then, 2 PiB ÷ 4 KiB = 549,755,813,888, and in the VDM 42', it is necessary to manage the validity of approximately 512 G pieces of 4 KiB data.

[0087] Also, assuming that one VDM fragment table T421' manages, for example, 4 KiB of data for 1,280 entries, we have 512G ÷ 1,280 = 429,496,729.6. Thus, the number of VDM fragment tables T421' required in VDM42' is 429,496,730.

[0088] Furthermore, assuming that the size of each pointer indicating a plurality of VDM fragment tables T421' is 32 bits (4 bytes), the total size of the pointers indicating all 429,496,730 VDM fragment tables T421' described above is 429,496,730 × 4 bytes = 1,717,986,920 bytes, which is approximately 1.6 GiB.

[0089] That is, when managing the validity of data written in the PBA in the non-volatile memory 4 using VDM42' according to the comparative example of the present embodiment, it is necessary to always hold the pointers indicating all the above-described 1.6 GiB of VDM fragment tables T421' in the memory 55 (that is, the information required for the management of VDM42' continues to occupy the memory 55), which may deteriorate the usability. Specifically, it is useful to hold the LUT41 in the memory 55 (cache memory 551) to improve the response speed (IO response speed) to commands from the host 2, but there is a possibility that sufficient storage space for holding the LUT41 cannot be secured by the pointers of each of the above-described VDM fragment tables T421'.

[0090] Also, although the non-volatile memory 4 is composed of a plurality of chips, for example, when the number of the chips or the capacity of the chips themselves is increased, the number of PBAs in the non-volatile memory 4 (that is, the storage area managed by the memory system 3) increases.

[0091] Accordingly, since the number of the above-described VDM fragment tables T421' also increases, the number of pointers indicating the VDM fragment tables T421' similarly increases, and it is necessary to secure a larger storage area in the memory 55 for the pointers.

[0092] Similarly, when the number of PBAs in the non-volatile memory 4 increases, the size of the VDM42' itself also increases. Therefore, if necessary, the storage area for caching the VDM42' may need to be expanded.

[0093] In response to this, for example, it is conceivable to secure a storage area by adding a memory (DRAM), but it is necessary to avoid an increase in cost. That is, in the VDM42' in the comparative example of the present embodiment, it is difficult to cope with technological innovation in the non-volatile memory 4 (that is, an increase in storage capacity).

[0094] Furthermore, when starting up the memory system 3, as described above, it is necessary to expand pointers indicating all the VDM fragment tables T421' onto the memory 55.

[0095] Also, when ending (stopping) the memory system 3, it is necessary to make all the pointers held on the memory 55 non-volatile. Specifically, for example, when one VDM fragment table T421' is cached in the memory 55 (cache memory 551), the pointer indicating the VDM fragment table T421' held on the memory 55 is changed to the address information in the cache memory 551. When ending the memory system 3, such a VDM fragment table T421' is written back to the non-volatile memory 4 (that is, made non-volatile). In this case, it is necessary to change the pointer (address information in the cache memory 551) indicating the VDM fragment table T421' to the PBA in the non-volatile memory 4 where the VDM fragment table T421' is written, and write the changed PBA (that is, the pointer) in the non-volatile memory 4 to the non-volatile memory 4. When ending the memory system 3, such processing is executed for all the VDM fragment tables T421' cached in the cache memory 551.

[0096] That is, in the comparative example of the present embodiment, in VDM42´, it takes time for the internal processing (start-up processing and shutdown processing) when starting up and shutting down the memory system 3.

[0097] Therefore, in the present embodiment, similar to the above-described LUT41, by adopting a VDM42 having a hierarchical structure, it is possible to efficiently manage the validity of the data written in the non-volatile memory 4.

[0098] Specifically, the VDM42 in the present embodiment has a hierarchical structure composed of a plurality of hierarchies, and is configured to include a plurality of VDM fragment tables for the plurality of hierarchies.

[0099] In such a VDM42, each of the plurality of VDM fragment tables is, for example, of the same size. Also, although details will be described later, in the VDM fragment table corresponding to the upper hierarchy among the plurality of VDM fragment tables corresponding to the plurality of hierarchies, a PBA (range) and reference destination information (hereinafter referred to as a VDM pointer) for referring to the VDM fragment table corresponding to the hierarchy lower than the VDM fragment table are stored. Note that the VDM pointer includes, for example, the PBA in the non-volatile memory 4 in which the reference destination VDM fragment table is stored. Also, the VDM fragment table corresponding to the lowest hierarchy in the hierarchical structure of VDM42 manages the validity of each of the data (for example, 4 KiB of data) of a predetermined size stored in the range of the PBA assigned to the VDM fragment table.

[0100] Hereinafter, with reference to FIG. 5, the VDM42 having a hierarchical structure in the present embodiment will be conceptually described. In the example shown in FIG. 5, for the sake of convenience, it is assumed that the VDM42 has a hierarchical structure composed of four hierarchies. In this case, the VDM42 includes a plurality of first VDM fragment tables T421 to fourth VDM fragment tables T424.

[0101] As shown in FIG. 5, the first VDM fragment table T421 is a VDM fragment table corresponding to the lowest layer (hereinafter referred to as the first layer) in the hierarchical structure of the VDM42. The second VDM fragment table T422 is a VDM fragment table corresponding to the layer above the first VDM fragment table T421 (hereinafter referred to as the second layer) in the hierarchical structure of the VDM42. The third VDM fragment table T423 is a VDM fragment table corresponding to the layer above the second VDM fragment table T422 (hereinafter referred to as the third layer) in the hierarchical structure of the VDM42. The fourth VDM fragment table T424 is a VDM fragment table corresponding to the layer above the third VDM fragment table T423 (hereinafter referred to as the fourth layer) in the hierarchical structure of the VDM42. In the example shown in FIG. 5, the fourth layer is the top layer in the hierarchical structure of the VDM42, and in the VDM42, the number of VDM fragment tables corresponding to the top layer (that is, the fourth VDM fragment table T424) is, for example, 1. In the present embodiment, the description will be made assuming that the number of the fourth VDM fragment tables T424 (the VDM fragment tables corresponding to the top layer) is 1, but the number of the fourth VDM fragment tables T424 may be plural.

[0102] Hereinafter, each of the above-described first VDM fragment table T421 to fourth VDM fragment table T424 will be described in detail.

[0103] First, a range of consecutive PBAs is assigned to each of the plurality of first VDM fragment tables T421, and the first VDM fragment table T421 includes a plurality of entries C421. Further, each of the plurality of entries C421 included in the first VDM fragment table T421 stores a bitmap (BMP) composed of 1-bit bit information for managing the validity of data stored in each of the plurality of PBAs corresponding to the range of PBAs assigned to the first VDM fragment table T421. In such a bitmap, for each PBA, for example, when the bit information is 1, it indicates that the data stored in the PBA is valid, and when the bit information is 0, it can indicate that the data stored in the PBA is invalid.

[0104] Note that the plurality of first VDM fragment tables T421 correspond to the plurality of VDM fragment tables T421' shown in FIG. 4 described above, and the entire range of PBAs in the non-volatile memory 4 capable of writing data based on a write command from the host 2 is divided into the number of VDM fragment tables T421, and the divided range of PBAs is assigned to each of the first VDM fragment tables T421. Thereby, in the plurality of VDM fragment tables T421, the validity of data written in the entire range of PBAs in the non-volatile memory 4 capable of writing data based on a write command from the host 2 can be managed.

[0105] Next, a range of PBA wider than the above-described first VDM fragment table T421 is assigned to each of the plurality of second VDM fragment tables T422, and the second VDM fragment table T422 includes a plurality of entries C422. Also, a range of PBA assigned to the first VDM fragment table T421 corresponding to the lower hierarchy of the second VDM fragment table T422 is assigned to each of the plurality of entries C422 included in the second VDM fragment table T422, and a VDM pointer indicating the position of the first VDM fragment table T421 is stored. In this case, the range of PBA assigned to each of the second VDM fragment tables T422 corresponds to the ranges of PBA assigned to all the first VDM fragment tables T421 indicated by the VDM pointers stored in each of the plurality of entries C422 included in the second VDM fragment table T422.

[0106] Also, a range of PBA wider than the above-described second VDM fragment table T422 is assigned to each of the plurality of third VDM fragment tables T423, and the third VDM fragment table T423 includes a plurality of entries C423. Also, a range of PBA assigned to the second VDM fragment table T422 corresponding to the lower hierarchy of the third VDM fragment table T423 is assigned to each of the plurality of entries C423 included in the third VDM fragment table T423, and a VDM pointer indicating the position of the second VDM fragment table T422 is stored. In this case, the range of PBA assigned to each of the third VDM fragment tables T423 corresponds to the ranges of PBA assigned to all the second VDM fragment tables T422 indicated by the VDM pointers stored in each of the plurality of entries C423 included in the third VDM fragment table T423.

[0107] Furthermore, a wider range of PBAs is assigned to the fourth VDM fragment table T424 than to the third VDM fragment table T423 described above. The fourth VDM fragment table T424 includes a plurality of entries C424. Also, to each of the plurality of entries C424 included in the fourth VDM fragment table T424, a range of PBAs assigned to the third VDM fragment table T423 for the lower hierarchy of the fourth VDM fragment table T424 is assigned, and a VDM pointer indicating the position of the third VDM fragment table T423 is stored. In this case, the range of LBAs assigned to the fourth VDM fragment table T424 corresponds to the ranges of PBAs assigned to all the third VDM fragment tables T423 indicated by the VDM pointers stored in each of the plurality of entries C424 included in the fourth VDM fragment table T424.

[0108] Note that when the number of fourth VDM fragment tables T424 corresponding to the topmost hierarchy in the hierarchical structure of VDM42 as described above is 1, the range of PBAs assigned to the fourth VDM fragment table T424 covers the entire range of PBAs in the non-volatile memory 4 where data validity is managed.

[0109] In the VDM42 having the hierarchical structure shown in FIG. 5 above, the VDM pointer stored in each of the entries C424 included in the fourth VDM fragment table T424 corresponding to the fourth hierarchy (the topmost hierarchy) indicates the third VDM fragment table T423 corresponding to the third hierarchy, the VDM pointer stored in each of the entries C423 included in the third VDM fragment table T423 indicates the second VDM fragment table T422 corresponding to the second hierarchy, the VDM pointer stored in each of the entries C422 included in the second VDM fragment table T422 indicates the first VDM fragment table T421 corresponding to the first hierarchy (the bottommost hierarchy), and each of the entries C421 included in the first VDM fragment table T421 is configured to store flag information (bitmap) indicating the validity of each of the pieces of data of a predetermined size stored in a plurality of PBAs.

[0110] According to such a VDM42, for example, by sequentially referring to the fourth VDM fragment table T424, the third VDM fragment table T423, the second VDM fragment table T422, and the first VDM fragment table T421 based on the PBA in which the data to be verified is stored, the validity of the data can be grasped.

[0111] That is, in the VDM42 shown in FIG. 5, since the validity of the data stored in all PBAs can be grasped from the fourth VDM fragment table T424 corresponding to the fourth layer (that is, the validity of the data managed in the first VDM fragment table), different from the VDM42' in the comparative example of the present embodiment described in FIG. 4 above, it is only necessary that the memory 55 holds only a VDM pointer (that is, one pointer) indicating the fourth VDM fragment table T424.

[0112] Here, in the example shown in FIG. 5, the first VDM fragment table T421 is a VDM fragment table corresponding to the lowest layer in the hierarchical structure of the VDM42. In each of the entries C421 included in the first VDM fragment table T421, flag information (bitmap) indicating the validity of each piece of data of a predetermined size stored in a continuous range of PBAs is stored. In this case, assuming that one first VDM fragment table T421 includes 32 entries C421, and further, a 32-bit bitmap indicating the validity of 32 pieces of data is stored in one entry C421, a range of 32 × 32 = 1,024 PBAs is allocated to one first VDM fragment table T421 corresponding to the first layer. In this case, assuming that the size of the data written to one PBA is 4 KiB as described above, in one first VDM fragment table T421, the validity of 4 KiB × 1,024 = 4 MiB of data can be managed.

[0113] Similarly, assume that one second - level VDM fragment table T422 contains 32 entries C422, and a VDM pointer indicating the first - level VDM fragment table T421 to which 1,024 PBAs for storing 4 MiB of data are assigned is stored in each of these entries C422 (that is, a range of 1,024 PBAs assigned to the first - level VDM fragment table T421 is assigned to each entry C422). Then, for one second - level VDM fragment table T422 corresponding to the second hierarchy, a range of 1,024×32 = 32,768 PBAs will be assigned. In this case, in one second - level VDM fragment table T422, the validity of 4 KiB×32,768 = 128 MiB of data can be managed.

[0114] Furthermore, assume that one third - level VDM fragment table T423 contains 32 entries C423, and a pointer indicating the second - level VDM fragment table T422 to which 32,768 PBAs for storing 128 MiB of data are assigned is stored in each of these entries C423 (that is, a range of 32,768 PBAs assigned to the second - level VDM fragment table T422 is assigned to each entry C423). Then, for one third - level VDM fragment table T423 corresponding to the third hierarchy, a range of 32,768×32 = 1,048,576 PBAs will be assigned. In this case, in one third - level VDM fragment table T423, the validity of 4 KiB×1,048,576 = 4 GiB of data can be managed.

[0115] Also, assume that one fourth VDM fragment table T424 contains 32 entries C424, and a pointer indicating a third VDM fragment table T423 to which 1,048,576 PBAs for storing 4 GiB of data are assigned is stored in each of the entries C424 (that is, a range of 1,048,576 PBAs assigned to the third VDM fragment table T423 is assigned to each entry C424). Then, a range of 1,048,576 × 32 = 33,554,432 PBAs is assigned to one fourth VDM fragment table T424 corresponding to the fourth layer. In this case, in one fourth VDM fragment table T424, the validity of 4 KiB × 33,554,432 = 128 GiB of data can be managed.

[0116] That is, in the example of VDM42 shown in FIG. 5, each of the first VDM fragment tables T421 manages a range of PBAs for storing 4 MiB of data, each of the second VDM fragment tables T422 manages a range of PBAs for storing 128 MiB of data, each of the third VDM fragment tables T423 manages a range of PBAs for storing 4 GiB of data, and the fourth VDM fragment table T424 manages a range of PBAs for storing 128 GiB of data.

[0117] In FIG. 5, for example, it has been described that a VDM pointer is stored in each of a plurality of entries C424 included in the fourth VDM fragment table T424. However, when a plurality of third VDM fragment tables T423 indicated by each of the VDM pointers are arranged continuously in the non-volatile memory 4, the fourth VDM fragment table T424 may be configured to store only a VDM pointer indicating the first third VDM fragment table T423 among the plurality of third VDM fragment tables T423 (that is, omit a VDM pointer indicating a third VDM fragment table T423 that is not the first). According to this, it is possible to reduce the size of VDM42. Although the fourth VDM fragment table T424 has been described here, the same applies to other VDM fragment tables.

[0118] Also, for example, when the validity (valid or invalid) of each of the 4 KiB of data written in the range of PBA assigned to one VDM fragment table is common, the validity of the data written in the range of the PBA in the VDM fragment table is collectively managed, and it is also possible to omit the VDM fragment table corresponding to the lower hierarchy than the VDM fragment table (that is, indicated by the pointer stored in the entry included in the VDM fragment table).

[0119] Specifically, for example, assume that the second VDM fragment table T422 manages the range of PBA in which 128 MiB of data is stored, and all of the 128 MiB of data (all the 4 KiB of data constituting it) is valid or all invalid. In this case, management data indicating that all of the 128 MiB of data stored in the range of PBA assigned to the second VDM fragment table T422 is valid or all invalid is held in the third VDM fragment table T423 corresponding to the upper hierarchy of the second VDM fragment table T422 (that is, including the entry storing the VDM pointer indicating the second VDM fragment table T422), and each of the second VDM fragment table T422 and the first VDM fragment table T421 corresponding to the lower hierarchy of the second VDM fragment table T422 may be discarded. According to this, since it becomes unnecessary to refer to the second VDM fragment table T422 and the first VDM fragment table T421 lower than the third VDM fragment table T423, it is possible to improve the access speed to VDM42.

[0120] FIG. 6 shows an example of the data structure of the first VDM fragment table T421 included in VDM42 in the present embodiment.

[0121] The first VDM fragment table T421 includes, for example, a plurality of map storage units 42a, a PBA storage unit 42b, and a management data storage unit 42c.

[0122] The map storage unit 42a corresponds to the entry C421 included in the first VDM fragment table T421 described in FIG. 5. That is, the number of map storage units 42a is, for example, 32. The map storage unit 42a stores a bitmap composed of 1-bit flag information that manages the validity (valid or invalid) of each 4 KiB of data written in the range of the PBA assigned to the map storage unit 42a (entry C421). When ranges of 32 PBAs are assigned to the map storage unit 42a, the size of the bitmap stored in the map storage unit 42a is 1 bit × 32 = 32 bits.

[0123] In addition, for example, 8-bit management data MD2 is attached to the bitmap stored in the map storage unit 42a, and the management data MD2 is stored in the map storage unit 42a together with the bitmap. As such management data MD2 attached to the bitmap, for example, a magic number called the VDM mode is set. The magic numbers set as the management data MD2 include "0xff" and "0x00".

[0124] Note that as described above, the bitmap stored in the map storage unit 42a is composed of 1-bit flag information indicating the validity of 4 KiB of data stored in each of the 32 PBAs assigned to the map storage unit 42a. However, in the following description, for convenience, the 4 KiB of data stored in each of the 32 PBAs is referred to as the data managed in the bitmap.

[0125] The magic number "0xff" indicates that all the data managed in the bitmap to which the magic number (management data MD2) is attached is valid (i.e., all the flag information constituting the bitmap is 1). That is, according to this magic number "0xff", the validity of the data written in a certain range of PBA can be collectively managed, and without referring to the bitmap to which the magic number is attached, it can be grasped that all the data managed in the bitmap is valid.

[0126] The magic number "0x00" indicates that all the data managed in the bitmap to which the magic number (management data MD2) is attached is invalid (i.e., all the flag information constituting the bitmap is 0). That is, according to this magic number "0x00", similar to the above-mentioned magic number "0xff", the validity of the data written in a certain range of PBA can be collectively managed, and without referring to the bitmap to which the magic number is attached, it can be grasped that all the data managed in the bitmap is invalid.

[0127] In addition, when the magic numbers "0xff" and "0x00" are not set as the management data MD2, it means that the bitmap to which the management data MD2 is attached is composed of flag information indicating validity and flag information indicating invalidity (i.e., the flag information indicating validity and the flag information indicating invalidity are mixed in the bitmap).

[0128] When the bitmap and the management data MD2 are stored in the map storage unit 42a as described above, the size of each of the map storage units 42a is 40 bits obtained by adding the size of the bitmap (32 bits) and the size of the management data MD2 (8 bits), and the total size of the 32 map storage units 42a is 160 bytes.

[0129] The PBA storage unit 42b stores the leading PBA within the range of PBAs assigned to the first VDM fragment table T421.

[0130] In the management data storage unit 42c, a Valid ADU Count indicating the number of valid data among a plurality of 4 KiB data stored within the range of PBAs assigned to the first VDM fragment table T421 and a Grain corresponding to the range of PBAs assigned to the first VDM fragment table T421 (the range of PBAs managed by the first VDM fragment table T421) are stored. In the case of the first VDM fragment table T421, the maximum value of the Valid ADU Count is 1,024.

[0131] Note that other information may be stored in the management data storage unit 42c. Specifically, identification information (hierarchical ID) for identifying the hierarchy (first hierarchy) corresponding to the first VDM fragment table T421 and the like may be stored in the management data storage unit 42c.

[0132] Here, in this embodiment, for example, when the VDM42 is updated, a part of the VDM42 (the VDM fragment table to be updated) is stored in the cache memory 551. In this case, a part of the VDM42 is stored in cache line units. Also, the part of the VDM42 updated in the cache memory 551 is written back to the non-volatile memory 4 in cache line units.

[0133] Assume the case where the first VDM fragment table T421 is stored in the cache memory 551 in cache line units. When the first VDM fragment table T421 stored in the cache memory 551 in this way is regarded as VDM cache data, the VDM cache data further includes, in addition to the above-described map storage unit 42a, PBA storage unit 42b, and management data storage unit 42c, a pointer indicating VDM cache data to be associated with each other in the cache memory 551, for example.

[0134] Specifically, the VDM cache data includes a previous pointer storage unit 42d that stores a pointer indicating the VDM cache data referenced before the VDM cache data, and a next pointer storage unit 42e that stores a pointer indicating other VDM cache data referenced after the VDM cache data. Note that pointers indicating the above-described LUT cache data may be stored in the previous pointer storage unit 42d and the next pointer storage unit 42e.

[0135] As the pointers stored in the above-described previous pointer storage unit 42d and next pointer storage unit 42e, for example, a PBA in which other VDM cache data is stored is used, but other forms of addresses may be used.

[0136] By using pointers to the VDM cache data before and after the VDM cache data to be referenced in this way, access to the cache memory 551 can be accelerated, and continuous access can be realized. Note that the VDM cache data may further include other management data.

[0137] In FIG. 6, the data structure of one first VDM fragment table T421 has been described, but all of the plurality of first VDM fragment tables T421 included in the VDM42 have the same data structure.

[0138] Next, FIG. 7 shows an example of the data structure of the second VDM fragment table T422 included in the VDM42 in the present embodiment. Here, mainly the differences from the first VDM fragment table T421 shown in FIG. 6 described above will be described.

[0139] In FIG. 6, the first VDM fragment table T421 has been described as including the map storage unit 42a, but the second VDM fragment table T422 includes a PBA storage unit 42f instead of the map storage unit 42a.

[0140] The PBA storage unit 42f corresponds to the entry C422 included in the second VDM fragment table T422 described in FIG. 5. That is, the number of PBA storage units 42f is, for example, 32. The PBA storage unit 42f stores the PBA in the non-volatile memory 4 where the first VDM fragment table T421 is stored as a pointer indicating the first VDM fragment table T421 corresponding to the lower layer of the second VDM fragment table T422. When the first VDM fragment table T421 corresponding to the lower layer is stored in the cache memory 551, the address information in the cache memory 551 is stored in the PBA storage unit 42f. The size of the PBA stored in the PBA storage unit 42f is, for example, 32 bits.

[0141] In addition, for example, 8-bit management data MD3 is attached to the PBA stored in the PBA storage unit 42f, and the management data MD3 is stored in the PBA storage unit 42f together with the bitmap. As the management data MD3 attached to the bitmap in this way, a magic number called the VDM mode is set in the same manner as the management data MD2 described in FIG. 6 above.

[0142] Although it has been described that "0xff" and "0x00" are set as magic numbers for the management data MD2, the magic numbers set for the management data MD3 further include "0xfc" and "0xfd" in addition to the "0xff" and "0x00".

[0143] The magic number "0xfc" indicates that the PBA to which the magic number (management data MD3) is attached is a PBA in the non-volatile memory 4. According to this magic number "0xfc", the first VDM fragment table T421 stored in the non-volatile memory 4 can be referred to (acquired) based on the PBA to which the magic number is attached.

[0144] The magic number "0xfd" indicates that the PBA with this magic number (management data MD3) is the address information in the cache memory 551. According to this magic number "0xfd", the first VDM fragment table T421 stored in the cache memory 551 can be referred to (acquired) based on the PBA with this magic number.

[0145] Note that the first VDM fragment table T421 referred to based on the PBA stored in the PBA storage unit 42f as described above is a VDM fragment table corresponding to the first layer to which the range of the PBA assigned to the PBA storage unit 42f (entry C422) is assigned.

[0146] Also, as the management data MD3, the above-mentioned magic numbers "0xff" or "0x00" may be set. When the magic number "0xff" is set as the management data MD3, it means that all of the 4 KiB data stored in the range of the PBA (for example, PBA for 1,024 pieces) assigned to the PBA storage unit 42f storing the PBA with this magic number is valid. On the other hand, when the magic number "0x00" is set as the management data MD3, it means that all of the 4 KiB data stored in the range of the PBA (for example, PBA for 1024 pieces) assigned to the PBA storage unit 42f storing the PBA with this magic number is invalid.

[0147] That is, when either the magic number "0xff" or "0x00" is set as the management data MD3, it can be grasped that all of the data stored in the range of the PBA assigned to the PBA storage unit 42f (entry C422) storing the PBA with this magic number is valid or invalid. In this case, it is not necessary to refer to the first VDM fragment table T421 corresponding to the lower layer based on the PBA with the magic number "0xff" or "0x00".

[0148] On the other hand, when the magic numbers "0xff" and "0x00" are not set as the management data MD3 (that is, the magic number "0xfc" or "0xfd" is set), it is possible to grasp that valid data and invalid data are mixed in the range of the PBA assigned to the PBA storage unit 42f (entry C422) that stores the PBA with the magic number. In this case, it is necessary to refer to the first VDM fragment table T421 corresponding to the lower layer based on the PBA with the magic number "0xfc" or "0xfd".

[0149] As described above, when the PBA and the management data MD3 are stored in the PBA storage unit 42f, the size of each of the PBA storage units 42f is 40 bits obtained by adding the size of the PBA (32 bits) and the size of the management data MD3 (8 bits), and the total size of the 32 PBA storage units 42f is 160 bytes.

[0150] Note that the second VDM fragment table T422 further includes the PBA storage unit 42b and the management data storage unit 42c in addition to the PBA storage unit 42f. Since the PBA storage unit 42b and the management data storage unit 42c are as described in FIG. 6, the detailed description thereof is omitted here.

[0151] In addition, the second VDM fragment table T422 (VDM cache data) stored in the cache memory 551 includes the previous pointer storage unit 42d and the next pointer storage unit 42e. Since the previous pointer storage unit 42d and the next pointer storage unit 42e are as described in FIG. 6, the detailed description thereof is omitted here.

[0152] In FIG. 7, the data structure of one second VDM fragment table T422 has been described. All of the plurality of second VDM fragment tables T422 included in the VDM42 have the same data structure.

[0153] In addition, the data structures of other VDM fragment tables (the third VDM fragment table T423 and the fourth VDM fragment table T424) other than the second VDM fragment table T422 are the same as those of the second VDM fragment table T422. That is, for example, in the third VDM fragment table T423, when one of the magic numbers "0xff" and "0x00" is set as the management data MD3, it is not necessary to refer to the second VDM fragment table T422 corresponding to the lower layer based on the PBA with the magic number attached. The same applies to the fourth VDM fragment table T424.

[0154] Note that in the examples shown in FIGS. 6 and 7 described above, the sizes of each of the first VDM fragment table T421 to the fourth VDM fragment table T424 are, for example, fixed lengths of 168 bytes, and the sizes of each of the VDM cache data stored in the cache memory 551 are, for example, fixed lengths of 188 bytes. However, in the present embodiment, it is assumed that the first VDM fragment table T421 to the fourth VDM fragment table T424 (that is, a plurality of VDM fragment tables included in the VDM42) are configured to have the same data structure.

[0155] In addition, as described in FIGS. 3, 6, and 7 described above, the LUT41 (each LUT fragment table included therein) and the VDM42 (each VDM fragment table included therein) in the present embodiment are configured to have the same data structure. Hereinafter, the relationship between the above-described LUT41 and VDM42 will be described.

[0156] First, as described above, the LUT41 is data for managing the PBA corresponding to the LBA. Assuming that one first LUT fragment table T411 corresponding to the lowest layer (the first layer) includes 32 entries C411 (PBA storage unit 41a), 32 LBAs (PBAs corresponding thereto) can be managed in the first LUT fragment table T411. Also, assuming that one second LUT fragment table T412 corresponding to one layer higher than the lowest layer (the second layer) similarly includes 32 entries C412, 32×32 = 1,024 LBAs (PBAs corresponding thereto) can be managed in the second LUT fragment table T412. Although the explanation here is up to the second layer, the same applies to layers higher than the second layer.

[0157] On the other hand, as described above, the VDM42 is data for managing the validity of the data stored in each PBA. Assuming that a 32-bit bitmap is stored in one entry C421 (map storage unit 42a) of one first VDM fragment table T421 corresponding to the lowest layer (the first layer), 32 bits × 32 = 1,024 PBAs (data stored therein) can be managed in the first VDM fragment table T421. Also, assuming that one second VDM fragment table T422 corresponding to one layer higher than the lowest layer (the second layer) similarly includes 32 entries C422, 1,024×32 = 32,768 PBAs (data stored therein) can be managed in the second VDM fragment table T422. Although the explanation here is up to the second layer, the same applies to layers higher than the second layer.

[0158] That is, in the present embodiment, the LUT41 and the VDM42 each manage one fragment table corresponding to the lower layer with one entry, and in both the LUT41 and the VDM42, 32 times the number of PBAs can be managed each time the layer goes up one level.

[0159] Here, assume a case where 4 MiB of data corresponding to a range of 1,024 consecutive LBAs is written (sequentially written) to 1,024 consecutive PBAs in the non-volatile memory 4. It is assumed that 4 KiB of data is written to each of the 1,024 PBAs.

[0160] In this case, it is necessary to manage the correspondence relationship between the LBAs corresponding to the 4 MiB of data written to the non-volatile memory 4 and the PBAs to which the data is written in the LUT 41. However, as described above, the second LUT fragment table T412 can manage 1,024 LBAs (the PBAs corresponding thereto).

[0161] Therefore, when the 1,024 LBAs managed by the second LUT fragment table T412 (that is, those assigned to the second LUT fragment table T412) match the 1,024 LBAs corresponding to the above-described 4 MiB of data, among the LUT pointers stored in the plurality of entries C413 included in the third LUT fragment table T413 corresponding to the upper hierarchy of the second LUT fragment table T412, the LUT pointer indicating the second LUT fragment table T412 can be updated to the first PBA among the 1,024 PBAs to which the 4 MiB of data is written. According to this, the correspondence relationship between the LBAs corresponding to the above-described 4 MiB of data and the PBAs to which the data is written can be managed with one entry C413 included in the third LUT fragment table T413.

[0162] On the other hand, when 4 MiB of data is written to 1,024 consecutive PBAs in the non-volatile memory 4 as described above, it is necessary to manage the 4 MiB of data as valid data in the VDM 42. However, as described above, the first VDM fragment table T421 can manage 1,024 PBAs.

[0163] Therefore, when the 1,024 PBAs managed by the first VDM fragment table T421 (i.e., assigned to the first VDM fragment table T421) match the 1,024 PBAs into which the above-mentioned 4 MiB of data is written, among the VDM pointers stored in a plurality of entries C422 included in the second VDM fragment table T422 corresponding to the upper layer of the first VDM fragment table T421, the management data MD3 (magic number) attached to the VDM pointer indicating the first VDM fragment table T421 can be updated to "0xff". According to this, it is possible to manage that the 4 MiB of data stored in the above-mentioned 1,024 PBAs is valid with one entry C422 included in the second VDM fragment table T422.

[0164] That is, when 4 MiB of data corresponding to a range of 1,024 consecutive LBAs as described above is written into 1,024 consecutive PBAs, the correspondence relationship between the LBA and the PBA can be managed by changing one entry (PBA) included in the LUT fragment table corresponding to two upper layers from the lowest layer included in the LUT41. Also, the validity of the 4 MiB of data written into the non-volatile memory 4 in this way can be managed by changing one entry (magic number) included in the VDM fragment table corresponding to one upper layer from the lowest layer included in the VDM42.

[0165] Thus, in this embodiment, by making the respective fragment tables included in the LUT41 and the VDM42 have the same data structure and aligning the management units in the LUT41 and the VDM42, it is possible to complete the update of the LUT41 and the VDM42 only by changing the entries included in the fragment tables of the upper layer without updating the fragment tables corresponding to the lowest layer.

[0166] Here, in order to complete the update of LUT41 and VDM42 by changing the entries included in the fragment table corresponding to the upper layer as described above, the VDM fragment table included in VDM42 having the same data structure as the LUT fragment table included in LUT41 M = y × N^x (hereinafter referred to as a conditional expression) needs to be satisfied.

[0167] In the above conditional expression, N is the number of entries included in the first VDM fragment table T421 corresponding to the lowest layer, and M is the number of 4 KiB of data (that is, the PBA where the data is stored) whose validity is managed in one entry included in the first VDM fragment table T421 corresponding to the lowest layer. Also, in the conditional expression, x is an integer of 0 or more, and y is an integer of 1 or more and less than N or the reciprocal of an integer of 1 or more and less than N.

[0168] Hereinafter, the relationship between N and M described above will be specifically described. Here, the number of PBAs (corresponding to LBAs) assigned to each LUT fragment table is referred to as the PBA management number of the LUT fragment table, and the number of PBAs assigned to each VDM fragment table is referred to as the PBA management number of the VDM fragment table.

[0169] Note that the number of PBAs (corresponding to LBAs) assigned to one entry included in the LUT fragment table (first LUT fragment table T411) corresponding to the first layer (lowest layer) is 1, and the same shall apply in the following description.

[0170] FIG. 8 shows the relationship between the PBA management number of the LUT fragment table corresponding to each layer and the PBA management number of the VDM fragment table when N = 32 and M = 32.

[0171] Here, when N = 32 and M = 32, the number of PBAs managed by the LUT fragment table corresponding to the first layer is 32, and the number of PBAs managed by the VDM fragment table (the first VDM fragment table T421) corresponding to the first layer is 1,024. Also, the number of PBAs managed by the LUT fragment table (the second LUT fragment table T412) corresponding to the second layer is 1,024, and the number of PBAs managed by the VDM fragment table (the second VDM fragment table T422) corresponding to the second layer is 32,768.

[0172] Although detailed explanations of the number of PBAs managed by the LUT fragment table and the number of PBAs managed by the VDM fragment table corresponding to the layer above the second layer are omitted, when N = 32, both the number of PBAs managed by the LUT fragment table and the number of PBAs managed by the VDM fragment table become 32 times as large when the layer goes up one level.

[0173] As described above, when comparing the LUT fragment table and the VDM fragment table corresponding to the same layer, the number of PBAs managed by the VDM fragment table is larger than the number of PBAs managed by the LUT fragment table. Also, when the number of PBAs managed by the entire LUT41 is the same as the number of PBAs managed by the entire VDM42, the number of layers constituting the hierarchical structure of VDM42 in this embodiment is smaller than the number of layers constituting the hierarchical structure of LUT41.

[0174] When N = 32 and M = 32, the above conditional expression is satisfied when x = 1 and y = 1. When the conditional expression is satisfied in this way, x corresponds to the hierarchical difference between the LUT fragment table and the VDM fragment table, and y corresponds to the ratio of the PBA management number of the LUT fragment table to the PBA management number of the VDM fragment table (that is, "PBA management number of VDM fragment table / PBA management number of LUT fragment table"). Specifically, when focusing on the LUT fragment table corresponding to the second layer where the hierarchical difference is 1 (that is, x = 1) and the VDM fragment table corresponding to the first layer, the PBA management number of the LUT fragment table is 1,024, the PBA management number of the VDM fragment table is 1,024, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 1 (that is, y = 1).

[0175] If N and M satisfy the above conditional expression, for example, when data corresponding to the range of 1,024 LBAs assigned to the LUT fragment table corresponding to the second layer is written into the non-volatile memory 4, the update of LUT41 can be completed by changing one entry (PBA stored in the PBA storage unit 41a) included in the LUT fragment table corresponding to the third layer. Similarly, when data corresponding to the range of 1,024 LBAs is written into 1,024 PBAs assigned to the VDM fragment table corresponding to the first layer, the update of VDM42 can be completed by changing one entry (magic number stored in the map storage unit 42a) included in the VDM fragment table corresponding to the second layer.

[0176] That is, when N = 32 and M = 32, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer (i is an integer of 1 or more) to the PBA management number of the VDM fragment table corresponding to the i - 1-th layer is 1:1. For example, when the continuity of LBA and PBA is ensured, the update of LUT41 can be corresponded by changing one entry of the LUT fragment table, and the update of VDM42 can be corresponded by changing one entry of VDM42.

[0177] Note that N = 32 and M = 32 described in FIG. 8 are one example that can most efficiently manage the LUT41 (corresponding relationship between LBA and PBA) and VDM42 (data validity). However, for example, even if N is changed, as long as the above conditional expression is satisfied, efficient management of the LUT41 and VDM42 can be realized.

[0178] Hereinafter, the case where N is changed will be described, but detailed descriptions of parts similar to those described in FIG. 8 above will be omitted.

[0179] FIG. 9 shows the relationship between the PBA management number of the LUT fragment table corresponding to each layer and the management number of the VDM fragment table when N = 8 and M = 32.

[0180] Here, when N = 8 and M = 32, the PBA management number of the LUT fragment table corresponding to the first layer is 8, and the PBA management number of the VDM fragment table corresponding to the first layer is 256. Also, the PBA management number of the LUT fragment table corresponding to the second layer is 64, and the PBA management number of the VDM fragment table corresponding to the second layer is 2,048.

[0181] Note that detailed descriptions of the PBA management number of the LUT fragment table and the PBA management number of the VDM fragment table corresponding to layers higher than the second layer are omitted. However, when N = 8, both the PBA management number of the LUT fragment table and the PBA management number of the VDM fragment table become 8 times when the layer goes up one level.

[0182] Also, when N = 8 and M = 32, the above conditional expression is satisfied when x = 1 and y = 4. Specifically, when focusing on the LUT fragment table corresponding to the second layer where the difference in layers is 1 (that is, x = 1) and the VDM fragment table corresponding to the first layer, the PBA management number of the LUT fragment table is 64, the PBA management number of the VDM fragment table is 256, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 4 (that is, y = 4).

[0183] For N and M that satisfy the above conditional expressions, for example, when data corresponding to a range of 256 LBAs assigned to the LUT fragment table for four partitions corresponding to the second layer is written to the non-volatile memory 4, the update of LUT41 can be completed by changing four entries included in the LUT fragment table corresponding to the third layer. Similarly, when data corresponding to a range of 256 LBAs is written to 256 PBAs assigned to the VDM fragment table corresponding to the first layer, the update of VDM42 can be completed by changing one entry included in the VDM fragment table corresponding to the second layer.

[0184] That is, when N = 8 and M = 32, the ratio of the number of PBAs managed by the LUT fragment table corresponding to the i-th layer to the number of PBAs managed by the VDM fragment table corresponding to the (i - 1)-th layer is 1:4. When the continuity of LBAs and PBAs is ensured as described above, the update of LUT41 can be handled by changing four entries in the LUT fragment table, and the update of VDM42 can be handled by changing one entry in VDM42.

[0185] When N = 8 and M = 32, the above conditional expressions are also satisfied when x = 2 and y = 1 / 2. Although detailed explanations are omitted, in this case, the ratio of the number of PBAs managed by the LUT fragment table corresponding to the i-th layer to the number of PBAs managed by the VDM fragment table corresponding to the (i - 2)-th layer is 2:1. When the continuity of LBAs and PBAs is ensured as described above, the update of LUT41 can be handled by changing one entry in the LUT fragment table, and the update of VDM42 can be handled by changing two entries in the VDM fragment table.

[0186] FIG. 10 shows the relationship between the number of PBAs managed by the LUT fragment table corresponding to each layer and the number of PBAs managed by the VDM fragment table when N = 16 and M = 32.

[0187] Here, when N = 16 and M = 32, the number of PBA managements of the LUT fragment table corresponding to the first layer is 16, and the number of PBA managements of the VDM fragment table corresponding to the first layer is 512. Also, the number of PBA managements of the LUT fragment table corresponding to the second layer is 256, and the number of PBA managements of the VDM fragment table corresponding to the second layer is 8,192.

[0188] Note that although detailed explanations of the number of PBA managements of the LUT fragment table and the number of PBA managements of the VDM fragment table corresponding to a layer higher than the second layer are omitted, when N = 16, both the number of PBA managements of the LUT fragment table and the number of PBA managements of the VDM fragment table become 16 times when the layer goes up one level.

[0189] Also, when N = 16 and M = 32, the above conditional expression is satisfied when x = 1 and y = 2. Specifically, when focusing on the LUT fragment table corresponding to the second layer with a layer difference of 1 (i.e., x = 1) and the VDM fragment table corresponding to the first layer, the number of PBA managements of the LUT fragment table is 256, the number of PBA managements of the VDM fragment table is 512, and "the number of PBA managements of the VDM fragment table / the number of PBA managements of the LUT fragment table" is 2 (i.e., y = 2).

[0190] If N and M satisfy the above conditional expression, for example, when data corresponding to the range of 512 LBAs assigned to two LUT fragment tables corresponding to the second layer is written into the non-volatile memory 4, the update of LUT41 can be completed by changing two entries included in the LUT fragment table corresponding to the third layer. Similarly, when data corresponding to the range of 512 LBAs is written into 512 PBAs assigned to the VDM fragment table corresponding to the first layer, the update of VDM42 can be completed by changing one entry included in the VDM fragment table corresponding to the second layer.

[0191] That is, when N = 16 and M = 32, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the (i - 1)-th layer is 1:2. When the continuity of the LBA and PBA is ensured as described above, the update of the LUT41 can be supported by changing 2 entries of the LUT fragment table, and the update of the VDM42 can be supported by changing 1 entry of the VDM fragment table.

[0192] In addition, when N = 16 and M = 32, the above conditional expression is also satisfied when x = 2 and y = 1 / 8. Although detailed explanation is omitted, in this case, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the (i - 2)-th layer is 8:1. When the continuity of the LBA and PBA is ensured as described above, the update of the LUT41 can be supported by changing 1 entry of the LUT fragment table, and the update of the VDM42 can be supported by changing 8 entries of the VDM fragment table.

[0193] FIG. 11 shows the relationship between the PBA management number of the LUT fragment table corresponding to each layer and the PBA management number of the VDM fragment table when N = 64 and M = 32.

[0194] Here, when N = 64 and M = 32, the PBA management number of the LUT fragment table corresponding to the first layer is 64, and the PBA management number of the VDM fragment table corresponding to the first layer is 2,048. Also, the PBA management number of the LUT fragment table corresponding to the second layer is 4,096, and the PBA management number of the VDM fragment table corresponding to the second layer is 131,072.

[0195] Regarding the PBA management number of the LUT fragment table and the PBA management number of the VDM fragment table corresponding to the layers above the second layer, detailed explanation is omitted. However, when N = 64, both the PBA management number of the LUT fragment table and the PBA management number of the VDM fragment table become 64 times when the layer goes up one level.

[0196] Also, when N = 64 and M = 32, the above conditional expression is satisfied when x = 0 and y = 32. Specifically, when focusing on the LUT fragment table corresponding to the first layer where the difference in hierarchy is 0 (i.e., x = 0) and the VDM fragment table corresponding to the first layer, the PBA management number of the LUT fragment table is 64, the PBA management number of the VDM fragment table is 2,048, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 32 (i.e., y = 32).

[0197] If N and M satisfy the above conditional expression, for example, when data corresponding to the range of 2,048 LBAs assigned to 32 LUT fragment tables corresponding to the first layer is written to the non-volatile memory 4, the update of LUT41 can be completed by changing 32 entries included in the LUT fragment table corresponding to the second layer. Similarly, when data corresponding to the range of 2,048 LBAs is written to 2,048 PBAs assigned to the VDM fragment table corresponding to the first layer, the update of VDM42 can be completed by changing 1 entry included in the VDM fragment table corresponding to the second layer.

[0198] That is, when N = 64 and M = 32, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-th layer is 1:32. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 32 entries of the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of the VDM fragment table.

[0199] In the case where N = 64 and M = 32, the above conditional expression is satisfied even when x = 1 and y = 1 / 2. Although detailed explanations are omitted, in this case, the ratio of the number of PBA managements of the LUT fragment table corresponding to the i-th layer to the number of PBA managements of the VDM fragment table corresponding to the (i - 1)-th layer is 2:1. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be corresponded to by changing 1 entry of the LUT fragment table, and the update of VDM42 can be corresponded to by changing 2 entries of the VDM fragment table.

[0200] Figure 12 shows the relationship between the number of PBA managements of the LUT fragment table corresponding to each layer and the number of PBA managements of the VDM fragment table when N = 128 and M = 32.

[0201] Here, when N = 128 and M = 32, the number of PBA managements of the LUT fragment table corresponding to the first layer is 128, and the number of PBA managements of the VDM fragment table corresponding to the first layer is 4,096. Also, the number of PBA managements of the LUT fragment table corresponding to the second layer is 16,384, and the number of PBA managements of the VDM fragment table corresponding to the second layer is 524,288.

[0202] Although detailed explanations are omitted for the number of PBA managements of the LUT fragment table and the number of PBA managements of the VDM fragment table corresponding to layers higher than the second layer, when N = 128, both the number of PBA managements of the LUT fragment table and the number of PBA managements of the VDM fragment table become 128 times when the layer goes up one level.

[0203] Also, when N = 128 and M = 32, the above conditional expression is satisfied when x = 0 and y = 32. Specifically, when focusing on the LUT fragment table corresponding to the first layer where the difference in hierarchy is 0 (i.e., x = 0) and the VDM fragment table corresponding to the first layer, the PBA management number of the LUT fragment table is 128, the PBA management number of the VDM fragment table is 4,096, and "PBA management number of VDM fragment table / PBA management number of LUT fragment table" is 32 (i.e., y = 32).

[0204] If N and M satisfy the above conditional expression, for example, when data corresponding to a range of 4,096 LBAs assigned to 32 LUT fragment tables corresponding to the first layer is written into the non-volatile memory 4, the update of LUT41 can be completed by changing 32 entries included in the LUT fragment table corresponding to the second layer. Similarly, when data corresponding to a range of 4,096 LBAs is written into 4,096 PBAs assigned to the VDM fragment table corresponding to the first layer, the update of VDM42 can be completed by changing 1 entry included in the VDM fragment table corresponding to the second layer.

[0205] That is, when N = 128 and M = 32, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-th layer is 1:32. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing 32 entries of the LUT fragment table, and the update of VDM42 can be handled by changing 1 entry of the VDM fragment table.

[0206] In addition, when N = 128 and M = 32, the above conditional expression is satisfied even when x = 1 and y = 1 / 4. Although detailed explanations are omitted, in this case, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-1-th layer is 4:1. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be supported by changing 1 entry of the LUT fragment table, and the update of VDM42 can be supported by changing 4 entries of the VDM fragment table.

[0207] In the above FIGS. 8 to 12, the description has been made assuming M = 32. Hereinafter, with reference to FIGS. 13 to 17, the case where M = 64 will be described. Since it is the same as FIGS. 8 to 12 described above except that M is changed, FIGS. 13 to 17 will be briefly described as appropriate.

[0208] FIG. 13 shows the relationship between the PBA management number of the LUT fragment table corresponding to each layer and the PBA management number of the VDM fragment table when N = 64 and M = 64.

[0209] When N = 64 and M = 64, the above conditional expression is satisfied when x = 1 and y = 1. That is, when N = 64 and M = 64, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-1-th layer is 1:1. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be supported by changing 1 entry of the LUT fragment table, and the update of VDM42 can be supported by changing 1 entry of the VDM42.

[0210] Note that, as described in FIG. 8 above, even when N = 32 and M = 32, the update of LUT41 can be handled by changing one entry of the LUT fragment table, and the update of VDM42 can be handled by changing one entry of VDM42. That is, in this embodiment, it can be said that more efficient management of LUT41 and VDM42 can be achieved when N = M.

[0211] FIG. 14 shows the relationship between the number of PBA managements of the LUT fragment table corresponding to each layer and the number of PBA managements of the VDM fragment table when N = 8 and M = 64.

[0212] When N = 8 and M = 64, the above conditional expression is satisfied when x = 2 and y = 1. That is, when N = 8 and M = 64, the ratio of the number of PBA managements of the LUT fragment table corresponding to the i-th layer to the number of PBA managements of the VDM fragment table corresponding to the (i - 2)-th layer is 1:1. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be handled by changing one entry of the LUT fragment table, and the update of VDM42 can be handled by changing one entry of VDM42.

[0213] Thus, even when N ≠ M, there may be cases where the update of LUT41 and the update of VDM42 can both be handled with one entry. According to this, for example, it can be said that more efficient management of LUT41 and VDM42 can be achieved even when M = N^x holds.

[0214] FIG. 15 shows the relationship between the number of PBA managements of the LUT fragment table corresponding to each layer and the number of PBA managements of the VDM fragment table when N = 16 and M = 64.

[0215] When N = 16 and M = 32, the above conditional expression is satisfied when x = 1 and y = 4. That is, when N = 16 and M = 64, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i - 1-th layer is 1:4. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be supported by changing 4 entries of the LUT fragment table, and the update of VDM42 can be supported by changing 1 entry of the VDM fragment table.

[0216] In addition, when N = 16 and M = 64, the above conditional expression is also satisfied when x = 2 and y = 1 / 4. In this case, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i - 2-th layer is 4:1. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be supported by changing 1 entry of the LUT fragment table, and the update of VDM42 can be supported by changing 4 entries of the VDM fragment table.

[0217] Figure 16 shows the relationship between the PBA management number of the LUT fragment table corresponding to each layer and the PBA management number of the VDM fragment table when N = 32 and M = 64.

[0218] When N = 32 and M = 64, the above conditional expression is satisfied when x = 1 and y = 2. That is, when N = 32 and M = 64, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i - 1-th layer is 1:2. When the continuity of LBA and PBA is ensured as described above, the update of LUT41 can be supported by changing 2 entries of the LUT fragment table, and the update of VDM42 can be supported by changing 1 entry of the VDM fragment table.

[0219] Incidentally, when N = 32 and M = 64, the above conditional expression is also satisfied when x = 2 and y = 1 / 16. In this case, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-2-th layer is 16:1. When the continuity of the LBA and PBA is ensured as described above, the update of the LUT41 can be corresponded by changing 1 entry of the LUT fragment table, and the update of the VDM42 can be corresponded by changing 16 entries of the VDM fragment table.

[0220] Figure 17 shows the relationship between the PBA management number of the LUT fragment table corresponding to each layer and the PBA management number of the VDM fragment table when N = 128 and M = 64.

[0221] When N = 128 and M = 64, the above conditional expression is satisfied when x = 0 and y = 64. That is, when N = 128 and M = 64, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-th layer is 1:64. When the continuity of the LBA and PBA is ensured as described above, the update of the LUT41 can be corresponded by changing 64 entries of the LUT fragment table, and the update of the VDM42 can be corresponded by changing 1 entry of the VDM fragment table.

[0222] Incidentally, when N = 128 and M = 64, the above conditional expression is also satisfied when x = 1 and y = 1 / 2. In this case, the ratio of the PBA management number of the LUT fragment table corresponding to the i-th layer to the PBA management number of the VDM fragment table corresponding to the i-1-th layer is 2:1. When the continuity of the LBA and PBA is ensured as described above, the update of the LUT41 can be corresponded by changing 1 entry of the LUT fragment table, and the update of the VDM42 can be corresponded by changing 2 entries of the VDM fragment table.

[0223] In this embodiment, the cases where M = 32 and M = 64 have been described. However, the M may be determined so as to correspond to the operation bit width (for example, 32 bits, 64 bits, etc.) in the memory system 3.

[0224] Next, the operation of the memory system 3 according to this embodiment will be described. First, with reference to the flowchart of FIG. 18, an example of the processing procedure of the memory system 3 when a write command is transmitted from the host 2 will be described.

[0225] When a write command is transmitted from the host 2 as described above, the communication interface control unit 51 receives the write command (step S1). The write command received in step S1 includes data (hereinafter referred to as target data) to be written to the nonvolatile memory 4 based on the write command and an LBA (hereinafter referred to as target LBA) for accessing the data. The target data is temporarily stored in the write buffer memory 52.

[0226] Next, the write control unit 561 writes the target data stored in the write buffer memory 52 to the nonvolatile memory 4 via the nonvolatile memory controller 54 (step S2). In the following description, the PBA in the nonvolatile memory 4 where the target data is written in step S2 is referred to as the target PBA for convenience.

[0227] When the process of step S2 is executed, the management unit 565 updates the VDM 42 based on the target PBA by cooperating with, for example, the nonvolatile memory controller 54 and the cache memory control unit 566 (step S3). In this step S3, the VDM 42 is updated so as to manage that the target data is valid (that is, the data written to the target PBA is valid).

[0228] Here, in the present embodiment, the VDM42 has a hierarchical structure and includes a plurality of VDM fragment tables corresponding to each layer. In this case, in step S3, one or more VDM fragment tables to which the target PBA is assigned are specified by referring to the VDM42, and if necessary, the specified VDM fragment table is read from the non-volatile memory 4. The VDM fragment table read from the non-volatile memory 4 in this way is stored in the cache memory 551 and updated on the cache memory 551. When the VDM fragment table specified as described above is already stored in the cache memory 551, it is not necessary to read the VDM fragment table from the non-volatile memory 4.

[0229] Next, among the entries included in the VDM fragment table specified in this way, the entry to which the target PBA is assigned is changed. The VDM fragment table with the entry thus changed is read from the cache memory 551 and written back to the non-volatile memory 4.

[0230] Note that the VDM fragment table whose entry is changed may be the VDM fragment table corresponding to the lowest layer in the hierarchical structure as described above, or may be the VDM fragment table corresponding to a layer higher than that layer.

[0231] Specifically, if the target PBA is a PBA in a relatively narrow range and it is impossible to manage the validity of the target data written to the target PBA without changing the entry included in the VDM fragment table corresponding to the lowest layer, the entry included in the VDM fragment table corresponding to the lowest layer is changed. In this case, among the entries included in the VDM fragment table corresponding to the lowest layer, the flag information (flag information corresponding to the target PBA) that constitutes the bitmap stored in the entry (map storage unit 42a) to which the target PBA is assigned is changed. Also, when the entire range of consecutive PBAs corresponding to the target PBA is the target PBA and is assigned to at least one entry included in the VDM fragment table corresponding to the lowest layer, the magic number (management data MD2) stored in the entry is changed to "0xff".

[0232] On the other hand, if the target PBA is a continuous PBA in a relatively wide range and it is possible to manage the validity of the target data written to the target PBA by changing the entry included in the VDM fragment table corresponding to a layer other than the lowest layer, the entry included in the VDM fragment table corresponding to a layer other than the lowest layer may be changed. In this case, among the entries included in the VDM fragment table corresponding to a layer other than the lowest layer, the magic number (management data MD3) stored in the entry (PBA storage unit 42f) to which the target PBA is assigned is changed to "0xff".

[0233] Note that when the entry included in the VDM fragment table corresponding to a layer other than the lowest layer is changed in this way, since the validity of the target data can be managed only by the VDM fragment table, the VDM fragment table corresponding to a layer lower than the VDM fragment table (that is, the VDM fragment table indicated by the pointer stored in the entry) can be discarded.

[0234] On the other hand, when it is necessary to change an entry included in the VDM fragment table corresponding to the lowest layer and the VDM fragment table does not exist (has been discarded), a VDM fragment table including the entry to which the target PBA is assigned is newly created.

[0235] In step S3, by executing such processing, the VDM42 stored in the non-volatile memory 4 can be updated. Note that the writing back of the VDM42 to the non-volatile memory 4 may be performed at any timing after step S3.

[0236] When the process of step S3 is executed, the management unit 565 updates the LUT41 based on the write command (target LBA) and the target PBA, for example, in cooperation with the non-volatile memory controller 54 and the cache memory control unit 566 (step S4). In this step S4, the LUT41 is updated so as to manage the correspondence between the target LBA and the target PBA (that is, the target LBA can be converted into the target PBA).

[0237] Here, in the present embodiment, the LUT41 has a hierarchical structure and includes a plurality of LUT fragment tables corresponding to each layer. In this case, in step S4, one or a plurality of LUT fragment tables to which the target LBA is assigned are specified by referring to the LUT41, and the specified LUT fragment table is read from the non-volatile memory 4 as necessary. The LUT fragment table read from the non-volatile memory 4 in this way is stored in the cache memory 551 and updated on the cache memory 551. Note that when the LUT fragment table specified as described above is already stored in the cache memory 551, it is not necessary to read the LUT fragment table from the non-volatile memory 4.

[0238] Next, among the entries included in the LUT fragment table thus specified, the entry to which the target LBA is assigned is changed. In this case, the PBA stored in the entry (PBA storage unit 41a) to which the target LBA is assigned is changed to the target PBA. The LUT fragment table with the entry thus changed is read from the cache memory 551 and written back to the non-volatile memory 4.

[0239] Note that the LUT fragment table in which the entry is changed may be the LUT fragment table corresponding to the lowest layer in the hierarchical structure as described above, or may be the LUT fragment table corresponding to a layer higher than that layer.

[0240] Specifically, if the target LBA is an LBA in a relatively narrow range and the correspondence between the target LBA and the target PBA cannot be managed without changing the entry included in the LUT fragment table corresponding to the lowest layer, the entry included in the LUT fragment table corresponding to the lowest layer is changed.

[0241] On the other hand, if the target LBA is, for example, a continuous LBA in a relatively wide range, the target data is written to continuous PBAs, and the correspondence between the target LBA and the target PBA can be managed by changing the entry included in the LUT fragment table corresponding to a layer other than the lowest layer, the entry included in the LUT fragment table corresponding to a layer other than the lowest layer may be changed.

[0242] In step S4, by executing such processing, the LUT41 stored in the non-volatile memory 4 can be updated. Note that the writing back of the LUT41 to the non-volatile memory 4 may be performed at any timing after step S4.

[0243] When the process of step S4 is executed, the management unit 565 transmits a response (completion response) to the write command received in step S1 to the host 2 via the communication interface control unit 51 (step S5).

[0244] Although the case where the LUT 41 and the VDM 42 are updated based on the write command from the host 2 has been described here, the LUT 41 and the VDM 42 also need to be updated in the same way when, for example, a Trim command is transmitted from the host 2.

[0245] Hereinafter, with reference to the flowchart of FIG. 19, an example of the processing procedure of the memory system 3 when a Trim command is transmitted from the host 2 will be described.

[0246] The Trim command is a command for invalidating data corresponding to a predetermined file when the predetermined file is deleted in the file system used by the host 2, for example. The Trim command is also referred to as, for example, an Unmap command or the like according to the interface standard for connecting the storage device. Note that the data written in the non-volatile memory 4 is not erased by the Trim command, and the data is erased by garbage collection.

[0247] When the above-described Trim command is transmitted from the host 2, the communication interface control unit 51 receives the Trim command (step S11). Note that the Trim command received in step S11 includes an LBA (range) for accessing the data to be invalidated. In the following description, the LBA included in the Trim command is referred to as the target LBA.

[0248] When the process of step S11 is executed, the address translation unit 564 refers to the LUT fragment tables included in the LUT 41 in order from the upper layer to convert the target LBA into a PBA (step S12). As a result, the address translation unit 564 obtains the PBA corresponding to the target LBA. In the following description, the PBA obtained by the address translation unit 564 is referred to as the target PBA.

[0249] Next, the management unit 565 updates the VDM 42 so as to manage that the data stored in the target PBA (that is, the data corresponding to the target LBA) is invalid (step S13). Note that the update process of the VDM 42 based on the Trim command is the same as the process shown in step S3 shown in FIG. 18 except for updating the VDM 42 so as to manage that the data is invalid, and thus the detailed description thereof is omitted here.

[0250] In addition, if the target PBA is a relatively wide range of consecutive PBAs and it is possible to manage that the data written in the target PBA is invalid by changing the entry included in the VDM fragment table corresponding to a layer other than the lowermost layer, among the entries included in the VDM fragment table corresponding to a layer other than the lowermost layer, the magic number stored in the entry to which the target PBA is assigned is changed to "0x00".

[0251] Also, when the entire range of consecutive PBAs assigned to at least one entry included in the VDM fragment table corresponding to the lowermost layer is the target PBA, the magic number stored in the entry is changed to "0x00".

[0252] Furthermore, the management unit 565 updates the LUT 41 so as to invalidate the correspondence relationship between the target LBA and the target PBA (the PBA in which the data to be invalidated is stored) (step S14). When invalidating the correspondence relationship between the LBA and the PBA in the LUT 41, for example, a magic number is set in an entry (PBA storage unit 41a) included in the LUT fragment table to which the LBA is assigned. Note that the update process of the LUT 41 based on the Trim command is the same as step S4 shown in FIG. 18 described above except for invalidating the correspondence relationship between the LBA and the PBA, and thus the detailed description thereof is omitted here.

[0253] As described above, when the LUT 41 and the VDM 42 are updated, the management unit 565 transmits a response (completion response) to the Trim command to the host 2 via the communication interface control unit 51 (step S15).

[0254] In the example shown in FIG. 19, it has been described that the completion response is transmitted to the host 2 after the LUT 41 and the VDM 42 are updated. However, for example, the update of the VDM 42 may be configured to be executed (that is, delayed execution) after the transmission of the completion response.

[0255] Here, the above-described VDM 42 is necessary for efficiently executing garbage collection. When the garbage collection is executed, it is necessary to refer to the VDM 42 to confirm whether the data written in each PBA in the non-volatile memory 4 is valid or invalid.

[0256] Hereinafter, with reference to the flowchart of FIG. 20, an example of the processing procedure of the memory system 3 when confirming whether the data written in a specific PBA (hereinafter referred to as the target PBA) in the non-volatile memory 4 is valid or invalid will be described.

[0257] First, in this embodiment, VDM42 has a hierarchical structure composed of a plurality of layers. In the memory 55, a VDM pointer (PBA in which the VDM fragment table is stored) indicating the VDM fragment table corresponding to the topmost layer among the plurality of layers is held. When the VDM fragment table corresponding to the topmost layer is stored in the non-volatile memory 4, the VDM pointer held in the memory 55 is the PBA in the non-volatile memory 4. When the VDM fragment table corresponding to the topmost layer is stored in the cache memory 551, the VDM pointer held in the memory 55 is the address information in the cache memory 551.

[0258] In this case, the management unit 565 reads the VDM fragment table from the non-volatile memory 4 or the cache memory 551 based on the VDM pointer held in the memory 55 (step S21).

[0259] Next, the management unit 565 refers to the magic number (hereinafter referred to as the target magic number) stored in the entry to which the target PBA is assigned among the plurality of entries included in the VDM fragment table (VDM fragment table corresponding to the topmost layer) read in step S1 (step S22).

[0260] When the VDM fragment table read in step S21 is not the VDM fragment table corresponding to the bottommost layer, as the magic number (management data MD3) stored in the entry included in the VDM fragment table, one of the above-mentioned "0xff", "0x00", "0xfc", and "0xfd" is set.

[0261] The management unit 565 determines whether or not the target magic number referred to in this way is "0xff" or "0x00" (step S23).

[0262] When it is determined that the target magic number is not "0xff" and "0x00" (NO in step S23), the management unit 565 determines whether the target magic number is "0xfc" or "0xfd" (step S24).

[0263] When it is determined that the target magic number is "0xfc" or "0xfd" (YES in step S24), the management unit 565 acquires the VDM pointer to which the target magic number is attached (step S25). When step S25 is executed, the process returns to step S21 and is repeated.

[0264] Here, as described above, the magic number "0xfc" indicates that the VDM pointer (PBA) to which the magic number is attached is the PBA in the non-volatile memory 4. Therefore, when the target magic number is "0xfc", in step S21 executed after step S25, based on the VDM pointer acquired in step S24, the VDM fragment table corresponding to the next layer (lower layer) is read from the non-volatile memory 4.

[0265] On the other hand, the magic number "0xfd" indicates that the VDM pointer (PBA) to which the magic number is attached is the address information in the cache memory 551. Therefore, when the target magic number is "0xfd", in step S21 executed after step S25, based on the VDM pointer acquired in step S24, the VDM fragment table corresponding to the next layer (lower layer) is read from the cache memory 551.

[0266] In this embodiment, by repeating the processes of steps S21 to S25 in this way, it becomes possible to sequentially refer to the VDM fragment tables corresponding to each layer.

[0267] On the other hand, assume that in step S23, it is determined that the target magic number is "0xff" or "0x00" (YES in step S23).

[0268] Here, the magic number "0xff" indicates that all the data written in the entire range of the PBA assigned to the entry where the magic number is stored is valid. That is, when the target magic number is "0xff", it can be understood that the data stored in the target PBA is valid, so the process shown in FIG. 20 ends.

[0269] Also, the magic number "0x00" indicates that the data written in the entire range of the PBA assigned to the entry where the magic number is stored is invalid. That is, when the target magic number is "0x00", it can be understood that the data stored in the target PBA is invalid, so the process shown in FIG. 20 ends.

[0270] Also, when it is determined in step S24 that the target magic number is not "0xfc" or "0xfd" (NO in step S24), in the entry to which the target PBA is assigned, the magic numbers "0xff", "0x00", "0xfc", and "0xfd" are not set. In this case, the VDM fragment table read in step S21 is the VDM fragment table corresponding to the lowest layer, and the validity of the data stored in the range of PBAs including the target PBA contained in the VDM fragment table is not common (that is, valid data and invalid data are mixed). In this case, the management unit 565 acquires the bitmap stored in the entry to which the target PBA of the VDM fragment table (the VDM fragment table corresponding to the lowest layer) read in step S21 is assigned (step S26). Based on the flag information indicating the validity of the data stored in the target PBA (that is, the flag information corresponding to the target PBA) among the plurality of flag information constituting the bitmap acquired in step S26 by the management unit 565, it is possible to determine whether the data is valid or invalid.

[0271] As described above, in the present embodiment, the VDM42 (data map) stored in the non-volatile memory � has a hierarchical structure composed of a plurality of layers including at least a first layer (the lowest layer) and a second layer (a layer higher than the lowest layer), and includes a plurality of first VDM fragment tables corresponding to the first layer and a second VDM fragment table corresponding to the second layer. Also, in the present embodiment, each of the plurality of first VDM fragment tables manages the validity of each of the data of a predetermined size (for example, 4 KiB) written in the range of PBAs (physical addresses) in the non-volatile memory � assigned to the first VDM fragment table. Further, in the present embodiment, the second VDM fragment table manages, for each first VDM fragment table, a VDM pointer indicating the first VDM fragment table (reference destination information for referring to the first VDM fragment table).

[0272] Here, as described in the comparative example of the above-described embodiment, when VDM42´ is configured to include only a plurality of VDM fragment tables T421´ corresponding to a single hierarchy, it is necessary to hold in the memory 55 all the pointers (PBAs in which the VDM fragment tables T421´ are stored) indicating each of the plurality of VDM fragment tables T421´. In contrast, in the present embodiment, due to the above-described configuration, it is sufficient that the VDM pointer indicating the VDM fragment table corresponding to the topmost hierarchy is held in the memory 55. Therefore, data that continuously occupies a certain storage area on the memory 55 can be reduced (as close as possible to 0 in terms of the management information of VDM42), and the validity of the data written in the non-volatile memory 4 can be efficiently managed.

[0273] Also, in the present embodiment, by reducing the data (VDM pointer indicating the VDM fragment table) stored in the memory 55 (e.g., DRAM) as described above, it becomes possible to preferentially expand the LUT41 on the memory 55 (cache it in the cache memory 551). Therefore, the response time (I / O response time) to commands from the host 2 can be shortened. When the process for the read command from the host 2 is executed, since it is not necessary to update VDM42, the I / O response time can be further shortened. Also, when the process for the above-described Trim command is executed, the process of updating VDM42 may be delayed. However, in such a configuration, the storage areas (i.e., memory ratios) assigned to the LUT41 and VDM42 may be dynamically changed.

[0274] Furthermore, in the comparative example of the present embodiment, as described above, the internal processes (start-up process and termination process) when starting up and terminating the memory system 3 take time. However, in the present embodiment, at the start-up process, the VDM pointer indicating the VDM fragment table corresponding to the topmost hierarchy is expanded in the memory 55, and at the termination process, the VDM pointer only needs to be made non-volatile. Therefore, the time required for the internal processes can be shortened.

[0275] Also, in the present embodiment, when the validity of each piece of data of a predetermined size written in the range of the PBA assigned to the first VDM fragment table in the second VDM fragment table is not common (that is, valid data and invalid data are mixed as the data written in the range of the PBA), a VDM pointer indicating the first VDM fragment table corresponding to the lower layer is managed. Further, when the validity of each piece of data of a predetermined size written in the range of the PBA assigned to the first VDM fragment table in the second VDM fragment table is common (that is, all of the data of a predetermined size written in the range of the PBA are valid or invalid), the validity of the data is managed collectively.

[0276] In the present embodiment, with such a configuration, for example, when updating the validity of data written in a wide and continuous range of PBAs, the VDM42 can be updated only by changing the entry (magic number) included in the second VDM fragment table, so that the process for managing the validity of data can be simplified. Specifically, for example, in the case of the memory system 3 (non-volatile memory 4) that can store several PiB of data, for example, by changing only the magic number (8 bits) stored in one entry included in the VDM fragment table corresponding to the topmost layer, the ranges of several G PBAs can be collectively operated (updated).

[0277] That is, in the present embodiment, for example, bit operations such as individually updating the bitmap included in the first VDM fragment table are suppressed, and the processing cost can be reduced.

[0278] Furthermore, in the present embodiment, since the range (granularity) of the PBA assigned to the VDM fragment table varies according to the layer, the VDM42 can be updated flexibly.

[0279] Also, for example, in the second VDM fragment table, when collectively managing the validity of each piece of data of a predetermined size written in the range of the PBA assigned to the first VDM fragment table, the first VDM fragment table can be discarded, and the storage area where the first VDM fragment table was stored can be released. According to this, in the present embodiment, it is possible to reduce the storage area required to store the VDM42.

[0280] Furthermore, in the present embodiment, the first VDM fragment table corresponding to the first layer and the second VDM fragment table corresponding to the second layer have the same data structure. Specifically, the first VDM fragment table manages the validity of data of a plurality of predetermined sizes (4 KiB) in each of a predetermined number (for example, 32) of entries. Also, the second VDM fragment table manages VDM pointers indicating each of the first VDM fragment data in each of a predetermined number (for example, 32) of entries.

[0281] In the present embodiment, with such a configuration, the hierarchical structure of the VDM42 becomes simple, and the calculation cost when referring to the VDM42 (each VDM fragment table) can be reduced. Also, for example, when referring to the VDM fragment table to which the target PBA is assigned, it is necessary to traverse a plurality of layers, but the processing in such a case can be made uniform regardless of the layer (that is, the same software code can be used), so that the VDM42 can be efficiently referred to.

[0282] Note that the VDM42 in the present embodiment only needs to have a hierarchical structure including at least the first and second layers, but the number of layers constituting the hierarchical structure of the VDM42 may be 3 or more. The number of layers constituting the hierarchical structure of the VDM42 may be appropriately changed based on, for example, the storage capacity (number of PBAs) of the non-volatile memory 4.

[0283] Furthermore, in the present embodiment, similar to VDM42, the LUT41 (address translation table) also has a hierarchical structure, and each of the plurality of LUT fragment tables included in LUT41 has the same data structure as the VDM fragment table included in VDM42.

[0284] According to such a configuration, even when traversing a plurality of hierarchies to refer to LUT41, software code similar to that of VDM42 can be used, so that efficient processing can be realized. Also, for example, the LUT41 (LUT fragment table) and VDM42 (VDM fragment table) updated on the cache memory 551 need to be written back to the non-volatile memory 4 (that is, made non-volatile). However, since the LUT fragment table and the VDM fragment table are configured to have the same size, it is possible to make them non-volatile in a batch without distinguishing between the LUT fragment table and the VDM fragment table. According to this, the writing efficiency of the LUT fragment table and the VDM fragment table to the non-volatile memory 4 is improved, and the non-volatilization cost can be reduced.

[0285] Note that in the present embodiment, since the number of PBA managements of the LUT fragment table corresponding to the lowest hierarchy is smaller than the number of PBA managements of the VDM fragment table corresponding to that hierarchy, the number of hierarchies (the first number) constituting the hierarchical structure of VDM42 is smaller than the number of hierarchies (the second number) constituting the hierarchical structure of LUT41.

[0286] Also, in the present embodiment, the number of entries N of the VDM fragment table and the number M of data of a predetermined size (that is, the PBA managed in that entry) whose validity is managed in one entry of the VDM fragment table corresponding to the lowest hierarchy are determined so as to satisfy the above conditional expression (M = y × N^x), and the LUT fragment table and the VDM fragment table are configured to have the same data structure.

[0287] In this embodiment, with such a configuration, the LUT41 can be updated only by changing the entry (PBA) included in the LUT fragment table corresponding to the upper layer, and the VDM42 can be updated only by changing the entry (magic number) included in the VDM fragment table without changing the bitmap (performing bit operations). Therefore, in this embodiment, it is possible to achieve both efficient management of the correspondence between the LBA and PBA in the LUT41 and efficient management of the data validity in the VDM42.

[0288] In order to achieve more efficient management in the LUT41 and VDM42, N and M that satisfy the conditional expression M = N^x (that is, M is a power of N), such as N = 8 and M = 64 described in FIG. 14 above, may be adopted, or N and M that satisfy the conditional expression M = N (that is, M is equal to N), such as N = 32 and M = 32 described in FIG. 8 and N = 64 and M = 64 described in FIG. 13, may be adopted. Also, N and M (values) may be configured to be appropriately set or changed by an administrator of the memory system 3 or the like.

[0289] Here, for example, the pointer size in the C language is the same as the operation bit width. In this case, if, for example, M is smaller than the operation bit width, a pointer (address information in the cache memory 551) cannot be stored in the entry of the fragment table as it is. In contrast, although it is conceivable to store the pointer after splitting it, the processing cost is high.

[0290] On the other hand, if M is larger than the operation bit width, it is possible to store the pointer in the entry of the fragment table as it is, but since there are unused bits, it is not efficient (the cache is wasted). Furthermore, in this case, since the size of the fragment table increases, the non-volatile cost increases. In contrast, for example, it is conceivable to execute a process of excluding unnecessary parts before making the fragment table non-volatile, but the processing cost is high.

[0291] Therefore, in the present embodiment, M may be determined so as to correspond to (e.g., match) the operation bit width (32 bits or 64 bits) in the memory system 3. According to such a configuration, since a pointer (address information in the cache memory 551) having the same operation bit width and size can be stored in an entry of the fragment table without being processed, the LUT 41 and the VDM 42 can be efficiently managed. Further, according to such a configuration, there is no need to unnecessarily increase the size of the fragment table.

[0292] Note that, in the present embodiment, the controller 5 included in the memory system 3 has been described as functioning as a flash translation layer (FTL) configured to execute data management and block management of the nonvolatile memory 4 (NAND type flash memory). However, the function as the FTL may be provided on the host 2 side connected to the memory system 3. In such a case, the LUT 41 and the VDM 42 described in the present embodiment are managed by the host 2, and the update process and the like of the LUT 41 and the VDM 42 are executed on the host 2 side. Further, in such a case, the address conversion from the LBA to the PBA may also be executed on the host 2 side, and in this case, the command from the host 2 (e.g., read command) may include the PBA.

[0293] Subsequently, control performed by the VDM 42 having the above-described configuration, that is, the memory system 3 of the present embodiment having the data map, to reduce the processing cost of the data map will be described.

[0294] As described above, the memory cell array of the nonvolatile memory 4 includes a plurality of blocks, and each of the blocks is composed of a number of pages. In the memory system 3 (SSD), each of the blocks functions as a data erasure unit. Also, each of the pages is a unit of data write operation and data read operation. The size of the block is an integer multiple of the size of the data (here, 4 kiB × 32 × 32 = 4 MiB) that the management data MD3 of the second VDM fragment table T422 can manage collectively.

[0295] Here, regarding the manner in which each of the plurality of blocks is cyclically used, first, with reference to FIG. 21, a general manner will be described as a comparative example. Here, the configuration of the memory system 3 (write control unit 561, garbage collection control unit 563) of the present embodiment will be used to describe the comparative example.

[0296] The plurality of blocks are roughly classified into blocks belonging to the free block group a1 (free block a11) and blocks belonging to the allocated block group a2 (writing block a21, written block a22).

[0297] The free block a11 is a block in which data writing has not been performed. The write control unit 561 receives the supply of the free block a11 and writes the write data in which the write command from the host 2 requests writing to the nonvolatile memory 4. When the write data is written, the block migrates from the free block a11 to the writing block a21. That is, the writing block a21 is the block to which the write control unit 561 is setting as the data write destination.

[0298] While there are empty pages in the writing block a21, the write control unit 561 executes writing of write data to the writing block a21. When write data is written to all pages in the writing block a21, that block migrates from the writing block a21 to the written block a22. That is, the written block a22 is a block in which data writing by the write control unit 561 has been completed. When the write control unit 561 completes writing data to a certain writing block 21, it newly receives a supply of free block a11 and executes writing of write data.

[0299] As the above process progresses, the number of free blocks a11 decreases while the number of written blocks a22 increases. Also, in an SSD where data overwriting cannot be performed, data update is executed by invalidating the pre-update data stored in a certain page and writing the post-update data to another page. Therefore, in a certain written block a22, a situation may occur where invalid data occupies the majority.

[0300] The garbage collection control unit 563 moves the valid data in N written blocks a22 with a large amount of invalid data to M (M < N) blocks to create N - M free blocks a11. That is, through the garbage collection (GC) of the garbage collection control unit 563, some of the written blocks a22 migrate to free blocks a11.

[0301] In this way, each of the plurality of blocks is cyclically used as free block a11 → writing block a21 → written block a22 → free block a11.

[0302] Here, referring to FIG. 22, check the flag information of the data map (VDM42) and the size of the data that manages the validity of various management data (MD2, MD3) included in the memory system 3 of the present embodiment. In FIG. 22, reference sign b1 indicates the size of the data that manages the validity of the flag information of the first VDM fragment table T421. The flag information represents the validity of the data written in one PBA (here, 4 kiB) with 1 bit.

[0303] As described above, the first VDM fragment table T421 has, for example, 32 entries. Each entry includes, for example, 32 pieces of flag information. The 32 pieces of flag information in each entry form a 32-bit bitmap in which each bit indicates the validity of 4 kiB of data for the data written in 32 PBAs (4 kiB × 32 = 128 kiB of data).

[0304] Reference sign b2 indicates the size of the data that manages the validity of the management data MD2 of the first VDM fragment table T421. The management data MD2 is provided for each entry of the first VDM fragment table T421. The management data MD2 can be set with a magic number that collectively represents the validity of 128 kiB of data indicated by a 32-bit bitmap formed by 32 pieces of flag information. That is, the management data MD2 can collectively represent the validity of 128 kiB of data.

[0305] Reference sign b3 indicates the size of the data that manages the validity of the management data MD3 of the second VDM fragment table T422. The management data MD3 is provided one by one for each first VDM fragment table T421. The management data MD3 can be set with a magic number that collectively represents the validity of 128 kiB × 32 = 4 MiB of data indicated by 32 pieces of management data MD2 of the first VDM fragment table T421 (the validity of the data written in 1024 PBAs indicated by 32 × 32 = 1024 pieces of flag information). That is, the management data MD3 can collectively represent the validity of 4 MiB of data.

[0306] In the memory system 3 of the present embodiment having a data map (VDM42) including the flag information and management data (MD2, MD3), when all of the data written to one block is, for example, an integer multiple of the size of data (128 kiB) for which the management data MD2 can manage validity collectively, the operation (bit operation) of the flag information becomes unnecessary. Further, for example, when it is an integer multiple of the size of data (4 MiB) for which the management data MD3 can manage validity collectively, the operation of the management data MD2 also becomes unnecessary.

[0307] In other words, for data having a size smaller than the size of data (128 kiB) for which the management data MD2 can manage validity collectively, or data having an integer multiple of the size + a size less than the size (data including a fraction less than the size), the operation of the flag information is required. Therefore, the write data of the host 2 is preferably aligned to an integer multiple of the size of data (128 kiB) for which the management data MD2 can manage validity collectively, or further, to an integer multiple of the size of data (4 MiB) for which the management data MD3 can manage validity collectively.

[0308] However, the host 2 frequently generates data accesses to the memory system 3 in extremely small sizes, for example, less than 4 kiB, with respect to, for example, the file system used by the operating system (OS) to manage files, directories, etc. Further, the host 2 can vary the unit of data access to the memory system 3 according to the processing of an application program operating under the control of the OS.

[0309] Suppose that the write control unit 561 receives the supply of the free block a11 and first writes data having a size smaller than the size of the data (128 kiB) that the management data MD2 can manage the validity in a batch. In this case, next, even if data that is an integral multiple of the size of the data (128 kiB) that the management data MD2 can manage the validity in a batch is sent as write data, for the write data written to the writing-in progress block a21 (transferred from the above free block a11) following the previous data, hereinafter, for a part thereof (the fractional parts at the front and back), operation of flag information becomes necessary.

[0310] Based on this point, next, with reference to FIG. 23, an example of a usage mode of a block in the memory system 3 of the present embodiment will be described.

[0311] Also in the memory system 3 of the present embodiment, the write control unit 561 writes write data to the free block a11. The difference from the above comparative example is that the write control unit 561 in the present embodiment secures a plurality of types of writing-in progress blocks a21 as write destinations of data according to the size of the write data (for example, the first block a21-1, the second block a21-2, the third block a21-3). More specifically, the write control unit 561 controls the writing of data so that data having a size smaller than the size of the data (128 kiB) that the management data MD2 can manage the validity in a batch or data having a size that is an integral multiple of the size + a size less than the size and data having a size that is an integral multiple of the size (data including a fraction less than the size) do not coexist in one block. In other words, the write control unit 561 aggregates data that requires operation of flag information into the same type of block.

[0312] Note that, as described in the above comparative example, each of the plurality of blocks is cyclically used as free block a11 → writing block a21 → written block a22 → free block a11. Therefore, for example, when the block used for writing as the first block a21-1 shifts to the written block a22 → free block a11, next time, not only the first block a21-1, but also any of the first block a21-1, the second block a21-2, or the third block a21-3 can be supplied to the write control unit 561. That is, each block is not pre-associated with any of the first block a21-1, the second block a21-2, or the third block a21-3.

[0313] Alternatively, each block may have a number of pages that make up the block determined each time the block transitions from a state belonging to the free block group a1 to a state belonging to the allocated block group a2. That is, recombination of a number of pages that make up each of the plurality of blocks may be appropriately performed.

[0314] FIG. 24 is a diagram for explaining an example of selection of a write destination block by the write control unit 561 in the present embodiment.

[0315] First, the write control unit 561 determines whether the size of the write data of host 2 is an integer multiple of the size (128 kiB) of the data that the management data MD2 can manage in a lump. If it is not an integer multiple of 128 kiB, the write control unit 561 selects the second block a21-2 as the write destination of the write data at this time. That is, the second block a21-2 is a block that aggregates data that requires operation of flag information.

[0316] If it is an integer multiple of 128 kiB, the write control unit 561 then determines whether the size of the write data of host 2 is an integer multiple of the size of the data (4 MiB) for which the management data MD3 can manage validity collectively. Here, it is assumed that the data map (VDM42) has a hierarchical structure including a first VDM fragment table T421 (the first layer [the lowest layer]) and a second VDM fragment table T422 (the second layer [the upper layer of the first layer]). However, for example, when there is no hierarchical structure such as only the first VDM fragment table T421, when the write control unit 561 determines that the size of the write data of host 2 is an integer multiple of 128 kiB, the first block a21-1 may be selected as the write destination of the write data.

[0317] If it is not an integer multiple of 4 MiB, the write control unit 561 selects the first block a21-1 as the write destination of the write data. The first block a21-1 is a block for data that does not require operation of flag information but requires operation of management data MD2. On the other hand, if it is an integer multiple of 4 MiB, the write control unit 561 selects the third block a21-3 as the write destination of the write data. The third block a21-3 is a block for data that does not require operation of flag information and management data MD2 and only requires operation of management data MD3.

[0318] When the write control unit 561 is writing data to, for example, the first block a21-1, even if there is space in the second block a21-2 or the third block a21-3 when the block is full, these are not selected as the write destination of the data. Instead, it receives a supply of a new free block a11 to make it the first block a21-1 and executes the writing of the remaining data.

[0319] In this way, in the memory system 3 of the present embodiment, by switching the write destination block according to the size of the write data of host 2, for the first block a21-1 and the third block a21-3 other than the second block a21-2, it is possible to eliminate the need for flag information operations (bit operations) during data writing and data update (when invalidating pre-update data). For the third block a21-3, it is further possible to eliminate the need for operations on the management data MD2.

[0320] Also, in garbage collection (GC), for the block that has migrated from the first block a21-1, which is one of the writing blocks a21, to the written block a22, when moving the valid data within the block, it is not necessary to refer to the flag information (bit scan). For the block that has migrated from the third block a21-3 to the written block a22, it is further not necessary to refer to the management data MD2. For both the source block and the destination block of the movement, flag information operations are not required, and only operations on the management data MD2 and management data MD3, or only management data MD3, are sufficient.

[0321] Furthermore, in garbage collection (GC), when a block that has migrated from the first block a21-1 or the third block a21-3 to the written block a22 is selected as a target, an effect of reducing overhead can also be expected. For example, when the page size is 16 kiB and only 4 kiB out of 16 kiB is valid, 12 kiB of unnecessary reading occurs, such as "reading 16 kiB and writing 4 kiB". Since only large data in units of 128 kiB or 4 MiB can exist in the block that has migrated from the first block a21-1 or the third block a21-3 to the written block a22, such waste does not occur. Moreover, reading of valid data and writing of the valid data to the destination can be executed in a combined size of multiple pages.

[0322] Also, when the data map (VDM42) has a hierarchical structure, by switching the write destination block according to the size of the write data, the address continuity is maintained. For example, the compression rate of table compression can be increased, and the memory capacity secured on the memory 55 for the data map can also be reduced. The amount of reduction in this memory capacity can be used to improve the performance of the memory system 3, or alternatively, the capacity of the memory 55 itself can be reduced.

[0323] FIG. 25 is a flowchart showing an example of a procedure for selecting a write destination block according to the data size, which is included in the data write operation of the memory system 3 according to the present embodiment described with reference to FIG. 18. This procedure is a procedure executed by the write control unit 561 in step S2 of FIG. 18.

[0324] The write control unit 561 determines whether the size of the data is a multiple of 128 kiB (which can manage the validity of the management data MD2 collectively) (step S31). If it is not a multiple of 128 kiB (NO in step S31), the write control unit 561 selects the second block a21-2 as the write destination of the data (step S32).

[0325] If it is a multiple of 128 kiB (YES in step S31), the write control unit 561 then determines whether the size of the data is a multiple of 4 MiB (which can manage the validity of the management data MD3 collectively) (step S33). If it is a multiple of 4 MiB (YES in step S33), the write control unit 561 selects the third block a21-3 as the write destination of the data (step S34). On the other hand, if it is not a multiple of 4 MiB (NO in step S33), the write control unit 561 selects the first block a21-1 as the write destination of the data (step S35).

[0326] As described above, the memory system 3 of the present embodiment can reduce the processing cost of the data map (VDM42) by switching the write destination block according to the data size.

[0327] Note that, as described above, host 2 may have the function as FTL, and LUT 41 and VDM 42 may be managed by host 2, and the update process and the like of the LUT 41 and VDM 42 may be executed on the host 2 side. In this case, the selection of the write destination block for reducing the processing cost of the data map may be executed on the host 2 side. Further, in this case, M, which is the number of data (PBA in which the data is stored) whose validity is managed in one entry included in the first VDM fragment table T421 corresponding to the lowest layer, may be determined so as to correspond to the arithmetic bit width in host 2.

[0328] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0329] 1... Information processing system, 2... Host, 3... Memory system, 4... Non-volatile memory, 5... Controller, 41... LUT (Address translation table), 41a... PBA storage (entry), 41b... LBA storage section, 41c... Management data storage section, 41d... Previous pointer storage section, 41e... Next pointer storage section, 42... VDM (Data map), 42a... Map storage section, 42b... PBA storage section, 42c... Management data storage section, 42d... Previous pointer storage section, 42e... Next pointer storage section, 42f... PBA storage section, 51... Communication interface control section, 52... Write buffer memory, 53... Read buffer memory, 54... Non-volatile memory controller, 55... Memory, 56... Processor, 551... Cache memory, 561... Write control section, 562... Read control section, 563... Garbage collection control section, 564... Address translation section, 565... Management section, 566... Cache memory control section.

Claims

1. In a memory system connectable to a host, a non-volatile memory including a plurality of blocks including at least a first block and a second block; a controller that controls writing of data to the non-volatile memory or reading of data from the non-volatile memory in response to a command from the host; comprising: the controller manages the validity of data written in the non-volatile memory using a data map; the data map includes a plurality of first fragment tables; each of the plurality of first fragment tables holds first information indicating the validity of each of data of a predetermined size written in a range of physical addresses in the non-volatile memory assigned to the first fragment table, and second information indicating the validity of a plurality of data of a predetermined size in each of a predetermined number of entries; when the size of write data for which the write command from the host requests writing to the non-volatile memory is an integer multiple of the total amount of data whose validity is indicated by the second information, the controller selects the first block as the destination block for writing, and when it is not an integer multiple, the controller selects the second block as the destination block for writing; the controller selects the destination block so that the write data whose size is an integer multiple of the total amount of data whose validity is indicated by the second information and the write data whose size is not an integer multiple of the total amount of data whose validity is indicated by the second information are not mixed in any of the plurality of blocks; A memory system.

2. In each of the predetermined number of entries of each of the plurality of first fragment tables, a bitmap is formed by arranging the first information indicating the validity of each of the plurality of data of a predetermined size whose validity is indicated by the second information, the size of the bitmap corresponds to the arithmetic bit width in the controller; The memory system according to claim 1.

3. the data map has a hierarchical structure including at least a first layer corresponding to the plurality of first fragment tables and a second layer higher than the first layer, and further includes a second fragment table corresponding to the second layer; The second fragment table holds, for each of the first fragment tables, third information for referring to the first fragment table, and fourth information collectively indicating the validity of data of the predetermined size written in the range of physical addresses assigned to the first fragment table when the validity of each of the data of the predetermined size is common, When the size of the write data is an integer multiple of the total amount of data whose validity is collectively indicated by the fourth information, the controller selects the third block as the write destination block. The memory system according to claim 1 or 2.

4. In an information processing system including a host and a memory system communicably connected to the host, the memory system has a non-volatile memory including a plurality of blocks including at least a first block and a second block, the host manages the validity of data written in the non-volatile memory using a data map, the data map includes a plurality of first fragment tables, each of the plurality of first fragment tables holds first information indicating the validity of each of the data of a predetermined size written in the range of physical addresses in the non-volatile memory assigned to the first fragment table, and second information indicating the validity of a plurality of data of a predetermined size in each of a predetermined number of entries, when the size of write data for which the host requests writing to the non-volatile memory to the memory system is an integer multiple of the total amount of data whose validity is indicated by the second information, the host selects the first block as the write destination block, and when it is not an integer multiple, the host selects the second block as the write destination block, the host selects the write destination block so that the write data whose size is an integer multiple of the total amount of data whose validity is indicated by the second information and the write data whose size is not an integer multiple of the total amount of data whose validity is indicated by the second information are not mixed in any of the plurality of blocks. Information processing system.

5. In each of the predetermined number of entries of each of the plurality of first fragment tables, a bitmap is formed by arranging the first information indicating the validity of each of the plurality of data of the predetermined size whose validity is indicated by the second information. The size of the bitmap corresponds to the arithmetic bit width in the host. The information processing system according to claim 4. **Claim 6** The data map has a hierarchical structure including at least a first layer corresponding to the plurality of first fragment tables and a second layer higher than the first layer, and further includes a second fragment table corresponding to the second layer. For each of the first fragment tables, the second fragment table holds third information for referring to the first fragment table and fourth information collectively indicating the validity of the data of the predetermined size written in the range of the physical address assigned to the first fragment table when the validity of each of the data of the predetermined size is common. When the size of the write data is an integral multiple of the total amount of data whose validity is collectively indicated by the fourth information, the host selects a third block as the write destination block. The information processing system according to claim 4 or 5.

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