Memory system

Abstract

To realize a memory system capable of handling abnormal power outages.SOLUTION: A controller for a memory system specifies, in response to power recovery for the memory system, a third storage position which is included in a plurality of storage positions included in a block and at which second-stage program operation has been last executed. The controller stores data whose fourth storage position, where first-stage program operation has been executed before the second-stage program operation for the third storage position, cannot be read, and determines whether or not first condition has been satisfied which specifies that the plurality of memory cells included in the fifth storage position at which the first-stage program operation should be executed immediately after the first-storage operation performed on the fourth storage position has a threshold voltage corresponding to an erasure state.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] Embodiments of the present invention relate to a technique for controlling a non-volatile memory.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories have become widely popular. Memory systems are used as storage for various computing devices such as computers, mobile devices, and in-vehicle devices.

[0003] For example, in a memory system mounted on a mobile device of a type with a removable battery, when the battery is removed from the mobile device, the power supply to the memory system is suddenly cut off without warning to the memory system.

[0004] Therefore, countermeasures against abnormal power-off, in which the power supply to the memory system is suddenly cut off, are required.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] One problem to be solved by an embodiment of the present invention is to provide a memory system capable of coping with abnormal power-off.

Means for Solving the Problems

[0007] According to an embodiment, a memory system includes a non-volatile memory including a plurality of blocks each of which is a unit of a data erasure operation, each of the plurality of blocks includes a plurality of storage locations, and each of the plurality of storage locations includes a plurality of memory cells, and a controller electrically connected to the non-volatile memory. The controller is configured to execute a data writing operation on a write destination block among the plurality of blocks using a multi-stage programming operation including at least a first-stage programming operation and a second-stage programming operation. The writing of data to the write destination block is performed in such an order that the first-stage programming operation for a first storage location of the write destination block is executed, after the first-stage programming operation for the first storage location is completed, the first-stage programming operation for a second storage location of the write destination block is executed, and in response to completion of the first-stage programming operation for the second storage location, the second-stage programming operation for the first storage location is executed. After power supply to the memory system is cut off, the controller identifies a third storage location among the plurality of storage locations included in a first block among the plurality of blocks in response to the power to the memory system being restored, where the second-stage programming operation was last executed. The controller stores data that cannot be read in a fourth storage location where the first-stage programming operation was executed before the second-stage programming operation for the third storage location, and determines whether a first condition that each of the plurality of memory cells included in a fifth storage location where the first-stage programming operation should be executed next after the first-stage programming operation for the fourth storage location has a threshold voltage corresponding to an erased state is satisfied. If the first condition is satisfied, the controller determines the fifth storage location as the next write destination location.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a configuration example of an information processing system 1 including a memory system 3 according to the first embodiment. The memory system 3 according to the first embodiment is a storage device including a non-volatile memory.

[0010] The information processing system 1 includes a host (host device) 2 and a memory system 3. The host 2 and the memory system 3 can be connected via a bus 4.

[0011] Host 2 is an information processing device. Host 2 is, for example, a personal computer, a server computer, a mobile device, or an in-vehicle device. Host 2 accesses the memory system 3. Specifically, Host 2 sends a write command, which is a command for writing data, to the memory system 3. Also, Host 2 sends a read command, which is a command for reading data, to the memory system 3.

[0012] The memory system 3 is a semiconductor storage device. The memory system 3 is, for example, a solid state drive (SSD) or a Universal Flash Storage (UFS) device. The memory system 3 includes non-volatile memory. The memory system 3 writes data to the non-volatile memory. And the memory system 3 reads data from the non-volatile memory.

[0013] Bus 4 is, for example, PCI Express TM (PCIe TM ) standard, or a bus compliant with the Mobile Industry Processor Interface TM (MIPI TM ) standard. Bus 4 is a transmission path that connects Host 2 and the memory system 3. Bus 4 is used for transmitting data and input / output (I / O) commands from Host 2 to the memory system 3, and for transmitting data and responses from the memory system 3 to Host 2. The I / O command is a command for writing or reading data to / from the non-volatile memory. The I / O command includes a write command and a read command.

[0014] Next, the internal configuration of Host 2 will be described. Host 2 includes a processor 21 and a memory 22.

[0015] The processor 21 is, for example, a central processing unit (CPU). The processor 21 communicates with the memory system 3 via the bus 4. The processor 21 executes software (host software) loaded into the memory 22 from the memory system 3 or other storage devices connected to the host 2. The host software includes an operating system, a file system, a device driver, or an application program.

[0016] The memory 22 is, for example, a volatile memory. The memory 22 is, for example, a dynamic random access memory (DRAM).

[0017] Next, the internal configuration of the memory system 3 will be described. The memory system 3 includes a controller 5 and a non-volatile memory 6. An example of the non-volatile memory 6 is a NAND type flash memory. Hereinafter, the non-volatile memory 6 will be referred to as the NAND memory 6.

[0018] The controller 5 is a memory controller. The controller 5 is, for example, a semiconductor device such as a system-on-a-chip (SoC). The controller 5 is electrically connected to the NAND memory 6. The controller 5 executes writing and reading of data to and from the NAND memory 6. Also, the controller 5 executes communication with the host 2 via the bus 4. As a physical interface connecting the controller 5 and the NAND memory 6, for example, a Toggle NAND flash interface or an Open NAND Flash Interface (ONFI) is used. The functions of each part of the controller 5 can be realized by dedicated hardware, a processor that executes a program, or a combination thereof.

[0019] The NAND memory 6 is, for example, a two-dimensional structure flash memory or a three-dimensional structure flash memory. The NAND memory 6 includes a plurality of blocks. Each block is the minimum unit for erasing data stored in the NAND memory 6, that is, the unit of the data erasing operation.

[0020] The memory system 3 may include a dynamic random access memory (DRAM) 7. The DRAM 7 is a volatile memory. A part of the storage area of the DRAM 7 temporarily holds, for example, write data received from the host 2 or read data read from the NAND memory 6. That is, the DRAM 7 may be used as a write buffer or a read buffer.

[0021] The memory system 3 further includes a power supply circuit 8. The power supply circuit 8 is a power supply control circuit. The power supply circuit 8 supplies power supplied from the host 2, for example, to each component of the memory system 3.

[0022] Next, the internal configuration of the controller 5 will be described. The controller 5 includes a host interface (host I / F) 51, a CPU 52, a static RAM (SRAM) 53, a direct memory access controller (DMAC) 54, an ECC (Error Checking and Correction) circuit 55, a DRAM interface (DRAM I / F) 56, and a NAND interface (NAND I / F) 57. These components are interconnected via an internal bus 50.

[0023] The host interface 51 is a hardware interface circuit. The host interface 51 executes communication with the host 2. The host interface 51 receives, for example, an I / O command from the host 2.

[0024] The CPU 52 is a processor. The CPU 52 controls a host interface 51, an SRAM 53, a DMAC 54, an ECC circuit 55, a DRAM interface 56, and a NAND interface 57. The CPU 52 loads a control program (firmware) stored in the NAND memory 6 or a ROM (not shown) into the SRAM 53 and performs various processes by executing this firmware. Note that the firmware may be loaded into the DRAM 7.

[0025] The CPU 52 executes, for example, as a flash translation layer (FTL), management of data stored in the NAND memory 6 and management of blocks included in the NAND memory 6. Management of data stored in the NAND memory 6 includes, for example, management of mapping information indicating the correspondence between each logical address and each physical address. The logical address is an address used by the host 2 to access the NAND memory 6. The logical address is, for example, an LBA (logical block address). The physical address is an address indicating the position of a physical storage element included in the NAND memory 6. The CPU 52 manages the mapping between each logical address and each physical address using a logical-to-physical translation table (L2P table) 71. Also, management of blocks included in the NAND memory 6 includes, for example, garbage collection, management of bad blocks, and wear leveling.

[0026] The SRAM 53 is a volatile memory. The SRAM 53 is used, for example, as a working area for the CPU 52. Also, a part of the storage area of the SRAM 53 may be used as a write buffer or a read buffer.

[0027] The DMAC 54 is a circuit that executes direct memory access (DMA). The DMAC 54 executes data transfer between the memory 22 of the host 2 and the DRAM 7 or the SRAM 53.

[0028] The ECC circuit 55 is a circuit that performs data encoding and decoding. When writing data to the NAND memory 6, the ECC circuit 55 executes an encoding process. In the encoding process, the ECC circuit 55 adds ECC parity as redundant code to the data to be written. The ECC circuit 55 executes a decoding process using the ECC parity added to the data read from the NAND memory 6. In the decoding process, the ECC circuit 55 corrects errors in the read data. When the ECC circuit 55 successfully corrects an error in the data read from the NAND memory 6, that is, when the error in the read data can be corrected, the ECC circuit 55 notifies the CPU 52 of the ECC pass. When the ECC circuit 55 fails to correct an error in the data read from the NAND memory 6, that is, when the error in the read data cannot be corrected, the ECC circuit 55 notifies the CPU 52 of an ECC error.

[0029] The DRAM interface 56 is a circuit that controls the DRAM 7. The DRAM interface 56 stores data in the DRAM 7 and reads out the data stored in the DRAM 7.

[0030] The NAND interface 57 is a circuit that controls the NAND memory 6. The NAND interface 57 includes, for example, NAND controllers 571-0, 571-1, 571-2, …, 571-31. Each of the NAND controllers 571-0, 571-1, 571-2, …, 571-31 is connected to one or more flash dies included in the NAND memory 6 via a corresponding one of one or more channels (ch) 0, 1, 2, …, 31. A flash die is also referred to as a flash chip. The NAND controllers 571-0, 571-1, 571-2, …, 571-31 control, for example, flash die (#0) 61-0, flash die (#1) 61-1, …, flash die (#31) 61-31 included in the NAND memory 6, respectively.

[0031] Next, the information stored in the DRAM 7 will be described. The information stored in the DRAM 7 includes an L2P table 71, a block management table 72, a free block list 73, a single-level cell (SLC) active block list 74, and a quad-level cell (QLC) active block list 75. Part or all of the L2P table 71, the block management table 72, the free block list 73, the SLC active block list 74, and the QLC active block list 75 may be stored in the SRAM 53 instead of the DRAM 7.

[0032] The L2P table 71 manages the mapping between each logical address and each physical address in units of a predetermined size such as a sector.

[0033] The block management table 72 manages each block included in the NAND memory 6. The block management table 72 manages, for example, whether each block is available or not.

[0034] The free block list 73 manages each block of the NAND memory 6 that does not store valid data as a free block. The data stored in each block is roughly classified into valid data and invalid data. Here, the valid data means the latest data referred to from the L2P table 71. That is, the valid data is the data stored in the physical storage element whose position is specified by the physical address associated with (i.e., mapped to) the logical address. The valid data is the data that may be read from the host 2 later. On the other hand, the invalid data means the old data that is no longer referred to from the L2P table 71. That is, the invalid data is the data stored in the physical storage element whose position is specified by the physical address not associated with (i.e., the mapping is canceled) the logical address. The invalid data is the data that is no longer likely to be read by the host 2.

[0035] Each of the SLC active block list 74 and the QLC active block list 75 manages the active blocks of the NAND memory 6. An active block is a block that stores at least valid data. Specifically, the SLC active block list 74 manages the active blocks that store the valid data written in the SLC mode. The SLC mode is a write mode that stores 1-bit data per memory cell of the NAND memory 6. The QLC active block list 75 manages the active blocks that store the valid data written in the QLC mode. The QLC mode is a write mode that stores 4-bit data per memory cell of the NAND memory 6.

[0036] Next, a configuration example of the flash die 61 included in the NAND memory 6 will be described. FIG. 2 is a block diagram showing a configuration example of the flash die 61 of the NAND memory 6 included in the memory system 3 according to the first embodiment.

[0037] Here, the configuration of the flash die 61 will be described by focusing on the flash die (#0) 61-0. Other flash dies also have the same configuration as the flash die (#0) 61-0. The flash die (#0) 61-0 includes a peripheral circuit 611-0 and a memory cell array 612-0.

[0038] The peripheral circuit 611-0 is a circuit that controls the memory cell array 612-0. The peripheral circuit 611-0 includes, for example, a row decoder, a column decoder, a sense amplifier, a latch circuit, and a voltage generation circuit. The peripheral circuit 611-0 executes a program operation, a read operation, or an erase operation on the memory cell array 612-0 in response to receiving an address and a command from the NAND controller 571-0.

[0039] The memory cell array 612-0 includes a plurality of blocks (BLK0, BLK1, BLK2, …). Each block BLK is a set of non-volatile memory cell transistors (hereinafter simply referred to as memory cell transistors or memory cells). Each block includes a plurality of string units (SU0, SU1, SU2, SU3). Each string unit SU is a set of memory cell transistors. Each string unit SU includes a plurality of NAND strings NS (also simply referred to as strings). Each NAND string NS is a set of memory cell transistors.

[0040] In FIG. 2, the case where each block includes four string units SU0, SU1, SU2, and SU3 has been described. The number of string units SU included in each block may be three or less, or may be five or more. Note that a configuration in which each block includes only one string unit SU may be used. That is, each block includes one or more string units SU.

[0041] Next, a configuration example of a block will be described. FIG. 3 is a diagram showing a configuration example of a block of the NAND memory 6 included in the memory system 3 according to the first embodiment.

[0042] In FIG. 3, the configuration of the block will be described by focusing on the block BLK0. Other blocks also have the same configuration as the block BLK0. The block BLK0 includes four string units (SU0, SU1, SU2, SU3). The four string units (SU0, SU1, SU2, SU3) are arranged in a direction (horizontal direction) orthogonal to the direction (vertical direction) in which a plurality of word lines WL0 to WL7 are stacked. Each string unit SU includes a plurality of NAND strings NS. One end of each NAND string NS is connected to a corresponding bit line among a plurality of bit lines (BL0 to BL(L-1)). Each NAND string NS extends in the vertical direction. Control gates of a plurality of memory cell transistors included in each NAND string NS are respectively connected to a plurality of word lines (WL0, WL1, …, WL7).

[0043] Next, the circuit configuration of the block will be described. FIG. 4 is a diagram showing a circuit configuration example of a block of the NAND memory 6 included in the memory system 3 according to the first embodiment.

[0044] In FIG. 4, the configuration of the block will be described by focusing on the block BLK0. Other blocks also have the same configuration as the block BLK0. The block BLK0 includes four string units (SU0, SU1, SU2, SU3). Each string unit SU includes a plurality of NAND strings NS.

[0045] Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and two selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer and holds data non-volatilely. Then, the memory cell transistors MT (MT0 to MT7) are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. Note that the number of memory cell transistors MT in the NAND string NS is not limited to eight.

[0046] The gate of each selection transistor ST1 of the string unit SU0 is connected to the selection gate line SGD0 corresponding to the string unit SU0. The gate of each selection transistor ST1 of the string unit SU1 is connected to the selection gate line SGD1 corresponding to the string unit SU1. The gate of each selection transistor ST1 of the string unit SU2 is connected to the selection gate line SGD2 corresponding to the string unit SU2. The gate of each selection transistor ST1 of the string unit SU3 is connected to the selection gate line SGD3 corresponding to the string unit SU3. On the other hand, the gates of the selection transistors ST2 of the string units SU0 to SU3 are commonly connected to the selection gate line SGS. Note that the gates of the selection transistors ST2 of the string units SU0 to SU3 may be connected to different selection gate lines (SGS0 to SGS3) for each string unit. The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to the word lines WL0 to WL7, respectively.

[0047] The program operation and read operation by the peripheral circuit 611 can be executed collectively for a plurality of memory cells MT connected to one word line in one string unit SU. The set of memory cells MT selected collectively during the program operation and read operation is referred to as a memory cell group MG. The memory cell group MG is a unit of the program operation and read operation and is treated as a storage location. When each memory cell MT is configured to store 1-bit data, the size of the data stored per memory cell group MG is referred to as a page. When each memory cell MT is configured to store 4-bit data, the size of the data stored per memory cell group MG is 4 pages.

[0048] The erase operation by the peripheral circuit 611 is executed in block units. That is, the data stored in all the memory cells MT included in one block are erased collectively.

[0049] Next, the restart process after an abnormal power-off occurs during the data writing operation will be described. FIG. 5 is a diagram showing the data state of block BLK0 when an abnormal power-off occurs during the data writing operation in the memory system 3 according to the first embodiment and the data state of block BLK0 when the memory system 3 is restarted. Here, the case where the data writing operation is executed using the full-sequence program operation will be described. The full-sequence program operation is a program operation for writing data to one storage position (memory cell group MG) in one string unit SU by one program operation. The program operation includes, for example, one or more program loops. Each program loop includes a first operation of injecting charge into the charge storage layer of the memory cell MT to increase the threshold voltage of the memory cell MT, and a second operation of verifying whether the threshold voltage of the memory cell MT has reached a voltage corresponding to the data to be written.

[0050] (a) The controller 5 executes the data writing operation for block BLK0 assigned as the write destination block using the full-sequence program operation. The data stored in each storage position where the program operation is completed is referred to as write-completed data. The write-completed data is data that can be read. The controller 5 periodically records, as the write destination position, information indicating the storage position in the write destination block where the data writing operation should be executed next in the NAND memory 6. Here, the controller 5 records write destination position A as the storage position where the data writing operation should be executed next.

[0051] (b) Next, the controller 5 executes a data writing operation using a full sequence program operation from the memory location indicated by the write destination position A to the memory location indicated by the write destination position B. Here, assume a case where abnormal power-off occurs during the execution of the program operation for the memory location indicated by the write destination position B. Abnormal power-off is a phenomenon in which the power supply to the memory system 3 is cut off without the memory system 3 receiving a shutdown notification from the host 2 in advance.

[0052] (c) If a power-off occurs during the execution of the program operation for the memory location indicated by the write destination position B, the program operation is interrupted before it is completed. As a result, this memory location becomes a memory location containing unreadable data. Unreadable data is data that cannot be normally read from the NAND memory 6. When data is read from a memory location containing unreadable data, the ECC circuit 55 cannot correct the error of this data, so it outputs a status indicating an ECC error. The threshold voltage of each memory cell MT included in the memory location where this unreadable data is stored may already have been changed by the interrupted program operation. Therefore, the controller 5 does not execute the program operation for this memory location again.

[0053] When the power supply to the memory system 3 is restored and the memory system 3 restarts, the controller 5 acquires information indicating the write destination position from the NAND memory 6. Information indicating the write destination position B is not recorded in the NAND memory 6. Therefore, the information acquired from the NAND memory 6 indicates the write destination position A. The controller 5 reads data from the storage position indicated by the acquired write destination position A, and determines whether readable data is stored in this storage position. Readable data is data that can be normally read from the NAND memory 6. If readable data is stored in this storage position, error correction by the ECC circuit 55 can succeed. That is, the controller 5 can determine whether the data stored in the NAND memory 6 is readable data or unreadable data based on the ECC pass / ECC error notified by the ECC circuit 55 to the CPU 52. When the data stored in the storage position indicated by the write destination position A is readable data, the controller 5 further reads the data stored in the storage position subsequent to the write destination position A, and determines whether the data stored in this storage position is readable data.

[0054] (e) By repeating the operation described in (d), the controller 5 identifies the first memory location storing the unreadable data. Then, the controller 5 determines whether the identified memory location is in an erased state. For all memory cells MT included in the memory location in the erased state, no program operation has been executed after the erase operation. If the identified memory location is in the erased state, the controller 5 can execute a data write operation on the identified memory location. Therefore, the controller 5 continues the data write operation on the block BLK0. On the other hand, if the identified memory location is not in the erased state, the controller 5 cannot continue the data write operation on the identified memory location. In this case, the controller 5 may register the block BLK0 in the block management table 72 as a block unavailable for data writing and newly assign another block as the write destination block. Then, the controller 5 can execute a data write operation on the block newly assigned as the write destination block.

[0055] Thus, in the case of using the full sequence program operation, the controller 5 can determine whether a power failure has occurred during the execution of the program operation by the process of determining whether readable data is stored in each of several memory locations and the process of determining whether the first memory location storing the unreadable data is in the erased state.

[0056] Next, the threshold voltage distribution of a plurality of memory cells in which data is written in the QLC mode will be described. In the QLC mode, 4 bits of data are written per memory cell. FIG. 6 is a diagram showing an example of the threshold voltage distribution of a plurality of memory cells of the NAND memory 6 included in the memory system 3 according to the first embodiment.

[0057] The threshold voltage Vth of each memory cell changes according to the amount of charge held in the charge storage layer of each memory cell. The NAND memory 6 stores information by associating a plurality of data values indicating the information to be stored with the threshold voltage distribution of the threshold voltage Vth of the memory cells.

[0058] In the QLC mode, the threshold voltages that each memory cell can have are divided into 16 threshold voltage ranges. These 16 threshold voltage ranges are sequentially named, from the lower threshold voltage side, as the Er state, A state, B state, C state, …, O state. The threshold voltage Vth of each memory cell is controlled to belong to any one of the threshold voltage ranges by a program operation.

[0059] These 16 states respectively correspond to different 4-bit data. The threshold voltage Vth of a memory cell programmed with the 4-bit data corresponding to the A state is set in the threshold voltage range from Vr1 to Vr2. Similarly, the threshold voltage Vth of a memory cell programmed with the 4-bit data corresponding to the B state is set in the threshold voltage range from Vr2 to Vr3. Similarly, the threshold voltage Vth of a memory cell programmed with the 4-bit data corresponding to the O state is set in the threshold voltage range from Vr15 to Vr16. The same applies to the other states.

[0060] Next, a multi-stage program operation will be described. FIG. 7 is a diagram showing the procedure of the multi-stage program operation executed in the memory system 3 according to the first embodiment when writing data in the QLC mode.

[0061] The controller 5 executes a data writing operation for each of a plurality of memory locations included in the write destination block using a multi-stage program operation including at least a first-stage program operation and a second-stage program operation. In the first-stage program operation, data for four pages to be written is transferred to the NAND memory 6, and this data is written to a plurality of memory cells (memory cell group MG) included in a memory location within the write destination block connected to a certain word line. In the first-stage program operation, the threshold voltage of each memory cell is roughly set. In this state, data cannot be normally read from each memory cell. In the second-stage program operation, data for the same four pages as the data transferred in the first-stage program operation is transferred to the NAND memory 6 again, and this data is written to the memory cell group MG corresponding to this memory location. In the second-stage program operation, the threshold voltage of each memory cell is set to a target threshold voltage corresponding to the data to be written. When the second-stage program operation is completed, data can be correctly read from each memory cell.

[0062] The second-stage program operation for each memory location is executed after the first-stage program operation for another memory location connected to a word line subsequent to the word line to which this memory location is connected is executed.

[0063] As the multi-stage program operation, for example, a foggy fine program operation can be used. The foggy fine program operation includes a foggy program operation and a fine program operation. The foggy program operation is a program operation (first-stage program operation) for roughly setting the threshold voltage of each memory cell. The fine program operation is a program operation (second-stage program operation) for adjusting the threshold voltage of each memory cell to set the threshold voltage of each memory cell to the target threshold voltage.

[0064] The foggy fine program operation for the write destination block is executed as follows. Hereinafter, a memory location connected to a certain word line WLx and included in a certain string unit SUy is referred to as MG(WLx, SUy).

[0065] (1) First, the foggy program operation for MG(WL0, SU0) is executed. Here, write data having a size of 4 pages, that is, write data having a size 4 times the page size, is transferred to the NAND memory 6. The page size corresponds to the number of strings included in one string unit SU, that is, the number of memory cells included in one memory location (memory cell group MG).

[0066] (2) Next, the foggy program operation for MG(WL0, SU1) is executed.

[0067] (3) Next, the foggy program operation for MG(WL0, SU2) is executed.

[0068] (4) Next, the foggy program operation for MG(WL0, SU3) is executed.

[0069] (5) When the foggy program operations for MG(WL0, SU0) to MG(WL0, SU3) are completed, the foggy program operation for MG(WL1, SU0) is executed.

[0070] When the foggy program operation for MG(WL1, SU0) is completed, the fine program operation for MG(WL0, SU0) is executed. Here, the same write data as that used in the foggy program operation for MG(WL0, SU0) is transferred to the NAND memory 6 again. Then, the fine program operation for MG(WL0, SU0) is executed. When this fine program operation is completed, MG(WL0, SU0) enters the fine program state. The data stored at the memory location in the fine program state is readable data that can be correctly read out.

[0071] (7) Next, the foggy program operation for MG(WL1, SU1) is executed.

[0072] (8) When the foggy program operation for MG(WL1, SU1) is completed, the fine program operation for MG(WL0, SU1) is executed. When the fine program operation is completed, MG(WL0, SU1) enters the fine program state.

[0073] (9) Next, the foggy program operation for MG(WL1, SU2) is executed.

[0074] (10) When the foggy program operation for MG(WL1, SU2) is completed, the fine program operation for MG(WL0, SU2) is executed. As a result, MG(WL0, SU2) enters the fine program state.

[0075] (11) Next, the foggy program operation for MG(WL1, SU3) is executed.

[0076] (12) When the foggy program operation for MG(WL1, SU3) is completed, the fine program operation for MG(WL0, SU3) is executed. As a result, MG(WL0, SU3) enters the fine program state.

[0077] (13) When the foggy program operation for MG(WL1, SU0)~MG(WL1, SU3) is completed, the foggy program operation for MG(WL2, SU0) is executed.

[0078] (14) When the foggy program operation for MG(WL2, SU0) is completed, the fine program operation for MG(WL1, SU0) is executed. As a result, MG(WL1, SU0) enters the fine program state.

[0079] (15) Next, the foggy program operation for MG(WL2, SU1) is executed.

[0080] (16) When the foggy program operation for MG(WL2, SU1) is completed, the fine program operation for MG(WL1, SU1) is executed. As a result, MG(WL1, SU1) enters the fine program state.

[0081] (17) Next, the foggy program operation for MG(WL2, SU2) is executed.

[0082] (18) When the foggy program operation for MG(WL2, SU2) is completed, the fine program operation for MG(WL1, SU2) is executed. As a result, MG(WL1, SU2) enters the fine program state.

[0083] Next, the order in which the foggy and fine program operations are executed for each of the plurality of memory locations included in each block will be described. FIG. 8 is a diagram showing the writing order of the multi-stage program operations for a block executed in the memory system 3 according to the first embodiment.

[0084] Each block contains one or more string units SU. The controller 5 is connected to a certain word line (the first word line) and executes a foggy programming operation on one or more memory cell groups MG (referred to as the first storage locations) respectively included in one or more string units SU. After the foggy programming operations for all of the one or more first storage locations are completed, the controller 5 is connected to a second word line subsequent to the first word line and executes a foggy programming operation on one of the one or more memory cell groups MG (referred to as the second storage locations) respectively included in one or more string units SU at a second storage location.

[0085] In response to the completion of the foggy programming operation for this one second storage location, the controller 5 executes a fine programming operation on the first storage location that is connected to the first word line and is included in the same string unit as this one second storage location.

[0086] The controller 5 executes foggy and fine programming operations on a plurality of storage locations included in the write destination block in such a write order. And the data written to each storage location becomes readable after the fine programming operation for each storage location is completed.

[0087] In FIG. 8, the write order for a plurality of storage locations included in one block is represented by numbers. Here, it is assumed that the number of word lines per block is 8 (word lines WL0 to WL7). In the first data write operation, a foggy programming operation on MG (WL0, SU0) is executed.

[0088] In the second data writing operation, a foggy programming operation for MG(WL0, SU1) is executed. In the third data writing operation, a foggy programming operation for MG(WL0, SU2) is executed. In the fourth data writing operation, a foggy programming operation for MG(WL0, SU3) is executed.

[0089] In the fifth data writing operation, a foggy programming operation for MG(WL1, SU0) is executed. In the sixth data writing operation, a fine programming operation for MG(WL0, SU0) is executed.

[0090] In the seventh data writing operation, a foggy programming operation for MG(WL1, SU1) is executed. In the eighth data writing operation, a fine programming operation for MG(WL0, SU1) is executed.

[0091] In the ninth data writing operation, a foggy programming operation for MG(WL1, SU2) is executed. In the tenth data writing operation, a fine programming operation for MG(WL0, SU2) is executed.

[0092] In the eleventh data writing operation, a foggy programming operation for MG(WL1, SU3) is executed. In the twelfth data writing operation, a fine programming operation for MG(WL0, SU3) is executed.

[0093] In the thirteenth data writing operation, a foggy programming operation for MG(WL2, SU0) is executed. In the fourteenth data writing operation, a fine programming operation for MG(WL1, SU0) is executed.

[0094] Thus, MG(WL x, SU y+1) is the memory location where a foggy program operation should be executed next after the foggy program operation for MG(WL x, SU y). Also, MG(WL x+1, SU0) is the memory location where a foggy program operation should be executed next after the foggy program operation for MG(WL x, SU3). MG(WL x+1, SU y) is the memory location where a foggy program operation was executed before the fine program operation for MG(WL x, SU y). Also, MG(WL x+1, SU y+1) is the memory location where a foggy program operation should be executed next after the fine program operation for MG(WL x, SU y).

[0095] Next, the threshold voltage distributions of the plurality of memory cells included in each memory location will be described. First, the threshold voltages of the plurality of memory cells included in the memory location in the erase state will be described. FIG. 9 is a diagram showing the threshold voltage distribution of the plurality of memory cells included in the memory location in the erase state in the memory system according to the first embodiment.

[0096] The threshold voltage of each of the plurality of memory cells included in the memory location in the erase state is lower than the erase page threshold voltage. The erase page threshold voltage is, for example, 0V. The erase page threshold voltage is, for example, Vr1 described with reference to FIG. 6. In other words, after the erase operation is executed, the memory location where the threshold voltages of any of the plurality of memory cells are maintained within the threshold voltage range of the Er state is the memory location in the erase state. There are no memory cells having a threshold voltage equal to or higher than the erase page threshold voltage in the memory location in the erase state. Therefore, the controller 5 can determine whether or not the memory location is in the erase state by executing an erase page check on the memory location. In the erase page check, the controller 5 determines whether or not the memory location includes a memory cell having a threshold voltage equal to or higher than the erase page threshold voltage.

[0097] Also, the memory location in the erased state is also a memory location from which data cannot be read normally. When data is read from the memory location in the erased state, since the ECC parity is not stored, the ECC circuit 55 cannot correct the error in the read data.

[0098] In the erase page check, the controller 5 may obtain the raw data read from the memory location by bypassing the ECC circuit 55. If the data of all memory cells included in the raw data corresponds to the Er state, the controller 5 can determine that all memory cells included in the memory location have the threshold voltage corresponding to the erased state.

[0099] Alternatively, when a circuit for counting the number of memory cells having a threshold voltage equal to or higher than the erase page threshold voltage is provided in the controller 5, the controller 5 may determine whether all memory cells included in the memory location have the threshold voltage corresponding to the erased state based on the count value output from this circuit. This circuit can control the NAND memory 6, for example, to apply the erase page threshold voltage as the read voltage to the word line to be subjected to the erase page check. Then, this circuit can count the number of memory cells storing data other than the data corresponding to the Er state included in the data read from the NAND memory 6 as the number of memory cells having a threshold voltage equal to or higher than the erase page threshold voltage.

[0100] The memory location in the erased state is a memory location where a data write operation can be executed.

[0101] Next, the threshold voltage distribution of a plurality of memory cells included in the memory location storing readable data will be described. FIG. 10 is a diagram showing the threshold voltage distribution of a plurality of memory cells included in a memory location in a state where data can be read in the memory system according to the first embodiment.

[0102] The memory locations from which data can be read are the memory locations of the full-sequence program state where the full-sequence program operation has been completed, or the memory locations of the fine program state where the fine program operation has been completed. When data is read from this memory location, since the ECC parity is stored, the ECC circuit 55 can correct errors in the read data. The threshold voltage of each memory cell included in this memory location has been changed to a threshold voltage corresponding to the data stored in that memory cell. Therefore, the threshold voltage of each memory cell included in this memory location has a threshold voltage corresponding to any one of the Er state, A state, B state, C state, …, O state. The memory location of the full-sequence program state or the fine program state cannot be used to write new data unless an erase operation is performed on the block including this memory location.

[0103] Next, the threshold voltage distribution of a plurality of memory cells included in the memory location where the foggy program operation has been completed will be described. FIG. 11 is a diagram showing the threshold voltage distribution of a plurality of memory cells included in the memory location of the foggy program state where the foggy program operation has been completed in the memory system 3 according to the first embodiment. The memory location of the foggy program state is a memory location where the foggy program operation has been completed and the fine program operation has not yet been started.

[0104] The threshold voltage of each memory cell included in the memory location of the foggy program state is set with low precision. Therefore, the memory location of the foggy program state is a memory location from which data cannot be read normally. When data is read from the memory location of the foggy program state, the ECC circuit 55 cannot correct the error in this data. On the other hand, the memory location of the foggy program state may include memory cells having a threshold voltage equal to or higher than the erase page threshold voltage. Therefore, the controller 5 can distinguish between the memory location of the foggy program state and the memory location of the erase state.

[0105] The storage location of the foggy program state is a storage location capable of executing the second-stage program operation (fine program operation). That is, the storage location of the foggy program state is not an erased state but a storage location where the fine program operation can be executed.

[0106] Next, the threshold voltage distribution of a plurality of memory cells included in the storage location in a state where power-off occurs during the data writing operation will be described. FIG. 12 is a diagram showing the threshold voltage distribution of a plurality of memory cells included in the storage location in a state where power-off occurs during the data writing operation in the memory system 3 according to the first embodiment.

[0107] The storage location where these operations are interrupted due to the power supply to the memory system 3 being cut off during the execution of the data writing operation (full sequence program operation, foggy program operation, or fine program operation) is a storage location in a program interruption state storing data that cannot be correctly read. When data is read from the storage location in the program interruption state, the ECC circuit 55 cannot correct the error of this read data. On the other hand, the threshold voltages of some memory cells included in the storage location in the program interruption state exceed the erase page threshold voltage. Therefore, the controller 5 can distinguish between the storage location in the program interruption state and the storage location in the erased state.

[0108] Since the storage location in the program interruption state is not in the erased state, it cannot be used for writing new data.

[0109] Hereinafter, a state where there is no storage location in the program interruption state, that is, a case where the state of the storage location is any one of the full sequence program state, the fine program state, the foggy program state, or the erased state, is referred to as a state where the writing operation is normally stopped.

[0110] Even if data is read from either the storage location of the program interruption state or the storage location of the foggy program state, an ECC error is determined by the ECC circuit 55, and in the erase page check, it is determined that this storage location is not in the erased state. Therefore, based on only these two determinations, the controller 5 cannot correctly determine whether this storage location is in the program interruption state or the foggy program state.

[0111] Next, the data writing operation corresponding to the write command received from the host 2 and the data writing operation internally executed by the garbage collection operation will be described. FIG. 13 is a diagram showing an example of the data writing operation corresponding to the write command received from the host 2 and the data writing operation internally executed by the garbage collection operation, which are executed in the memory system according to the first embodiment. First, the data writing operation corresponding to the write command received from the host 2, that is, the data writing operation executed based on the write command received from the host 2 will be described.

[0112] The controller 5 acquires the write data associated with the write command received from the host 2 from the memory 22 of the host 2, and temporarily stores the acquired write data in the write buffer (WB). A part of the storage area of the DRAM 7 may be used as the write buffer, or a part of the storage area of the SRAM 53 may be used as the write buffer.

[0113] The controller 5 selects an SLC block from the free block list 73 and assigns the selected SLC block to the write destination block. The SLC block is a block in which data writing in the SLC mode is executed among the blocks included in the NAND memory 6. If an SLC block has already been assigned to the write destination block, the controller 5 omits this operation.

[0114] When the total size of the write data stored in the write buffer reaches the write unit, the controller 5 writes the write data to the SLC block assigned to the write destination block. At this time, the controller 5 executes a data write operation in the SLC mode.

[0115] When the SLC block assigned to the write destination block becomes full, the controller 5 registers the SLC block in the SLC active block list 74 and releases the SLC block from the write destination block. Then, the controller 5 selects another SLC block from the free block list 73 and assigns the selected another SLC block to the write destination block.

[0116] Also, the controller 5 executes a garbage collection operation on the SLC blocks included in the SLC active block list 74 during the idle state or in response to the number of SLC blocks (free SLC blocks) included in the free block list 73 falling below the threshold. The idle state means a state where there are no commands from the host 2 to be executed.

[0117] The controller 5 selects a QLC block from the free block list 73 and assigns it to the copy destination block. The QLC block is a block in the NAND memory 6 in which a foggy fine program operation in the QLC mode is executed. Each memory cell included in the QLC block stores 4-bit data. Therefore, the QLC block has a capacity four times that of the SLC block. If a QLC block has already been assigned to the copy destination block, the controller 5 omits this operation.

[0118] The controller 5 selects an arbitrary block from the SLC active block list 74 and assigns it to the source block for copying. The controller 5 may preferentially select a block with a small amount of stored valid data. Alternatively, the controller 5 may select a block to be assigned to the source block for copying based on any algorithm.

[0119] The controller 5 selects the valid data stored at the storage location of the source block (source storage location) and reads out the selected valid data. The controller 5 writes the read valid data to the storage location (destination storage location) in the destination block using the foggy fine program operation in QLC mode. The controller 5 updates the L2P table 71 so that the physical address associated with the logical address corresponding to this valid data is changed from the physical address indicating the source storage location to the physical address indicating the destination storage location. As a result, the valid data stored at the source storage location becomes invalid data.

[0120] When the source block becomes a block that does not hold valid data, the controller 5 returns this block to the free block list 73 and releases it from the source block.

[0121] Then, the controller 5 selects an arbitrary block from the SLC active block list 74 again and assigns it to the source block for copying.

[0122] Also, when the QLC block assigned to the destination block becomes full, the controller 5 registers that QLC block in the QLC active block list 75 and releases it from the destination block.

[0123] Here, the case where the controller 5 executes the foggy fine program operation when writing data to the QLC block by the garbage collection operation has been described. However, even when writing data based on the write command received from the host 2, the QLC block may be assigned as the write destination block. Hereinafter, the operation of writing data to the write destination block will be described. This write destination block may be the copy destination block in the garbage collection operation, or may be the block to which data from the host 2 should be written.

[0124] As described above, in the memory system 3, in addition to the data writing operation in the SLC mode, the data writing operation in the QLC mode is executed. The data writing operation in the QLC mode is executed using a multi-stage program operation.

[0125] Next, the operation when power-off occurs during the data writing operation using the multi-stage program operation will be described.

[0126] FIG. 14 is a diagram showing the relationship between the foggy fine program operation and the abnormal power-off determination process executed in the memory system according to the comparative example.

[0127] Here, it is assumed that the power supply to the memory system is cut off after the foggy program operation for the storage location (MG(WL N+2, SU2)) included in the string unit SU2 and connected to the word line WL N+2 (N is an integer of 1 or more) is completed, and before the fine program operation for the storage location (MG(WL N+1, SU2)) included in the string unit SU2 and connected to the word line WL N+1 is started.

[0128] After the power supply to the memory system is cut off and then restored, in response to the restoration of the power supply to the memory system, the controller acquires the write destination position stored in the NAND memory, and determines whether the data stored in each storage position subsequent to the write destination position is readable data.

[0129] Thereby, the controller can determine that four storage positions (MG(WL N, SU0) to MG(WL N, SU3)) connected to the word line WL N and two storage positions (MG(WL N+1, SU0) and MG(WL N+1, SU1)) out of the four storage positions (MG(WL N+1, SU0) to MG(WL N+1, SU3)) connected to the word line WL N+1 are in the fine program state. The storage position that became the fine program state last is MG(WL N+1, SU1).

[0130] Then, the controller determines whether each storage position subsequent to MG(WL N+1, SU1), which became the fine program state last, is in the erased state by, for example, performing an erase page check on each storage position subsequent to MG(WL N+1, SU1), which became the fine program state last.

[0131] Thereby, the controller can determine that MG(WL N+1, SU2), MG(WL N+1, SU3), MG(WL N+2, SU0), MG(WL N+2, SU1), and MG(WL N+2, SU2) are not in the erased state.

[0132] However, the controller cannot determine whether each storage position that is not in the erased state is a storage position in the foggy program state or a storage position in the program interrupted state.

[0133] Therefore, from the information obtained by these determinations, the state of MG(WL N+1, SU2) to MG(WL N+2, SU2) is (1) State where power-off occurs during the execution of the fine program operation for MG(WL N+1, SU2) (2) State where power-off occurs during the execution of the foggy program operation for MG(WL N+2, SU2) (3) Power-off occurred between the completion of the foggy program operation for MG(WL N+2, SU2) and the start of the fine program operation for MG(WL N+1, SU2), but the writing operation was stopped normally It is impossible to determine which of the above is the case.

[0134] That is, the controller cannot determine whether the previous writing operation was stopped normally.

[0135] Therefore, the memory system 3 according to the first embodiment executes the data writing operation according to the rule of executing the foggy program operation and the fine program operation that becomes executable by the completion of this foggy program operation as a series of program operations.

[0136] FIG. 15 is a diagram showing a first example of the relationship between the foggy-fine program operation and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0137] The controller 5 executes the data writing operation for a plurality of storage positions included in the writing destination block in accordance with the writing order of the foggy-fine program operation described with reference to FIG. 8. The controller 5 executes the fine program operation for MG(WL N+1, SU2) in response to the completion of the foggy program operation for MG(WL N+2, SU2). That is, the controller 5 executes the foggy program operation for MG(WL N+2, SU2) and the fine program operation for MG(WL N+1, SU2) as a series of program operations.

[0138] Here, assume that after the fine program operation for MG(WL N+1, SU2) is completed, the power supply to the memory system 3 is cut off due to an abnormal power-off.

[0139] After the power supply to the memory system 3 is cut off, in response to the restoration of the power supply to the memory system 3, that is, in response to the resumption of the power supply to the memory system 3, the controller 5 acquires information indicating the write destination position from the NAND memory 6. The controller 5 reads data from the storage position indicated by the acquired information, and based on the result of error correction by the ECC circuit 55 (ECC pass or ECC error), determines whether the data stored in this storage position is readable data. If the data stored in this storage position is readable data, that is, if it is an ECC pass, the controller 5 reads the data stored in the storage position subsequent to this storage position, and based on the result of error correction by the ECC circuit 55, determines again whether the data stored in this storage position is readable data.

[0140] In this way, until the first storage position where unreadable data is stored is found, the controller 5 determines whether the data stored in the storage position to be read is readable data while changing the storage position to be read. Thereby, the controller 5 specifies the last storage position where readable data is stored. That is, the controller 5 specifies the storage position where the data that became readable last among the plurality of storage positions included in the write destination block is stored. Here, the controller 5 specifies MG(WL N+1, SU2) as the storage position where the data that became readable last is stored.

[0141] Next, the controller 5 determines whether the first condition that (1-A) among the four memory positions connected to the word line subsequent to the word line to which the specified memory position is connected, the memory position included in the same string unit as the specified memory position stores unreadable data, and (1-B) the memory position for which the foggy program operation should be executed next after the foggy program operation for this memory position is in the erased state is satisfied.

[0142] Specifically, first, the controller 5 reads data from MG(WL N+2, SU2) and determines whether MG(WL N+2, SU2) stores unreadable data based on the result of error correction (ECC pass or ECC error) by the ECC circuit 55.

[0143] If MG(WL N+2, SU2) stores unreadable data, the controller 5 determines whether MG(WL N+2, SU3), which is the memory position for which the foggy program operation should be executed next after the foggy program operation for MG(WL N+2, SU2), is in the erased state.

[0144] Since the last memory position storing readable data is MG(WL N+1, SU2), the foggy program operation for MG(WL N+2, SU2) is completed. Therefore, if MG(WL N+2, SU2) stores unreadable data and MG(WL N+2, SU3) is in the erased state, the controller 5 can determine that the foggy program operation for MG(WL N+2, SU2) is completed.

[0145] That is, when MG(WL N+2, SU2) stores unreadable data and MG(WL N+2, SU3) is in an erase state, the controller 5 can determine that MG(WL N+2, SU2) is in a foggy program state. Also, since MG(WL N+2, SU3) is in an erase state, the fine write operation for MG(WL N+1, SU3) has not been started. Therefore, the controller 5 can determine that MG(WL N+1, SU3) is also in a foggy program state.

[0146] When MG(WL N+2, SU2) stores unreadable data and MG(WL N+2, SU3) is in an erase state, the first condition is satisfied. Therefore, in this case, the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, that is, there is no storage location in the block assigned as the write destination block in a program interrupted state. Then, the controller 5 determines this MG(WL N+2, SU3) determined to be in an erase state as the next write destination position.

[0147] That is, when the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, it continues the data write operation for the block assigned as the write destination block and determines MG(WL N+2, SU3) as the storage location where the next foggy program operation should be executed.

[0148] When the first condition is not satisfied, the controller 5 determines that there is a storage location where power-off occurred during the execution of the foggy program operation or the fine program operation, that is, the previous write operation of the memory system 3 was not normally stopped. For example, when MG(WL N+2, SU2) stores unreadable data but MG(WL N+2, SU3) is not in an erase state, the controller 5 determines that the previous write operation was not normally stopped.

[0149] Note that the controller 5 determines whether the condition that MG(WL N+2, SU2) stores unreadable data instead of being in an erased state and MG(WL N+2, SU3) is in an erased state is satisfied. If the condition is satisfied, the controller 5 may determine that the previous write operation of the memory system 3 was normally stopped.

[0150] Next, a case where it is determined that the previous write operation of the memory system 3 was not normally stopped will be described. FIG. 16 is a diagram showing a second example of the relationship between the foggy fine program operation and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0151] Here, it is assumed that a power-off occurs during the execution of the foggy program operation for MG(WL N+2, SU2).

[0152] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described with reference to FIG. 15. Here, the controller 5 identifies MG(WL N+1, SU1) as the last storage location where readable data is stored.

[0153] Next, the controller 5 determines whether a storage location included in the same string unit as the identified storage location among the four storage locations connected to the word line subsequent to the word line to which the identified storage location is connected stores unreadable data. That is, the controller 5 determines whether MG(WL N+2, SU1) stores unreadable data.

[0154] If MG(WL N+2, SU1) stores unreadable data, the controller 5 determines whether MG(WL N+2, SU2), which is the storage location where the foggy program operation should be executed next after the foggy program operation for MG(WL N+2, SU1), is in an erased state.

[0155] If a power failure occurs during the execution of the foggy program operation for MG(WL N+2, SU2), data cannot be read normally from MG(WL N+2, SU2). Also, MG(WL N+2, SU2) includes one or more memory cells having a threshold voltage higher than the erase page threshold voltage. Therefore, MG(WL N+2, SU2) is determined not to be in the erase state. From this result, the controller 5 determines that it was not possible to complete the foggy program operation for MG(WL N+2, SU2) and the fine program operation for MG(WL N+1, SU2) as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL N+2, SU2) is in the foggy program state or whether a power failure occurred during the execution of the foggy program operation for MG(WL N+2, SU2).

[0156] Also, the controller 5 cannot determine whether MG(WL N+1, SU2) is in the foggy program state or whether a power failure occurred during the execution of the fine program operation for MG(WL N+1, SU2). This is because the data stored in MG(WL N+1, SU2) is unreadable data and MG(WL N+2, SU2) is not in the erase state. For this reason, MG(WL N+1, SU2) may be in the foggy program state or may be in a program interrupted state where a power failure occurred during the execution of the fine program operation.

[0157] Thus, when there may be a storage location in the block assigned as the write destination block in a program interrupted state, the controller 5 determines that the previous write operation of the memory system 3 was not stopped normally.

[0158] When the controller 5 determines that the previous write operation has not stopped normally, it registers, in the block management table 72, the block assigned to the write destination block as an unavailable block. The controller 5 releases the registered block from the write destination block. Then, the controller 5 selects another block from the free block list 73. The controller 5 newly assigns the selected block to the write destination block. The controller 5 determines the first storage position MG(WL0, SU0) among the storage positions included in the newly assigned block as the next write destination position. Note that the first condition is not satisfied even when the data stored in MG(WL N+2, SU1) is readable data. Also in this case, it is determined that the previous write operation has not stopped normally.

[0159] Next, another case where it is determined that the previous write operation of the memory system 3 has not stopped normally will be described. FIG. 17 is a diagram showing a third example of the relationship between the foggy fine program operation and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0160] Here, it is assumed that a power-off occurs during the execution of the fine program operation for MG(WL N+1, SU2).

[0161] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage position in which readable data is stored in the same procedure as the procedure described with reference to FIG. 15. When a power-off occurs during the execution of the fine program operation for MG(WL N+1, SU2), data cannot be normally read from MG(WL N+1, SU2). Therefore, the controller 5 identifies MG(WL N+1, SU1) as the last storage position in which readable data is stored.

[0162] Next, the controller 5 determines whether a memory location included in the same string unit as the specified memory location among the four memory locations connected to the word line subsequent to the word line to which the specified memory location is connected stores unreadable data. That is, the controller 5 determines whether MG(WL N+2, SU1) stores unreadable data.

[0163] If MG(WL N+2, SU1) stores unreadable data, the controller 5 determines whether MG(WL N+2, SU2), which is the memory location at which a foggy program operation should be executed next after the foggy program operation for MG(WL N+2, SU1), is in an erased state.

[0164] Since MG(WL N+2, SU2) is in a foggy program state, data cannot be read normally from MG(WL N+2, SU2). Also, MG(WL N+2, SU2) includes one or more memory cells having a threshold voltage higher than the erase page threshold voltage. Therefore, MG(WL N+2, SU2) is determined not to be in an erased state. From this result, the controller 5 determines that it was not possible to complete the foggy program operation for MG(WL N+2, SU2) and the fine program operation for MG(WL N+1, SU2) as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL N+2, SU2) is in a foggy program state or whether a power-off occurred during the execution of the foggy program operation for MG(WL N+2, SU2).

[0165] Further, the controller 5 cannot determine whether MG(WL N+1, SU2) is in the fog program state or whether a power-off occurred during the execution of the fine program operation for MG(WL N+1, SU2). This is because the data stored in MG(WL N+1, SU2) is unreadable data and MG(WL N+2, SU2) is not in the erase state. Therefore, MG(WL N+1, SU2) may be in the fog program state or may be in a program interruption state where a power-off occurred during the execution of the fine program operation.

[0166] In this way, when there may be a storage location in the block assigned as the write destination block in the program interruption state, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0167] Next, another case where it is determined that the previous write operation of the memory system 3 did not stop normally will be described. FIG. 18 is a diagram showing a fourth example of the relationship between the fog / fine program operation and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0168] Here, it is assumed that a power-off occurs after the fog program operation for MG(WL N+2, SU2) is completed and before the execution of the fine program operation for MG(WL N+1, SU2) is started.

[0169] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. Here, the controller 5 identifies MG(WL N+1, SU1) as the last storage location where readable data is stored.

[0170] Next, the controller 5 determines whether a memory location included in the same string unit as the specified memory location among the four memory locations connected to the word line subsequent to the word line to which the specified memory location is connected stores unreadable data. That is, the controller 5 determines whether MG(WL N+2, SU1) stores unreadable data.

[0171] If MG(WL N+2, SU1) stores unreadable data, the controller 5 determines whether MG(WL N+2, SU2), which is the memory location where the foggy program operation should be executed next after the foggy program operation for MG(WL N+2, SU1), is in an erased state.

[0172] Since MG(WL N+2, SU2) is in the foggy program state, data cannot be normally read from MG(WL N+2, SU2). Also, MG(WL N+2, SU2) includes one or more memory cells having a threshold voltage higher than the erase page threshold voltage. Therefore, MG(WL N+2, SU2) is determined not to be in the erased state. From this result, the controller 5 determines that it was not possible to complete the foggy program operation for MG(WL N+2, SU2) and the fine program operation for MG(WL N+1, SU2) as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL N+2, SU2) is in the foggy program state or whether a power-off occurred during the execution of the foggy program operation for MG(WL N+2, SU2).

[0173] In addition, the controller 5 cannot determine whether MG(WL N+1, SU2) is in the foggy program state or whether a power cut occurred during the execution of the fine program operation for MG(WL N+1, SU2). This is because the data stored in MG(WL N+1, SU2) is unreadable data and MG(WL N+2, SU2) is not in the erase state. For this reason, MG(WL N+1, SU2) may be in the foggy program state or may be in a program interruption state where a power cut occurred during the execution of the fine program operation.

[0174] Thus, when there may be a storage location in the block assigned as the write destination block where the program interruption state is stored, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0175] Next, the data writing operation for the four storage locations connected to the word line at the head of the write destination block will be described. First, the data writing operation for the four storage locations connected to the word line at the head of the block executed in the memory system according to the comparative example will be described. FIG. 19 is a diagram showing the relationship between the foggy / fine program operation for the head word line of the write destination block and the abnormal power cut determination process executed in the memory system according to the comparative example.

[0176] Here, assume that a power cut occurs to the memory system after the foggy program operation for MG(WL0, SU2) is completed and before the foggy program operation for MG(WL0, SU3) is started.

[0177] Whenever data to be written to one of the four memory locations connected to word line WL0 is prepared, the controller of the memory system according to the comparative example writes this data to one of the memory locations connected to word line WL0 using a foggy program operation. Therefore, power-off of the memory system can occur while the fine program operation has not been completed for any of the four memory locations connected to word line WL0.

[0178] In the case of FIG. 19, after the memory system restarts, the controller cannot determine whether MG(WL0, SU2) is in either the foggy program state or the program interruption state where power-off occurred during the execution of the foggy program operation.

[0179] Therefore, in the memory system 3 according to the first embodiment, the foggy program operation for the four memory locations connected to the word line at the head of the write destination block is started in response to the first fine program operation becoming executable. FIG. 20 is a diagram showing a first example of the relationship between the foggy-fine program operation for the word line at the head of the write destination block and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0180] The controller 5 executes, as a series of program operations, a foggy program operation for four memory locations (MG(WL0, SU0) to MG(WL0, SU3)) connected to the word line WL0 which is the first word line, a foggy program operation for the memory location (MG(WL1, SU0)) connected to the word line WL1 and included in the string unit SU0, and a fine program operation for MG(WL0, SU0). That is, the controller 5 waits until the data to be written to MG(WL0, SU0) to MG(WL0, SU3) and the data to be written to MG(WL1, SU0) are prepared. The controller 5 waits, for example, until all of these data are stored in the write buffer. In response to all of these data being prepared, the controller 5 executes a foggy program operation for MG(WL0, SU0) to MG(WL0, SU3), a foggy program operation for MG(WL1, SU0), and a fine program operation for MG(WL0, SU0).

[0181] Thereby, the controller 5 can complete the fine program operation for MG(WL0, SU0) as long as an abnormal power-off does not occur. When the data stored in MG(WL0, SU0) is readable data, the controller 5 can execute an abnormal power-off determination process for the write destination block in the same procedure as the operation described in FIG. 15. When the data stored in MG(WL0, SU0) is unreadable data and MG(WL0, SU0) is not in an erased state when the memory system 3 is restarted, the controller 5 can determine that the previous write operation of the memory system 3 was not stopped normally.

[0182] The following will be specifically described. In FIG. 20, it is assumed that after the fine program operation for MG(WL0, SU0) is completed, the power supply to the memory system 3 is cut off due to an abnormal power-off.

[0183] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. Here, the controller 5 identifies MG(WL0, SU0) as the last storage location where readable data is stored.

[0184] Next, the controller 5 determines whether the storage location included in the same string unit as the identified storage location among the four storage locations connected to the word line subsequent to the word line to which the identified storage location is connected stores unreadable data. That is, here, the controller 5 determines whether MG(WL1, SU0) stores unreadable data.

[0185] If MG(WL1, SU0) stores unreadable data, the controller 5 determines whether MG(WL1, SU1), which is the storage location where the foggy program operation should be executed next after the foggy program operation for MG(WL1, SU0), is in an erased state.

[0186] Since the last storage location where readable data is stored is MG(WL0, SU0), the foggy program operation for MG(WL1, SU0) is completed. Therefore, if MG(WL1, SU0) stores unreadable data and MG(WL1, SU1) is in an erased state, the controller 5 can determine that the foggy program operation for MG(WL1, SU0) is completed.

[0187] That is, when MG(WL1, SU0) stores unreadable data and MG(WL1, SU1) is in an erase state, the controller 5 can determine that MG(WL1, SU0) is in a foggy program state. Also, since MG(WL1, SU1) is in an erase state, the fine write operation for MG(WL0, SU1) has not been started. Therefore, the controller 5 can also determine that MG(WL0, SU1) is in a foggy program state.

[0188] When MG(WL1, SU0) stores unreadable data and MG(WL1, SU1) is in an erase state, the first condition is satisfied. Therefore, in this case, the controller 5 determines that the previous write operation of the memory system 3 has stopped normally, that is, there is no storage location in the block assigned as the write destination block in a program interrupted state. Then, the controller 5 determines this MG(WL1, SU1) that has been determined to be in an erase state as the next write destination position.

[0189] That is, when the controller 5 determines that the previous write operation of the memory system 3 has stopped normally, it continues the data write operation for the block assigned as the write destination block and determines MG(WL1, SU1) as the storage location where the next foggy program operation should be executed.

[0190] When the first condition is not satisfied, the controller 5 determines that there is a storage location where power-off occurred during the execution of the foggy program operation or the fine program operation, that is, the previous write operation of the memory system 3 has not stopped normally. For example, when MG(WL1, SU0) stores unreadable data but MG(WL1, SU1) is not in an erase state, the controller 5 determines that the previous write operation has not stopped normally.

[0191] Note that the controller 5 may determine whether the condition that MG(WL1, SU0) stores non-readable data instead of being in an erased state and MG(WL1, SU1) is in an erased state is satisfied, and if it is satisfied, determine that the previous write operation of the memory system 3 was normally stopped.

[0192] Next, a case where it is determined that the previous write operation of the memory system 3 was not normally stopped will be described. FIG. 21 is a diagram showing a second example of the relationship between the foggy fine program operation for the first word line of the write destination block and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0193] Here, assume that a power-off occurs during the execution of the foggy program operation for MG(WL1, SU0).

[0194] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. In the case of FIG. 21, no storage location stores readable data. Therefore, the controller 5 determines that there is no storage location where readable data is stored, that is, no storage location in the fine program state. Therefore, the controller 5 determines that the foggy program operations for MG(WL0, SU0) to MG(WL0, SU3), the foggy program operation for MG(WL1, SU0), and the fine program operation for MG(WL0, SU0) could not be completed as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL1, SU0) is in the foggy program state or whether a power-off occurred during the execution of the foggy program operation for MG(WL1, SU0).

[0195] In addition, the controller 5 cannot determine whether MG(WL0, SU0) is in the foggy program state or whether a power-off occurred during the execution of the fine program operation for MG(WL0, SU0).

[0196] In this way, when there may be a storage location in the program interruption state in the block assigned as the write destination block, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0197] When the controller 5 determines that the previous write operation did not stop normally, it registers the block assigned as the write destination block as an unusable block in the block management table 72. The controller 5 releases the registered block from the write destination block. Then, the controller 5 selects another block from the free block list 73. The controller 5 newly assigns the selected block as the write destination block. The controller 5 determines MG(WL0, SU0), which is the first storage location among the storage locations included in the newly assigned block, as the next write destination position.

[0198] Next, another case where it is determined that the previous write operation of the memory system 3 did not stop normally will be described. FIG. 22 is a diagram showing a third example of the relationship between the foggy / fine program operation for the first word line of the write destination block and the abnormal power-off determination process executed in the memory system 3 according to the first embodiment.

[0199] Here, it is assumed that a power-off occurs during the execution of the fine program operation for MG(WL0, SU0).

[0200] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. In the case of FIG. 22, no storage location stores readable data. Therefore, the controller 5 determines that there is no storage location where readable data is stored, that is, there is no storage location in the fine program state. Accordingly, the controller 5 determines that the foggy program operations for MG(WL0, SU0) to MG(WL0, SU3), the foggy program operation for MG(WL1, SU0), and the fine program operation for MG(WL0, SU0) could not be completed as a series of program operations.

[0201] In this case, the controller 5 cannot determine whether MG(WL0, SU0) is in the foggy program state or whether a power cut occurred during the execution of the fine program operation for MG(WL0, SU0). Also, the controller 5 cannot determine whether MG(WL1, SU0) is in the foggy program state or whether a power cut occurred during the execution of the foggy program operation for MG(WL1, SU0).

[0202] Thus, when there may be a storage location in the program interruption state in the block assigned as the write destination block, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0203] Next, another case where it is determined that the previous write operation of the memory system 3 did not stop normally will be described. FIG. 23 is a diagram showing a fourth example of the relationship between the foggy / fine program operation for the first word line of the write destination block and the abnormal power cut determination process executed in the memory system 3 according to the first embodiment.

[0204] Here, assume that a power-off occurs after the foggy program operation for MG(WL1, SU0) is completed and before the execution of the fine program operation for MG(WL0, SU0) is started.

[0205] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. In the case of FIG. 23, no storage location stores readable data. Therefore, the controller 5 determines that there is no storage location where readable data is stored, that is, there is no storage location in the fine program state. Accordingly, the controller 5 determines that the foggy program operations for MG(WL0, SU0) to MG(WL0, SU3), the foggy program operation for MG(WL1, SU0), and the fine program operation for MG(WL0, SU0) could not be completed as a series of program operations.

[0206] In this case, the controller 5 cannot determine whether MG(WL1, SU0) is in the foggy program state or whether a power-off occurred during the execution of the foggy program operation for MG(WL1, SU0). Also, the controller 5 cannot determine whether MG(WL0, SU0) is in the foggy program state or whether a power-off occurred during the execution of the fine program operation for MG(WL0, SU0).

[0207] Thus, when there may be a storage location in the program interrupted state in the block assigned as the write destination block, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0208] In FIGS. 20 to 23, the case where the fine program operation for MG(WL0, SU0) becomes executable after the foggy program operation for MG(WL1, SU0) is completed has been described. However, the foggy / fine program operations may be executed in other program orders. For example, the fine program operation for MG(WL0, SU0) may become executable after the foggy program operation for MG(WL0, SU1) is completed. In this case, the foggy program operation for MG(WL0, SU0) is started when the data to be written to MG(WL0, SU0) and MG(WL0, SU1) is prepared.

[0209] Next, the case where the number of string units included in each block is one will be described. FIG. 24 is a diagram showing a first example of the relationship between the foggy / fine program operation and the abnormal power-off determination process when the number of string units SU included in each block is one in the memory system 3 according to the first embodiment. Hereinafter, the storage location connected to a certain word line WLx is referred to as MG(WLx).

[0210] When the number of string units SU included in each block is one, the controller 5 executes the data writing operation in the order of the foggy program operation for MG(WL0), the foggy program operation for MG(WL1), the fine program operation for MG(WL0), the foggy program operation for MG(WL2), and the fine program operation for MG(WL1).

[0211] Here, the controller 5 executes the foggy program operation and the fine program operation that becomes executable due to the completion of this foggy program operation as a series of program operations. Therefore, the controller 5 executes the foggy program operation for MG(WL1) and the fine program operation for MG(WL0) as a series of program operations.

[0212] The following will be specifically described. In FIG. 24, assume a case where, after the fine program operation for MG (WL6) is completed, the power supply to the memory system 3 is cut off due to an abnormal power-off.

[0213] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. Here, the controller 5 identifies MG (WL6) as the last storage location where readable data is stored.

[0214] Next, the controller 5 determines whether a storage location included in the same string unit as the identified storage location among the storage locations connected to the word line subsequent to the word line to which the identified storage location is connected stores unreadable data. Here, since there is only one string unit, the controller 5 simply refers to the storage location connected to the subsequent word line. That is, the controller 5 determines whether MG (WL7) stores unreadable data.

[0215] When MG (WL7) stores unreadable data, the controller 5 determines whether MG (WL8), which is the storage location where the foggy program operation should be executed next after the foggy program operation for MG (WL7), is in an erased state.

[0216] Since the last storage location where readable data is stored is MG (WL6), the foggy program operation for MG (WL7) is completed. Therefore, if MG (WL7) stores unreadable data and MG (WL8) is in an erased state, the controller 5 can determine that the foggy program operation for MG (WL7) is completed.

[0217] When MG(WL7) stores unreadable data and MG(WL8) is in an erased state, the first condition is satisfied. Therefore, the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, that is, there is no storage location in the block assigned as the write destination block in a program interrupted state. Then, the controller 5 determines this MG(WL8) in the erased state as the next write destination location.

[0218] When the first condition is not satisfied, the controller 5 determines that there is a storage location where power-off occurred during the execution of the foggy program operation or the fine program operation, that is, the previous write operation of the memory system 3 was not normally stopped. For example, when MG(WL7) stores unreadable data but MG(WL8) is not in an erased state, the controller 5 determines that the previous write operation was not normally stopped.

[0219] Next, a case where it is determined that the previous write operation of the memory system 3 was not normally stopped will be described. FIG. 25 is a diagram showing a second example of the relationship between the foggy / fine program operation and the abnormal power-off determination process when the number of string units included in each block is one, which is executed in the memory system 3 according to the first embodiment.

[0220] Here, it is assumed that power-off occurs during the execution of the foggy program operation for MG(WL7).

[0221] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 specifies the last storage location where readable data is stored in the same procedure as the procedure described with reference to FIG. 15. Here, the controller 5 specifies MG(WL5) as the last storage location where readable data is stored.

[0222] Next, it is determined whether a memory location connected to a word line subsequent to the word line to which the specified memory location is connected stores unreadable data. That is, the controller 5 determines whether MG(WL6) stores unreadable data.

[0223] If MG(WL6) stores unreadable data, the controller 5 determines whether MG(WL7), which is the memory location where the foggy program operation should be executed next after the foggy program operation for MG(WL6), is in an erased state.

[0224] If a power-off occurs during the execution of the foggy program operation for MG(WL7), the controller 5 cannot normally read data from MG(WL7). Also, MG(WL7) includes one or more memory cells having a threshold voltage higher than the erase page threshold voltage. Therefore, MG(WL7) is determined not to be in an erased state. From this result, the controller 5 determines that it was not possible to complete the foggy program operation for MG(WL7) and the fine program operation for MG(WL6) as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL7) is in a foggy program state or whether a power-off occurred during the execution of the foggy program operation for MG(WL7).

[0225] Also, the controller 5 cannot determine whether MG(WL6) is in a foggy program state or whether a power-off occurred during the execution of the fine program operation for MG(WL6).

[0226] Thus, if there may be a memory location in a program interrupted state in the block assigned as the write destination block, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0227] When the controller 5 determines that the previous write operation has not stopped normally, it registers, in the block management table 72, the block assigned to the write destination block as an unusable block. The controller 5 releases the registered block from the write destination block. Then, the controller 5 selects another block from the free block list 73. The controller 5 newly assigns the selected another block to the write destination block. The controller 5 determines the head storage position MG(WL0) among the storage positions included in the newly assigned another block as the next write destination position.

[0228] Next, another case where it is determined that the previous write operation of the memory system 3 has not stopped normally will be described. FIG. 26 is a diagram showing a third example of the relationship between the foggy fine program operation and the abnormal power-off determination process when the string unit included in each block is 1 in the memory system 3 according to the first embodiment.

[0229] Here, it is assumed that a power-off occurs during the execution of the fine program operation for MG(WL6).

[0230] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage position in which readable data is stored in the same procedure as the procedure described with reference to FIG. 15. When a power-off occurs during the execution of the fine program operation for MG(WL6), data cannot be normally read from MG(WL6). Therefore, the controller 5 identifies MG(WL5) as the last storage position in which readable data is stored.

[0231] Next, the controller 5 determines whether the storage position connected to the word line subsequent to the word line to which the identified storage position is connected stores unreadable data. That is, the controller 5 determines whether MG(WL6) stores unreadable data.

[0232] When MG(WL6) stores unreadable data, the controller 5 determines whether MG(WL7), which is the storage location where the foggy program operation should be executed next after the foggy program operation for MG(WL6), is in an erased state.

[0233] Since MG(WL7) is in the foggy program state, data cannot be read normally from MG(WL7). Also, MG(WL7) includes one or more memory cells having a threshold voltage higher than the erase page threshold voltage. Therefore, MG(WL7) is determined not to be in an erased state. From this result, the controller 5 determines that it could not complete the foggy program operation for MG(WL7) and the fine program operation for MG(WL6) as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL7) is in the foggy program state or whether a power-off occurred during the execution of the foggy program operation for MG(WL7).

[0234] Also, the controller 5 cannot determine whether MG(WL6) is in the foggy program state or whether a power-off occurred during the execution of the fine program operation for MG(WL6). This is because the data stored in MG(WL6) is unreadable data and MG(WL7) is not in an erased state. For this reason, MG(WL6) may be in the foggy program state or may be in a program interrupted state where a power-off occurred during the execution of the fine program operation.

[0235] Thus, when there may be a storage location in the interrupted program state in the block assigned as the write destination block, the controller 5 determines that the previous write operation of the memory system 3 did not stop normally.

[0236] Next, another case will be described in which it is determined that the previous write operation of the memory system 3 did not stop normally. FIG. 27 is a diagram showing a fourth example of the relationship between the foggy fine program operation and the abnormal power-off determination process when the string unit included in each block is 1, which is executed in the memory system 3 according to the first embodiment.

[0237] Here, it is assumed that a power-off occurs between the completion of the foggy program operation for MG(WL7) and the start of the execution of the fine program operation for MG(WL6).

[0238] After the power supply to the memory system 3 is cut off and the memory system 3 restarts, the controller 5 identifies the last storage location where readable data is stored in the same procedure as described in FIG. 15. Here, the controller 5 identifies MG(WL5) as the last storage location where readable data is stored.

[0239] Next, the controller 5 determines whether the storage location connected to the word line subsequent to the word line to which the identified storage location is connected stores unreadable data. That is, the controller 5 determines whether MG(WL6) stores unreadable data.

[0240] If MG(WL6) stores unreadable data, the controller 5 determines whether MG(WL7), which is the storage location where the foggy program operation should be executed next after the foggy program operation for MG(WL6), is in the erased state.

[0241] Since MG(WL7) is in the foggy program state, data cannot be read normally from MG(WL7). Also, MG(WL7) includes one or more memory cells having a threshold voltage higher than the erase page threshold voltage. Therefore, MG(WL7) is determined not to be in the erase state. From this result, the controller 5 determines that it was not possible to complete the foggy program operation for MG(WL7) and the fine program operation for MG(WL6) as a series of program operations. In this case, the controller 5 cannot determine whether MG(WL7) is in the foggy program state or whether a power cut occurred during the execution of the foggy program operation for MG(WL7).

[0242] Also, it is not possible to determine whether MG(WL6) is in the foggy program state or whether a power cut occurred during the execution of the fine program operation for MG(WL6). This is because the data stored in MG(WL6) is unreadable data and MG(WL7) is not in the erase state. For this reason, MG(WL6) may be in the foggy program state or may be in a program interruption state where a power cut occurred during the execution of the fine program operation.

[0243] Thus, when there may be a storage location in the program interruption state in the block assigned as the write destination block, the controller 5 determines that the previous write operation of the memory system 3 was not stopped normally.

[0244] Next, the procedure of the abnormal power-off determination process will be described. FIG. 28 is a flowchart showing the procedure of the abnormal power-off determination process executed in the memory system 3 according to the first embodiment. After the power supply to the memory system 3 is cut off, when the memory system 3 restarts, that is, when the power supply to the memory system 3 is resumed, the controller 5 executes the abnormal power-off determination process. The abnormal power-off determination process is a process of determining whether the previous write operation of the memory system 3 was normally stopped and appropriately determining the next write destination position.

[0245] When the power supply to the memory system 3 is resumed, the controller 5 acquires information indicating the write destination position (step S102). The controller 5 reads out the information indicating the write destination position from the NAND memory 6. The information indicating the write destination position is periodically stored in the NAND memory 6. Therefore, the storage position indicated as the write destination position by the information acquired from the NAND memory 6 is a storage position among the storage positions included in the block assigned to the write destination block at the time of the previous power-off, in which the data write operation has already been completed.

[0246] The controller 5 starts a data read operation from the storage position indicated by the information acquired in step S102 (step S103). The controller 5 executes a data read operation on the storage position indicated by the information acquired in step S102 and checks the result of error correction by the ECC circuit 55 (ECC pass or ECC error). Thereby, the controller 5 determines whether the data stored in this storage position is readable data. If the data stored in this storage position is readable data, the controller 5 executes a data read operation on the next storage position following this storage position and checks the result of error correction by the ECC circuit 55. Thereby, the controller 5 determines whether the data stored in the next storage position is readable data.

[0247] The controller 5 identifies the last storage location where readable data is stored (step S104) by repeating the data read operation and the confirmation of the error correction result in step S103. The last storage location where readable data is stored is the storage location where the data that became readable last among the plurality of storage locations included in the write destination block is stored.

[0248] The controller 5 determines whether the data stored in the storage location connected to the next word line following the word line connected to the identified last storage location (that is, the last storage location where readable data is stored) and included in the same string unit as the identified last storage location is readable data (step S105).

[0249] If the data stored in the storage location connected to the next word line following the word line connected to the identified last storage location and included in the same string unit as the identified last storage location is not readable data (No in step S105), the process by the controller 5 proceeds to step S106. In this case, the data stored in the storage location connected to the next word line following the word line connected to the identified last storage location and included in the same string unit as the identified last storage location is unreadable data.

[0250] The controller 5 determines whether the memory location where the next foggy program operation should be executed after the foggy program operation for the memory location storing the unreadable data is in an erased state (step S106). The controller 5 executes an erase page check on the memory location where the next foggy program operation should be executed after the foggy program operation for the memory location storing the unreadable data. By executing the erase page check, the controller 5 determines whether the target memory location contains memory cells whose threshold voltage is equal to or higher than the erase page threshold voltage. If the target memory location does not contain memory cells whose threshold voltage is equal to or higher than the erase page threshold voltage, the controller 5 determines that the target memory location is in an erased state.

[0251] If the memory location where the next foggy program operation should be executed after the foggy program operation for the memory location storing the unreadable data is in an erased state (Yes in step S106), that is, if the first condition is satisfied (No in step S105 and Yes in step S106), the controller 5 determines that the previous write operation of the memory system 3 was normally stopped (step S107). The controller 5 recognizes that the previous power-off occurred between the completion of the fine program operation for the memory location specified in step S104 and the start of the foggy program operation for the memory location where the erase page check was executed in step S106. From this, the controller 5 determines that the previous write operation of the memory system 3 was normally stopped.

[0252] The controller 5 determines the memory location determined to be in an erased state in step S106 as the next write destination location where the next foggy program operation should be executed (step S108). That is, when the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, it decides to continue writing to the block assigned to the write destination block.

[0253] If the next word line connected to the word line to which the last memory location specified in step S104 is connected and the data stored in the memory location included in the same string unit as the specified last memory location is readable data (Yes in step S105), the process by the controller 5 returns to step S104.

[0254] In this case, the first condition is not satisfied. Moreover, it is determined that the last memory location specified in step S104 is incorrect. Therefore, the controller 5 specifies again the last memory location in which readable data is stored (step S104).

[0255] Also, if the memory location for which the foggy program operation should be executed next after the foggy program operation for the memory location determined to store unreadable data in step S105 is not in the erased state (No in step S106), the controller 5 determines that the previous write operation of the memory system 3 was not normally stopped (step S109). The controller 5 recognizes that the previous power-off of the memory system 3 occurred between the start of the foggy program operation for the memory location determined not to be in the erased state in step S106 and the completion of the fine program operation for the memory location for which the fine program operation should be executed next after the fine program operation for the memory location specified in step S104. Therefore, the controller 5 determines that the previous write operation of the memory system 3 was not normally stopped. In this case, there may be a memory location in the program interrupted state in the block assigned as the write destination block.

[0256] In this case, the first condition is not satisfied. Therefore, the controller 5 determines the block assigned to the write destination block as an unusable block (step S110). The controller 5 registers this block as an unusable block in the block management table 72.

[0257] The controller 5 allocates another block as the new write destination block (step S111). The controller 5 selects another block from the free block list 73. Then, the controller 5 allocates this selected another block as the write destination block.

[0258] The controller 5 determines the first storage position among the plurality of storage positions included in the block allocated to the write destination block, that is, one of the storage positions connected to the first word line, as the next write destination position (step S112).

[0259] Basically, regardless of whether the previous power-off was an abnormal power-off in which the power supply was suddenly cut off or a power-off executed after receiving a shutdown notification from the host 2, the controller 5 can execute the abnormal power-off determination process each time the power supply is resumed.

[0260] Note that the controller 5 may execute the abnormal power-off determination process in response to the resumption of power supply only when the previous power-off was an abnormal power-off. When receiving a shutdown notification from the host 2, the controller 5 performs shutdown preparation processing including processing for saving necessary data in the NAND memory 6. Therefore, the controller 5 determines, in response to the resumption of power supply, for example, whether information indicating that the shutdown preparation processing has been completed is stored in the NAND memory 6, and may determine that the previous power-off was an abnormal power-off when the information indicating that the shutdown preparation processing has been completed is not stored in the NAND memory 6.

[0261] Next, the procedure of the data writing operation for the write destination block will be described. FIG. 29 is a flowchart showing the procedure of the data writing operation executed in the memory system 3 according to the first embodiment.

[0262] The controller 5 determines whether the data to be written to the write destination block is ready (step S21). For example, the controller 5 determines whether the size of the data to be written has reached the size of the write unit. The size of the write unit is the size of the data to be written to one memory location (memory cell group MG) of the write destination block. When writing data to the write destination block in QLC mode, the size of the write unit is the size of 4 pages.

[0263] If the data to be written to the write destination block is not ready (No in step S21), the controller 5 waits until the data to be written to the write destination block is ready.

[0264] If the data to be written to the write destination block is ready (Yes in step S21), the controller 5 determines whether the next write destination memory location is the memory location connected to the first word line of the write destination block (step S22).

[0265] If the next write destination memory location is not the memory location connected to the first word line of the write destination block (No in step S22), the controller 5 executes a fog program operation on the next write destination memory location (step S23).

[0266] The controller 5 executes a fine program operation on the memory location where the fine program operation has become executable by the fog program operation executed in step S23 (step S24).

[0267] When the next write destination memory location is the memory location connected to the word line at the head of the write destination block (Yes in step S22), the controller 5 determines whether the total size of the data to be written to the write destination block has reached the size at which the fine program operation can be executed (step S25). For example, when the write destination block includes four string units SU, the size at which the fine program operation can be executed is the data size for five memory locations (five memory cell groups MG). Therefore, when writing data in the QLC mode to the write destination block, the size at which the fine program operation can be executed is the size for 20 pages.

[0268] When the total size of the data to be written to the write destination block has not reached the size at which the fine program operation can be executed (No in step S25), the controller 5 waits until the total size of the data to be written to the write destination block reaches the size at which the fine program operation can be executed. In this case, the process by the controller 5 returns to step S25.

[0269] When the total size of the data to be written to the write destination block has reached the size at which the fine program operation can be executed (Yes in step S25), the controller 5 executes the foggy program operation until the fine program operation can be executed (step S23). That is, the controller 5 executes the foggy program operation for one or more memory locations connected to the word line at the head of the write destination block and the foggy program operation for one memory location connected to the word line following the head word line.

[0270] Then, the controller 5 executes the fine program operation for the memory location for which the fine program operation has become executable by the foggy program operation executed in step S23 (step S24).

[0271] Thus, in the first embodiment, the controller 5 can determine whether the previous write operation has stopped normally by using the rule of executing the foggy program operation and the fine program operation that becomes executable by the completion of this foggy program operation as a series of program operations, and thereby can appropriately determine the next write destination position.

[0272] Next, in the first embodiment, a method for determining whether the storage position where the fine program operation in a series of program operations should be executed is in the foggy program state or in the program interruption state where power-off occurred during the execution of the fine program operation will be described.

[0273] For example, in the case of FIG. 18, MG(WL N+1, SU2) is a storage position where it cannot be determined whether it is in the foggy program state or in the program interruption state where power-off occurred during the execution of the fine program operation.

[0274] When it is determined that the foggy program operation for MG(WL N+2, SU2) and the fine program operation for MG(WL N+1, SU2) cannot be completed as a series of program operations, the controller 5 may execute the following operations.

[0275] The controller 5 executes the fine program operation for MG(WL N+1, SU2). When the fine program operation for MG(WL N+1, SU2) is completed, the controller 5 determines whether it can normally read data from MG(WL N+1, SU2). If it can normally read data from MG(WL N+1, SU2), the controller 5 can determine that MG(WL N+1, SU2) was in the foggy program state when the previous write operation stopped.

[0276] Next, in the first embodiment, a countermeasure for enabling a series of program operations to be completed even if an abnormal power-off occurs during the execution of a write operation will be described.

[0277] As shown by the dashed line in FIG. 1, the memory system 3 may further include a capacitor 81. The capacitor 81 is an element that can store electric power. The capacitor 81 is electrically connected to the power supply circuit 8. When the value of the power supply voltage supplied from the host 2 decreases due to an abnormal power-off, the power supply circuit 8 supplies the electric power stored in the capacitor 81 to each component of the memory system 3.

[0278] When an abnormal power-off occurs, the controller 5 uses the electric power from the capacitor 81 to continue the write operation at least until the execution of the series of program operations in progress is completed. For example, in the case of FIG. 16, an abnormal power-off occurs during the execution of the foggy program operation for MG(WL N+2, SU2). In this case, the controller 5 uses the electric power from the capacitor 81 to continue the foggy program operation for MG(WL N+2, SU2). When the foggy program operation for MG(WL N+2, SU2) is completed, the controller 5 uses the electric power from the capacitor 81 to execute the fine program operation for MG(WL N+1, SU2). Thereby, the series of program operations is completed.

[0279] Also, for example, in the case of FIG. 17, an abnormal power-off occurs during the execution of the fine program operation for MG(WL N+1, SU2). In this case, the controller 5 uses the electric power from the capacitor 81 to continue the fine program operation for MG(WL N+1, SU2). Thereby, the series of program operations is completed.

[0280] Also, for example, in the case of FIG. 18, an abnormal power-off occurs between the completion of the foggy program operation for MG(WL N+2, SU2) and the start of the fine program operation for MG(WL N+1, SU2). In this case, the controller 5 uses the power from the capacitor 81 to execute the fine program operation for MG(WL N+1, SU2). As a result, a series of program operations is completed.

[0281] Next, in the first embodiment, an operation of writing information indicating a storage location where the writing operation was interrupted using the power from the capacitor 81 into the NAND memory 6 will be described.

[0282] For example, in the case of FIG. 16, an abnormal power-off occurs during the execution of the foggy program operation for MG(WL N+2, SU2). In this case, the controller 5 uses the power from the capacitor 81 to write information indicating MG(WL N+2, SU2) where the writing was interrupted into the NAND memory 6.

[0283] Also, for example, in the case of FIG. 17, an abnormal power-off occurs during the execution of the fine program operation for MG(WL N+1, SU2). In this case, the controller 5 uses the power from the capacitor 81 to write information indicating MG(WL N+1, SU2) where the writing was interrupted into the NAND memory 6.

[0284] Also, for example, in the case of FIG. 18, an abnormal power-off occurs between the completion of the foggy program operation for MG(WL N+2, SU2) and the start of the fine program operation for MG(WL N+1, SU2). In this case, the controller 5 writes information indicating that the writing operation was interrupted between the foggy program operation for MG(WL N+2, SU2) and the fine program operation for MG(WL N+1, SU2) into the NAND memory 6.

[0285] By writing information regarding the memory location where the write operation was interrupted into the NAND memory 6 in this manner, it is possible to easily determine whether the previous write operation stopped normally or not.

[0286] (Second Embodiment) The second embodiment will be described. FIG. 30 is a block diagram showing a configuration example of the information processing system 1 including the memory system 3 according to the second embodiment.

[0287] Almost all the components included in the memory system 3 according to the second embodiment are the same as those of the memory system 3 according to the first embodiment described with reference to FIG. 1. Therefore, the differences from the memory system 3 according to the first embodiment will be described with attention.

[0288] In the memory system 3 according to the second embodiment, the controller 5 further manages foggy program management information 76. The foggy program management information 76 is stored in, for example, the DRAM 7.

[0289] The foggy program management information 76 is information indicating the memory locations in the foggy program state among the plurality of memory locations included in the block assigned to the write destination block. Specifically, the foggy program management information 76 indicates each memory location where the foggy program operation has been completed and the fine program operation has not been started.

[0290] Next, the operation of updating the foggy program management information 76 in response to the completion of the foggy program operation will be described. FIG. 31 is a diagram showing the foggy program operation executed in the memory system 3 according to the second embodiment.

[0291] As shown in the initial state in FIG. 31, the MG(WL N, SU0) connected to the word line WL N is in the fine programming state. The other three MGs(WL N, SU1), (WL N, SU2), (WL N, SU3) connected to the word line WL N are in the foggy programming state. Also, the MG(WL N+1, SU0) connected to the word line WL N+1 is also in the foggy programming state. Therefore, as shown in the initial state in FIG. 31, the foggy programming management information 76 manages information indicating MG(WL N, SU1) to MG(WL N, SU3) and information indicating MG(WL N+1, SU0).

[0292] Step 1: The controller 5 executes, for example, a foggy programming operation on MG(WL N+1, SU1).

[0293] Step 2: In response to the completion of the foggy programming operation, the controller 5 updates the foggy programming management information 76 stored in the DRAM 7. The controller 5 adds information indicating the storage location where the foggy programming operation has been completed, that is, information indicating MG(WL N+1, SU1), to the foggy programming management information 76.

[0294] Step 3: The controller 5 writes the updated foggy programming management information 76 to the NAND memory 6.

[0295] In this way, the controller 5 updates the foggy programming management information 76 in response to the completion of the foggy programming operation. Then, the controller 5 stores the updated latest foggy programming management information 76 in the NAND memory 6.

[0296] In this way, after the foggy program operation is completed, the foggy program management information 76 is updated and written to the NAND memory 6. Therefore, for example, if a power failure occurs during the execution of the foggy program operation for MG(WL N+1, SU1), the information indicating this MG(WL N+1, SU1) is not registered in the foggy program management information 76. Therefore, when the power supply to the memory system 3 is resumed, the controller 5 can correctly determine each storage position of the foggy program state in the block assigned to the write destination block at the time of power failure by reading the foggy program management information 76 from the NAND memory 6. Then, the controller 5 can determine that the MG(WL N+1, SU1) storing unreadable data is in a program interrupted state. Therefore, the controller 5 can determine that the previous write operation did not stop normally.

[0297] Next, the operation of updating the foggy program management information 76 before starting the fine program operation will be described. FIG. 32 is a diagram showing the fine program operation executed in the memory system 3 according to the second embodiment. Here, it is assumed that after the state shown in FIG. 31, the fine program operation for MG(WL N, SU1) is started.

[0298] Step 1: Before starting the fine program operation for MG(WL N, SU1), the controller 5 updates the foggy program management information 76. That is, the controller 5 deletes the information indicating MG(WL N, SU1) for which the fine program operation will be executed next from the foggy program management information 76.

[0299] Step 2: The controller 5 writes the updated foggy program management information 76 to the NAND memory 6.

[0300] Step 3: The controller 5 executes the fine program operation for MG(WL N, SU1).

[0301] Thus, before starting the fine program operation for a certain memory location, the controller 5 updates the foggy program management information 76 so that the information indicating this memory location is deleted from the foggy program management information 76. Then, the controller 5 stores the updated latest foggy program management information 76 in the NAND memory 6.

[0302] If a power-off occurs during the execution of the fine program operation for MG(WL N, SU1), this MG(WL N, SU1) enters the program interrupted state instead of the foggy program state. This MG(WL N, SU1) has already been deleted from the foggy program management information 76. Therefore, even if a power-off occurs during the execution of the fine program operation, when the power supply to the memory system 3 is resumed, the controller 5 can correctly determine the foggy program state of each memory location in the block assigned to the write destination block at the time of power-off by reading the foggy program management information 76 from the NAND memory 6.

[0303] Therefore, based on the foggy program management information 76, the controller 5 can correctly determine whether each memory location storing unreadable data is in the foggy program state or the program interrupted state. Therefore, the controller 5 can correctly determine whether there is a memory location in the program interrupted state in the block assigned to the write destination block at the time of power-off. If it is determined that there is no memory location in the program interrupted state in the block, the controller 5 continues the data writing operation for this block.

[0304] Specifically, when the power supply to the memory system 3 is resumed, the controller 5 can execute the following abnormal power-off determination process.

[0305] The controller 5 reads the foggy program management information 76 from the NAND memory 6. The controller 5 refers to the foggy program management information 76 to check the status of the foggy program in the write destination block. Here, assume that the foggy program management information 76 shown in FIG. 32 is stored in the NAND memory 6. In the foggy program management information 76 shown in FIG. 32, MG(WL N, SU2), MG(WL N, SU3), MG(WL N+1, SU0), and MG(WL N+1, SU1) are the storage locations of the foggy program status. Also, MG(WL N, SU2) is the oldest storage location having the foggy program status. And MG(WL N+1, SU1) is the newest storage location having the foggy program status.

[0306] The controller 5 determines whether the second condition is satisfied, that is, (2-A) the storage location (MG(WL N, SU1)) where the foggy program operation was executed immediately before the foggy program operation for the oldest storage location (MG(WL N, SU2)) having the foggy program status indicated by the foggy program management information 76 stores readable data, (2-B) each of the storage locations (MG(WL N, SU2), MG(WL N, SU3), MG(WL N+1, SU0), and MG(WL N+1, SU1)) indicated by the foggy program management information 76 stores unreadable data, and (2-C) the storage location (MG(WL N+1, SU2)) where the foggy program operation should be executed next after the foggy program operation for the newest storage location (MG(WL N+1, SU1)) having the foggy program status indicated by the foggy program management information 76 is in the erased state.

[0307] If this condition is satisfied, the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, and determines MG(WL N+1, SU2) as the next write destination location.

[0308] If this condition is not satisfied, the controller 5 determines that the previous write operation of the memory system 3 has not stopped normally and there is a storage location in the write destination block in a program interrupted state, and allocates a new block as the write destination block.

[0309] Next, when the number of string units included in each block is one, the operation of updating the foggy program management information 76 in response to the completion of the foggy program operation will be described. FIG. 33 is a diagram showing the foggy program operation when the number of string units included in each block is one, which is executed in the memory system 3 according to the second embodiment.

[0310] In the example shown in FIG. 33, MG(WL0) to MG(WL6) are in the fine program state. MG(WL7) is in the foggy program state. Therefore, information indicating MG(WL7) is managed in the foggy program management information 76.

[0311] Step 1: The controller 5 executes a foggy program operation on, for example, the storage location connected to the word line WL8.

[0312] Step 2: In response to the completion of the foggy program operation, the controller 5 updates the foggy program management information 76 stored in the DRAM 7. The controller 5 adds information indicating the storage location where the foggy program operation has been completed, that is, information indicating MG(WL8), to the foggy program management information 76.

[0313] Step 3: The controller 5 writes the updated foggy program management information 76 to the NAND memory 6.

[0314] Next, when the number of string units included in each block is one, the operation of updating the fog program management information 76 before starting the fine program operation will be described. FIG. 34 is a diagram showing the fine program operation when the number of string units included in each block is one, which is executed in the memory system 3 according to the second embodiment. Here, it is assumed that after the state shown in FIG. 33, the fine program operation for MG(WL7) is started.

[0315] Step 1: Before starting the fine program operation for MG(WL7), the controller 5 updates the fog program management information 76. The controller 5 then deletes from the fog program management information 76 the information indicating MG(WL7) for which the next fine program operation will be executed.

[0316] Step 2: The controller 5 writes the updated fog program management information 76 to the NAND memory 6.

[0317] Step 3: The controller 5 executes the fine program operation for MG(WL7).

[0318] In this way, even when the number of string units included in each block is one, the controller 5 updates the fog program management information 76 and writes it to the NAND memory 6 in the same manner as when the number of string units included in each block is two or more.

[0319] Next, the process of updating the fog program management information 76 will be described. FIG. 35 is a flowchart showing the procedure of updating and storing the fog program management information 76 in response to the completion of the fog program operation, which is executed in the memory system 3 according to the second embodiment.

[0320] First, the controller 5 determines whether the fog program operation for a certain storage location has been completed (step S31).

[0321] When the foggy program operation is not completed (No in step S31), the controller 5 waits until the foggy program operation is completed.

[0322] When the foggy program operation is completed (Yes in step S31), the controller 5 updates the foggy program management information 76 (step S32). The controller 5 adds information indicating the storage location that has become the foggy program state due to the completion of the foggy program operation to the foggy program management information 76.

[0323] The controller 5 writes the foggy program management information 76 updated in step S32 to the NAND memory 6 (step S33). As a result, the updated foggy program management information 76 is stored in the NAND memory 6. The updated foggy program management information 76 may be written to, for example, an SLC block.

[0324] FIG. 36 is a flowchart showing the procedure of processing for updating and storing the foggy program management information 76 before starting the fine program operation executed in the memory system 3 according to the second embodiment.

[0325] First, the controller 5 determines whether a fine program operation for any storage location is executable (step S41).

[0326] When the fine program operation is not executable (No in step S41), the controller 5 waits until the fine program operation becomes executable.

[0327] When the fine program operation is executable (Yes in step S41), the controller 5 updates the foggy program management information 76 (step S42). The controller 5 deletes information indicating the storage location where the executable fine program operation is to be executed from the foggy program management information 76.

[0328] The controller 5 writes the foggy program management information 76 updated in step S42 to the NAND memory 6 (step S43). Thereby, the updated foggy program management information 76 is stored in the NAND memory 6.

[0329] Then, the controller 5 executes the fine program operation (step S44).

[0330] Next, the abnormal power-off determination process will be described. FIG. 37 is a flowchart showing the procedure of the abnormal power-off determination process executed in the memory system 3 according to the second embodiment.

[0331] When the power supply to the memory system 3 is resumed, the controller 5 reads the foggy program management information 76 from the NAND memory 6 (step S502).

[0332] The controller 5 acquires the foggy program status of the write destination block from the foggy program management information 76 read in step S502 (step S503).

[0333] The controller 5 refers to the foggy program management information 76 to check the foggy program status of the write destination block (step S504). Specifically, the controller 5 identifies the oldest storage location with the foggy program status and the newest storage location with the foggy program status from the foggy program management information 76. Then, the controller 5 determines whether the second condition is satisfied, that is, (1) the storage location where the foggy program operation was executed one before the foggy program operation for the oldest storage with the foggy program status stores readable data, (2) each storage location indicated by the foggy program management information 76 stores unreadable data, and (3) the storage location where the foggy program operation should be executed next after the foggy program operation for the newest storage location with the foggy program status is in the erase state.

[0334] When the second condition is satisfied (Yes in step S504), the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, that is, there is no storage location in the program interruption state in the block assigned as the write destination block (step S505).

[0335] The controller 5 determines the next write destination position based on the foggy program management information 76 read in step S502 (step S506). The storage location where the foggy program operation should be executed next after the foggy program operation for the newest storage location with the foggy program status is determined as the next write destination position.

[0336] When the second condition is not satisfied (No in step S504), the controller 5 determines that the previous write operation of the memory system 3 was not normally stopped (step S507).

[0337] The controller 5 registers, in the block management table 72, the block assigned to the write destination block as a non - available block (step S508).

[0338] The controller 5 assigns another block as a new write destination block (step S509). The controller 5 selects another block from the free block list 73 and assigns the selected block as the write destination block.

[0339] The controller 5 determines the storage position at the head of another block as the next write destination position (step S510).

[0340] Basically, regardless of whether the previous power - off was an abnormal power - off in which the power supply was suddenly cut off or a power - off executed after receiving a shutdown notification from the host 2, the controller 5 can execute the abnormal power - off determination process each time the power supply is resumed.

[0341] Note that the controller 5 may execute the abnormal power - off determination process in response to the resumption of power supply only when the previous power - off was an abnormal power - off.

[0342] As described above, in the memory system 3 according to the second embodiment, using the foggy program management information 76 written in the NAND memory 6, the controller 5 can determine whether the previous write operation was normally stopped, and thereby can appropriately determine the next write destination position.

[0343] (Third Embodiment) In the memory system 3 according to the third embodiment, a configuration for reducing the number of times of writing the foggy program management information 76 to the NAND memory 6 is adopted.

[0344] Specifically, in the memory system 3 according to the third embodiment, the fog program management information 76 is written into the NAND memory 6 only in the case of abnormal power-off where the power supply to the memory system 3 is cut off without notification from the host 2.

[0345] First, the configuration of the memory system 3 according to the third embodiment will be described. FIG. 38 is a diagram showing a configuration example of the information processing system 1 including the memory system 3 according to the third embodiment.

[0346] Almost all the components included in the memory system 3 according to the third embodiment are the same as those of the memory system 3 according to the second embodiment described with reference to FIG. 30. Therefore, the differences will be described with attention.

[0347] The memory system 3 according to the third embodiment further includes a capacitor 81.

[0348] When an abnormal power-off occurs, the controller 5 executes a process of storing the fog program management information 76 in the NAND memory 6 using the power from the capacitor 81.

[0349] Next, the fog program operation and the operation of writing the fog program management information 76 into the NAND memory 6 will be described. FIG. 39 is a diagram showing the fog program operation and the process of storing the fog program management information in the NAND memory 6 executed in the memory system 3 according to the third embodiment.

[0350] Step 1: The controller 5 executes, for example, a fog program operation on MG(WL N+1, SU1).

[0351] Step 2: In response to the completion of the fog program operation, the controller 5 updates the fog program management information 76 stored in the DRAM 7. The controller 5 adds information indicating MG(WL N+1, SU1) for which the fog program operation has been completed to the fog program management information 76.

[0352] Also, similar to the second embodiment, before starting the fine-program operation for a certain memory location, the controller 5 updates the fog-program management information 76 stored in the DRAM 7 so that the information indicating this memory location is deleted.

[0353] When the controller 5 detects that an abnormal power-off has occurred, it writes the fog-program management information 76 stored in the DRAM 7 to the NAND memory 6. At this time, the controller 5 and the NAND memory 6 operate using the power stored in the capacitor 81. After writing the fog-program management information 76 to the NAND memory 6, the controller 5 controls the power circuit 8 to stop the operation of the memory system 3.

[0354] Then, when the power supply to the memory system 3 is resumed, the controller 5 reads the fog-program management information 76 from the NAND memory 6.

[0355] Next, the process of managing the fog-program management information 76 will be described. FIG. 40 is a flowchart showing the procedure of the process for managing the fog-program management information executed in the memory system 3 according to the third embodiment.

[0356] First, the controller 5 determines whether an abnormal power-off has occurred (step S61).

[0357] If an abnormal power-off has occurred (Yes in step S61), the controller 5 writes the fog-program management information 76 stored in the DRAM 7 to the NAND memory 6 (step S62).

[0358] If an abnormal power-off has not occurred (No in step S61), the controller 5 determines whether the fog-program operation is executable (step S63).

[0359] When the foggy program operation is not executable (No in step S63), the controller 5 waits until the foggy program operation becomes executable or an abnormal power-off occurs.

[0360] When the foggy program operation is executable (Yes in step S63), the controller 5 executes the foggy program operation (step S64).

[0361] Then, in response to the completion of the foggy program operation, the controller 5 updates the foggy program management information 76 (step S65). The controller 5 adds information indicating the storage location where the foggy program operation has been completed to the foggy program management information 76.

[0362] The controller 5 determines whether the fine program operation is executable (step S66).

[0363] When the fine program operation is not executable (No in step S66), the controller 5 waits until the fine program operation becomes executable.

[0364] When the fine program operation is executable (Yes in step S66), before starting the fine program operation, the controller 5 updates the foggy program management information 76 (step S67). The controller 5 deletes information indicating the storage location where the fine program operation is to be executed from the foggy program management information 76.

[0365] The controller 5 executes the fine program operation (step S68). Then, the processing by the controller 5 returns to step S61.

[0366] Thus, in the memory system 3 according to the third embodiment, in the same manner as in the second embodiment, the controller 5 can determine whether the previous write operation has stopped normally.

[0367] Furthermore, by using the capacitor 81, the foggy program management information 76 is written into the NAND memory 6 only when an abnormal power cut occurs, so that the frequency of the operation of writing the foggy program management information 76 into the NAND memory 6 can be reduced as compared with the case where the foggy program management information 76 is written into the NAND memory 6 every time the foggy program management information 76 is updated. Therefore, the influence on the write amplification and the I / O performance can be suppressed.

[0368] (Fourth Embodiment) Since the components of the memory system 3 according to the fourth embodiment are the same as those of the memory system 3 according to the third embodiment described in FIG. 38, the description thereof will be omitted.

[0369] The data writing operation executed in the memory system 3 according to the fourth embodiment will be described. In the memory system 3 according to the fourth embodiment, when an abnormal power cut occurs, a writing operation is executed to transition all the storage positions in the foggy program state to the fine program state using the power stored in the capacitor 81. FIG. 41 is a diagram showing an additional writing operation for transitioning the threshold voltage of a memory cell from the foggy program state to the fine program state, which is executed in the memory system 3 according to the embodiment.

[0370] As shown in FIG. 41(a), for the storage positions in the foggy program state where the foggy program operation has been executed and the fine program operation has not been executed yet, the threshold voltages of each of the plurality of memory cells included therein are set with a rough accuracy that cannot normally read data.

[0371] In the memory system 3 according to the fourth embodiment, when an abnormal power cut occurs while there are storage positions in the foggy program state, the controller 5 uses the power stored in the capacitor 81 to execute a fine program operation on the storage positions in the foggy program state.

[0372] As shown in FIG. 41(b), each of the plurality of memory cells included in the storage location of the fine program state has a threshold voltage corresponding to the data value to be stored in each memory cell.

[0373] Next, a block in which a data writing operation is executed when an abnormal power-off occurs will be described. FIG. 42 is a diagram showing the state of each storage location of the block when an abnormal power-off occurs and the state of each storage location of the block after an additional writing operation is executed in the memory system 3 according to the fourth embodiment.

[0374] FIG. 42(a) shows the state of each storage location of the block when an abnormal power-off occurs. Here, it is assumed that an abnormal power-off occurs between the completion of the fog program operation for MG(WL N+2, SU2) and the completion of the fine program operation for MG(WL N+1, SU2).

[0375] When an abnormal power-off occurs, the controller 5 executes an additional writing operation to change each storage location in the fog program state included in the write destination block to the fine program state using the power stored in the capacitor 81.

[0376] In order to execute a fine program operation for the storage locations included in each string unit connected to a certain word line, it is necessary to perform a fog program operation for the storage locations included in the same string unit connected to the next word line following this word line. In the example of the additional writing operation shown in FIG. 42(a), after the controller 5 completes the fine program operation for MG(WL N+1, SU2), it performs a fog program operation for MG(WL N+2, SU3). In this case, dummy data may be written to MG(WL N+2, SU3).

[0377] (b) of FIG. 42 shows the state of each memory location of the write destination block after the additional write operation is executed. As shown in (b) of FIG. 42, all the memory locations included in the write destination block become in the fine program state. Since the write destination block is full, the controller 5 registers this write destination block in the QLC active block list 75.

[0378] Then, when the power supply to the memory system 3 is resumed, the controller 5 selects another block from the free block list 73 and assigns the selected block as a new write destination block. Then, the controller 5 determines the memory location at the head of the new write destination block as the next write destination location.

[0379] Next, the procedure of the data write operation at the time of abnormal power-off will be described. FIG. 43 is a flowchart showing the procedure of the data write operation at the time of abnormal power-off executed in the memory system 3 according to the fourth embodiment.

[0380] First, the controller 5 determines whether an abnormal power-off has occurred (step S71).

[0381] If an abnormal power-off has not occurred (No in step S71), the controller 5 waits until an abnormal power-off occurs.

[0382] If an abnormal power-off has occurred (Yes in step S71), the controller 5 executes an additional write operation (step S72). The controller 5 continues the additional write operation until the fine program operation for all the memory locations included in the write destination block is completed and the write destination block becomes full.

[0383] As described above, in the memory system 3 according to the fourth embodiment, when an abnormal power-off occurs, the controller 5 continues the additional writing operation until the write destination block is full. Therefore, when the power supply to the memory system 3 is resumed, the controller 5 does not need to determine whether the previous power-off was an abnormal power-off.

[0384] (Fifth Embodiment) Since the components of the memory system 3 according to the fifth embodiment are the same as those of the memory system 3 according to the first embodiment described in FIG. 1, the description thereof is omitted.

[0385] In the fifth embodiment, the controller 5 writes a flag (foggy flag) to at least one memory cell for storing a management flag among a plurality of memory cells included in the storage location. The foggy flag is information indicating that this storage location is in the foggy program state.

[0386] First, the foggy flag will be described. FIG. 44 is a diagram showing the threshold voltage distribution of a plurality of memory cells included in a storage location in the foggy program state in the memory system 3 according to the fifth embodiment, and the threshold voltage distribution of a plurality of memory cells included in a storage location in the program interruption state where a power-off occurred during the execution of the foggy program operation.

[0387] Each of the plurality of storage locations included in each block includes a plurality of memory cells for storing data and at least one memory cell for storing management information. Hereinafter, at least one memory cell for storing management information is referred to as a redundant memory cell.

[0388] In response to the completion of the foggy program operation for a certain storage location, the controller 5 writes a foggy flag to the redundant memory cell included in that storage location.

[0389] The threshold voltage of the redundant memory cell written with the foggy flag is higher than the threshold voltage range used in the foggy fine-program operation. That is, in response to the completion of the foggy program operation for a certain storage location, the controller 5 sets the threshold voltage of the redundant memory cell included in that storage location to be higher than the threshold voltage range used in the foggy fine-program operation, thereby writing the foggy flag to the redundant memory cell.

[0390] FIG. 44(a) shows the threshold voltage distribution of a plurality of memory cells included in the storage location where the foggy program operation has been completed. The threshold voltage distribution of the plurality of memory cells included in the storage location where the foggy program operation has been completed is set to a rough accuracy that makes it impossible to normally read the data. And the threshold voltage of the redundant memory cell among the plurality of memory cells is set higher than the threshold voltage range used in the foggy fine-program operation. Specifically, the threshold voltage of the redundant memory cell written with the foggy flag is set to a value higher than the foggy flag threshold voltage and lower than the fine flag threshold voltage. The foggy flag threshold voltage is higher than, for example, Vr16 described with reference to FIG. 6.

[0391] The controller 5 can determine that the foggy flag is written in this storage location by, for example, confirming that there is a memory cell having a threshold voltage equal to or higher than the foggy flag threshold voltage in this storage location and there is no memory cell having a threshold voltage equal to or higher than the fine flag threshold voltage.

[0392] In this way, the storage location where the foggy program operation has been completed stores unreadable data and further stores the foggy flag. Therefore, the controller 5 can determine that the storage location where the foggy flag exists and the data cannot be normally read is the storage location in the foggy program state.

[0393] (b) of FIG. 44 shows the threshold voltage distribution of a plurality of memory cells included in a memory location where power-off occurred during the execution of the foggy program operation. The foggy flag is not written in the redundant memory cells of this memory location. Therefore, the threshold voltages of all the memory cells included in this memory location are within the threshold voltage range used in the foggy fine program operation.

[0394] For example, the controller 5 can determine that the foggy flag is not written in this memory location by confirming that there is no memory cell having a threshold voltage equal to or higher than the foggy flag threshold voltage in this memory location.

[0395] As described above, the memory location where power-off occurred during the execution of the foggy program operation stores unreadable data but does not store the foggy flag. Therefore, the controller 5 can determine that a memory location where the foggy flag does not exist and data cannot be read normally is a memory location in the program interruption state, that is, a memory location where power-off occurred during the execution of the foggy program operation.

[0396] Next, the fine flag will be described. FIG. 45 is a diagram showing the threshold voltage distribution of a plurality of memory cells included in a memory location in the program interruption state where power-off occurred during the execution of the fine program operation and the threshold voltage distribution of a plurality of memory cells included in the memory location in the fine program state in the memory system 3 according to the fifth embodiment.

[0397] When the fine program operation for a certain memory location becomes executable, before starting the fine program operation, the controller 5 removes the fog flag from the redundant memory cells included in this memory location. Specifically, the controller 5 changes the threshold voltage of the redundant memory cells from the voltage corresponding to the fog flag threshold voltage to the voltage corresponding to the fine flag threshold voltage, thereby removing the fog flag from the redundant memory cells. The redundant memory cells having the threshold voltage corresponding to the fine flag threshold voltage are also referred to as the memory cells in which the fine flag is written. That is, the controller 5 writes the fine flag to the redundant memory cells, thereby removing the fog flag from the redundant memory cells.

[0398] Fig. 45(a) shows the threshold voltage distribution of a plurality of memory cells included in the memory location where power-off occurred during the execution of the fine program operation. In the redundant memory cells of this memory location, the fog flag is not written. That is, the memory location where power-off occurred during the execution of the fine program operation stores unreadable data and does not store the fog flag (while storing the fine flag). Therefore, the controller 5 can determine that the memory location where the fog flag does not exist and data cannot be read normally is the memory location in the program interruption state.

[0399] Also, the controller 5 may determine whether the fine flag exists. In this case, the controller 5 can also determine that the memory location where the fine flag exists and data cannot be read normally is the memory location where power-off occurred during the execution of the fine program operation.

[0400] Figure 45(b) shows the threshold voltage distribution of a plurality of memory cells included in a memory location where the fine program operation has been completed. In the redundant memory cells of this memory location, the foggy flag is not written. That is, the memory location where the fine program operation has been completed stores readable data and does not store the foggy flag (while storing the fine flag). The controller 5 determines that the memory location from which data can be read normally is a memory location in the fine program state.

[0401] In this way, the controller 5 can correctly determine the memory location in the foggy program state by checking the foggy flag of the memory location storing unreadable data. That is, based on whether the foggy flag is stored in each memory location storing unreadable data, the controller 5 can correctly determine whether each memory location storing unreadable data is in the foggy program state or the program interrupted state. Therefore, the controller 5 can correctly determine whether there is a memory location in the program interrupted state in the block assigned to the write destination block at the time of power-off. When it is determined that there is no memory location in the program interrupted state in the block, the controller 5 continues the data writing operation for this block.

[0402] Specifically, when the power supply to the memory system 3 is resumed, the controller 5 may execute the following abnormal power-off determination process.

[0403] After the power supply to the memory system 3 is cut off and then restored, when the power supply to the memory system 3 is resumed, the controller 5 identifies the storage location among the plurality of storage locations included in the write destination block where the data that became readable last is stored. Then, the controller 5 determines whether the third condition that (3-A) each of the first number of storage locations where a foggy program operation is executed next to the storage location where the data that became readable last is stored stores unreadable data and a foggy flag, and (3-B) the storage location where a foggy program operation should be executed next to the foggy program operation for the first number of storage locations is in an erased state, is satisfied.

[0404] The first number is determined based on the number of string units SU included in each block.

[0405] For example, when each block includes four string units SU, the first number is 4 (or 5). When each block includes one string unit SU, the first number is 1 (or 2).

[0406] Therefore, in the case where each block includes four string units SU, the controller 5 determines whether the third condition that each of the four or five storage locations where a foggy program operation should be executed next to the storage location where the data that became readable last is stored stores unreadable data and a foggy flag, and the storage location where a foggy program operation should be executed next to the foggy program operation for these four or five storage locations is in an erased state, is satisfied.

[0407] For example, similar to the example shown in FIG. 7, when the fine program operation for MG(WL1, SU2) is completed, it is the storage location where the data that was last made readable by MG(WL1, SU2) is stored. At this time, the storage location where the foggy program operation was executed next after the foggy program operation for MG(WL1, SU2) is MG(WL1, SU3). The controller 5 determines whether MG(WL1, SU3) stores unreadable data and a foggy flag. Furthermore, the controller 5 determines whether the three storage locations from MG(WL2, SU0) to MG(WL2, SU2) store unreadable data and a foggy flag. Here, the first number is four. Then, the controller 5 determines whether MG(WL2, SU3), which is the storage location where the foggy program operation should be executed next after the foggy program operation for MG(WL2, SU2), is in an erased state. Thereby, the controller 5 determines whether the third condition is satisfied.

[0408] Also, in the case where each block includes only one string unit SU, the controller 5 checks whether each of the one or two storage locations where the foggy program operation was executed next after the foggy program operation for the storage location where the data that was last made readable is stored contains unreadable data and a foggy flag, and whether the storage location where the foggy program operation should be executed next after the foggy program operation for these one or two storage locations is in an erased state.

[0409] Each storage location storing unreadable data and a foggy flag is a storage location in the foggy program state where the foggy program operation is completed and the fine program operation has not started.

[0410] Therefore, when this condition is satisfied, it can be determined that there is no storage location in the block assigned to the write destination block in the program interruption state. In this case, the controller 5 determines the storage location in the erase state where the foggy program operation should be executed next, following the foggy program operation for the storage location storing the unreadable data and the foggy flag, as the next write destination location.

[0411] Next, the foggy program operation will be described. FIG. 46 is a flowchart showing the procedure of the foggy program operation executed in the memory system 3 according to the fifth embodiment.

[0412] First, the controller 5 determines whether the foggy program operation for the storage location where the foggy program operation should be executed next is executable (step S81).

[0413] If the foggy program operation is not executable (No in step S81), the controller 5 waits until the foggy program operation becomes executable.

[0414] If the foggy program operation is executable (Yes in step S81), the controller 5 executes the foggy program operation for this storage location (step S82).

[0415] When the foggy program operation for this storage location is completed, the controller 5 writes the foggy flag to the redundant memory cell by setting the threshold voltage of the redundant memory cell at this storage location to the voltage corresponding to the foggy flag threshold voltage (step S83).

[0416] Next, the fine program operation will be described. FIG. 47 is a flowchart showing the procedure of the fine program operation executed in the memory system 3 according to the fifth embodiment.

[0417] First, the controller 5 determines whether a fine program operation can be executed for the memory location where the fine program operation is to be executed next (step S91).

[0418] If the fine program operation cannot be executed (No in step S91), the controller 5 waits until the fine program operation can be executed.

[0419] If the fine program operation can be executed (Yes in step S91), before starting the fine program operation for this memory location, the controller 5 removes the foggy flag from the redundant memory cell of this memory location (step S92). That is, the controller 5 changes the threshold voltage of this redundant memory cell to a voltage corresponding to the fine flag threshold voltage.

[0420] Then, the controller 5 executes the fine program operation for this memory location (step S93).

[0421] Next, the procedure of the abnormal power-off determination process will be described. FIG. 48 is a flowchart showing the procedure of the abnormal power-off determination process executed in the memory system according to the fifth embodiment.

[0422] When the power supply to the memory system 3 is resumed, the controller 5 acquires information indicating the write destination position from the NAND memory 6 (step S1002).

[0423] Then, the controller 5 specifies the last memory location where readable data is stored by executing data read operations for several memory locations starting from the memory location indicated by the acquired information (steps S1003 to S1005).

[0424] In this case, first, the controller 5 specifies the memory location indicated by the acquired information as the first memory location for which the data read operation is to be executed (step S1003).

[0425] The controller 5 determines whether the data written in the specified storage location is readable data (step S1004). If the data written in the specified storage location is readable data (Yes in step S1004), the controller 5 specifies the next storage location following the specified storage location (step S1005). Then, the process by the controller 5 returns to step S1004. In step S1004, the controller 5 determines whether the data written in the storage location specified in step S1005 is readable data.

[0426] If the storage location following the storage location storing the readable data stores unreadable data, the controller 5 determines that the storage location storing the readable data is the last storage location where the readable data is stored.

[0427] When the last storage location where the readable data is stored is determined, the controller 5 determines whether the storage location following this last storage location where the readable data is stored, that is, the storage location where the foggy program operation is executed next with respect to this last storage location, is in the foggy program state (steps S1006 to S1009).

[0428] If the subsequent storage location stores unreadable data and stores a fog flag, it can be determined that this subsequent storage location is in the foggy program state. Here, the fact that the subsequent storage location stores unreadable data has already been confirmed in step S1004. Therefore, the controller 5 only needs to determine whether the subsequent storage location stores a fog flag.

[0429] Alternatively, the controller 5 may first determine whether the subsequent memory location is in an erased state. In this case, when it is determined that the subsequent memory location is not in an erased state, the controller 5 may determine whether the subsequent memory location stores a foggy flag.

[0430] Here, as an example, the case where the controller 5 first determines whether the subsequent memory location is in an erased state and, when it is determined that the subsequent memory location is not in an erased state, determines whether the subsequent memory location stores a foggy flag will be described.

[0431] The controller 5 determines whether the subsequent memory location is in an erased state (step S1006). That is, the controller 5 determines whether there is a memory cell having a threshold voltage equal to or higher than the erase page threshold voltage in the subsequent memory location.

[0432] When the subsequent memory location is not in an erased state (No in step S1006), the controller 5 determines whether a flag is written in the subsequent memory location (step S1007). The controller 5 determines whether there is a memory cell having a threshold voltage equal to or higher than the foggy flag threshold voltage in a plurality of memory cells included in the subsequent memory location.

[0433] If a flag is written in a subsequent memory location (Yes in step S1007), the controller 5 determines whether the flag written in the subsequent memory location is either a foggy flag or a fine flag (step S1008). The controller 5 determines whether there is a memory cell having a threshold voltage equal to or higher than the fine flag threshold voltage in a plurality of memory cells included in the subsequent memory location. If there is a memory cell having a threshold voltage equal to or higher than the fine flag threshold voltage, the controller 5 determines that the flag written in the subsequent memory location is a fine flag. Also, if there is no memory cell having a threshold voltage equal to or higher than the fine flag threshold voltage, the controller 5 determines that the flag written in the subsequent memory location is a foggy flag.

[0434] If the flag written in the subsequent memory location is a foggy flag (foggy flag in step S1008), the controller 5 specifies a memory location subsequent to the subsequent memory location (step S1009). Then, the process by the controller 5 returns to step S1006. In step S1006, the controller 5 determines whether the memory location specified in step S1009 is in an erased state.

[0435] In this way, the controller 5 determines whether each of the first number of memory locations where a foggy programming operation is executed next to the foggy programming operation for the memory location storing the data that became finally readable stores unreadable data and a foggy flag.

[0436] A memory location subsequent to each of the first number of memory locations storing unreadable data and a foggy flag is specified in step S1009. Then, in step S1006, the controller 5 determines whether the memory location subsequent to the first number of memory locations is in an erased state.

[0437] If the subsequent memory location is in an erased state (Yes in step S1006), the controller 5 determines that the previous write operation of the memory system 3 was normally stopped, that is, there is no memory location in a program interrupted state in the block assigned as the write destination block (step S1010).

[0438] Then, the controller 5 determines the subsequent memory location as the next write destination location (step S1011).

[0439] If the subsequent memory location is not in an erased state (No in step S1006) and the foggy flag is not written to the subsequent memory location (No in step S1007 or fine flag in step S1008), the controller 5 determines that the previous write operation was not normally stopped (step S1012).

[0440] Also, in the process of determining whether each of the first number of memory locations stores unreadable data and a foggy flag, if the foggy flag is not written to the memory location to be determined (No in step S1007 or fine flag in step S1008), the controller 5 also determines that the previous write operation was not normally stopped (step S1012). That is, the controller 5 determines that there may be a memory location in a program interrupted state in the block assigned as the write destination block.

[0441] The controller 5 determines the write destination block as an unavailable block (step S1013).

[0442] The controller 5 assigns another block as a new write destination block (step S1014). The controller 5 selects another block from the free block list 73. Then, the controller 5 assigns the selected block as the write destination block.

[0443] The controller 5 determines the storage position at the head of another block as the next write destination position (step S1015). The controller 5 determines the storage position at the head of the block assigned to the write destination block in step S1014 as the next write destination position.

[0444] As described above, in the fifth embodiment, a foggy flag is written to at least one memory cell (redundant memory cell) among the plurality of memory cells included in each storage position. Then, after the power supply to the memory system 3 is cut off, in response to the resumption of the power supply to the memory system 3, the controller 5 determines that each of the first number of storage positions where the foggy program operation was executed next to the foggy program operation for the storage position storing the data that became readable last stores unreadable data and the foggy flag, and determines whether the condition that the storage position where the foggy program operation should be executed next to the foggy program operation for the first number of storage positions is in the erased state is satisfied. Thereby, the controller 5 can correctly determine whether the previous write operation was normally stopped.

[0445] Basically, regardless of whether the previous power-off was an abnormal power-off in which the power supply was suddenly cut off or a power-off executed after receiving a shutdown notification from the host 2, the controller 5 can execute the abnormal power-off determination process each time the power supply is resumed.

[0446] Note that the controller 5 may execute the abnormal power-off determination process in response to the resumption of the power supply only when the previous power-off was an abnormal power-off.

[0447] As described above, according to the first to fifth embodiments, even if the power supply to the memory system 3 is suddenly cut off due to an abnormal power-off during the execution of the first-stage program operation (foggy program operation) or the second-stage program operation (foggy program operation), the next write destination position can be correctly determined.

[0448] It should be noted that it is also possible to appropriately combine any two or more of the first to fifth embodiments.

[0449] Also, in the first to fifth embodiments, the case where after writing the data received from the host 2 into the SLC block, the data stored in the SLC block is written into the QLC block using a multi-stage program operation was described. However, the configurations of the first to fifth embodiments are not limited to this. For example, the data received from the host 2 may be written into the QLC block using a multi-stage program operation.

[0450] The last storage location where readable data is stored is the storage location where the second-stage program operation (i.e., the fine program operation) was last executed. Unreadable data is also referred to as data that cannot be read.

[0451] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0452] 1... Information processing system, 2... Host, 3... Memory system, 4... Bus, 5... Controller, 6... NAND flash memory, 7... DRAM, 8... Power supply circuit, 21... Processor, 22... Memory, 50... Internal bus, 51... Host interface, 52... CPU, 53... SRAM, 54... DMAC, 55... ECC circuit, 56... DRAM interface, 57... NAND interface, 71... L2P table, 72... Block management table, 73... Free block list, 74... SLC active block list, 75... QLC active block list.

Claims

1. A memory system comprising: a non-volatile memory including a plurality of blocks each being a unit of data erasure operation, each of the plurality of blocks including a plurality of storage locations, and each of the plurality of storage locations including a plurality of memory cells; and a controller electrically connected to the non-volatile memory and configured to execute a data writing operation to a write destination block among the plurality of blocks using a multi-stage programming operation including at least a first-stage programming operation and a second-stage programming operation; wherein writing of data to the plurality of storage locations included in the write destination block is executed in an order in which the first-stage programming operation for a first storage location of the write destination block is executed, after the first-stage programming operation for the first storage location is completed, the first-stage programming operation for a second storage location of the write destination block is executed, and in response to completion of the first-stage programming operation for the second storage location, the second-stage programming operation for the first storage location is executed; the controller is configured to: after power supply to the memory system is cut off, in response to power to the memory system being restored, identify a third storage location among the plurality of storage locations included in a first block among the plurality of blocks, where the second-stage programming operation was last executed; determine whether a first condition is satisfied, where data stored in a fourth storage location where the first-stage programming operation was executed before the second-stage programming operation for the third storage location is unreadable, and each of the plurality of memory cells included in a fifth storage location where the first-stage programming operation should be executed next after the first-stage programming operation for the fourth storage location has a threshold voltage corresponding to an erased state; and if the first condition is satisfied, determine the fifth storage location as the next write destination location. A memory system.

2. The controller is configured to: When the first condition is not satisfied, the first block is managed as an unavailable block, a second block among the plurality of blocks is assigned as a new write destination block, and a leading storage position among the plurality of storage positions included in the second block is determined as the next write destination position. The memory system according to claim 1.

3. Each of the plurality of blocks includes a plurality of word lines, and each of the plurality of word lines connects a plurality of the storage positions. The controller is When the first storage position and the second storage position are connected to a leading word line of the write destination block, wait until at least the first data to be written to the first storage position and the second data to be written to the second storage position are prepared, in response to the first data and the second data being prepared, execute the first-stage program operation for the first storage position and the first-stage program operation for the second storage position, configured to execute the second-stage program operation for the first storage position in response to at least the completion of the first-stage program operation for the second storage position. The memory system according to claim 1.

4. The controller is after the power supply to the memory system is cut off due to an abnormal power-off and the power to the memory system is restored, identify the third storage position, determine whether the first condition is satisfied, and when the first condition is satisfied, determine the fifth storage position as the next write destination position. The memory system according to claim 1.

5. A memory system, a non-volatile memory including a plurality of blocks each being a unit of a data erasing operation, each of the plurality of blocks including a plurality of storage positions, and each of the plurality of storage positions including a plurality of memory cells, a controller electrically connected to the non-volatile memory and configured to execute a data writing operation for a write destination block among the plurality of blocks using a multi-stage program operation including at least a first-stage program operation and a second-stage program operation. Writing data to the plurality of memory locations included in the write destination block is executed in the order that the first-stage program operation for the first memory location of the write destination block is executed, and after the first-stage program operation for the first memory location is completed, the first-stage program operation for the second memory location of the write destination block is executed, and in response to the completion of the first-stage program operation for the second memory location, the second-stage program operation for the first memory location is executed. The controller manages first information indicating each memory location having a first state in which the first-stage program operation has been completed and the second-stage program operation has not been started among the plurality of memory locations included in the first block among the plurality of blocks. In response to the completion of the first-stage program operation for one of the plurality of memory locations, the first information is updated so that information indicating the one memory location for which the first-stage program operation has been completed is added to the first information. Before starting the second-stage program operation for one of the plurality of memory locations, the first information is updated so that information indicating the one memory location for which the second-stage program operation is to be started is deleted from the first information. is configured to save the updated first information in the non-volatile memory. Memory system. **Claim 6** The controller after the power supply to the memory system is cut off, in response to the power to the memory system being restored, reads the first information from the non-volatile memory. A third storage location where the first-stage program operation was executed immediately before the first-stage program operation for the oldest storage location having the first state indicated by the first information stores readable data, each storage location indicated by the first information stores unreadable data, and each of a plurality of memory cells included in a fifth storage location where the first-stage program operation is to be executed next after the first-stage program operation for the newest fourth storage location having the first state indicated by the first information has a threshold voltage corresponding to an erased state. It is determined whether or not the second condition is satisfied, When the second condition is satisfied, it is configured to determine the fifth storage location as the next write destination location The memory system according to claim 5.

7. The controller, When the second condition is not satisfied, the first block is managed as an unavailable block, a second block among the plurality of blocks is assigned as a new write destination block, and the first storage location among the plurality of storage locations included in the second block is determined as the next write destination location. It is configured to The memory system according to claim 6.

8. The controller, After the power supply to the memory system is cut off due to an abnormal power cut, in response to the power to the memory system being restored, The first information is read from the non-volatile memory, It is determined whether or not the second condition is satisfied, When the second condition is satisfied, it is configured to determine the fifth storage location as the next write destination location. The memory system according to claim 6.

9. The memory system further includes a capacitor for storing the power supplied to the memory system, The controller, While the power is being supplied to the memory system, the updated first information is not saved in the non-volatile memory. When the power supply to the memory system is cut off, the power stored in the capacitor is used to save the updated first information in the non-volatile memory. It is configured to The memory system according to claim 5.

10. A memory system, A non-volatile memory including a plurality of blocks each being a unit of a data erasure operation, each of the plurality of blocks including a plurality of storage positions, each of the plurality of storage positions including a plurality of first memory cells for storing data and at least one second memory cell for storing management information, the non-volatile memory A controller electrically connected to the non-volatile memory and configured to execute a data writing operation for each of the plurality of first memory cells included in a write destination block among the plurality of blocks using a multi-stage program operation including at least a first-stage program operation and a second-stage program operation The writing of data to the plurality of storage positions included in the write destination block is executed in the order that the first-stage program operation for the first storage position of the write destination block is executed, after the first-stage program operation for the first storage position is completed, the first-stage program operation for the second storage position of the write destination block is executed, and in response to the completion of the first-stage program operation for the second storage position, the second-stage program operation for the first storage position is executed The controller In response to the completion of the first-stage program operation for each storage position among the plurality of storage positions included in the first block among the plurality of blocks, a first flag is written to the second memory cell by setting the threshold voltage of the second memory cell included in each storage position to a first voltage higher than a threshold voltage range used in the multi-stage program operation Before starting the second-stage program operation for each storage position among the plurality of storage positions, the first flag is removed from the second memory cell by changing the threshold voltage of the second memory cell included in each storage position from the first voltage to a second voltage higher than the first voltage Memory system

11. The controller After the power supply to the memory system is cut off, in response to the restoration of the power to the memory system Among the plurality of storage positions included in the first block, the third storage position where the second-stage program operation was last executed is specified Whether a third condition is satisfied, which is that a fourth storage location where the first-stage program operation was executed next to the first-stage program operation for the third storage location stores unreadable data and the first flag, and each of the plurality of first memory cells included in a fifth storage location where the first-stage program operation should be executed next to the first-stage program operation for the fourth storage location has a threshold voltage corresponding to an erased state. When the third condition is satisfied, it is configured to determine the fifth storage location as the next write destination location. The memory system according to claim 10.

12. The controller is When the third condition is not satisfied, it is configured to manage the first block as an unusable block, allocate a second block among the plurality of blocks as a new write destination block, and determine the first storage location among the plurality of storage locations included in the second block as the next write destination location. The memory system according to claim 11.

13. The controller is After the power supply to the memory system is cut off due to an abnormal power interruption, in response to the power to the memory system being restored, Identify the third storage location, Determine whether the third condition is satisfied, When the third condition is satisfied, it is configured to determine the fifth storage location as the next write destination location. The memory system according to claim 11.

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