Multi-channel multiplexer

Abstract

The circuit (400) includes a first switch assembly (111) having a first input node and a first output node, and a second switch assembly (112) having a second input node and a second output node. The circuit further includes a third switch assembly (430), an operational amplifier (130), and a buffer (410). The third switch assembly (430) has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer (410) has a buffer input and a buffer output. The buffer input is coupled to the input stage of the operational amplifier (130). The buffer output is coupled to the third switch assembly (430).

Description

Technical Field

[0001] Application examples include those that include a sensor processing system and a multiplexer. One or more sensors can be coupled to the multiplexer. The sensors are coupled to the processing system via the multiplexer. The multiplexer includes a plurality of channels, each channel potentially being coupled to a separate sensor. The processing system processes the signals from one sensor at a time. To receive and process the signal from a given sensor coupled to one of the multiple channels, a control signal to the multiplexer enables the channel corresponding to the desired sensor while disabling the remaining channels of the multiplexer.

Summary of the Invention

[0002] In one example, a circuit includes first, second, and third switch assemblies, a buffer, and a bulk bias circuit. The first switch assembly has a first input node and a first output node. The second switch assembly has a second input node and a second output node. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node. The third output node is coupled to the first output node. The third switch assembly includes a first transistor that includes a bulk. The buffer has a buffer input and a buffer output. The buffer input is coupled to the first output node and the buffer output is coupled to the third switch assembly. The bulk bias circuit is coupled to the bulk of the first transistor. The bulk bias circuit is configured to bias the bulk of the first transistor with a first bias voltage in response to the voltage on the input node exceeding a first voltage level and to bias the bulk of the first transistor with a second bias voltage in response to the voltage on the input node falling below a second voltage level.

[0003] For a detailed description of the various examples, reference is now made to the accompanying drawings.

Brief Description of the Drawings

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Figure 1

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Figure 2

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Figure 3

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Figure 4

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Figure 5

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Figure 6

Mode for Carrying Out the Invention

[0010] A multiplexer can include several independent channels that pass data from each input to a single output. In sensing applications, the multiplexer can pass data from a set of sensors coupled to the input to a processor coupled to the output. Control signals from a multiplexer controller enable one of the channels, while the channels corresponding to sensors not intended to be processed by the sensor processing system at a given time are disabled. Each channel of the multiplexer includes a solid-state switch (transistor) used to enable and disable the channel. When a transistor is "on," current can flow through that transistor. When the transistor is "off," the main conduction path (e.g., the channel of a metal-oxide-semiconductor field-effect transistor) is off, and generally no current flows. However, when the transistor is off, leakage current may flow through that transistor.

[0011] In many applications, the leakage current of the transistor is not a problem. However, in other applications, leakage current may be a problem. For example, in the above-described application where multiple sensors are coupled to a processing system via a multiplexer, even when the transistor is off for a disabled channel, leakage current may still flow through the transistor of that channel. If the output impedance of the sensor connected to that channel is large, due to the large output impedance of that sensor, even a small leakage current can cause a significant voltage across the entire sensor. The undesirably generated voltage in a disabled channel can modify (e.g., add to) the voltage generated by the sensor enabled for that channel, thereby undesirably changing the sensor signal intended to be processed.

[0012] The examples described in this specification relate to a multiplexer in which each channel of the multiplexer includes a plurality of metal oxide semiconductor field effect transistors (MOS transistors). One or more of the channels of the multiplexer bias the bulk of at least one of the MOS transistors to reduce leakage current that would otherwise exist due to the low amplitude voltage generated by a sensor on the enabled channel. Also, a buffer is provided whose input is coupled to the output of the multiplexer. The output of the buffer is coupled to one or more of the channels of the multiplexer. When a given channel is off, rather than grounding the internal node of that given channel, the internal node is coupled to the output voltage level of the multiplexer via the buffer. Thus, the drain-source potential difference across the MOS transistor in each “off” channel is approximately 0V, and therefore, even if a leakage current were to flow between the drain and source of the transistor, it would be very small.

[0013] FIG. 1 shows an example of a system 100 including a multiplexer (“mux”) circuit 110 coupled to an operational amplifier (“op-amp”) 130. The multiplexer circuit 110 includes a plurality of channels. In this example, the multiplexer circuit 110 includes five channels indicated by 101, 102, 103, 104, and 105. Each channel is coupled to a respective input, and the inputs of channels 101 - 105 are indicated by inp1, inp2, inp3, inp4, and inp5, respectively. A device such as a sensor can be connected to each channel input. In this example, five sensors (S1, S2, S3, S4, S5) can be coupled to the op-amp 130 via the multiplexer circuit 110. (In response to channel selection signal 139) via a control signal from the controller 140 to the multiplexer circuit 110, one channel is enabled (turned on) at a time and the remaining four channels are disabled (turned off). The signal from the sensor for which the channel is enabled is provided to node N1 via the multiplexer circuit 110 and thus to the non-inverting (+) input of the op-amp 130. The op-amp 130 has its output connected to its inverting (-) input and thus the op-amp 130 is configured for unity gain. Other configurations of the op-amp (such as a gain greater than 1) are possible. The output from the op-amp 130 is coupled to a processing system 150 to process the output signal of the op-amp. The processing system 150 can include a microprocessor, a filter, or other types of processing electronics.

[0014] The multiplexer circuit 110 includes a switch assembly for each channel. Channel 101 has a switch assembly 111, and channels 102 - 105 each have a switch assembly 112 - 115. Input inp1 can be coupled to node N1 when switch assembly 111 is "on". Similarly, any of inputs inp2 - inp5 can be coupled to node N1 when their respective switch assemblies 111 - 115 are on. Node N1 is connected to the non-inverting input of an operational amplifier. In this example, only one of switch assemblies 111 - 115 is on at a time, and the remaining switch assemblies are off.

[0015] In the example of FIG. 1, each switch assembly 111 - 115 includes three switches S1, S2, and S3. S1 and S2 are connected in series between the associated channel input and node N1. The multiplexer controller 140 generates control signals to switches S1 - S3 of switch assemblies 111 - 115 to turn each respective switch on or off. The node between S1 and S2 is shown as node N2. S3 of each switch assembly is coupled between node N2 and ground. When S3 is on, each node N2 is coupled to ground potential. To turn on the switch assembly and thereby enable the channel, its switches S1 and S2 are turned on and its switch S3 is turned off. To turn off the switch assembly and thereby disable the channel, its switches S1 and S2 are turned off and its switch S3 is turned on. As shown in the example of FIG. 1, S1 and S2 of switch assembly 111 are on and the corresponding switch S3 is off. S1 and S2 of the remaining four switch assemblies 112 - 115 are off and their switches S3 are on. Thus, in this example, channel 101 is enabled and channels 102 - 105 are off.

[0016] Even when the channel switch assembly is configured to be off (where its S1 and S2 are off and its S3 is on), there may be leakage current flowing through S2. To represent the leakage current through S2 of the off-switch assemblies 112 - 115, leakage currents Ileak1, Ileak2, Ileak3, and Ileak4 are shown in FIG. 1. Part of the reason for the leakage current is due to the fact that the on channel (channel 101 in this example) provides a voltage from its input inp1 to node N1 via switch assembly 111, and all of the switch assemblies 111 - 115 are coupled to node N1 as shown. Therefore, the voltage on node N1 from channel 101 is also provided to one terminal of S2 of the four off-switch assemblies 112 - 115. Since the output impedance of the sensor connected to the channel input can be made relatively high (e.g., several hundred megaohms), even a small amount of leakage current can generate a voltage across the output impedance of that channel. The voltage due to the leakage current from the off channel is additive (or subtractive depending on the indication of the leakage current) to the voltage generated by the sensor from the on channel, and thus distorts the signal of that sensor.

[0017] Figure 2 shows an exemplary implementation of each switch S2 of switch assemblies 111 - 115. The reason for the leakage current can be confirmed through the description of Figure 2. Referring to Figure 2, S2 of each switch assembly 111 - 115 includes a p-type MOS transistor MP1 coupled to an n-type MOS transistor MN1. The drains of MP1 and MN1 are commonly connected at node N1, and the sources of MP1 and MN1 are commonly connected at node N2. The gates of MP1 and MN1 are driven by a control signal to turn the transistors of S2 on and off. To turn S2 on, both MP1 and MN1 are turned on. To turn S2 off, both MP1 and MN1 are turned off. In the exemplary configuration shown in Figure 2, the gate of MN1 is driven by a low (e.g., ground) control signal, and the gate of MP1 is driven by a high control signal (shown as Vdda, the supply voltage). Driving the gate of MN1 low and the gate of MP1 high turns both MP1 and MN1 off. Thus, Figure 2 shows the off state for S2.

[0018] MOS transistors have parasitic bulk diodes. Figure 2 shows the drain-bulk diode D1 and the bulk-source diode D2 of MP1. As described above, the voltage on node N1 is driven by a sensor for which the switch assembly is on. S2 in Figure 2 represents the S2 switch of a switch assembly that is off. The voltage labeled Vin represents the voltage on node N1 from a sensor of another channel (e.g., channel 101) that is on. The node N2 of S2 in Figure 2 receives the ground potential through S3 (which is on) of each respective switch assembly. The bulk of MP1 of S2 is biased to Vdda.

[0019] When S2 is off, S2 has multiple leakage current sources. First, when Vin is 0V (for example, the voltage from a sensor coupled to on-channel 101), D1 is reverse-biased, whereby current Ib1 flows through D1. Thus, the leakage current Ileak (when Vin is low, for example 0V) is equal to -Ib1 + Idsn (Idsn is the leakage current through MN1). However, Idsn may be substantially smaller than Ib1, and therefore, Ileak is approximately equal to -Ib1. Second, when Vin is higher (for example, Vdda), Ileak is equal to the sum of the drain-source leakage currents of MP1 and MN1 (Idsp + Idsn). Both Idsp and Idsn are proportional to Vin (for example, the larger Vin is, the larger Idsp and Idsn become). Some examples described herein reduce the leakage current Ileak through S2 of the switch assembly by using a bulk bias circuit 610 (FIG. 6) and a buffer (for example, buffer 310 in FIG. 3 and buffer 410 in FIG. 4) when such a switch assembly is off.

[0020] FIG. 3 shows an example of a system 300 that includes a multiplexer circuit 110, an operational amplifier 130, and a buffer 310. Sensors S1 - S5, a multiplexer controller 140, and a processing system 150 are not shown for simplicity. The architecture of system 300 is substantially the same as that of system 100 in FIG. 1, except that it includes a buffer 310. In the system of FIG. 1, each switch S3 is coupled between its respective node N2 and ground. When S3 is on in FIG. 1, each node N2 is grounded. Grounding node N2 results in a leakage current through the MP1 and MN1 transistors of S2 when node N1 is at a voltage sufficiently high with respect to ground. The buffer 310 in FIG. 3 is coupled between node N1 and the switch S3 of switch assemblies 112 - 115 at node N3. The buffer 310 is configured for unity gain, and thus the output voltage of the buffer (node N3) is equal to its input voltage (node N1). The voltage on N1 is approximately equal to the voltage generated by the sensor for which the switch assembly is on (switch assembly 111 in the example of FIG. 3). Thus, the voltage on N3 is also equal to the voltage on N1.

[0021] In the example of FIG. 2, when S3 turns on, N2 is coupled to ground. By grounding N2, a sufficiently large drain - source voltage is generated across both MP1 and MN1, and leakage currents Idsp and Idsn flow through MP1 and MN1. In FIG. 3, instead of grounding N2 in switch assemblies 112 - 115, N2 is coupled to N3, which has a voltage approximately the same as the voltage on N1. In that way, a much lower drain - source voltage (approximately 0V) is generated across MP1 and MN1 for S2 of switch assemblies 112 - 115. Advantageously, when channel 101 is enabled and channels 102 - 105 are disabled, the use of buffer 310 results in a much lower leakage current through the MP1 and MN1 of S2 of switch assemblies 112 - 115 when Vin is significantly greater than 0V (as can be caused by the use of the enabled channel 101).

[0022] Since buffer 310 drives all the switches S3 of switch assemblies 112, 113, 114, and 115, buffer 310 is sized to be large enough to power all four switches S3 of switch assemblies 112, 113, 114, and 115.

[0023] FIG. 4 shows an exemplary system 400 that includes a multiplexer circuit 402, an operational amplifier 130, a buffer 410, a switch assembly 430, and a switch S4. Sensors S1 - S5, multiplexer controller 140, and processing system 150 are not shown for simplicity. Multiplexer circuit 402 has an architecture similar to that of multiplexer circuit 110 described above. Multiplexer circuit 402 includes switch assemblies 111 - 115. The node that interconnects all the switches S2 of switch assemblies 112 - 115 is denoted as N4 in FIG. 4. Switch assembly 430 is coupled between node N4 and the output of buffer 410. Switch assembly 430 has an architecture similar to that of switch assemblies 111 - 115. Switch assembly 430 includes switches S5, S6, and S7 as shown. Switches S5 and S6 are coupled in series between nodes N1 and N4. The node between S5 and S6 is denoted as intermediate node (INT). S7 is coupled between INT and the output of buffer 410.

[0024] Buffer 410 generates an output voltage that is approximately equal to its input voltage (the voltage on node N1). The buffer 410 in FIG. 4 drives switch assembly 430 instead of directly driving switch assemblies 112 - 115. As a result of driving one switch assembly 430, buffer 410 can have lower output current requirements and thus can be made smaller than buffer 310 in FIG. 3.

[0025] When the switch assembly 111 is turned on (similar to the example in FIG. 4), the switch assemblies 112 - 115 and 430 are turned off, and the switch S4 is turned on. S4 is coupled between the node N4 and ground. By turning on S4, the node N4 is grounded. When the switch assembly 111 is enabled and the switch assemblies 112 - 115 and 430 are off, little or no leakage current flows through the switch assemblies 112 - 115 and 430. The buffer 410 provides the same advantage to the switch assembly 430 to reduce its leakage current as described above for the buffer 310. When using any of inp2 - inp4, the switch assembly of that specific input is turned on, the remaining switch assemblies among 111 - 115, and S4 are turned off, and the switch assembly 430 is turned on.

[0026] FIG. 5 shows an exemplary implementation of a buffer 410 (or 310) coupled to the input stage 510 of the operational amplifier 130. The input stage 510 includes transistors M1 - M5. In the input stage of this example, M1, M2, M5 are PMOS transistors, and M3, M4 are NMOS transistors. M5 is a current source device, whose gate is biased at a voltage labeled BIAS1 to generate a tail current Itail. M1 and M2 include a differential transistor pair. The sources of M1 and M2 are both connected to the drain of M5. The positive (+) input of the operational amplifier 130 is coupled to the gate of M1 and labeled IN_P. The negative (-) input of the operational amplifier 130 is coupled to the gate of M2 and labeled IN_M. The gates of the transistors M3 and M4 are biased at a voltage labeled BIAS2.

[0027] Buffer 410 includes transistors M6, M7, and M8. In this example, M6 and M8 include PMOS transistors and M7 includes an NMOS transistor. The gate of M8 is biased with a voltage denoted as BIAS3, and the source of M8 is connected to the supply voltage Vdda. In one example, BIAS3 is equal to BIAS1. The drain of M8 is connected to the source of M6 and node N5. In that way, the drain of M8 and the source of M6 are connected to the op-amp input stage 510 at node N5. The drains of M6 and M7 are both connected to the gate of M6 at node N6. Node N6 represents the output of buffer 410, which is connected to node N3 in FIG. 3 and, in the case of buffer 410, is connected to switch S3 of switch assembly 430 in FIG. 4. The gate of M7 is biased with a voltage denoted as BIAS4, and the source of M7 is connected to ground. In one example, BIAS4 is equal to BIAS2.

[0028] The current flowing through M8 is denoted as I1. The current I1 is, to some extent, a function of the size of M8 (the ratio of its channel width (W) to channel length (L)) and the gate-source voltage (Vgs) of M8. The source of M8 is coupled to Vdda, and the gate of M8 is BIAS3. Thus, BIAS3, and the ratio of the channel width to length of M8, define the magnitude of the current I1. When BIAS3 is equal to BIAS1 and the W / L of M8 is 1 / 16 of the W / L of M5, I1 becomes 1 / 16 of Itail. In one example, BIAS3, and the ratio of the channel width to length of M8, result in a magnitude of I1 that is 1 / 16 of the magnitude of Itail, and that ratio may be different from 1 / 16 in other examples. Further, the ratio of the channel width to the length of M6 is 1 / 8 of the ratio of the channel width to the length of M1 or M2 (which are of equal size themselves). The sources of M1, M2, and M6 are all connected together at node N5. The current density flowing through M6 is the same as that of M1 and M2. Therefore, I1 through M6 is 1 / 16 of Itail, but the W / L of M6 is 1 / 8 of the W / L of M1 or M2. As shown in FIG. 4, since the output of the op-amp 130 is connected to its negative input (IN_M), IN_P generally remains approximately equal to IN_M. Since the source voltage of M6 is equal to the source voltages of M1 and M2 and the current density is the same, the gate voltage of M6 is equal to the gate voltages IN_P or IN_M of M1 and M2, respectively. Thus, the output voltage of the buffer 410 on node N6 becomes approximately equal to IN_P.

[0029] As described above with respect to FIG. 2, when Vin is a relatively low voltage and the bulk of the MP1 transistor is biased at the supply voltage (Vdda), the drain-bulk parasitic diode D1 of switch S2 of the switch assemblies 112 - 115 is reverse-biased, thereby allowing leakage current to flow through each of such switches S2.

[0030] FIG. 6 shows a system 600 in which the bulk of the PMOS transistor of switch S2 is biased at a voltage lower than Vdda when Vin is a low voltage.

[0031] The exemplary system 600 in FIG. 6 includes an input stage 510 of an operational amplifier 130, a buffer 410, a bulk bias circuit 610, switches S1, S2, and S4, and a switch assembly 430. ISRC1 in buffer 410 represents M8 in FIG. 5. In this example, switch S6 of switch assembly 430 includes transistors M10 and M11. Also, switch S5 includes transistors M12 and M13. Switch assembly 430 is shown in its off state, so switch S7 is on. S7 is shown in its symbolic form. In some implementations, S7 includes a single transistor or a pair of PMOS / NMOS transistors. M10 and M12 include PMOS transistors, and M11 and M13 include NMOS transistors. The sources of M10 and M11 are both connected and connected to the IN_P input (gate of M1) of the input stage 510 of the operational amplifier. The drains of M10 and M11 are both connected at node INT. S7 is shown in its closed (on) state and couples INT to the output of buffer 410 (node N6). The sources of M12 and M13 are also connected to INT. The drains of M12 and M13 are both connected at node N4 provided to switch assemblies 112 - 115 as shown in FIG. 4. Switch S4 is coupled between node N4 and ground and is closed (on) when switch assembly 430 is off. S5 and S6 are off when switch assembly 430 is off. To turn S5 and S6 off, a supply voltage (Vdda) as shown is provided to the gates of PMOS transistors M10 and M12, and a ground voltage as shown is provided to NMOS transistors M11 and M13.

[0032] S1 includes transistors M14 and M15, and S2 includes transistors M16 and M17. In this example, M14 and M16 include PMOS transistors, and M15 and M17 include NMOS transistors. The drains of M15 and M16 are commonly connected at the input inp1 of channel 101. The sources of M16 and M17 are commonly connected at node N1 to which the gate of M1 within the input stage 510 of the operational amplifier is connected. The configuration of FIG. 6 illustrates the on state of switch assembly 111. Therefore, the gates of PMOS transistors M14 and M16 are grounded to turn on M14 and M16, and the gates of NMOS transistors M15 and M17 receive the supply voltage Vdda to turn on M15 and M17. Also, switch S3 (FIG. 4) of switch assembly 111 is turned off, so node N2 is not pulled to ground. S3 is not shown in FIG. 5.

[0033] The exemplary bulk bias circuit 610 includes transistors M18 and M19. In this implementation, M18 and M19 are PMOS transistors. The source of M18 is connected to Vdda, the drain of M18 is connected to the source of M19 at node N7, and the drain of M19 is connected to ground. The bulk of M19 is connected to the source of M19. When M19 is configured as a source follower, current I2 branches from Vdda through M18 and M19 to ground. The voltage on the source of M19 is about 1 threshold voltage (about 1V) higher than the gate voltage of M19. The signal on the gate of M19 is the voltage on node N1. When switch assembly 111 is on (S1 and S2 are on) and the voltage on inp1 is low, the voltage on N1 is low, current I2 flows through M19, and as a result, the voltage on the source of M19 is about 1V greater than its gate voltage (N1). Node N7 is coupled to the bulk of M1 and M2 within the input stage of the op amp, and to the bulk of M10 within switch S6, and to the bulk of M16 of S2 within switch assembly 111. The corresponding bulk of the PMOS transistors of S2 of other switch assemblies 112 - 115 can also be similarly coupled to node N7. The voltage on node N7 is used to bias the bulk of M1, M2, and M10. When input inp1 is low enough to turn on M10, the voltage on node N7 is pulled down to about 1V above the voltage on inp1, so that the bulk of M1, M2, and M10 are biased to a voltage much lower than Vdda (e.g., 1V). Biasing the bulk of M10 to a voltage substantially lower than Vdda causes the bulk - source parasitic diode D3 of M10 to be biased at a voltage much closer to 0V than when the bulk of M10 is biased to Vdda. When D3 is biased at 0V or a relatively small voltage, the leakage current through D3 is much smaller than when D3 is biased at a larger voltage. By biasing the bulk of PMOS M10 within switch assembly 430 to a lower voltage when the voltage on inp1 is small (compared to when inp1 has a larger voltage), the leakage current through switch assembly 430 is reduced compared to the case of permanently biasing the bulk of M10 at Vdda.

[0034] The term "coupled" is used throughout this specification. This term can encompass a connection, communication, or signal path that enables a functional relationship consistent with the description in this specification. For example, when device A generates a signal for controlling device B to perform a certain action, in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B via intervening component C when intervening component C does not substantially change the functional relationship between device A and device B and device B is controlled by device A via a control signal generated by device A.

Claims

1. A circuit comprising: a plurality of inputs; a plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly, each of the plurality of switch assemblies comprising: a first switch coupled between each input of the plurality of inputs and an internal node; a second switch coupled to the internal node; a third switch coupled to the internal node; the plurality of switch assemblies; a buffer having an input coupled to the second switch of each of the first, second, and third switch assemblies and an output coupled to the third switch of each of the second and third switch assemblies, the buffer comprising: a first transistor having a gate coupled to a first bias voltage node; a second transistor having a gate coupled to a second bias voltage node; a third transistor coupled between the first and second transistors, the third transistor having a gate and a drain coupled to the gate; the buffer; the circuit.

2. The circuit according to claim 1, wherein the third switch of the first switch assembly is coupled to a ground node.

3. The circuit according to claim 1, wherein the buffer is configured as a unity gain buffer.

4. The circuit according to claim 1, further comprising an operational amplifier having a first input coupled to the second switch of each of the plurality of switch assemblies, a second input, and an output.

5. The circuit according to claim 4, wherein the output of the operational amplifier is coupled to the second input of the operational amplifier.

6. The circuit according to claim 4, wherein the operational amplifier is configured as a unity gain buffer.

7. The circuit according to claim 1, wherein the plurality of switch assemblies are configured as multiplexers.

8. The circuit according to claim 7, further comprising a multiplexer controller coupled to the first, second, and third switches of each of the plurality of switch assemblies.

9. A circuit comprising: a plurality of inputs; a multiplexer output node; A plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly, each of the plurality of switch assemblies being a first switch coupled between each input of the plurality of inputs and an internal node, a second switch coupled between the internal node and the multiplexer output node, a third switch coupled to the internal node, the plurality of switch assemblies including a buffer having an input coupled to the second switch of the first, second, and third switch assemblies and an output coupled to the third switch of the second and third switch assemblies, a first transistor having a gate coupled to a first bias voltage node, a second transistor having a gate coupled to a second bias voltage node, a third transistor coupled between the first and second transistors, the third transistor having a gate and a drain coupled to the gate, the buffer including a circuit including

10. The circuit according to claim 9, wherein the buffer is configured as a unity gain buffer.

11. The circuit according to claim 9, further comprising an operational amplifier having a first input coupled to the multiplexer output node, a second input, and an output.

12. The circuit according to claim 11, wherein the output of the operational amplifier is coupled to the second input of the operational amplifier.

13. The circuit according to claim 11, wherein the operational amplifier is configured as a unity gain buffer.

14. The circuit according to claim 9, wherein the plurality of switch assemblies are configured as a multiplexer.

15. The circuit according to claim 9, further comprising a multiplexer controller coupled to the first, second, and third switches of each of the plurality of switch assemblies.

16. A circuit comprising a plurality of inputs, a plurality of switch assemblies including a first switch assembly, a second switch assembly, and a third switch assembly, each of the plurality of switch assemblies being a first switch coupled between each input of the plurality of inputs and an internal node, a second switch coupled to the internal node, a third switch coupled to the internal node; the plurality of switch assemblies, including; a buffer having an input coupled to the second switch of each of the first, second, and third switch assemblies and an output coupled to the third switch of the second and third switch assemblies, a first transistor having a gate coupled to a first bias voltage node; a second transistor having a gate coupled to a second bias voltage node; a third transistor coupled between the first and second transistors, the third transistor having a gate and a drain coupled to the gate; the buffer, including; an operational amplifier having a first input coupled to the second switch of the plurality of switch assemblies, a second input, and an output coupled to the second input; a circuit, including.

17. The circuit according to claim 16, wherein the buffer is configured as a unity gain buffer.

18. The circuit according to claim 16, wherein each first switch of the plurality of switch assemblies is coupled to each input of the plurality of inputs.

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