Display substrate and display device

Abstract

To reduce a load on a reset signal line in a display substrate to thereby extend the charge time of a pixel drive circuit and improve a display effect of the display substrate.SOLUTION: In a display substrate, the display substrate comprises a base substrate 110, a first gate layer 130, a second gate layer 140, and a first conductive layer 150. The first gate layer includes a reset signal line extending along a first direction and a first electrode block CE1. The second gate layer includes a second electrode block CE2 configured to form a storage capacitor with the first electrode block. The first conductive layer includes a power line 151 extending along a second direction. The reset signal line 131 and the power line have a first overlapping area. The second electrode block and the power line have a second overlapping area 351. A width of the power line located in the first overlapping area is less than a width of the power line located in the second overlapping area 352. The first direction and the second direction intersect each other.SELECTED DRAWING: Figure 28B

Description

[Technical Field]

[0001] The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0002] With the continuous development of display technology, organic light emitting diode (OLED) display technology is being applied to various electronic devices due to its advantages such as self-luminance, wide viewing angle, high contrast, low power consumption, and fast response speed.

[0003] On the other hand, with the continuous development of organic light emitting diode display technology, the requirements for the performance of organic light emitting diode display products, such as power, color cast, brightness, stability, etc., are increasing. Summary of the Invention [Means for solving the problem]

[0004] The embodiments of the present disclosure provide a display substrate and a display device, which can reduce the load of the reset signal line by reducing the width of the power line in a first overlap region where the reset signal line and the power line overlap, thereby extending the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0005] At least one embodiment of the present disclosure provides a display substrate comprising: a base substrate; a first gate layer located on the base substrate; a second gate layer located on one side of the first gate layer away from the base substrate; and a first conductive layer located on one side of the second gate layer away from the base substrate, wherein the first gate layer comprises a reset signal line and a first electrode block extending along a first direction; the second gate layer comprises a second electrode block configured to form a storage capacitor with the first electrode block; the first conductive layer comprises a power line extending along a second direction; the reset signal line and the power line have a first overlapping region; the second electrode block and the power line have a second overlapping region; a width of the power line located in the first overlapping region is less than a width of the power line located in the second overlapping region; and the first direction and the second direction intersect.

[0006] For example, in a display substrate according to an embodiment of the present disclosure, the width of the power line in the first overlapping region is less than the average width of the power line.

[0007] For example, in a display substrate according to one embodiment of the present disclosure, the power line has a main body extension portion and a contraction portion, the width of the contraction portion is less than the width of the main body extension portion, and the orthogonal projection of the contraction portion on the base substrate overlaps with the orthogonal projection of the reset signal line on the base substrate.

[0008] For example, in a display substrate according to one embodiment of the present disclosure, the first gate layer further includes a gate line extending along the first direction, the gate line and the power line have a third overlapping region, and the width of the power line located in the third overlapping region is less than the width of the power line located in the second overlapping region.

[0009] For example, in a display substrate according to an embodiment of the present disclosure, the width of the power line in the second overlapping region is less than the average width of the power line.

[0010] For example, in a display substrate according to one embodiment of the present disclosure, the power line has a main body extension portion and a contraction portion, the width of the contraction portion is less than the width of the main body extension portion, and the orthogonal projection of the contraction portion on the base substrate overlaps with the orthogonal projection of the gate line on the base substrate.

[0011] For example, in a display substrate according to one embodiment of the present disclosure, the first conductive layer further includes a data line extending along the second direction, the data line and the reset signal line have a fourth overlapping region, and the width of the reset signal line in the fourth overlapping region is less than the average width of the reset signal line.

[0012] For example, in a display substrate according to an embodiment of the present disclosure, the width of the reset signal line located in the fourth overlapping region is less than ¾ of the maximum width of the reset signal line.

[0013] For example, a display substrate according to one embodiment of the present disclosure further includes a semiconductor layer located on one side of the first gate layer closer to the base substrate, the second gate layer includes an initialization signal line extending along the first direction, the data line and the initialization signal line have a fifth overlapping region, the initialization signal line and the semiconductor layer have a sixth overlapping region, and the width of the initialization signal line located in the fifth overlapping region is less than the width of the initialization signal line located in the sixth overlapping region.

[0014] For example, in a display substrate according to an embodiment of the present disclosure, the width of the initialization signal line located in the fifth overlapping region is less than the average width of the initialization signal line.

[0015] For example, in a display substrate according to one embodiment of the present disclosure, the power line has a main body extension portion and a contraction portion, the width of the contraction portion is less than the width of the main body extension portion, and the orthogonal projection of the contraction portion on the base substrate does not overlap with the orthogonal projection of the semiconductor layer on the base substrate.

[0016] For example, in a display substrate according to one embodiment of the present disclosure, the second gate layer further includes a conductive block, the body extension portion includes a connection portion connected to the conductive block, the orthogonal projection of the connection portion on the base substrate partially overlaps with the orthogonal projection of the semiconductor layer on the base substrate, and the connection portion is adjacent to the reduction portion in the second direction.

[0017] For example, in a display substrate according to an embodiment of the present disclosure, the semiconductor layer includes a first unit, a second unit, a third unit, a fourth unit, a fifth unit, a sixth unit, and a seventh unit, and the first unit includes a first channel region and first source regions and first drain regions located on both sides of the first channel region, the second unit includes a second channel region and second source regions and second drain regions located on both sides of the second channel region, and the third unit includes a third channel region and third source regions located on both sides of the third channel region. the fourth unit comprises a fourth channel region and a fourth source region and a fourth drain region located on either side of the fourth channel region; the fifth unit comprises a fifth channel region and a fifth source region and a fifth drain region located on either side of the fifth channel region; the sixth unit comprises a sixth channel region and a sixth source region and a sixth drain region located on either side of the sixth channel region; and the seventh unit comprises a seventh channel region and a seventh source region and a seventh drain region located on either side of the seventh channel region.

[0018] For example, in a display substrate according to one embodiment of the present disclosure, the sixth drain region is connected to the third drain region, the third source region, the first drain region, and the fifth source region are connected to a first node, the first source region, the second drain region, and the fourth drain region are connected to a second node, and the fifth drain region is connected to the seventh drain region.

[0019] For example, in a display substrate according to an embodiment of the present disclosure, the sixth source region and the seventh source region are connected to the initialization signal line.

[0020] For example, in a display substrate according to an embodiment of the present disclosure, the second source region is connected to the data line.

[0021] For example, in a display substrate according to an embodiment of the present disclosure, the fourth source region is connected to the power line.

[0022] For example, a display substrate according to one embodiment of the present disclosure further includes a first flat layer located on one side of the first conductive layer away from the base substrate, a second conductive layer located on one side of the first flat layer away from the first conductive layer and having a connection electrode, a second flat layer located on one side of the second conductive layer away from the first flat layer, and an anode located on one side of the second flat layer away from the second conductive layer, wherein the first flat layer has a first via, and the connection electrode is connected to a fifth drain region through the first via, and the second flat layer has a second via, and the anode is connected to the connection electrode through the second via.

[0023] At least one embodiment of the present disclosure further provides a display device including the display substrate described above.

[0024] In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be apparent that the drawings in the following description are only some embodiments of the present disclosure and are not intended to limit the present disclosure. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a schematic cross-sectional view of a part of a display substrate. [Figure 2] FIG. 2 shows a schematic diagram of the display substrate shown in FIG. 1 emitting light. [Figure 3]FIG. 3 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. [Figure 4A] FIG. 4A is a schematic cross-sectional view of a display substrate taken along the direction AA in FIG. 3 according to one embodiment of the present disclosure. [Figure 4B] FIG. 4B is another cross-sectional schematic view of the display substrate taken along the direction AA of FIG. 3 according to an embodiment of the present disclosure. [Figure 5A] FIG. 5A is a schematic cross-sectional view of a display substrate taken along the line BB in FIG. 3 according to one embodiment of the present disclosure. [Figure 5B] FIG. 5B is a schematic cross-sectional view of the display substrate taken along the GG direction of FIG. 3 according to one embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic plan view of a light emitting element of a display substrate according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a schematic diagram of the planar relationship between the second conductive layer and the anode layer of the display substrate according to one embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a partial cross-sectional schematic view of another display substrate. [Figure 10] FIG. 10 is a partial cross-sectional schematic view of another display substrate. [Figure 11] FIG. 11 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. [Figure 12A] FIG. 12A is a schematic cross-sectional view of a display substrate taken along the HH direction in FIG. 11 according to one embodiment of the present disclosure. [Figure 12B] FIG. 12B is a schematic cross-sectional view of the display substrate taken along the JJ direction in FIG. 11 according to one embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic diagram of a display device according to an embodiment of the present disclosure. [Figure 17] Figure 17 is a schematic diagram of the deposition process using a fine metal mask. [Figure 18] FIG. 18 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a schematic cross-sectional view of a display substrate taken along the CC direction in FIG. 18 according to an embodiment of the present disclosure. [Figure 20] FIG. 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. [Figure 21] FIG. 21 is a schematic cross-sectional view of a display substrate taken along the DD direction of FIG. 20 according to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a schematic cross-sectional view of the display substrate in the EE direction of FIG. 20 according to one embodiment of the present disclosure. [Figure 23] FIG. 23 is a schematic diagram of a display device according to an embodiment of the present disclosure. [Figure 24] FIG. 24 illustrates a method for manufacturing a display substrate according to an embodiment of the present disclosure. [Figure 25] FIG. 25 is a schematic plan view of a mask plate group according to one embodiment of the present disclosure. [Figure 26] FIG. 26 is a schematic plan view of a mask plate group according to one embodiment of the present disclosure. [Figure 27] FIG. 27 is a schematic plan view of a mask plate group according to one embodiment of the present disclosure. [Figure 28A] FIG. 28A is a partial schematic diagram of another display substrate according to one embodiment of the present disclosure. [Figure 28B] FIG. 28B is a partial schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 29] FIG. 29 is a cross-sectional schematic diagram of a display substrate in the FF direction of FIG. 28A according to one embodiment of the present disclosure. [Figure 30A] FIG. 30A is a schematic plan view of multiple film layers of a display substrate according to one embodiment of the present disclosure. [Figure 30B] FIG. 30B is a schematic plan view of multiple film layers of a display substrate according to one embodiment of the present disclosure. [Figure 30C]FIG. 30C is a schematic plan view of multiple film layers of a display substrate according to one embodiment of the present disclosure. [Figure 30D] FIG. 30D is a schematic plan view of multiple film layers of a display substrate according to one embodiment of the present disclosure. [Figure 31] FIG. 31 is an equivalent schematic diagram of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure. [Figure 32] FIG. 32 is a schematic diagram of a display device according to an embodiment of the present disclosure. [Figure 33] FIG. 33 is a partial schematic diagram of a display substrate according to one embodiment of the present disclosure. [Figure 34] FIG. 34 is a cross-sectional schematic diagram of a display substrate taken along the KK direction of FIG. 33 according to one embodiment of the present disclosure. [Figure 35A] FIG. 35A is a schematic cross-sectional view of a display substrate in the MM direction of FIG. 33 according to one embodiment of the present disclosure. [Figure 35B] FIG. 35B is a schematic cross-sectional view of the display substrate taken along the NN direction of FIG. 33 according to one embodiment of the present disclosure. [Figure 35C] FIG. 35C is a schematic cross-sectional view of the display substrate in the QQ direction of FIG. 33 according to one embodiment of the present disclosure. [Figure 36] FIG. 36 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. [Figure 37A] FIG. 37A is a partial schematic diagram of another display substrate according to one embodiment of the present disclosure. [Figure 37B] FIG. 37B is a partial schematic diagram of another display substrate according to an embodiment of the present disclosure. [Figure 38] FIG. 38 is a schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] In order to more clearly explain the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only some embodiments of the present disclosure, and are not all embodiments. Based on the described embodiments of the present disclosure, any other embodiments that can be obtained by a person skilled in the art without requiring creative work also fall within the scope of the present disclosure.

[0027] Unless otherwise defined, technical or scientific terms used herein should have the ordinary meaning that can be understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are used only to distinguish different components. Terms such as "comprise" or "include" mean that the element or component listed before the term covers the element or component listed after the term and its equivalents, but does not exclude other elements or components.

[0028] Display devices have many performance specifications such as power, brightness, color coordinates, etc., and color cast is one of the important parameters. Generally, there are many factors that affect the color cast of an organic light-emitting diode (OLED) display device, and from the perspective of display substrate (organic light-emitting diode array substrate or rear panel) design, the flatness of the anode has a significant impact on color cast.

[0029] Fig. 1 is a partial cross-sectional schematic diagram of a display substrate. Fig. 2 is a schematic diagram showing the light-emitting state of the display substrate shown in Fig. 1. As shown in Fig. 1, a sub-pixel of the display substrate includes, in order, a base substrate 110, a semiconductor layer 120, a first gate layer 130, a second gate layer 140, a first conductive layer 150, a first planar layer 241, a second conductive layer 160, a second planar layer 242, an anode 175, and a pixel defining layer 190.

[0030] The semiconductor layer 120, the first gate layer 130, the second gate layer 140, and the first conductive layer 150 can form a pixel driving circuit including a thin film transistor and a storage capacitor; The second conductive layer 160 has a connecting electrode 161 connected to a pixel driving circuit through a via (not shown) in the first planar layer 241, and the anode 170 is connected to the connecting electrode 161 through a via 271 in the second planar layer 242. The pixel defining layer 190 has an opening 191 for exposing a part of the anode 170, and when a subsequent organic light-emitting layer 180 is formed in the opening 191, the anode 175 contacts the organic light-emitting layer 180 and can be driven to emit light, and the area defined by the opening 191 is the effective light-emitting area of the sub-pixel.

[0031] The vias 271 in the second planar layer 242 affect the planarity of the anodes 175. If the vias 271 are close to the openings 191 (i.e., the effective light-emitting area), the anodes 175 at the openings 191 will be tilted, causing the light-emitting direction of the subpixels to shift. If the tilt directions of the anodes of different color subpixels are different, the intensities of light emitted in different directions from the subpixels of different colors (e.g., red, green, and blue) will not match, resulting in a color cast phenomenon. For example, a display screen having the display substrate may appear red when viewed from one side, but blue when viewed from the other side.

[0032] In contrast, an embodiment of the present disclosure provides a display substrate and a display device, the display substrate comprising a base substrate, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, and a plurality of light-emitting element groups, wherein the first conductive layer is located on the base substrate, the first flat layer is located on one side of the first conductive layer away from the base substrate, the second conductive layer is located on one side of the first flat layer away from the first conductive layer, the second flat layer is located on one side of the second conductive layer away from the first flat layer, and the plurality of light-emitting element groups are located on one side of the second flat layer away from the base substrate.

[0033] The plurality of light emitting element groups are arranged along a first direction to form a plurality of light emitting element columns, and are arranged along a second direction to form a plurality of light emitting element rows, each of the light emitting element groups comprising one first light emitting element, one second light emitting element, one third light emitting element, and one fourth light emitting element, the second light emitting element and the third light emitting element being arranged along the second direction to form a light emitting element pair, the first light emitting element, the light emitting element pair, and the third light emitting element being arranged along the first direction, the first light emitting element comprising a first anode, the second light emitting element comprising a second anode, the third light emitting element comprising a third anode, and the fourth light emitting element comprising a fourth anode, the second conductive layer comprising a first connecting electrode, a second connecting electrode, a the second flat layer has a first via, a second via, a third via and a fourth via, the first anode is connected to the first connection electrode through the first via, the second anode is connected to the second connection electrode through the second via, the third anode is connected to the third connection electrode through the third via, and the fourth anode is connected to the fourth connection electrode through the fourth via, and the multiple third vias corresponding to one light-emitting element row are approximately on a first straight line extending along the first direction, and the orthogonal projection on the base substrate of the fourth via that is closest to the first straight line is located on one side close to the fourth anode corresponding to the fourth via on the first straight line.

[0034] As a result, by moving the position of the fourth via closer to the fourth anode, the display substrate increases the distance between the fourth via and the effective light-emitting area of the adjacent first light-emitting element, thereby ensuring the flatness of the first anode located in the effective light-emitting area of the first light-emitting element and preventing color cast; by shortening the distance between the fourth via and the effective light-emitting area of the fourth light-emitting element, the resistance between the fourth anode located in the effective light-emitting area of the fourth light-emitting element and the fourth connecting electrode is reduced; and by increasing the distance between the first anode and the fourth anode, short-circuiting between the first anode and the fourth anode caused by residues from the manufacturing process is prevented.

[0035] Hereinafter, a display substrate and a display device provided according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] An embodiment of the present disclosure provides a display substrate, in which Fig. 3 is a schematic plan view of the display substrate according to the embodiment of the present disclosure, Figs. 4A and 4B are schematic cross-sectional views of the display substrate taken along the AA direction of Fig. 3 according to the embodiment of the present disclosure, Fig. 5A is a schematic cross-sectional view of the display substrate taken along the BB direction of Fig. 3 according to the embodiment of the present disclosure, Fig. 5B is a schematic cross-sectional view of the display substrate taken along the GG direction of Fig. 3 according to the embodiment of the present disclosure, and Fig. 6 is a schematic plan view of a light-emitting element of the display substrate according to the embodiment of the present disclosure.

[0037] As shown in Figures 3, 4A, 4B, 5A, 5B, and 6, the display substrate 100 comprises a base substrate 110, a first conductive layer 150, a first flat layer 241, a second conductive layer 160, a second flat layer 242, and a plurality of light-emitting element groups 310, wherein the first conductive layer 150 is located on the base substrate 110, the first flat layer 241 is located on one side of the first conductive layer 150 away from the base substrate 110, the second conductive layer 160 is located on one side of the first flat layer 241 away from the first conductive layer 150, the second flat layer 242 is located on one side of the second conductive layer 160 away from the first flat layer 241, and the plurality of light-emitting element groups 310 are located on one side of the second flat layer 242 away from the base substrate 110.

[0038] The plurality of light emitting element groups 310 are arranged along a first direction to form a plurality of light emitting element columns 320, and are arranged along a second direction to form a plurality of light emitting element rows 330, and each of the light emitting element groups 310 includes one first light emitting element 311, one second light emitting element 312, one third light emitting element 313, and one fourth light emitting element 314, and the second light emitting element 312 and the third light emitting element 313 are arranged along the second direction. The first light-emitting element 311, the light-emitting element pair 315, and the fourth light-emitting element 314 are arranged along a first direction, the first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754, and the second conductive layer 160 includes a first connecting electrode 1611, The second flat layer 242 includes a first via 2421, a second via 2422, a third via 2423 and a fourth via 2424, the first anode 1751 is connected to the first connection electrode 1611 through the first via 2421, the second anode 1752 is connected to the second connection electrode 1612 through the second via 2422, and the third The anode 1753 is connected to the third connection electrode 1613 through a third via 2423, and the fourth anode 1754 is connected to the fourth connection electrode 1614 through a fourth via 2424. The third vias 2423 corresponding to one light-emitting element row 330 are located approximately on a first straight line 301 extending along the first direction, and the orthogonal projection on the base substrate 110 of the fourth via 2424 that is closest to the first straight line 301 is It is located on one side of the first straight line 301 close to the fourth anode 1754 corresponding to the fourth via 2424. However, the first conductive layer and the second conductive layer are stacked in order along the direction away from the base substrate.

[0039] In the display substrate provided by the embodiments of the present disclosure, the second light-emitting element and the third light-emitting element are arranged along the second direction to form a light-emitting element pair, and the first light-emitting element, the light-emitting element pair, and the third light-emitting element are arranged along the first direction, i.e., the second anode and the third anode are arranged along the second direction to form an anode pair, and the first anode, the anode pair, and the third anode are arranged along the first direction.

[0040] The orthogonal projection of the fourth via on the base substrate that is closest to the first line is located on one side of the first line closer to the fourth anode, i.e., the display substrate moves the position of the fourth via closer to the fourth anode, thereby achieving the following beneficial effects: (1) increasing the distance between the fourth via and the effective light-emitting area of the adjacent first light-emitting element ensures the flatness of the first anode located in the effective light-emitting area of the first light-emitting element and prevents color cast; (2) shortening the distance between the fourth via and the effective light-emitting area of the fourth light-emitting element reduces the resistance between the fourth anode located in the effective light-emitting area of the fourth light-emitting element and the fourth connecting electrode; and (3) increasing the distance between the first anode and the fourth anode prevents short-circuiting between the first anode and the fourth anode due to manufacturing residues.

[0041] 5A, 5B, and 6, the display substrate moves the position of the fourth via 2424 closer to the fourth anode 1754, thereby increasing the distance between the fourth via 2424 and the effective light-emitting area of the adjacent first light-emitting element (i.e., the area defined by the opening 1951). Furthermore, because the fourth anode has a connection portion connected to the pixel driving circuit below it, even if the position of the fourth via 2424 is moved closer to the fourth anode 1754, it does not overlap with the effective light-emitting area of the fourth light-emitting element (i.e., the area defined by the opening 1954).

[0042] In this case, there is an appropriate distance between the fourth via 2424 and the effective light-emitting area of the adjacent first light-emitting element and the effective light-emitting area of the adjacent fourth light-emitting element, thereby simultaneously ensuring the flatness of the first anode located in the effective light-emitting area of the first light-emitting element and the fourth anode located in the effective light-emitting area of the fourth light-emitting element, and further avoiding the occurrence of color cast.

[0043] 5A, 5B, and 6, the display substrate moves the position of the fourth via 2424 closer to the fourth anode 1754, thereby further shortening the distance between the fourth via 2424 and the effective light-emitting area of the fourth light-emitting element, and thereby reducing the resistance between the fourth anode located in the effective light-emitting area of the fourth light-emitting element and the fourth connecting electrode. Meanwhile, the display substrate moves the position of the fourth via 2424 closer to the fourth anode 1754, thereby further increasing the distance between the first anode 1751 and the fourth anode 1754, and thereby preventing a short circuit between the first anode 1751 and the fourth anode 1754 due to residues from the manufacturing process.

[0044] For example, the shortest distance between the orthogonal projection of the first anode on the base substrate and the orthogonal projection of the adjacent fourth anode on the base substrate exceeds 0.8 times the width in the first direction of the effective light-emitting area of the first light-emitting element, thereby effectively avoiding short circuits between the first anode and the fourth anode due to residues from the manufacturing process.

[0045] For example, as shown in FIG. 6 , the fourth anode 1754 has a main body portion 1754A and a connecting portion 1754B, and the effective light-emitting area of the fourth light-emitting element 314 is located within the orthogonal projection of the main body portion 1754A on the base substrate 110. The connecting portion 1754B is connected to the corresponding fourth connecting electrode 1614 through a fourth via 2424 and is located on one side of the first straight line 301 close to the main body portion 1754A, thereby effectively reducing the area of the connecting portion and thereby reducing the resistance between the fourth anode and the fourth connecting electrode located in the effective light-emitting area of the fourth light-emitting element.

[0046] For example, as shown in FIG. 6, the fourth anode 1754 further includes a first supplementary portion 1754C, which can cover two channel regions of the compensation thin film transistor of the corresponding pixel driving circuit, thereby improving the stability and service life of the compensation thin film transistor, and improving the long-term luminescence stability and service life of the display substrate.

[0047] In some examples, as shown in FIG. 6, the first supplementary portion 1754C protrudes from the fourth main body portion 1754A to the third anode 1753 and is located on one side of the fourth connecting portion 1754B closer to the fourth main body portion 1754A.

[0048] 6, the first supplementary portion 1754C is connected to both the fourth body portion 1754A and the fourth connecting portion 1754B, thereby allowing the display substrate to fully utilize the area on the display substrate and closely arrange the first anode, the second anode, the third anode, and the fourth anode, thereby ensuring the resolution of the display substrate.

[0049] 4A , the display substrate includes, in order, a base substrate 110, a semiconductor layer 120, a first insulating layer 361, a first gate layer 130, a second insulating layer 362, a second gate layer 140, an interlayer insulating layer 363, a first conductive layer 150, a first planar layer 241, a second conductive layer 160, and a second planar layer 242. The first gate layer 130 may include a gate line 131 and a first electrode block CE1, and the second gate layer may include a second gate block CE2, where the orthogonal projection of the first electrode block CE1 on the base substrate 110 at least partially overlaps with the orthogonal projection of the second electrode block CE2 on the base substrate 110, thereby forming a storage capacitor.

[0050] For example, as shown in FIG. 4A, the first conductive layer 150 may further include a power line and a data line, and the second conductive layer 160 may overlap the power line and be electrically connected to the power line, and may include a conductive portion that can reduce the resistance of the power line.

[0051] For example, as shown in Figure 4B, the display substrate may further include a protective layer 364 located between the first conductive layer 150 and the first flat layer 241. Of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may not include a protective layer.

[0052] In some examples, as shown in FIG. 6, the plurality of second vias 2422 corresponding to the light emitting element row 330 adjacent to the light emitting element row 330 corresponding to the first straight line 301 are also located substantially on the first straight line 301 .

[0053] 3 , the fourth via 2424 of one light-emitting element group 310 is located on one side of the bisector along the second direction of the first anode 1751 of the light-emitting element group 310 adjacent to the light-emitting element group 310 in the second direction, for example, on one side of the bisector along the second direction of the first anode 1751, which is closer to the second anode 1752 of the light-emitting element group 310 in which the first anode 1751 is located. In other words, the fourth via 2424 of one light-emitting element group is located on one side of the bisector along the second direction of the first anode of the light-emitting element group adjacent to the light-emitting element group in the second direction. In some examples, as shown in FIG. 3, in one light-emitting element group 310, the first via 2421 is located on one side of the bisector of the first anode 1751 along the second direction, for example, on one side of the bisector of the first anode 1751 along the second direction, closer to the third anode 1753, the second via 2422 is located on one side of the bisector of the second anode 1752 along the second direction, closer to the first anode 1751, and the third via 2423 is located on one side of the bisector of the third anode 1753 along the second direction, closer to the first anode 1751.

[0054] In some examples, as shown in FIG. 6, the plurality of fourth vias 2424 corresponding to one light-emitting element row 330 are approximately on a straight line extending along the first direction and passing through the plurality of first anodes 1751 or the plurality of first vias 2421 corresponding to the light-emitting element row 330.

[0055] In some examples, as shown in FIG. 6, the plurality of fourth vias 2424 corresponding to one light-emitting element column 320 extend approximately along the second direction and are on a second straight line passing through the effective light-emitting areas of the plurality of first anodes 1751 or the plurality of first light-emitting elements 311 corresponding to the light-emitting element column 320.

[0056] In some examples, as shown in FIG. 6, the distance from the fourth anode 1754 to the nearest first anode 1751 is less than the distance from the first anode 1751 to the nearest fourth anode 1754 located in the same row.

[0057] 6 , the light-emitting element group 310 includes a first light-emitting element group and a second light-emitting element group that are adjacent to each other in the second direction and are respectively arranged in two adjacent light-emitting element rows 330, and the connection portion of the fourth anode 1754 of the first light-emitting element group and the connection portion of the first anode 1751 of the second light-emitting element group are both located on the same side of the bisector of the fourth anode 1754 along the second direction. In other words, the connection portion of the fourth anode and the connection portion of the first anode adjacent to the fourth anode in the second direction are located on the same side of the bisector of the body portion of the fourth anode along the second direction.

[0058] In some examples, as shown in FIG. 6, the shape of the main body of the first anode 1751 includes a hexagon, and the point of the first anode 1751 closest to the fourth anode 1754 adjacent to the first anode 1751 in the second direction is a vertex of the hexagon.

[0059] In some examples, as shown in FIG. 6, two adjacent light-emitting element rows 330 are arranged with a 1 / 2 pitch offset, and the pitch is equal to the distance between the centers of the effective light-emitting areas of the two first light-emitting elements 311 of two adjacent light-emitting element groups 310 in the first direction.

[0060] In some examples, as shown in FIG. 6, the first line 301 is located between two adjacent light emitting element rows 330 .

[0061] 5A, 5B, and 6, the orthogonal projection of the first via 2421 closest to the first line 301 on the base substrate 110 is located on one side of the first line 301 closer to the first anode 1751 corresponding to the first via 2421. That is, the display substrate moves the position of the first via in a direction closer to the first anode, thereby achieving the following beneficial effects: (1) increasing the distance between the first via and the effective light-emitting area of the fourth light-emitting element closest in the second direction, thereby ensuring the flatness of the fourth anode located in the effective light-emitting area of the adjacent fourth light-emitting element and further avoiding the occurrence of color cast, (2) shortening the distance between the first via and the effective light-emitting area of the first light-emitting element, thereby reducing the resistance between the first anode located in the effective light-emitting area of the first light-emitting element and the first connecting electrode, and (3) increasing the distance between the first anode and the fourth anode, thereby avoiding short-circuiting between the first anode and the fourth anode due to residues from the manufacturing process. Of course, the embodiments of the present disclosure are not limited thereto, and the orthogonal projection of the first via on the base substrate may be on the first straight line.

[0062] 6 , the distance between the orthogonal projection of the fourth via 2424 on the base substrate 110 and the orthogonal projection of the first straight line 301 on the base substrate 110 is greater than the distance between the orthogonal projection of the first via 2421 on the base substrate 110 and the orthogonal projection of the first straight line 301 on the base substrate 110. In other words, the offset amount of the fourth via is greater than that of the first straight line. Of course, the embodiments of the present disclosure are not limited thereto, and the offset amount of the fourth via from the first straight line may be the same as that of the first via.

[0063] 6 , there is a first shortest distance L1 between the orthogonal projection of the effective light-emitting area of the second light-emitting element 312 on the base substrate 110 and the orthogonal projection of the second via 2422 on the base substrate 110, and there is a second shortest distance L2 between the orthogonal projection of the effective light-emitting area of the third light-emitting element 313 on the base substrate 110 and the orthogonal projection of the third via 2423 on the base substrate 110, and the first shortest distance L1 and the second shortest distance L2 are approximately the same. However, the phrase "the first shortest distance and the second shortest distance being approximately the same" not only includes the case where the first shortest distance and the second shortest distance are completely the same, but also includes the case where the difference between the first shortest distance and the second shortest distance is less than 1 micron.

[0064] Therefore, according to the display substrate, the second anode located in the effective light-emitting area of the second light-emitting element and the third anode located in the effective light-emitting area of the third light-emitting element can be inclined to the same degree but in opposite directions, thereby effectively avoiding the occurrence of color cast. However, if the second anode located in the effective light-emitting area of the second light-emitting element and the third anode located in the effective light-emitting area of the third light-emitting element are not inclined, the degree of inclination of the second anode in the effective light-emitting area of the second light-emitting element and the third anode located in the effective light-emitting area of the third light-emitting element is considered to be zero, and the first shortest distance between the orthogonal projection of the effective light-emitting area of the second light-emitting element on the base substrate and the orthogonal projection of the second via on the base substrate may be the shortest distance between the edge of the orthogonal projection of the effective light-emitting area of the second light-emitting element on the base substrate and the edge of the orthogonal projection of the second via on the base substrate; similarly, the second shortest distance between the orthogonal projection of the effective light-emitting area of the third light-emitting element on the base substrate and the orthogonal projection of the third via on the base substrate may be the shortest distance between the edge of the orthogonal projection of the effective light-emitting area of the third light-emitting element on the base substrate and the edge of the orthogonal projection of the third via on the base substrate.

[0065] 6, in some examples, the distance C between the orthogonal projection of the fourth via 2424 on the base substrate 110 and the orthogonal projection of the effective light-emitting area of the first light-emitting element 311 adjacent in the second direction on the base substrate 110 is more than 1.2 times the width A in the first direction of the effective light-emitting area of the first light-emitting element 311 adjacent in the second direction, thereby ensuring that the display substrate has relatively high flatness of the first anode located in the effective light-emitting area of the first light-emitting element.

[0066] In some examples, as shown in FIG. 6, the shortest distance B between the fourth via 2424 of one light-emitting element group 310 and the first anode 1751 of an adjacent light-emitting element group 310 is less than the distance E between the fourth via 2424 of the light-emitting element group 310 and the effective light-emitting area of the corresponding fourth light-emitting element 314.

[0067] 6 , the shortest distance between the fourth anode 1754 of one light-emitting element group 310 and the first anode 1751 of the light-emitting element group 310 that is closest to the fourth anode 1754 in the second direction is the distance between the vertex of the first anode 1751 of the adjacent light-emitting element group 310 and the fourth anode 1754 of the light-emitting element group 310. In other words, the vertex of the first anode 1751 of the adjacent light-emitting element group 310 is the point that is closest to the fourth anode 1754 of the light-emitting element group 310. For example, the shape of the orthogonal projection of the first anode 1751 on the base substrate 110 is a hexagon, and the vertex is the vertex on the major axis of the hexagon.

[0068] 3, 4A, 4B, 5A, 5B, and 6, the display substrate 100 further includes a pixel defining layer 190 located on one side of the first anode 1751, the second anode 1752, the third anode 1753, and the fourth anode 1754, away from the base substrate 110, the pixel defining layer 190 having a first opening 1951, a second opening 1952, a third opening 1953, and a fourth opening 1954. The first light-emitting element 311 includes a first light-emitting portion 1851, the second light-emitting element 312 includes a second light-emitting portion 1852, the third light-emitting element 313 includes a third light-emitting portion 1853, and the fourth light-emitting element 314 includes a fourth light-emitting portion 1854. the first opening 1951 is located within an orthogonal projection of the first anode 1751 on the base substrate 110, and at least a portion of the first light-emitting portion 1851 is located in the first opening 1951 to cover an exposed portion of the first anode 1751; the second opening 1952 is located within an orthogonal projection of the second anode 1752 on the base substrate 110, and at least a portion of the second light-emitting portion 1852 is located in the second opening 1952 to cover an exposed portion of the second anode 1752; The third opening 1953 is located within the orthogonal projection of the third anode 1753 on the base substrate 110, and at least a portion of the third light-emitting portion 1853 is located in the third opening 1953 to cover the exposed portion of the third anode 1753, and the fourth opening 1954 is located within the orthogonal projection of the fourth anode 1754 on the base substrate 110, and at least a portion of the fourth light-emitting portion 1854 is located in the fourth opening 1954 to cover the exposed portion of the fourth anode 1754. The area defined by the first opening 1951 is the effective light-emitting area of the first light-emitting element 313, the area defined by the second opening 1952 is the effective light-emitting area of the second light-emitting element 312, the area defined by the third opening 1953 is the effective light-emitting area of the third light-emitting element 313, and the area defined by the fourth opening 1954 is the effective light-emitting area of the fourth light-emitting element 314.

[0069] 6 , the distance C between the orthogonal projection of the fourth via 2424 on the base substrate 110 and the orthogonal projection of the first opening 1951 adjacent to the fourth via 2424 in the second direction on the base substrate 110 is more than 1.2 times the width A in the first direction of the first opening 1951. This ensures that the display substrate has a relatively high degree of flatness for the first anode located in the first opening (i.e., the portion of the first anode exposed by the first opening).

[0070] In some examples, as shown in Figures 3, 4A, 4B, 5A, 5B, and 6, the display substrate 100 comprises a first flat layer 241 and a first conductive layer 150, where the first flat layer 241 is located on one side of the second conductive layer 160 closer to the base substrate 110, and the first conductive layer 150 is located on one side of the first flat layer 241 closer to the base substrate 110. The first conductive layer 150 has a first drain 1511, a second drain 1512, a third drain 1513 and a fourth drain 1514, and the first flat layer 241 has a fifth via 2415, a sixth via 2416, a seventh via 2417 and an eighth via 2418, and the first connection electrode 1611 is connected to the first drain 1511 via the fifth via 2415, the second connection electrode 1612 is connected to the second drain 1512 via the sixth via 2416, the third connection electrode 1613 is connected to the third drain 1513 via the seventh via 2417, and the fourth connection electrode 1614 is connected to the fourth drain 1514 via the eighth via 2418.

[0071] In some examples, as shown in Figures 4A and 4B, the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654, wherein the first drain 1511 is part of the first pixel driving circuit 2651, the second drain 1512 is part of the second pixel driving circuit 2652, the third drain 1513 is part of the third pixel driving circuit 2653, and the fourth drain 1514 is part of the fourth pixel driving circuit 2654. The first pixel driving circuit 2651 is connected to the first anode 1751 via the first connecting electrode 1611 and applies a driving signal to the first anode 1751, the second pixel driving circuit 2652 is connected to the second anode 1752 via the second connecting electrode 1612 and applies a driving signal to the second anode 1752, the third pixel driving circuit 2653 is connected to the third anode 1753 via the third connecting electrode 1613 and applies a driving signal to the third anode 1753, and the fourth pixel driving circuit 2654 is connected to the fourth anode 1754 via the fourth connecting electrode 1614 and applies a driving signal to the fourth anode 1754.

[0072] 7 is a schematic diagram of the planar relationship between the second conductive layer and the anode layer of a display substrate according to an embodiment of the present disclosure. As shown in FIGS. 6 and 7, the second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the first direction, and the second conductive layer 160 includes a first conductive portion 1621, a second conductive portion 1622, and a third conductive portion 1623 extending along the second direction. and a fourth conductive portion 1624, wherein the first conductive portion 1621 is located on one side of the first anode 1751 away from the anode pair 1755, the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755, the third conductive portion 1623 is located between the anode pair 1755 and the fourth anode 1754, and the fourth conductive portion 1624 overlaps with the fourth anode 1754. In the display substrate, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, and the fourth conductive portion 1624 extending along the second direction can be connected to the power line of the first conductive layer 150 to reduce the resistance of the power line.

[0073] 7 , the orthogonal projections of the first conductive portion 1621 and the second conductive portion 1622 on the base substrate 110 do not overlap with the orthogonal projection of the first anode 1751 on the base substrate 110, and the orthogonal projections of the second conductive portion 1622 and the third conductive portion 1623 on the base substrate 110 do not overlap with the orthogonal projection of the anode pair 1755 on the base substrate 110. As a result, the first conductive portion 1621 and the second conductive portion 1622 have little effect on the planarity of the first anode 175, and the second conductive portion 1622 and the third conductive portion 1623 have little effect on the planarity of the second anode 1752 and the third anode 1753 of the anode pair 1755. Of course, the embodiments of the present disclosure are not limited thereto, and the first conductive portion, the second conductive portion, and the third conductive portion may overlap with the anodes.

[0074] For example, the orthogonal projections of the first conductive portion 1621 and the second conductive portion 1622 on the base substrate 110 have first and second overlapping portions, respectively, with the orthogonal projections of the first anode 1751 on the base substrate 110, and the areas of the first overlapping portion and the second overlapping portion are substantially the same, thereby improving the flatness of the first anode 1751. Similarly, the orthogonal projections of the second conductive portion 1622 and the third conductive portion 1623 on the base substrate 110 have third and fourth overlapping portions, respectively, with the orthogonal projections of the anode pair 1755 on the base substrate 110, and the areas of the third overlapping portion and the fourth overlapping portion are substantially the same, thereby improving the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755. However, the above "almost the same" includes cases where they are completely the same and cases where the difference between the two is less than 10% of the average value of both.

[0075] For example, the first overlapping portion and the second overlapping portion are symmetrical with respect to the bisector along the second direction of the main body portion of the first anode 1751, i.e., the effective light-emitting area of the first light-emitting element 311, thereby further enhancing the flatness of the effective light-emitting area of the first light-emitting element 311, and the third overlapping portion and the fourth overlapping portion are symmetrical with respect to the bisector along the second direction of the anode pair 1755, thereby further enhancing the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755.

[0076] 7 , the orthogonal projection of the fourth conductive portion 1624 on the base substrate 110 passes through the center of the orthogonal projection of the fourth anode 1754 on the base substrate 110, and the orthogonal projection of the bisector of the fourth conductive portion 1624 along the second direction on the base substrate 110 overlaps with the orthogonal projection of the bisector of the effective light-emitting area of the fourth light-emitting element 314 along the second direction on the base substrate 110. This can also improve the flatness of the fourth anode 1754.

[0077] In some examples, as shown in FIG. 7 , the second conductive layer 160 further comprises a fifth conductive portion 1625 and a sixth conductive portion 1626 extending along the first direction, wherein the fifth conductive portion 1625 is connected to the second conductive portion 1622 and the third conductive portion 1623, respectively, and is located between the second anode 1752 and the third anode 1753, and the sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624, respectively, and is located between the first anode 1751 and the fourth anode 1754 adjacent in the second direction. As a result, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625 and the sixth conductive portion 1626 can form a mesh structure, which can further reduce the resistance of the power line of the first conductive layer and further improve the electrical performance of the display substrate.

[0078] 7, the second conductive portion 1622 includes a main body portion 1622A extending along the second direction, a spacer block 1622B, and a connection block 1622C. The spacer block 1622B is located on one side of the main body portion 1622A close to the first anode 1751 and is spaced apart from the main body portion 1622A. The spacer block 1622B is connected to the main body portion 1622A via the connection block 1622C. Generally, since the size (i.e., width) of the first anode in the first direction is small, the distance between the first conductive portion and the main body portion of the second conductive portion is large. Therefore, installing the spacer block can improve the symmetry of the first conductive portion and the second conductive portion on both sides of the first anode, thereby improving the flatness of the first anode.

[0079] In some examples, the first light-emitting element is configured to emit light of a first color, the second and third light-emitting elements are configured to emit light of a second color, and the fourth light-emitting element is configured to emit light of a third color.

[0080] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is, the display substrate uses a GGRB pixel arrangement structure.

[0081] An embodiment of the present disclosure further provides a display device. FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 8, the display device 400 includes any of the display substrates 100 described above. As a result, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device ensures the flatness of the first anode located in the effective light-emitting area of the first light-emitting element, thereby avoiding color cast; reduces the resistance between the fourth anode located in the effective light-emitting area of the fourth light-emitting element and the fourth connecting electrode; and increases the distance between the first anode and the fourth anode, thereby avoiding short-circuiting between the first anode and the fourth anode due to residues from the manufacturing process.

[0082] For example, the display device may be a display panel, or may be an electronic product with a display function, such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigation device, or a digital photo frame.

[0083] On the other hand, the inventors of the present application have found that the second source / drain metal layer under the anode is thick and unevenly distributed, which also causes the anode to be uneven.

[0084] 9 is a partial cross-sectional view of another display substrate, and FIG. 10 is a partial cross-sectional view of another display substrate. As shown in FIG. 9, the second source / drain metal layer 160 includes a plurality of wirings 168. If there are wirings 168 on one side below the anode 175 but not on the other side, there will be a height difference on both sides of the anode 175, which will cause the anode 175 to tilt and result in color cast. As shown in FIG. 10, if there are wirings 168 on both sides of the anode 175 or if there are no wirings 168 below the anode 175, the anode 175 can be made more flat, which will ensure that the luminous intensity of the anode 175 in different directions is consistent and will effectively reduce color cast.

[0085] In contrast, an embodiment of the present disclosure provides a display substrate and a display device, the display substrate comprising a base substrate, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, and a plurality of light-emitting element groups, wherein the first conductive layer is disposed on the base substrate, the first flat layer is disposed on one side of the first conductive layer away from the base substrate, the second conductive layer is disposed on one side of the first flat layer away from the first conductive layer, the second flat layer is disposed on one side of the second conductive layer away from the first flat layer, and the plurality of light-emitting element groups are disposed on one side of the second flat layer away from the second conductive layer. The plurality of light emitting element groups are arranged along a first direction to form a plurality of light emitting element columns, and are arranged along a second direction to form a plurality of light emitting element rows, and each of the light emitting element groups includes one first light emitting element, one second light emitting element, one third light emitting element, and one fourth light emitting element, the first light emitting element including a first anode, and the second conductive layer including a first conductive portion and a second conductive portion extending along the second direction, the first conductive portion being located on one side of the first anode, and the second conductive portion being located on one side of the first anode away from the first conductive portion. the first conductive portion has an extension portion and an offset portion, the orthogonal projection of the effective light-emitting area of the first light-emitting element on a straight line extending along the second direction is covered by the orthogonal projection of the offset portion on the straight line, the orthogonal projection of the offset portion on the base substrate and the orthogonal projection of the first anode on the base substrate are arranged at a distance from each other, the extension portion is close to the second conductive portion, and the straight line on which the edge extending along the second direction is located is the first straight line, and the offset portion is arranged at a distance from the first straight line and is located on one side of the first straight line away from the second conductive portion. Therefore, the first conductive portion is located on one side of the first anode, the second conductive portion is located on one side of the first anode away from the first conductive portion, and the orthogonal projection of the offset portion on the base substrate and the orthogonal projection of the first anode on the base substrate are spaced apart. Therefore, the first conductive portion and the second conductive portion of the second conductive layer have little effect on the flatness of the first anode, thereby ensuring a higher flatness of the first anode, which in turn ensures that the luminous intensities of the first anode in different directions are consistent, and further effectively reduces color cast.

[0086] Hereinafter, a display substrate and a display device provided according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0087] One embodiment of the present disclosure provides a display substrate. Fig. 11 is a schematic plan view of another display substrate according to one embodiment of the present disclosure, Fig. 12A is a schematic cross-sectional view of the display substrate according to one embodiment of the present disclosure taken along the HH direction of Fig. 11, Fig. 12B is a schematic cross-sectional view of the display substrate according to one embodiment of the present disclosure taken along the JJ direction of Fig. 11, Fig. 13 is a schematic plan view of another display substrate according to one embodiment of the present disclosure, and Fig. 14 is a schematic plan view of another display substrate according to one embodiment of the present disclosure. To clearly show the positional relationship between each conductive portion of the second conductive layer and the anode, only the second conductive layer and the anode layer are shown in Fig. 14.

[0088] As shown in Figures 11-14, the display substrate 100 comprises a base substrate 110, a first conductive layer 150, a first flat layer 241, a second conductive layer 160, a second flat layer 242, and a plurality of light-emitting element groups 310, wherein the second conductive layer 160 is located on the base substrate 110, the second flat layer 242 is located on one side of the second conductive layer 160 away from the base substrate 110, and the plurality of light-emitting element groups 310 are located on one side of the second flat layer 242 away from the base substrate 110. A plurality of light-emitting element groups 310 are arranged along a first direction to form a plurality of light-emitting element columns 320, and are arranged along a second direction to form a plurality of light-emitting element rows 330, and each of the light-emitting element groups 310 includes one first light-emitting element 311, one second light-emitting element 312, one third light-emitting element 313, and one fourth light-emitting element 314, and the first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754, and the second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, and the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the first direction. The second conductive layer 160 has a first conductive portion 1621 and a second conductive portion 1622 extending along the second direction, and the first conductive portion 1621 is located on one side of the first anode 1751 away from the anode pair 1755, and the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755, i.e., on one side of the first anode 1751 away from the first conductive portion 1621. The first conductive portion 1621 has an extension portion 1621A and an offset portion 1621B, and the orthogonal projection on a straight line extending along the second direction of the effective light-emitting area of the first light-emitting element 311 is covered by the orthogonal projection on a straight line of the offset portion 1621B, i.e., the orthogonal projection of the effective light-emitting area of the first light-emitting element 311 on the first conductive portion 1621 is at the position of the offset portion 1621B, i.e., the offset portion 1621B corresponds to the effective light-emitting area of the first light-emitting element 311.The orthogonal projection of the offset portion 1621B on the base substrate 110 and the orthogonal projection of the first anode 1751 on the base substrate 110 are disposed at a distance from each other, the extension portion 1621A is close to the second conductive portion 1622, and the straight line on which the edge extending along the second direction is located is the first straight line 302, and the offset portion 1621B is disposed at a distance from the first straight line 302 and is located on one side of the first straight line 302 away from the second conductive portion 1622. However, the first conductive layer and the second conductive layer are laminated in order along the direction away from the base substrate.

[0089] In the display substrate provided by the embodiments of the present disclosure, the first conductive portion is located on one side of the first anode, the second conductive portion is located on one side of the first anode, and the orthogonal projection of the offset portion on the base substrate is spaced apart from the orthogonal projection of the first anode on the base substrate, so the first conductive portion and the second conductive portion of the second conductive layer have little effect on the flatness of the first anode, thereby ensuring a higher flatness of the first anode, ensuring that the luminous intensity of the first anode in different directions is consistent, and effectively reducing color cast. Furthermore, because the offset portion is spaced apart from the first line and located on one side of the first line, away from the second conductive portion, the offset portion is offset away from the first anode, providing space for the first anode, thereby achieving close anode placement and ensuring a higher flatness of the first anode.

[0090] However, the arrangement of the above-mentioned multiple light-emitting elements may refer to the arrangement shown in Figure 6, i.e., two adjacent light-emitting element rows are installed with a 1 / 2 pitch offset, and the pitch is equal to the distance between the centers of the effective light-emitting areas of the two first light-emitting elements of two light-emitting element groups adjacent in the first direction.

[0091] In some examples, the first light-emitting element 311 is configured to emit light of a first color, the second light-emitting element 312 and the third light-emitting element 313 are configured to emit light of a second color, and the fourth light-emitting element 314 is configured to emit light of a third color.

[0092] In some examples, the first color is red, the second color is green, and the third color is blue.

[0093] 11-14, the orthogonal projection of the first straight line 302 on the base substrate 110 passes through the orthogonal projection of the first anode 1751 on the base substrate 110, thereby enabling the display substrate to achieve close anode placement while simultaneously ensuring higher flatness of the first anode.

[0094] 11-14, the bisector of extension portion 1621A extending in the second direction is located on second line 303, and offset portion 1621B is spaced apart from second line 303 and is located on one side of second line 303 away from second conductive portion 1622. As a result, because the offset portion is spaced apart from the second line and is located on one side of the second line away from the anode pair, the offset portion is offset in a direction away from the first anode, providing space for the placement of the first anode, thereby realizing close anode placement and ensuring greater flatness of the first anode.

[0095] 11-14, the orthogonal projection of the second straight line 303 on the base substrate 110 passes through the orthogonal projection of the first anode 1751 on the base substrate 110, thereby enabling the display substrate to achieve close anode placement while simultaneously ensuring greater flatness of the first anode.

[0096] In some examples, as shown in Figures 11-14, the first anode 1751 extends along the second direction, and the second conductive portion 1622 has a main body portion 1622A and a spacer block 1622B extending along the second direction, wherein the orthogonal projection of the main body portion 1622A on the base substrate 110 and the orthogonal projection of the first anode 1751 on the base substrate 110 are spaced apart, and the spacer block 1622B is located on one side of the main body portion 1622A closer to the first anode 1751, and the distance between the orthogonal projection of the spacer block 1622B on the base substrate 110 and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 is approximately the same as the distance between the orthogonal projection of the first conductive portion 1621 on the base substrate 110 and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110.

[0097] In the display substrate, the size (i.e., width) of the first anode in the first direction is generally small, so the distance between the first conductive portion and the main body of the second conductive portion is large, and the distance between the orthogonal projection of the spacer block on the base substrate and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element on the base substrate is approximately the same as the distance between the orthogonal projection of the first conductive portion on the base substrate and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element on the base substrate. Therefore, installing the spacer block can improve the symmetry between the first conductive portion and the second conductive portion on both sides of the first anode, and further improve the flatness of the first anode.

[0098] In some examples, as shown in Figures 11-14, the distance between the orthogonal projection of the first conductive portion 1621 on the base substrate 110 and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 is less than the distance between the orthogonal projection of the main body portion 1622A on the base substrate 110 and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110.

[0099] For example, the ratio of the distance between the orthogonal projection of the first conductive portion 1621 on the base substrate 110 and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 to the distance between the orthogonal projection of the main body portion 1622A on the base substrate 110 and the orthogonal projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 is 1 / 3 or less.

[0100] 11-14, the orthogonal projection of the spacer block 1622B on the base substrate 110 and the orthogonal projection of the body portion 1622A on the base substrate 110 are spaced apart, and the second conductive portion 1622 further includes a connecting portion 1622C, and the spacer block 1622B is connected to the body portion 1622A through the connecting portion 1622C. As a result, since the spacer block 1622B is connected to the body portion 1622A through the connecting portion 1622C and is not integrally formed with the body portion 1622A, excessive overlap between the second conductive portion 1622 and underlying film layers such as semiconductor layers, gate layers, etc. can be avoided, thereby avoiding an increase in the load on the film layers below the second conductive portion 1622. As a result, the display substrate can increase the number of spacer blocks while ensuring normal operation of each subpixel.

[0101] 12B, the first conductive layer 150 includes a power line 151 and a data line 152 extending along the second direction, a first connection block 1541, and a second connection block 1542. The first connection block 1541 connects the initialization signal line to a corresponding source region of the pixel driving circuit, and the second connection block 1542 connects the drain region of the compensation thin film transistor to the first electrode block CE1, which can form a storage capacitor with the second electrode block CE2 and is also used as a gate for driving the thin film transistor. Therefore, the spacer block 1622B is connected to the body portion 1622A via the connecting portion 1622C, and is not integral with the body portion 1622A, so that excessive overlap between the second conductive portion 1622 and the second connecting block 1542 can be avoided, thereby reducing the load of the second connecting block 1542, i.e., the load of the drain of the compensation thin film transistor and the gate of the driving thin film transistor, and further improving the performance of the display substrate. However, although the display substrate uses a 7T1C pixel driving circuit, of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may use other suitable pixel driving circuit structures.

[0102] 12B , the orthogonal projection of the offset portion 1621B on the base substrate 110 and the orthogonal projection of the first anode 1751 on the base substrate are spaced apart, and the orthogonal projection of the spacer block 1622B on the base substrate 110 and the orthogonal projection of the first anode 1751 on the base substrate 110 are spaced apart. For example, as shown in FIG. 12B , the display substrate may further include a protective layer 364 located between the first conductive layer 150 and the first flat layer 241. Of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may not include a protective layer.

[0103] 11-14, the distance between the orthogonal projection of the spacer block 1622B on the base substrate 110 and the orthogonal projection of the body portion 1622A on the base substrate 110 exceeds the width of the orthogonal projection of the spacer block 1622B on the base substrate 110 along the first direction. This allows the display substrate to further avoid excessive overlap between the second conductive portion 1622 and underlying film layers such as semiconductor layers, gate layers, etc., thereby avoiding increasing the load on the film layers such as semiconductor layers, gate layers, etc. This allows the display substrate to increase the spacer block while ensuring normal operation of each subpixel.

[0104] 11-14, the second conductive portion 1622 includes two connecting portions 1622C, each of which is located at one end of the spacer block 1622B in the second direction, and the spacer block 1622B, the two connecting portions 1622C, and the body portion 1622A surround a rectangular opening. This allows the display substrate to further avoid excessive overlap between the second conductive portion 1622 and underlying film layers, such as the semiconductor layer, gate layer, etc., thereby avoiding increased loads on the semiconductor layer, gate layer, etc. This allows the display substrate to increase the number of spacer blocks while still ensuring normal operation of each subpixel.

[0105] In some examples, the ratio of the width of the spacer block in the first direction to the width of the main body portion in the first direction is 1 / 2 or less, and the ratio of the width of the spacer block in the first direction to the distance from the main body portion to the spacer block is 1 / 2 or less.

[0106] In some examples, the ratio of the length of the spacer block in the second direction to the length of the effective light-emitting area of the first light-emitting element in the second direction is 7 / 8 or more.

[0107] In some examples, the included angle between the central connecting line between the effective light-emitting area of the first light-emitting element and the spacer block and the first direction is less than 30 degrees. For example, the included angle between the central connecting line between the effective light-emitting area of the first light-emitting element and the spacer block and the first direction is zero, i.e., the central connecting line between the effective light-emitting area of the first light-emitting element and the spacer block is parallel to the first direction.

[0108] In some examples, the orthogonal projection of the spacer block on the base substrate and the orthogonal projection of the first anode on the base substrate are spaced apart, and the orthogonal projection of the first conductive portion on the base substrate and the orthogonal projection of the first anode on the base substrate are spaced apart.

[0109] In some examples, the overlapping area between the orthogonal projection of the spacer block on the base substrate and the orthogonal projection of the first anode on the base substrate is approximately the same as the overlapping area between the orthogonal projection of the first conductive portion on the base substrate and the orthogonal projection of the first anode on the base substrate. In some examples, as shown in Figures 11-14, the second conductive layer 160 further includes a third conductive portion 1623 and a fourth conductive portion 1624 extending along the second direction, wherein the third conductive portion 1623 is located between the anode pair 1755 and the fourth anode 1754, and the fourth conductive portion 1624 overlaps with the fourth anode 1754.

[0110] 11-14 , the distance between the orthogonal projection of the body portion 1622A of the second conductive portion 1622 on the base substrate 110 and the orthogonal projection of the bisector of the effective light-emitting area of the second light-emitting element 312 along the second direction on the base substrate 110 is approximately the same as the distance between the orthogonal projection of the third conductive portion 162 on the base substrate 110 and the orthogonal projection of the bisector of the effective light-emitting area of the second light-emitting element 312 along the second direction on the base substrate 110. This can improve the symmetry of the second conductive portion and the third conductive portion on both sides of the anode pair, and thereby further improve the flatness of the second anode and the third anode.

[0111] 11-14 , the fourth anode 1754 extends along the second direction, and the orthogonal projection of the fourth conductive portion 1624 on the base substrate 110 passes through the center of the orthogonal projection of the effective light-emitting area of the fourth light-emitting element 314 on the base substrate 110. Therefore, even if the fourth conductive portion 162 and the fourth anode 1754 overlap, the orthogonal projection of the fourth conductive portion 1624 on the base substrate 110 passes through the center of the orthogonal projection of the effective light-emitting area of the fourth light-emitting element 314 on the base substrate 110. Therefore, the fourth conductive portion can ensure higher flatness of the fourth anode, thereby ensuring that the light-emitting intensities of the fourth anode in different directions are consistent and further improving the color cast phenomenon.

[0112] In some examples, as shown in Figures 11-14, the second conductive layer 160 further includes a fifth conductive portion 1625 and a sixth conductive portion 1626 extending along the first direction, wherein the fifth conductive portion 1625 is connected to the main body portion 1622A and the third conductive portion 1623, respectively, and is located between the second anode 1752 and the third anode 1753 of the anode pair 1755, and the sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624, respectively, and is located between the first anode 1751 and the fourth anode 1754 adjacent in the second direction. As a result, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625 and the sixth conductive portion 1626 can form a mesh structure, which can further reduce the resistance of the power line of the first conductive layer and further improve the electrical performance of the display substrate.

[0113] In some examples, as shown in Figures 11-14, the second conductive layer 160 has a first connection electrode 1611, a second connection electrode 1612, a third connection electrode 1613, and a fourth connection electrode 1614, the second flat layer 242 has a first via 2421, a second via 2422, a third via 2423, and a fourth via 2424, and the first anode 1751 is connected to the first connection electrode 1611 through the first via 2421, the second anode 1752 is connected to the second connection electrode 1612 through the second via 2422, the third anode 1753 is connected to the third connection electrode 1613 through the third via 2423, and the fourth anode 1754 is connected to the fourth connection electrode 1614 through the fourth via 2424.

[0114] In some examples, as shown in Figures 11-14, the first planar layer 241 is located on one side of the second conductive layer 160 closer to the base substrate 110, and the first conductive layer 150 is located on one side of the first planar layer 241 closer to the base substrate 110. The first conductive layer 150 has a first drain 1511, a second drain 1512, a third drain 1513 and a fourth drain 1514, the first flat layer 241 has a fifth via 2415, a sixth via 2416, a seventh via 2417 and an eighth via 2418, the first connection electrode 1611 is connected to the first drain 1511 via the fifth via 2415, the second connection electrode 1612 is connected to the second drain 1512 via the sixth via 2416, the third connection electrode 1613 is connected to the third drain 1513 via the seventh via 2417, and the fourth connection electrode 1614 is connected to the fourth drain 1514 via the eighth via 2418.

[0115] In some examples, as shown in Figures 11-14, the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654, wherein the first drain 1511 is part of the first pixel driving circuit 2651, the second drain 1512 is part of the second pixel driving circuit 2652, the third drain 1513 is part of the third pixel driving circuit 2653, and the fourth drain 1514 is part of the fourth pixel driving circuit 2654. The first pixel driving circuit 2651 is connected to the first anode 1751 via the first connecting electrode 1611 and applies a driving signal to the first anode 1751, the second pixel driving circuit 2652 is connected to the second anode 1752 via the second connecting electrode 1612 and applies a driving signal to the second anode 1752, the third pixel driving circuit 2653 is connected to the third anode 1753 via the third connecting electrode 1613 and applies a driving signal to the third anode 1753, and the fourth pixel driving circuit 2654 is connected to the fourth anode 1754 via the fourth connecting electrode 1614 and applies a driving signal to the fourth anode 1754.

[0116] For example, the thickness range of the second conductive layer may be 0.6-0.8 microns, such as 0.7 microns, and the thickness range of the second planar layer may be 1.3-1.7 microns, such as 1.5 microns.

[0117] 15 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. To clearly illustrate the positional relationship between each conductive portion of the second conductive layer and the anode, only the second conductive layer and the anode layer are shown in FIG. 15. As shown in FIG. 15, the second conductive portion 1622 of the second conductive layer 160 does not have a spacer block, and the first conductive portion 1621 of the second conductive layer 160 has an extension portion 1621A and an offset portion 1621B. The orthogonal projection of the effective light-emitting area of the first light-emitting element 311 on the first conductive portion 1621 is located at the offset portion 1621B, i.e., the offset portion 1621B corresponds to the effective light-emitting area of the first light-emitting element 311. The orthogonal projection of the offset portion 1621B on the base substrate 110 and the orthogonal projection of the first anode 1751 on the base substrate 110 are spaced apart, the extension portion 1621A is close to the first anode 1751 and the straight line on which the edge extending along the second direction is located is the first straight line 302, and the offset portion 1621B is spaced apart from the first straight line 302 and is located on one side of the first straight line 302 away from the anode pair 1755.

[0118] In the display substrate provided by the embodiments of the present disclosure, the first conductive portion is located on one side of the first anode away from the anode pair, the second conductive portion is located between the first anode and the anode pair, and the orthogonal projection of the offset portion on the base substrate and the orthogonal projection of the first anode on the base substrate are spaced apart, so the first conductive portion and the second conductive portion of the second conductive layer have little effect on the flatness of the first anode, thereby ensuring a higher flatness of the first anode, ensuring that the luminous intensity of the first anode in different directions is consistent, and effectively reducing color cast.In addition, because the offset portion and the first straight line are spaced apart and located on one side of the first straight line away from the anode pair, the offset portion is offset away from the first anode, providing space for the first anode, thereby achieving close anode placement and ensuring a higher flatness of the first anode.

[0119] For example, as shown in FIG. 15 , the first anode 1751 may have a body portion 1751A, a connecting portion 1751B and a supplemental portion 1751C, where the effective light-emitting area of the first light-emitting element is in the body portion 1751A, the connecting portion 1751B connects the first anode 1751 to a corresponding pixel driving circuit, and the supplemental portion 1751C covers the potential at the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3 of the corresponding pixel driving circuit, thereby stabilizing the potential at the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3, and further improving the long-term light-emitting stability and service life of the display substrate.

[0120] 15 , the distance between the first anode 1751 and the offset portion 1621B may be in the range of 2.5-3.2 microns, e.g., 2.9 microns, the distance between the main body portion 1751A of the first anode 1751 and the second conductive portion 1622 may be in the range of 9-11 microns, e.g., 10.5 microns, the distance between the connection portion 1751B of the first anode 1751 and the second conductive portion 1622 may be in the range of 5-7 microns, the complementary portion 1751C of the first anode 1751 may partially overlap the second conductive portion 1622, and the width of the overlapping portion in the first direction is less than 1 micron, e.g., 0.79 microns. Because the distance between the edge of the complementary portion closest to the second conductive portion and the main body portion is large, the complementary portion 1751C partially overlaps the second conductive portion 1622 and has little effect on the flatness of the first anode.

[0121] An embodiment of the present disclosure further provides a display device. FIG. 16 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 16, the display device 400 includes any of the display substrates 100 described above. As a result, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device ensures the flatness of the first anode located in the effective light-emitting area of the first light-emitting element, thereby preventing color cast; reduces the resistance between the fourth anode located in the effective light-emitting area of the fourth light-emitting element and the fourth connecting electrode; and increases the distance between the first anode and the fourth anode, thereby preventing short-circuiting between the first anode and the fourth anode due to residues from the manufacturing process.

[0122] For example, the display device may be an electronic product with a display function, such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigation device, or a digital photo frame.

[0123] Meanwhile, in the manufacturing process of an organic light emitting diode display device, the light emitting layer is usually manufactured by a deposition process. To prevent the fine metal mask (FMM) from touching and damaging the organic light emitting diode display substrate during the deposition process, a spacer is usually formed on the organic light emitting diode display substrate and the fine metal mask is placed on the spacer. In this case, the spacer supports the fine metal mask, thereby protecting the organic light emitting diode display substrate.

[0124] However, after further research, the inventors of the present application found that, since spacers are typically located at the center of the vertical sides of the effective light-emitting area of a subpixel, when a fine metal mask is used for deposition, the opening edge of the fine metal mask is located at the center of the spacer. Due to manufacturing reasons, the center of the spacer is typically the thickest position (i.e., the top of the spacer). The opening edge of the fine metal mask directly contacts the top of the spacer, potentially damaging the spacer and generating particles and other foreign matter. FIG. 17 is a schematic diagram of the deposition process using a fine metal mask. As shown in FIG. 17, the opening edge 252 of the fine metal mask 250 is located at the top of the spacer 220, potentially damaging the top of the spacer 220 and potentially generating particles and other foreign matter. After the deposition process, when a film layer, such as a packaging layer, is formed on the display substrate, the generated particles and other foreign matter are likely to cause defects such as cracks in the packaging layer, thereby reducing the stability and reliability of the product.

[0125] In contrast, the present disclosure further provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate, a light-emitting layer, and a spacer. The light-emitting layer is disposed on the base substrate and includes a plurality of light-emitting portions. The spacer is disposed on one side of the light-emitting layer away from the base substrate, and the orthogonal projection of the top part of the spacer away from the base substrate is spaced apart from the edge of the orthogonal projection of the light-emitting portion on the base substrate. Thus, when the light-emitting portion is formed by performing a deposition process using a fine metal mask, the orthogonal projection of the edge of the opening of the fine metal mask on the base substrate is spaced apart from the orthogonal projection of the top part of the spacer on the base substrate. This prevents the edge of the opening of the fine metal mask from contacting the top part of the spacer, thereby avoiding the generation of foreign matter such as particles and further improving the yield rate of the display substrate.

[0126] Hereinafter, a display substrate, a manufacturing method thereof, and a display device provided according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0127] An embodiment of the present disclosure provides a display substrate, Fig. 18 is a schematic plan view of a display substrate according to an embodiment of the present disclosure, and Fig. 19 is a schematic cross-sectional view of the display substrate taken along CC direction in Fig. 18 according to an embodiment of the present disclosure.

[0128] 18 and 19, the display substrate 100 includes a base substrate 110, a light-emitting layer 180, and a spacer 220. The light-emitting layer 180 is located on the base substrate 110 and includes a plurality of light-emitting units 185. The spacer 220 is located on one side of the base substrate 110 where the light-emitting layer 180 is located. An orthogonal projection of a top 225 of the spacer 220, which is remote from the base substrate 110, on the base substrate 110 is spaced apart from an edge of the orthogonal projection of the light-emitting units 185 on the base substrate 110. The top of the spacer refers to a portion of the spacer remote from the base substrate, i.e., a portion with a large thickness. Furthermore, the term "spaced apart" as used above means that there is a predetermined distance between the orthogonal projection of the top of the spacer, which is remote from the base substrate, on the base substrate and the orthogonal projection of the light-emitting units on the base substrate, and they do not overlap or contact each other.

[0129] In the manufacturing process of the display substrate provided by the embodiment of the present disclosure, when the deposition process is performed using the fine metal mask 250 to form the light-emitting portion 185, as shown in Figure 19, the orthogonal projection of the opening edge 252 of the fine metal mask 250 on the base substrate 110 and the orthogonal projection of the top 225 of the spacer 220 on the base substrate 110 are spaced apart, thereby preventing the opening edge 252 of the fine metal mask 250 from contacting the top 225 of the spacer 220 and avoiding the generation of foreign matter such as particles. For example, as shown in Figure 19, the opening edge 252 of the fine metal mask 250 is located at the edge portion of the spacer 220, and the thickness of the edge portion of the spacer 220 is less than the thickness of the top 225 of the spacer 220, so the opening edge 252 of the fine metal mask 250 is suspended in mid-air and does not contact the spacer 220, thereby avoiding the generation of foreign matter such as particles due to scratches. Therefore, the display substrate can improve the stability, reliability and product yield of the display substrate.

[0130] 19, in some examples, the size of the middle portion of the spacer 220 in the direction perpendicular to the base substrate 110 is larger than the size of the edge portion of the spacer 220 in the direction perpendicular to the base substrate 110. In other words, the thickness of the middle portion of the spacer 220 is larger than the thickness of the edge portion of the spacer 220. As a result, when the orthogonal projection of the opening edge of the fine metal mask on the base substrate and the orthogonal projection of the middle portion of the spacer (i.e., the top of the spacer) on the base substrate are spaced apart, the opening edge of the fine metal mask is suspended in mid-air and is not in contact with the spacer, which prevents the generation of foreign matter such as particles due to scratches.

[0131] 19, the cross-sectional shape of the spacer 220 in a plane perpendicular to the base substrate 110 may include a semicircle. Of course, the embodiments of the present disclosure are not limited thereto. For example, when the cross-sectional shape of the spacer 220 is semicircular, the inclination angle of the semicircle ranges from 8 to 10 degrees.

[0132] 18, the orthogonal projection of the spacer 220 on the base substrate 110 is rectangular, and the orthogonal projection of the central axis of the spacer 220 on the base substrate 110 is spaced apart from the edge of the orthogonal projection of the light-emitting portion 185 on the base substrate 110. This prevents the opening edge of the fine metal mask from contacting the top of the spacer and prevents the generation of particles and other foreign matter, thereby improving the stability, reliability, and product yield of the display substrate. Of course, the orthogonal projection of the spacer on the base substrate in the embodiments of the present disclosure includes, but is not limited to, the above-mentioned rectangular shape, and other shapes are also possible.

[0133] 18, the distance between the orthogonal projection of the central axis of the spacer 220 on the base substrate 110 and the edge of the orthogonal projection of the light-emitting portion 185 on the base substrate 110 is greater than 6 microns, thereby effectively preventing the edge of the opening of the fine metal mask from contacting the top of the spacer and preventing the generation of particles and other foreign matter, thereby improving the stability, reliability, and product yield of the display substrate.

[0134] FIG. 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure, and FIG. 21 is a schematic cross-sectional view of the display substrate taken along the DD direction of FIG. 20 according to an embodiment of the present disclosure. To clearly illustrate the relationship between the spacers and the light-emitting portions, FIG. 20 only shows the base substrate, anode layer, light-emitting layer, and spacer. As shown in FIG. 20 , the orthogonal projection of the top portion 225 of the spacer 220, which is away from the base substrate 110, on the base substrate 110 is spaced apart from the edge of the orthogonal projection of the light-emitting portion 185 on the base substrate 110. As shown in FIG. 21 , when the fine metal mask is used to form the light-emitting portion through a deposition process, the opening edge 252 of the fine metal mask 250 is suspended and does not contact the spacer 220. This prevents the opening edge of the fine metal mask from contacting the top portion of the spacer and avoids the generation of foreign matter such as particles, thereby further improving the stability, reliability, and product yield of the display substrate.

[0135] In some examples, as shown in FIG. 20 , the plurality of light emitting units 185 are arranged along a first direction to form a plurality of light emitting group columns 280, and are arranged along a second direction to form a plurality of light emitting group rows 290. Each light emitting group 1850 includes one first light emitting unit 1851, one second light emitting unit 1852, one third light emitting unit 1853, and one fourth light emitting unit 1854. Two adjacent light emitting group rows 290 are arranged with a 1 / 2 pitch offset, and the pitch is equal to the distance between the centers of the two first light emitting units 1851 of the two adjacent light emitting groups 1850 in the first direction. The second light emitting unit 1852 and the third light emitting unit 1853 are arranged along the second direction to form a light emitting pair 1855. The first light emitting unit 1851, the light emitting pair 1855, and the fourth light emitting unit 1854 are arranged along the first direction. 20 , the orthogonal projection of the top 225 of the spacer 220 on the base substrate 110 is located between the orthogonal projection of the first light emitting portion 1851 of one light emitting group 1850 on the base substrate 110, the orthogonal projection of the third light emitting portion 1853 of the one light emitting group 1850 on the base substrate 110, and the orthogonal projection of the second light emitting portion 1852 and the fourth light emitting portion 1854 of another light emitting group 1850 adjacent in the second direction on the base substrate 110. This ensures that the orthogonal projection of the top 225 of the spacer 220 on the base substrate 110 and the orthogonal projection of the first light emitting portion 1851, the second light emitting portion 1852, the third light emitting portion 1853, and the fourth light emitting portion 1854 on the base substrate 110 are all spaced apart, and the space on the display substrate can be fully utilized.

[0136] For example, the first direction and the second direction are substantially perpendicular, but the term "the first direction and the second direction being substantially perpendicular" includes not only a case where the angle between the first direction and the second direction is 90 degrees, but also a case where the angle between the first direction and the second direction is in the range of 85-95 degrees.

[0137] For example, as shown in FIG. 20 , in the display substrate 100, two adjacent light-emitting groups 1850 in the second direction may be a first light-emitting group 1850A and a second light-emitting group 1850B, and the orthogonal projection of the top 225 of the spacer 220 on the base substrate 110 is located between the orthogonal projection of the first light-emitting portion 1851 of the first light-emitting group 1850A on the base substrate 110, the orthogonal projection of the third light-emitting portion 1853 of the first light-emitting group 1850A on the base substrate 110, the orthogonal projection of the second light-emitting portion 1852 of the second light-emitting group 1850B on the base substrate 110, and the orthogonal projection of the fourth light-emitting portion 1854 of the second light-emitting group 1850B on the base substrate 110. As a result, the display substrate can ensure that the orthogonal projection of the top 225 of the spacer 220 on the base substrate 110 and the orthogonal projection of the first light-emitting portion 1851, the second light-emitting portion 1852, the third light-emitting portion 1853 and the fourth light-emitting portion 1854 on the base substrate 110 are all spaced apart, and the space on the display substrate can be fully utilized.

[0138] For example, the orthogonal projection of the spacer 220 on the base substrate 110 may be a rectangle with a length of 20 microns and a width of 9.5 microns. In this case, the distance range between the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the third anode 1753 of the first light-emitting group 1850A on the base substrate 110 may be 8.5-9.5 microns, e.g., 8.9 microns, and the distance range between the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the fourth anode 1754 of the second light-emitting group 1850B on the base substrate 110 may be 6-7 microns, e.g., 6.3 microns.

[0139] For example, the distance range between the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the third light-emitting portion 1853 of the first light-emitting group 1850A on the base substrate 110 may be 0 microns, and they may even overlap each other. The distance range between the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the second light-emitting portion 1852 of the second light-emitting group 1850B on the base substrate 110 may be 0 microns, and they may even overlap each other.

[0140] 20 and 21 , the display substrate 100 further includes an anode layer 170 and a pixel defining layer 190, where the anode layer 170 is located between the base substrate 110 and the spacers 220 and the pixel defining layer 190 is located on one side of the anode layer 170 closer to the spacers 220. The anode layer 170 includes a plurality of anodes 175, and the pixel defining layer 190 includes a plurality of openings 195 to expose the anodes 175. The plurality of anodes 175 are disposed corresponding to the plurality of light-emitting portions 185, and the plurality of openings 195 are disposed corresponding to the plurality of light-emitting portions 185, and include a plurality of opening groups 1950, each of which includes one first opening 1951, one second opening 1952, one third opening 1953, and one fourth opening 1954. The plurality of anodes 175 are disposed corresponding to the plurality of light-emitting portions 185, and include a plurality of anode groups 1750, each of which includes one first anode 1751, one second anode 1752, one third opening 1953, and one fourth opening 1954. The light-emitting element 1850 comprises an anode 1753 and one fourth anode 1754, wherein the first light-emitting portion 1851 is at least partially located within the first opening 1951 and covers the exposed first anode 1751, the second light-emitting portion 1852 is at least partially located within the second opening 1952 and covers the exposed second anode 1752, the third light-emitting portion 1853 is at least partially located within the third opening 1953 and covers the exposed third anode 1753, and the fourth light-emitting portion 1854 is at least partially located within the fourth opening 1954 and covers the exposed fourth anode 1754.

[0141] For example, as shown in FIGS. 20 and 21, the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the first anode 1751 on the base substrate 110 may partially overlap.

[0142] For example, as shown in Figures 20 and 21, the first virtual line is parallel to the longitudinal direction of the spacer 220 and passes through the center of the spacer 220, the orthogonal projection shape of the first opening 1951 on the base substrate 110 is approximately elliptical, and the range of the ratio between the distance from the vertex in the major axis direction of the ellipse to the first virtual line and the shortest distance from the first opening 1951 to the first virtual line is 1.5-1.

[0143] For example, the distance range between the first opening 1951 and the second opening 1952 is 20-25 microns, the distance between the first opening 1951 and the third opening 1953 is also 20-25 microns, and the distance range between the first opening 1951 and the fourth opening 1954 is also 20-25 microns. Of course, the embodiments of the present disclosure are not limited thereto, and the distance between each opening may be determined according to the size of the actual product.

[0144] 20 and 21, the orthogonal projection of the spacer 220 on the base substrate 110 and the spacer block of the first opening 1951 on the base substrate 110 are provided. Thus, in the manufacturing process of the display substrate provided by the embodiments of the present disclosure, when the light emitting portion is formed by performing a deposition process using a fine metal mask, the edge of the opening of the fine metal mask can be prevented from contacting the top of the spacer, and the generation of foreign matter such as particles can be avoided.

[0145] For example, as shown in FIGS. 20 and 21, the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the first opening 1951 on the base substrate 110 are spaced apart.

[0146] In some examples, as shown in Figures 20 and 21, the orthogonal projection shape of the first opening 1951 on the base substrate 110 is approximately elliptical, the orthogonal projection shape of the spacer 220 on the base substrate 110 is rectangular, and the included angle between the long axis direction of the orthogonal projection shape of the first opening 1951 on the base substrate 110 and the extension direction of the orthogonal projection of the spacer 220 on the base substrate 110 is in the range of 20-70 degrees.

[0147] In some examples, as shown in Figures 20 and 21, the display substrate 100 further includes a pixel circuit layer 260 located on one side of the anode layer 170 closer to the base substrate 110 and having a plurality of pixel driving circuits 265, the plurality of pixel driving circuits 265 being arranged corresponding to the plurality of anodes 175, each anode 175 being electrically connected to a corresponding pixel driving circuit 265, the first anode 1751 having a body portion 1751A and a connection portion 1751B connected to the body portion 1751A, the orthogonal projection of the first opening 1951 on the base substrate 110 being inside the orthogonal projection of the body portion 1751A on the base substrate 110, and the connection portion 1751B being electrically connected to the corresponding pixel driving circuit 265.

[0148] 20 and 21, the orthogonal projection of the spacer 220 on the base substrate 110 and the orthogonal projection of the connecting portion 1751B on the base substrate 110 at least partially overlap with each other, thereby preventing the opening edge of the fine metal mask from coming into contact with the top of the spacer and preventing the generation of foreign matter such as particles, while also allowing full use of the space on the display substrate.

[0149] In some examples, as shown in Figures 20 and 21, the connection portion 1751B is located on the main body portion 1751A near the third anode 1753 of the same light-emitting group 1850 and the fourth anode 1754 of the adjacent light-emitting group 1850 in the second direction.

[0150] In some examples, the area defined by the first opening 1951 is a first effective light-emitting area of a first sub-pixel, the area defined by the second opening 1952 is a second effective light-emitting area of a second sub-pixel, the area defined by the third opening 1953 is a third effective light-emitting area of a third sub-pixel, and the area defined by the fourth opening 1954 is a fourth effective light-emitting area of a fourth sub-pixel, whereby the plurality of light-emitting groups, the plurality of opening groups, and the plurality of anode groups correspond to a plurality of pixel structures, respectively.

[0151] In some examples, the first light-emitting unit is configured to emit light of a first color, the second and third light-emitting units are connected and configured to emit light of a second color, and the fourth light-emitting unit is configured to emit light of a third color.

[0152] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is, the display substrate uses a GGRB pixel arrangement structure.

[0153] 22 is a schematic cross-sectional view of a display substrate taken along the EE direction of FIG. 20 according to one embodiment of the present disclosure. As shown in FIG. 22, during actual manufacturing, light-emitting portions 185 (e.g., first light-emitting layer 1851 and fourth light-emitting layer 1854) formed using a fine metal mask diffuse to form thin diffusion portions (e.g., diffusion portions 1851A and 1854A). This causes the size of the final light-emitting layer 185 to be larger than the size of the openings in the fine metal mask, resulting in overlap with spacers 220 and contact or overlap between adjacent light-emitting portions. In this case, the light-emitting layer refers to the portion of the light-emitting layer whose thickness is equal to or greater than the thickness of the diffusion portion, and does not include the diffusion portion.

[0154] An embodiment of the present disclosure further provides a display device. FIG. 23 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 23, the display device 400 includes any of the display substrates 100 described above. As a result, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can prevent the opening edge 252 of the fine metal mask from contacting the top of the spacer during manufacturing, and can avoid the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate.

[0155] For example, the display device may be an electronic product with a display function, such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigation device, or a digital photo frame.

[0156] An embodiment of the present disclosure further provides a method for manufacturing a display substrate. Figure 24 shows a method for manufacturing a display substrate according to an embodiment of the present disclosure. As shown in Figure 24, the method for manufacturing a display substrate includes the following steps S101-S103:

[0157] Step S101: Form a pixel definition layer on a base substrate, the pixel definition layer having a plurality of openings.

[0158] For example, the base substrate may be a quartz substrate, a glass substrate, a plastic substrate, etc., the pixel defining layer may be manufactured by a vapor deposition process, and the plurality of openings may be manufactured by an etching process, although the embodiments of the present disclosure are not limited thereto.

[0159] Step S102: Form a spacer on one side of the pixel definition layer away from the base substrate.

[0160] For example, the spacers can be formed together with the pixel defining layer through a half-tone or gray-tone mask by using the same film layer, thereby eliminating the mask process and reducing costs. For example, first, a layer structure for forming the pixel defining layer and the spacers is formed on a base substrate, and then a first photoresist pattern having fully retained portions, partially retained portions, and completely removed portions is formed on one side of the layer structure away from the base substrate using a half-tone or gray-tone mask. The layer structure is etched (e.g., wet-etched) using the first photoresist pattern to remove the layer structure corresponding to the fully removed portions and form multiple openings in the pixel defining layer. Then, the first photoresist pattern is ashed to remove the partially retained portions to form a second photoresist pattern. The layer structure is further etched using the second photoresist pattern to form spacers in the layer structure corresponding to the fully retained portions and form the pixel defining layer in the layer structure corresponding to the partially retained portions. Of course, the embodiments of the present disclosure are not limited thereto, and the spacers may be formed independently.

[0161] Step S103: Place a mask plate on one side of the spacer away from the base substrate, and use the mask plate as a mask to deposit luminescent material into the multiple openings to form a luminescent layer having multiple luminescent portions, the mask plate having multiple mask openings, and the orthogonal projection of the topmost part of the spacer away from the base substrate and the edge of the orthogonal projection of the mask opening on the base substrate are spaced apart.

[0162] In the manufacturing process of the display substrate provided by the embodiment of the present disclosure, a mask plate is placed on one side of the spacer away from the base substrate, and when a light-emitting material is deposited into the plurality of openings using the mask plate as a mask to form a light-emitting layer having a plurality of light-emitting portions, the orthogonal projection of the edge of the opening of the mask plate on the base substrate and the orthogonal projection of the top of the spacer on the base substrate are spaced apart, thereby preventing the edge of the opening of the mask plate from contacting the top of the spacer and avoiding the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate.

[0163] In some examples, the mask plate is a fine metal mask (FMM).

[0164] In some examples, the orthogonal projection of the spacer on the base substrate is rectangular, and the orthogonal projection of the center axis of the spacer on the base substrate in the longitudinal direction is spaced apart from the edge of the orthogonal projection of the light-emitting portion on the base substrate, thereby preventing the opening edge of the fine metal mask from contacting the top of the spacer and preventing the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate.

[0165] In some examples, the orthogonal projection of the spacer on the base substrate and the edge of the orthogonal projection of the light-emitting portion on the base substrate are spaced apart, which further prevents the opening edge of the fine metal mask from contacting the top of the spacer and prevents the generation of foreign matter such as particles, thereby further improving the stability, reliability, and product yield of the display substrate.

[0166] 25-27 are schematic plan views of a mask plate group according to an embodiment of the present disclosure. As shown in Figures 25-27, the mask plate group includes a first mask plate 510, a second mask plate 520, and a third mask plate 530. The first mask plate 510 includes a plurality of first mask openings 412 each for forming the first light-emitting portion 1851. The second mask plate 520 includes a plurality of second mask openings 422 each for forming the second light-emitting portion 1852 and the third light-emitting portion 1853. In other words, the second light-emitting portion 1852 and the third light-emitting portion 1853 are formed through the same mask opening. The third mask plate 530 includes a plurality of third mask openings 432 each for forming the fourth light-emitting portion 1854.

[0167] For example, as shown in FIGS. 25-27, in the manufacturing method of the display substrate, the step S103 includes the steps of placing a first mask plate 510 on one side of the spacer 220 away from the base substrate 110, and depositing a light-emitting material into the plurality of openings 1951 using the first mask plate 510 as a mask to form a plurality of first light-emitting portions 1851, as shown in FIG. 25; removing the first mask plate 510; and placing a second mask plate 520 on one side of the spacer 220 away from the base substrate 110, as shown in FIG. 27, the method includes the steps of: placing a third mask plate 530 on one side of the spacer 220 away from the base substrate 110; and using the third mask plate 530 as a mask, depositing a luminescent material in the plurality of openings 1951 and 1952 to form a plurality of second light-emitting portions 1852 and a plurality of third light-emitting portions 1853; removing the second mask plate 520; and, as shown in FIG. 27, placing a third mask plate 530 on one side of the spacer 220 away from the base substrate 110; and using the third mask plate 530 as a mask, depositing a luminescent material in the plurality of openings 1954 to form a plurality of fourth light-emitting portions 1854.

[0168] For example, as shown in Figures 25-27, the orthogonal projection of the topmost part of the spacer 220 on the base substrate 110, which is farthest from the base substrate 110, and the edge of the orthogonal projection of the first light-emitting portion 1851 or the fourth light-emitting portion 1854 on the base substrate 110 are spaced apart.

[0169] Meanwhile, with the continuous development of organic light-emitting diode (OLED) display technology, the requirements for display performance are also becoming increasingly higher. Through research, the inventors of the present application found that many factors affect the display performance of OLED displays, and that the loading of the gate layer affects the charging time of the pixel driving circuit, which has a significant impact on the display performance. Typically, the loading of the gate layer is mainly composed of the loading of the gate line and the reset signal line. Meanwhile, the loading of the data line (or source line) is directly related to the power of the IC. The higher the loading of the data line, the higher the requirements for the IC driver, which in turn increases the power of the IC. Therefore, controlling the loading between the gate line and the reset signal line and the loading on the data line can improve the display performance of OLED displays and reduce the power consumption of OLED displays.

[0170] In contrast, an embodiment of the present disclosure provides a display substrate and a display device, the display substrate comprising: a base substrate, a first gate layer, a second gate layer, and a first conductive layer, the first gate layer being disposed on the base substrate, the second gate layer being disposed on one side of the first gate layer away from the base substrate, the first conductive layer being disposed on one side of the second gate layer away from the base substrate, the first gate layer comprising a reset signal line and a first electrode block extending along a first direction, the second gate layer comprising a second electrode block forming a storage capacitor with the first electrode block, the first conductive layer comprising a power line extending along a second direction, the reset signal line and the power line having a first overlapping region, the second electrode block and the power line having a second overlapping region, the width of the power line located in the first overlapping region being less than the width of the power line located in the second overlapping region, and the first direction intersects with the second direction. Therefore, by reducing the width of the power supply line in the first overlap region where the reset signal line and the power supply line overlap, the display substrate can reduce the load on the reset signal line, thereby lengthening the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0171] Hereinafter, a display substrate and a display device provided according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0172] An embodiment of the present disclosure provides a display substrate. Figure 28A is a partial schematic view of another display substrate according to an embodiment of the present disclosure, Figure 28B is a partial schematic view of another display substrate according to an embodiment of the present disclosure, and Figure 29 is a cross-sectional schematic view of the display substrate in the FF direction of Figure 28A according to an embodiment of the present disclosure. In order to clearly show the stacked structure of each film layer of the pixel driving circuit structure in the display substrate, the anode layer and the second conductive layer are omitted from Figure 28B.

[0173] As shown in Figures 28A, 28B, and 29, the display substrate 100 comprises a base substrate 110, a first gate layer 130, a second gate layer 140, and a first conductive layer 150, wherein the first gate layer 130 is located on the base substrate 110, the second gate layer 140 is located on one side of the first gate layer 130 away from the base substrate 110, and the first conductive layer 150 is located on one side of the second gate layer 140 away from the base substrate 110. The first gate layer 130 includes a reset signal line 131 and a first electrode block CE1 extending along a first direction, the second gate layer 140 includes a second electrode block CE2 configured to form a storage capacitor with the first electrode block CE1, the first conductive layer 150 includes a power supply line 151 extending along a second direction, the reset signal line 131 and the power supply line 151 having a first overlapping region 351, and the second electrode block CE2 and the power supply line 151 having a second overlapping region 352, and the width of the power supply line 151 located in the first overlapping region 351 is smaller than the width of the power supply line 151 located in the second overlapping region 352. That is, the width of the power supply line 151 in the first overlapping region 351 is reduced, and the first direction and the second direction intersect, for example, are perpendicular to each other. However, the width of the power line is the size of the power line in a first direction, and correspondingly, the length of the power line is the size of the power line in a second direction.

[0174] In the display substrate provided by the embodiments of the present disclosure, by reducing the width of the power supply line in the first overlapping region where the reset signal line and the power supply line overlap, the overlapping area between the reset signal line and the power supply line can be reduced, thereby reducing the magnitude of the parasitic capacitance between the reset signal line and the power supply line.Therefore, by reducing the width of the power supply line in the first overlapping region where the reset signal line and the power supply line overlap, the display substrate can reduce the load on the reset signal line, thereby lengthening the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0175] In some examples, the first conductive layer may be a first source / drain metal layer, and the display substrate may further include a second conductive layer, i.e., a second source / drain metal layer. However, in order to clearly show the film layer structure on the display substrate, the display substrate shown in Figure 28A does not include a second conductive layer (second source / drain metal layer). Of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may be a single-layer source / drain metal layer display substrate without a second conductive layer.

[0176] In some examples, the width of the power lines 151 located in the first overlap region 351 is less than the average width of the power lines 151 .

[0177] 28A and 28B, the width of the power line 151 in the first overlapping region 351 is less than 5 / 7 of the maximum width of the power line 151, so that the display substrate can effectively reduce the load on the reset signal line.

[0178] In some examples, as shown in FIG. 28B, the power line 151 has a main body extension portion 151A and a contraction portion 151B, the width of the contraction portion 151B is less than the width of the main body extension portion 151A, and the orthogonal projection of the contraction portion 151B on the base substrate 110 overlaps with the orthogonal projection of the reset signal line 131 on the base substrate 110.

[0179] 28A and 28B , in some examples, the first gate layer 130 further includes a gate line 132 extending along a first direction, where the gate line 132 and the power line 151 have a third overlapping region 353, and the width of the power line 151 in the third overlapping region 353 is less than the width of the power line 151 located in the second overlapping region 352. That is, the width of the power line in the third overlapping region is also reduced. By reducing the width of the power line in the second overlapping region where the gate line and the power line overlap, the display substrate can reduce the load on the gate line, thereby further extending the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0180] In some examples, the width of the power line 151 in the third overlap region 353 is less than the average width of the power line 151 .

[0181] 28A and 28B, the width of the power line 151 in the third overlapping region 353 is less than 5 / 7 of the maximum width of the power line 151, so that the display substrate can effectively reduce the load on the reset signal line.

[0182] In some examples, as shown in FIG. 28B, the power line 151 has a main body extension portion 151A and a contraction portion 151B, the width of the contraction portion 151B is less than the width of the main body extension portion 151A, and the orthogonal projection of the contraction portion 151B on the base substrate 110 overlaps with the orthogonal projection of the gate line 132 on the base substrate 110.

[0183] In some examples, as shown in FIGS. 28A and 28B , the first conductive layer 150 further includes a data line 152 extending along the second direction, where the data line 152 and the reset signal line 131 have a fourth overlapping region 354, and the width of the reset signal line 131 in the fourth overlapping region 354 is less than the average width of the reset signal line 131. In the display substrate, reducing the width of the reset signal line in the fourth overlapping region can reduce the overlapping area between the reset signal line and the data line, thereby reducing the magnitude of the parasitic capacitance between the reset signal line and the data line. By reducing the width of the reset signal line in the fourth overlapping region, the display substrate can reduce the load on the data line, thereby reducing the driving power and further reducing the power of the display substrate. Note that the width of the reset signal line refers to the size of the reset signal line in the second direction, and correspondingly, the length of the reset signal line refers to the size of the reset signal line in the first direction.

[0184] 28A and 28B, the width of the reset signal line 131 in the fourth overlapping region 354 is less than ¾ of the maximum width of the reset signal line 131, so that the display substrate can effectively reduce the load on the data line.

[0185] 28A and 28B , the display substrate 100 further includes a semiconductor layer 120 located on one side of the first gate layer 130 closer to the base substrate 110, the second gate layer 140 including an initialization signal line 141 extending along the first direction, the data line 152 and the initialization signal line 141 having a fifth overlapping region 355, the initialization signal line 141 and the semiconductor layer 120 having a sixth overlapping region 356, and the width of the initialization signal line 141 located in the fifth overlapping region 355 being less than the width of the initialization signal line 141 located in the sixth overlapping region 356. In the display substrate, reducing the width of the initialization signal line in the fifth overlapping region can reduce the overlapping area between the initialization signal line and the data line, thereby reducing the magnitude of the parasitic capacitance between the initialization signal line and the data line. Therefore, by reducing the width of the initialization signal line in the fifth overlapping region, the display substrate can further reduce the load on the data line, thereby reducing the driving power and further reducing the power of the display substrate, where the width of the initialization signal line is the size of the initialization signal line in the second direction, and correspondingly, the length of the initialization signal line is the size of the initialization signal line in the first direction.

[0186] In some examples, the width of the initialization signal line 141 located in the fourth overlap region 354 is less than the average width of the initialization signal line 141 .

[0187] For example, as shown in FIG. 28B, the orthogonal projection of the reduced portion 151B that overlaps with the reset signal line 131 on the base substrate 110 also overlaps with the orthogonal projection of the initialization signal line 141 on the base substrate 110.

[0188] In some examples, as shown in FIG. 28B, the power line 151 has a main body extension portion 151A and a reduced portion 151B, the width of the reduced portion 151B is less than the width of the main body extension portion 151A, and the orthogonal projection of the reduced portion 151B on the base substrate 110 does not overlap with the orthogonal projection of the semiconductor layer 110 on the base substrate 110.

[0189] In some examples, as shown in FIG. 28B, the second gate layer 140 further comprises a conductive block 143, the main body extension portion 151A is connected to the conductive block 143, the orthogonal projection on the base substrate 110 and the orthogonal projection of the semiconductor layer 110 on the base substrate 110 partially overlap, and the second gate layer 140 comprises a connection portion 151C adjacent to the reduced portion 151B in the second direction.

[0190] For example, as shown in FIG. 28B, the connecting portion 151C may be located between two contracting portions 151B.

[0191] 28A and 28B, the width of the initialization signal line 141 in the fourth overlapping region 354 is less than ¾ of the maximum width of the initialization signal line 151. This allows the display substrate to effectively reduce the load on the data line.

[0192] For example, the semiconductor layer 120 may be made of a silicon-based semiconductor material such as polycrystalline silicon. Of course, the embodiments of the present disclosure are not limited thereto, and the semiconductor layer may be made of other semiconductor materials.

[0193] 30A-30D are schematic plan views of multiple film layers of a display substrate according to one embodiment of the present disclosure, and FIG. 31 is an equivalent schematic diagram of a pixel driving circuit of a display substrate according to one embodiment of the present disclosure.

[0194] For example, as shown in FIG. 30A , the semiconductor layer 120 includes a first unit 121, a second unit 122, a third unit 123, a fourth unit 124, a fifth unit 125, a sixth unit 126, and a seventh unit 127. The first unit 121 includes a first channel region C1, a first source region S1, and a first drain region D1 located on both sides of the first channel region C1. The second unit 122 includes a second channel region C2, a second source region S2, and a second drain region D2 located on both sides of the second channel region C2. The third unit 123 includes a third channel region C3, a third source region S4, and a second drain region D5 located on both sides of the third channel region C3. The fourth unit 124 comprises a fourth channel region C4, a fourth source region S4 and a fourth drain region D4 located on both sides of the fourth channel region C4, the fifth unit 125 comprises a fifth channel region C5, a fifth source region S5 and a fifth drain region S5 located on both sides of the fifth channel region C5, the sixth unit 126 comprises a sixth channel region C6, a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6, and the seventh unit 127 comprises a seventh channel region C7, a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region C7.

[0195] For example, as shown in Figures 30A and 31, the sixth drain region D6 is connected to the third drain region D3, the third source region S3, the first drain region D1, and the fifth source region S5 are connected to the first node N1, the first source region S1, the second drain region D2, and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 is connected to the seventh drain region D7.

[0196] For example, as shown in FIG. 30B, the first gate layer 130 includes a reset signal line 131 extending along the first direction, a gate line 132 extending along the first direction, a first electrode block CE1, and a transmission control line 133 extending along the first direction.

[0197] 30C, the second gate layer 140 includes an initialization signal line 141 extending along the first direction, a second electrode block CE2, and a conductive block 143. For example, the conductive block 143 is connected to a power supply line, thereby reducing the resistance of the power supply line.

[0198] As shown in FIG. 31, the sixth source region S6 and the seventh source region S7 are connected to the initialization signal line 141, and the first electrode block CE1 and the second electrode block CE2 can form a storage capacitor Cst.

[0199] 30D , the first conductive layer 150 includes a power supply line 151 and a data line 152 extending along the second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543. The first connection block 1541 connects the initialization signal line 141 to the sixth source region S6 and the seventh source region S7, the second connection block 1542 connects the third drain region D3 to the first electrode block CE1, and the third connection block 1543 is connected to the fifth drain region D5, and can be connected to the corresponding anode as a drain.

[0200] 31, the second source region S2 is connected to the data line 152, and the fourth source region S4 is connected to the power supply line 151. Thus, the first unit 121, the second unit 122, the third unit 123, the fourth unit 124, the fifth unit 125, the sixth unit 126, and the seventh unit 127 of the semiconductor layer 120 can form the reset signal line 131 and the gate line 132, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7.

[0201] One operation mode of the pixel driving circuit shown in FIG. 31 will be briefly described below. First, when a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the remaining current flowing through the anode of each subpixel is discharged to the sixth thin film transistor T6 via the seventh thin film transistor T7, thereby suppressing light emission caused by the remaining current flowing through the anode of each subpixel. Next, when a reset signal is transmitted to the reset signal line 131 and an initialization signal is transmitted to the initialization signal line 141, the sixth thin film transistor T6 is turned on, and an initialization voltage Vint is applied to the first gate of the first thin film transistor T1 and the first electrode block CE1 of the storage capacitor Cst via the sixth thin film transistor T6, thereby initializing the first gate and the storage capacitor Cst. Initializing the first gate allows the first thin film transistor T1 to be turned on.

[0202] Then, when transmitting a gate signal to the gate line 132 and a data signal to the data line 152, the second thin film transistor T2 and the third thin film transistor T3 are both conductive, and the data voltage Vd is applied to the first gate through the second thin film transistor T2 and the third thin film transistor T3. In this case, the voltage applied to the first gate is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0203] Then, the power supply line 151 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1, so that a charge corresponding to the difference between the voltages applied to the two electrodes of the storage capacitor Cst is stored in the storage capacitor Cst, and the first thin film transistor T1 is conductive for a predetermined time.

[0204] Then, when a transmission control signal is applied to the transmission control line 133, the fourth thin film transistor T4 and the fifth thin film transistor T5 are both turned on, and the fourth thin film transistor T4 applies the driving voltage Vel to the fifth thin film transistor T5. When the driving voltage Vel passes through the first thin film transistor T1, which is turned on by the storage capacitor Cst, a driving current Id flows through the first drain region D3 of the first thin film transistor T1 due to the difference between the corresponding driving voltage Vel and the voltage applied to its first gate via the storage capacitor Cst, and the driving current Id is applied to each sub-pixel via the fifth thin film transistor T5, thereby causing the light-emitting layer of each sub-pixel to emit light.

[0205] In some examples, as shown in FIGS. 29 and 31 , the display substrate 100 further includes a first flat layer 241, a second conductive layer 160, a second flat layer 242, and an anode 175, where the first flat layer 241 is located on one side of the first conductive layer 150 away from the base substrate 110, the second conductive layer 160 is located on one side of the first flat layer 241 away from the first conductive layer 150, and includes a connecting electrode 161, and the second flat layer 242 is located on the other side of the first flat layer 241 away from the first conductive layer 150. The second conductive layer 160 is located on one side away from the first flat layer 241, and the anode 175 is located on one side of the second flat layer 242 away from the second conductive layer 160, the first flat layer 241 has a first via H1, and the connection electrode 161 is connected to the fifth drain region S5 through the first via H1, and the second flat layer 242 has a second via H2, and the anode 175 is connected to the connection electrode 161 through the second via H2.

[0206] An embodiment of the present disclosure further provides a display device. FIG. 32 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 32, the display device 400 includes any of the display substrates 100 described above. As a result, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can reduce the load on the gate layer, thereby lengthening the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0207] For example, the display device may be an electronic product with a display function, such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigation device, or a digital photo frame.

[0208] Meanwhile, the long-term luminance stability of an organic light-emitting diode (OLED) display device is also an important specification or indicator of the organic light-emitting diode display device. Through research, the inventors of the present application have found that there are many factors that affect the long-term luminance stability of an organic light-emitting diode display device, and that in addition to the service life of the luminescent material itself, the operating state of the thin film transistor in the pixel driving circuit also has a certain impact on both the luminance and the long-term luminance stability.

[0209] In contrast, an embodiment of the present disclosure provides a display substrate and a display device, the display substrate comprising a base substrate, a pixel circuit layer, and an anode layer, the pixel circuit layer being located on the base substrate and comprising a plurality of pixel driving circuits, the anode layer being located on one side of the pixel circuit layer away from the base substrate and comprising a plurality of anodes, the plurality of pixel driving circuits being arranged in one-to-one correspondence with the plurality of anodes, each comprising a functional thin film transistor, and comprising a first pixel driving circuit and a second pixel driving circuit arranged adjacent to each other, the channel regions of the functional thin film transistors in the first pixel driving circuit and the second pixel driving circuit both orthogonally projected on the base substrate overlap with the orthogonal projection on the base substrate of the anode corresponding to the first pixel driving circuit, thereby simultaneously shielding the channel regions of the functional thin film transistors in the first pixel driving circuit and the second pixel driving circuit through the anode, thereby improving the stability and service life of the functional thin film transistors, and thereby improving the long-term luminescence stability and service life of the display substrate.

[0210] Hereinafter, a display substrate and a display device provided according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0211] An embodiment of the present disclosure provides a display substrate, in which Fig. 33 is a partial schematic view of a display substrate according to an embodiment of the present disclosure, Fig. 34 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure taken along the KK direction of Fig. 33 according to an embodiment of the present disclosure, Fig. 35A is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure taken along the MM direction of Fig. 33 according to an embodiment of the present disclosure, Fig. 35B is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure taken along the NN direction of Fig. 33 according to an embodiment of the present disclosure, and Fig. 35C is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure taken along the QQ direction of Fig. 33 according to an embodiment of the present disclosure.

[0212] As shown in Figures 33 and 34, the display substrate 100 includes a base substrate 110, a pixel circuit layer 260, and an anode layer 170, where the pixel circuit layer 260 is located on the base substrate 110 and includes a plurality of pixel driving circuits 265, and the anode layer 170 is located on one side of the pixel circuit layer 260 away from the base substrate 110 and includes a plurality of anodes 175. The pixel driving circuits 265 are arranged in one-to-one correspondence with the anodes 175, and each pixel driving circuit 256 includes a functional thin film transistor such as a compensation thin film transistor T3. The pixel driving circuits 265 include a first pixel driving circuit 2657 and a second pixel driving circuit 2658 arranged adjacent to each other, and the orthogonal projections of the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 overlap with the orthogonal projections of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110. However, the terms "first" and "second" in the first pixel driving circuit and the second pixel driving circuit are merely used to distinguish the two pixel driving circuits from each other; the specific structures of the two pixel driving circuits are the same, and the functional thin film transistors may be other thin film transistors in the pixel driving circuits.

[0213] In the display substrate provided by the embodiments of the present disclosure, the orthogonal projections on the base substrate 110 of the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 both overlap with the orthogonal projection on the base substrate 110 of the anode 175 corresponding to the first pixel driving circuit 2657, so that the anode 175 corresponding to the first pixel driving circuit 2657 can partially or completely shield the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658. As a result, the display substrate can improve the stability and service life of the compensation thin film transistor T3 in the first pixel driving circuit and the compensation thin film transistor T3 in the second pixel driving circuit 2658, thereby improving the long-term luminescence stability and service life of the display substrate. 30A-30D are schematic plan views of multiple film layers of a display substrate according to an embodiment of the present disclosure, and FIG. 31 is an equivalent schematic diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure. The pixel driving circuit uses a 7T1C pixel driving structure. During the light-emitting phase, the voltage at node N3 controls the on / off state of first thin film transistor T1 (i.e., driving thin film transistor), and the stability of first thin film transistor T1 directly affects the long-term light-emitting stability of the organic light-emitting diode display device. During the charging phase, the charging voltage at node N3 is related to the states of third thin film transistor T3 (i.e., compensation thin film transistor), first thin film transistor T1, and second thin film transistor T2. Typically, thin film transistors are particularly sensitive to light, and when the thin film transistor (especially the channel region) is exposed to light, the characteristics of the thin film transistor are likely to drift, affecting the normal operation of the pixel driving circuit. In the embodiments of the present disclosure, the channel region of the compensation thin film transistor is shielded through the anode, which can improve the stability and extend the service life of the compensation thin film transistor, thereby improving the long-term luminescence stability and extend the service life of the display substrate.

[0214] In some examples, as shown in Figures 33-35C, the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 are both in the orthogonal projection on the base substrate 110 of the anode 175 (i.e., the fourth anode 1754) corresponding to the first pixel driving circuit 2657, and the anode 175 corresponding to the first pixel driving circuit 2657 can completely block the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658, thereby further improving the stability and service life of the compensation thin film transistor, and further improving the long-term luminescence stability and service life of the display substrate.

[0215] In some examples, as shown in FIG. 30A , the compensation thin film transistor T3 may be a thin film transistor with a double-gate structure, which can improve the reliability of the compensation thin film transistor. The channel region of the compensation thin film transistor T3 includes a first channel region C1 and a second channel region C2 spaced apart, and the compensation thin film transistor T3 further includes a common electrode SE located between the first channel region C1 and the second channel region C2. As shown in FIGS. 33-35B , the orthogonal projections of the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the common electrode SE of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 overlap with the orthogonal projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110. As a result, the anode 175 corresponding to the first pixel driving circuit 2657 can partially or completely shield the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the common electrode SE of the compensation thin film transistor T3 in the second pixel driving circuit 2658, thereby further improving the stability and service life of the compensation thin film transistor, and further improving the long-term luminescence stability and service life of the display substrate.

[0216] FIG. 36 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. As shown in FIG. 36, the plurality of anodes 175 includes a plurality of anode groups 1750, each of which includes a first anode 1751, a second anode 1752, a third anode 1753, and a fourth anode 1754. However, the first, second, third, and fourth anodes may be anodes for subpixels of different shapes and different colors. Of course, the embodiment of the present disclosure is not limited thereto, and at least two of the first, second, third, and fourth anodes may be anodes for subpixels of the same shape and color.

[0217] 36 , the plurality of anodes 175 include a plurality of anode groups 1750 arranged along a first direction to form a plurality of anode group columns 380 and arranged along a second direction to form a plurality of anode group rows 390, each anode group 1750 including one first anode 1751, one second anode 1752, one third anode 1753, and one fourth anode 1754, and two adjacent anode group rows 390 are disposed with a ½ pitch offset, the pitch being equal to the distance between the centers of the two first anodes 1751 of the two adjacent anode groups 1750 in the first direction. The second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, and the first anode 1751, anode pair 1755, and fourth anode 1754 are arranged along the second direction. The display substrate thereby provides a pixel arrangement structure, thereby improving the display effect of a display device using the display substrate. The anode group provided by the embodiments of the present disclosure includes, but is not limited to, the pixel arrangement structure described above, and the center of the first anode is the center of the main body of the first anode, i.e., the effective light-emitting area of the first light-emitting element corresponding to the first anode. For example, the first direction and the second direction are substantially perpendicular. The term "the first direction and the second direction being substantially perpendicular" includes not only cases where the angle between the first direction and the second direction is 90 degrees, but also cases where the angle between the first direction and the second direction is in the range of 85-95 degrees.

[0218] In some examples, as shown in FIG. 33 , a first pixel driving circuit 2657 and a second pixel driving circuit 2658 are arranged along the first direction, and a fourth anode 1754 in one anode group 1750 is arranged corresponding to and electrically connected to the first pixel driving circuit 2657, and a second anode 1752 in another anode group 1750 is arranged corresponding to and electrically connected to the second pixel driving circuit 2658.

[0219] In some examples, as shown in FIGS. 33, 34, and 36, the display substrate 100 further includes a pixel defining layer 190 located on one side of the anode layer 170 away from the base substrate 110 and including a plurality of openings 195, the plurality of openings 195 including a plurality of opening groups 1950, each of the opening groups 1950 including one first opening 1951, one second opening 1952, one third opening 1953, and one fourth opening 1954, The opening 1951 is positioned corresponding to the first anode 1751 and exposes the first anode 1751, the second opening 1952 is positioned corresponding to the second anode 1752 and exposes the second anode 1752, the third opening 1953 is positioned corresponding to the third anode 1753 and exposes the third anode 1753, and the fourth opening 1954 is positioned corresponding to the fourth anode 1754 and exposes the fourth anode 1754.

[0220] As shown in FIGS. 33 and 36 , the first anode 1751 includes a first body portion 1751A and a first connection portion 1751B, the orthogonal projection of the first opening 1951 on the base substrate 110 is inside the orthogonal projection of the first body portion 1751A on the base substrate 110, and the first connection portion 1751B is connected to the pixel driving circuit 265 corresponding to the first anode 1751; the second anode 1752 includes a second body portion 1752A and a second connection portion 1752B, the orthogonal projection of the second opening 1952 on the base substrate 110 is inside the orthogonal projection of the second body portion 1752A on the base substrate 110, and the second connection portion 1752B is connected to the pixel driving circuit 265 corresponding to the second anode 1752; The anode 1753 has a third body portion 1753A and a third connection portion 1753B, the orthogonal projection of the third opening 1953 on the base substrate 110 is inside the orthogonal projection of the third body portion 1753A on the base substrate 110, and the third connection portion 1753B is connected to the pixel driving circuit 265 corresponding to the third anode 1753, the fourth anode 1754 has a fourth body portion 1754A and a fourth connection portion 1754B, the orthogonal projection of the fourth opening 1954 on the base substrate 110 is inside the orthogonal projection of the fourth body portion 1754A on the base substrate 110, and the fourth connection portion 1754B is connected to the pixel driving circuit 265 corresponding to the fourth anode 1754 (for example, the above-mentioned first pixel driving circuit 2657).

[0221] 33 and 36, the shape of first body portion 1751A and the shape of first opening 1951 are substantially the same, the shape of second body portion 1752A and the shape of second opening 1952 are substantially the same, the shape of third body portion 1753A and the shape of third opening 1953 are substantially the same, and the shape of fourth body portion 1754A and the shape of fourth opening 1954 are substantially the same. For example, when the shape of fourth opening 1954 is hexagonal, the shape of fourth body portion 1754A is also hexagonal. Of course, the shapes of the fourth opening and the fourth body portion are not limited to hexagonal and may be other shapes, such as oval.

[0222] 33-36, the fourth anode 1754 further includes a first supplemental portion 1754C, and the orthogonal projections of the first channel region C31 and the second channel region C32 of the compensation thin film transistor T3 in the first pixel driving circuit 2657 corresponding to the fourth anode 1754 on the base substrate 110 respectively overlap with the orthogonal projection of the first supplemental portion 1754C on the base substrate 110. By adding the first supplemental portion to the fourth anode in the display substrate, the fourth anode can cover two channel regions of the compensation thin film transistor in the corresponding pixel driving circuit, thereby improving the stability and service life of the compensation thin film transistor, and thereby improving the long-term luminescence stability and service life of the display substrate.

[0223] In some examples, as shown in Figures 33-36, the first supplemental portion 1754C protrudes from the fourth body portion 1754A to the third anode 1753 and is located on one side of the fourth connecting portion 1754B closer to the fourth body portion 1754A. In some examples, as shown in Figures 33-36, the first supplemental portion 1754C is connected to both the fourth body portion 1754A and the fourth connecting portion 1754B. This allows the display substrate to fully utilize the area on the display substrate and closely arrange the first anode, second anode, third anode, and fourth anode, thereby ensuring the resolution of the display substrate.

[0224] For example, as shown in FIG. 35A, the orthogonal projection of the first supplemental portion 1754C on the base substrate 110 and the orthogonal projection of the common electrode SE of the compensation thin-film transistor T3 on the base substrate 110 partially overlap.

[0225] For example, as shown in FIG. 35A, the orthogonal projection of the first supplemental portion 1754C on the base substrate 110 covers the orthogonal projection of the second channel region C32 of the compensation thin film transistor T3 on the base substrate 110.

[0226] 35A, the orthogonal projection of the fourth body portion 1754A on the base substrate 110 covers the drain region D3 of the compensation thin film transistor T3. For example, as shown in FIG. 35C, the first conductive layer 150 includes a second connection block 1542 for connecting the drain region of the compensation thin film transistor T3 with the first electrode block CE1, and the first electrode block CE1 can form a storage capacitor with the second electrode block CE2, and The connecting portion 1752B of the second anode 1752 extends away from the third anode 1753, overlaps with the second connecting block 1542, and covers the second connecting block 1542, so that the connecting portion 1752 can stabilize the potential on the gate of the driving thin film transistor and the drain of the compensation thin film transistor, thereby further improving the long-term luminescence stability and extending the service life of the display substrate.

[0227] Fig. 37A is a partial schematic view of another display substrate according to one embodiment of the present disclosure, and Fig. 37B is a partial schematic view of another display substrate according to one embodiment of the present disclosure, in which only the anode layer is shown to clearly show the shape of each anode.

[0228] 37A and 37B, the fourth anode 1754 further includes a second supplemental portion 1754D, such that the orthogonal projection of the second channel region C2 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 overlaps with the orthogonal projection of the second supplemental portion 1754D on the base substrate 110. By adding the second supplemental portion to the fourth anode, the fourth anode can partially or completely cover the second channel region C2 of the compensation thin film transistor T3 in the second pixel driving circuit 2658, thereby improving the stability and service life of the compensation thin film transistor, and thereby improving the long-term luminescence stability and service life of the display substrate.

[0229] In some examples, as shown in Figures 37A and 37B, the second supplemental portion 1754D projects from the fourth body portion 1754A in a first direction toward the first anode 1751 in the adjacent anode group 1750.

[0230] However, as shown in Figures 37A and 37B, the orthogonal projection of the first channel region C1 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 is within the orthogonal projection of the fourth body portion 1754A on the base substrate 110.

[0231] In some examples, as shown in Figures 37A and 37B, the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 overlaps with the orthogonal projection of the first supplementary portion 1754C on the base substrate 110, and the orthogonal projection of the common electrode SE of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 overlaps with the orthogonal projection of the fourth body portion 1754A of the fourth anode 1754 corresponding to the first pixel driving circuit 2657 on the base substrate 110.

[0232] In some examples, as shown in Figures 37A and 37B, the orthogonal projection on the base substrate 110 of the channel region of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 is within the orthogonal projection on the base substrate 110 of the first body portion 1751A.

[0233] 31, the pixel driving circuit 265 further includes a driving thin film transistor T1, the gate G1 of which is connected to the drain D3 of the compensation thin film transistor T3. As shown in FIG. 37A, the first anode 1751 further includes a third supplemental portion 1751C, which protrudes from the first body portion 1751A to the third anode 1753. The orthogonal projections of the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 on the base substrate 110 are within the orthogonal projections of the third supplemental portion 1751C on the base substrate 110. This allows the display substrate to stabilize the potentials of the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3 through the third supplemental portion 1751C, thereby further improving the long-term luminescence stability and extending the service life of the display substrate.

[0234] In some examples, as shown in Figures 37A and 37B, the orthogonal projection on the base substrate 110 of the first channel region C31 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 is within the orthogonal projection on the base substrate 110 of the third body portion 1753A.

[0235] 37A and 37B , the third anode 1753 further includes a fourth supplemental portion 1753C, and the orthogonal projection of the second channel region C32 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 on the base substrate 110 is inside the orthogonal projection of the fourth supplemental portion 1753C on the base substrate 110. Thus, the body portion and the fourth supplemental portion of the third anode partially or completely block the first channel region C31 and the second channel region C32 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753, thereby improving the stability and service life of the compensation thin film transistor, and thereby improving the long-term luminescence stability and service life of the display substrate.

[0236] In some examples, as shown in Figures 33 and 34, the pixel circuit layer 260 further includes a semiconductor layer 120, a first gate layer 130, a second gate layer 140, and a first conductive layer 150, where the first gate layer 130 is located on one side of the semiconductor layer 120 away from the base substrate 110, the second gate layer 140 is located on one side of the first gate layer 130 away from the base substrate 110, and the first conductive layer 150 is located on one side of the second gate layer 140 away from the base substrate 110.

[0237] For example, as shown in FIG. 30A , the semiconductor layer 120 includes a plurality of pixel driving units 1200, which are arranged corresponding to a plurality of anodes 175. Each pixel driving unit 1200 includes a first unit 121, a second unit 122, a third unit 123, a fourth unit 124, a fifth unit 125, a sixth unit 126, and a seventh unit 127. The first unit 121 includes a first channel region C1, a first source region S1 and a first drain region D1 located on both sides of the first channel region C1. The second unit 122 includes a second channel region C2, a second source region S2 and a second drain region D2 located on both sides of the second channel region C2. The third unit 123 includes a third channel region C3. The fourth unit 124 comprises a fourth channel region C4, a fourth source region S4 and a fourth drain region D4 located on both sides of the fourth channel region C4, the fifth unit 125 comprises a fifth channel region C5, a fifth source region S5 and a fifth drain region S5 located on both sides of the fifth channel region C5, the sixth unit 126 comprises a sixth channel region C6, a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6, and the seventh unit 127 comprises a seventh channel region C7, a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region C7.

[0238] For example, as shown in Figures 30A and 31, the sixth drain region D6 is connected to the third drain region D3, the third source region S3, the first drain region D1, and the fifth source region S5 are connected to the first node N1, the first source region S1, the second drain region D2, and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 is connected to the seventh drain region D7.

[0239] For example, as shown in FIG. 30B, the first gate layer 130 includes a reset signal line 131 extending along the first direction, a gate line 132 extending along the first direction, a first electrode block CE1, and a transmission control line 133 extending along the first direction. The reset signal line 131 overlaps the seventh channel region C7 and the sixth channel region C6, forming the seventh unit 127 and the sixth unit 126 together with the seventh thin film transistor T7 and the sixth thin film transistor T6; the gate line 132 overlaps the third channel region C3 and the second channel region C2, forming the third unit 123 and the second unit 122 together with the third thin film transistor T3 and the second thin film transistor T2; the first electrode block CE1 overlaps the first channel region C1, forming the first unit 121 together with the first thin film transistor T1; the transmission control line 133 overlaps the fourth channel region C4 and the fifth channel region C5, forming the fourth unit 124 and the fifth unit 125 together with the fourth thin film transistor T4 and the fifth thin film transistor T5. Therefore, the third thin film transistor T3 is a compensation thin film transistor.

[0240] For example, as shown in FIG. 30B, the reset signal line 131, the gate line 132, and the transmission control line 133 all extend along the first direction, and the reset signal line 131, the gate line 132, the first electrode block CE1, and the transmission control line 133 are arranged along the second direction.

[0241] For example, as shown in FIG. 30C , the second gate layer 140 includes an initialization signal line 141 extending along a first direction, a second electrode block CE2, and a conductive block 143. For example, the conductive block 143 is connected to a power line, thereby reducing the resistance of the power line. The initialization signal line 141 is connected to the seventh source region S7 and the first source region S1. The orthogonal projection of the second electrode block CE2 on the base substrate 110 at least partially overlaps with the orthogonal projection of the first electrode block CE1 on the base substrate 110 to form a storage capacitor Cst. However, the conductive block can also serve a certain light-shielding role. Furthermore, only a portion of the leftmost conductive block in FIG. 33 is shown, and the shape of the leftmost conductive block in FIG. 33 is the same as the shapes of the other conductive blocks.

[0242] 30D , the first conductive layer 150 includes a power supply line 151 and a data line 152 extending along the second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543. The data line 152 is connected to the second source region S2, the fourth source region S4 is connected to the power supply line 151, the first connection block 1541 connects the initialization signal line 141 to the sixth source region S6 and the seventh source region S7, the second connection block 1542 connects the third drain region D3 to the first electrode block CE1, and the third connection block 1543 is connected to the fifth drain region D5, which can be connected as a drain to a corresponding anode.

[0243] One operation mode of the pixel driving circuit shown in FIG. 31 will be briefly described below. First, when a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the remaining current flowing through the anode of each subpixel is discharged to the sixth thin film transistor T6 via the seventh thin film transistor T7, thereby suppressing light emission caused by the remaining current flowing through the anode of each subpixel. Next, when a reset signal is transmitted to the reset signal line 131 and an initialization signal is transmitted to the initialization signal line 141, the sixth thin film transistor T6 is turned on, and an initialization voltage Vint is applied to the first gate of the first thin film transistor T1 and the first electrode block CE1 of the storage capacitor Cst via the sixth thin film transistor T6, thereby initializing the first gate and the storage capacitor Cst. Initializing the first gate allows the first thin film transistor T1 to be turned on.

[0244] Then, when transmitting a gate signal to the gate line 132 and a data signal to the data line 152, the second thin film transistor T2 and the third thin film transistor T3 are both conductive, and the data voltage Vd is applied to the first gate through the second thin film transistor T2 and the third thin film transistor T3. In this case, the voltage applied to the first gate is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0245] Then, the power supply line 151 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1, so that a charge corresponding to the difference between the voltages applied to the two electrodes of the storage capacitor Cst is stored in the storage capacitor Cst, and the first thin film transistor T1 is conductive for a predetermined time.

[0246] Then, when a transmission control signal is applied to the transmission control line 133, the fourth thin film transistor T4 and the fifth thin film transistor T5 are both turned on, and the fourth thin film transistor T4 applies the driving voltage Vel to the fifth thin film transistor T5. When the driving voltage Vel passes through the first thin film transistor T1, which is turned on by the storage capacitor Cst, a driving current Id flows through the first drain region D3 of the first thin film transistor T1 due to the difference between the corresponding driving voltage Vel and the voltage applied to its first gate via the storage capacitor Cst, and the driving current Id is applied to each sub-pixel via the fifth thin film transistor T5, thereby causing the light-emitting layer of each sub-pixel to emit light.

[0247] In some examples, as shown in FIGS. 33 and 34 , the display substrate 100 further includes a first flat layer 241, a second conductive layer 160, a second flat layer 242, and an anode 175, where the first flat layer 241 is located on one side of the first conductive layer 150 away from the base substrate 110, the second conductive layer 160 is located on one side of the first flat layer 241 away from the first conductive layer 150, and includes a connecting electrode 161, and the second flat layer 242 is located on one side of the second conductive layer 160 away from the first flat layer 241, the anode 175 is located on one side of the second flat layer 242 away from the second conductive layer 160, the first flat layer 241 has a first via H1, and the connection electrode 161 is connected to the sixth drain region S6 through the first via H1, the second flat layer 242 has a second via H2, and the anode 175 is connected to the connection electrode 161 through the second via H2.

[0248] In some examples, as shown in FIGS. 33, 34, and 36, the display substrate 100 further includes a light-emitting layer 180 located on one side of the anode layer 170 away from the base substrate 110 and including a plurality of light-emitting portions 185, the plurality of light-emitting portions 185 including a plurality of light-emitting groups 1850, each of which includes one first light-emitting portion 1851, one second light-emitting portion 1852, one third light-emitting portion 1853, and one fourth light-emitting portion 1854, the first light-emitting portion 1851 being at least partially located in the first opening 1951 and covering the exposed first anode 1751, and the second light-emitting portion 1852 being at least partially the third light-emitting portion 1753 is at least partially located in the third opening 1953 and covers the exposed third anode 1753; the fourth light-emitting portion 1854 is at least partially located in the fourth opening 1954 and covers the exposed fourth anode 1754; the first light-emitting portion 1851 is configured to emit light of a first color, the second light-emitting portion 1852 and the third light-emitting portion 1853 are configured to emit light of a second color, and the fourth light-emitting portion 1854 is configured to emit light of a third color.

[0249] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is, the display substrate uses a GGRB pixel arrangement structure.

[0250] For example, as shown in FIG. 34 , the overlapping area between the first conductive portion 1621 located on one side of the first anode 1751 away from the second anode 1752 and the power line 151 located in the first conductive layer 150 is less than the overlapping area between the second conductive portion 1622 located on one side of the first anode 1751 closer to the second anode 1752 and the power line 151 in the first conductive layer 150.

[0251] An embodiment of the present disclosure further provides a display device. FIG. 38 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 38, the display device 400 includes any of the display substrates 100 described above. This allows the display device to have beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can improve the stability and extend the service life of the compensation thin film transistor, thereby improving the long-term luminescence stability and extending the service life of the display substrate.

[0252] For example, the display device may be an electronic product with a display function, such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigation device, or a digital photo frame.

[0253] In addition, (1) The drawings of the embodiments of the present disclosure relate only to the structure of the embodiments of the present disclosure, and other structures may refer to conventional designs. (2) Where not inconsistent, features of the same and different embodiments of the present disclosure may be combined with each other.

[0254] Although the specific embodiments of the present disclosure have been described above, they do not limit the scope of protection of the present disclosure, and the patent scope of the present disclosure should be regulated by the appended claims.

Claims

1. A display substrate, A base substrate; a first gate layer located on the base substrate; a second gate layer located on one side of the first gate layer away from the base substrate; a first conductive layer located on one side of the second gate layer away from the base substrate; the first gate layer includes a reset signal line and a first electrode block extending along a first direction; the second gate layer includes a second electrode block configured to form a storage capacitor with the first electrode block; the first conductive layer includes a power supply line extending along a second direction; the reset signal line and the power supply line have a first overlapping region; the second electrode block and the power supply line have a second overlapping region; a width of the power supply line located in the first overlapping region is less than a width of the power supply line located in the second overlapping region; the first direction and the second direction intersect, the first conductive layer further includes a data line extending along the second direction, the second electrode block has a first width in an overlapping region with the data line and a second width in a second overlapping region with the power supply line, the second width being greater than the first width; the display substrate further includes a semiconductor layer located on one side of the first gate layer closer to the base substrate, the semiconductor layer including a first unit, a second unit, and a third unit, the first unit including a first channel region and first source and drain regions located on both sides of the first channel region, the third unit including two third channel regions, a common electrode located between the two third channel regions, and third source and drain regions located on both sides of the two third channel regions; the first electrode block overlaps the first channel region of the first unit and functions as a gate electrode of the first unit; the third source region is connected to the first drain region, and the third drain region is connected to the gate electrode of the first unit; the second gate layer further includes a conductive block whose orthogonal projection on the base substrate overlaps with an orthogonal projection of the common electrode on the base substrate; the power supply line includes a block overlapping region that overlaps with the conductive block, and in the block overlapping region, an average width of the power supply line is less than a width of the power supply line in the second overlapping region. Display board.

2. the power supply line includes a main body extension portion and a contraction portion, the width of the contraction portion is less than the width of the main body extension portion, and an orthogonal projection of the contraction portion on the base substrate and an orthogonal projection of the reset signal line on the base substrate overlap with each other. The display substrate according to claim 1 .

3. the display substrate further includes a second thin film transistor including a gate connected to the gate line and arranged to connect to the data line; the gate line and the power supply line have a third overlapping region, and a width of the power supply line located in the third overlapping region is less than a width of the power supply line located in the second overlapping region; The display substrate according to claim 1 .

4. a width of the power supply line in the first overlapping region is less than an average width of the power supply line; The display substrate according to claim 3 .

5. the power line includes a main body extension portion and a contraction portion, the width of the contraction portion is less than the width of the main body extension portion, and an orthogonal projection of the contraction portion on the base substrate and an orthogonal projection of the gate line on the base substrate overlap with each other; The display substrate according to claim 3 .

6. the data line and the reset signal line have a fourth overlapping region, and the width of the reset signal line at the fourth overlapping region is less than the width of the reset signal line at the first overlapping region; The display substrate according to any one of claims 1 to 3.

7. the data line and the reset signal line have a fourth overlapping region, and in at least one pixel unit region, the width of the reset signal line in the fourth overlapping region is less than an average width of the reset signal line; The display substrate according to any one of claims 1 to 3.

8. a width of the reset signal line located in the fourth overlapping region is less than ¾ of a maximum width of the reset signal line; The display substrate according to claim 7 .

9. The second gate layer includes an initialization signal line extending along the first direction; the data line and the initialization signal line have a fifth overlapping region; the initialization signal line and the semiconductor layer have a sixth overlapping region; a width of the initialization signal line located in the fifth overlapping region is less than a width of the initialization signal line located in the sixth overlapping region; The display substrate according to claim 8 .

10. In at least one pixel unit region, a width of the initialization signal line located in the fifth overlap region is less than an average width of the initialization signal line. The display substrate according to claim 9 .

11. the semiconductor layer further includes a fourth unit, a fifth unit, a sixth unit, and a seventh unit; the fourth unit includes a fourth channel region and a fourth source region and a fourth drain region located on both sides of the fourth channel region; the fifth unit includes a fifth channel region and a fifth source region and a fifth drain region located on both sides of the fifth channel region; the sixth unit includes a sixth channel region and a sixth source region and a sixth drain region located on both sides of the sixth channel region; the seventh unit includes a seventh channel region and a seventh source region and a seventh drain region located on both sides of the seventh channel region; The display substrate according to claim 9 .

12. the sixth drain region is connected to the third drain region; the third source region, the first drain region, and the fifth source region are connected to a first node; the first source region, the second drain region, and the fourth drain region are connected to a second node; the fifth drain region is connected to the seventh drain region; The display substrate according to claim 11 .

13. 13. The display substrate according to claim 12, wherein the sixth source region and the seventh source region are connected to the initialization signal line.

14. 13. The display substrate according to claim 12, wherein the second source region is connected to the data line.

15. The display substrate according to claim 12 , wherein the fourth source region is connected to the power supply line.

16. a first planar layer located on one side of the first conductive layer away from the base substrate; a second conductive layer located on one side of the first planar layer away from the first conductive layer and including a connection electrode; a second planar layer located on one side of the second conductive layer away from the first planar layer; an anode located on one side of the second planar layer away from the second conductive layer; the first planar layer includes a first via; the connection electrode is connected to the fifth drain region through the first via; the second planar layer includes a second via; the anode is connected to the connection electrode through the second via; The display substrate according to claim 9 .

17. A display device comprising the display substrate according to any one of claims 1 to 3.

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