Error control for memory devices

Abstract

Methods, systems, and devices for error control for memory devices are described. The memory device may be configured to perform memory management operations, including error control operations. For example, the memory device may be configured to perform an error control operation on data stored in a first memory cell coupled to a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled to a target row of the memory array based on performing the error control operation on the data, and to determine whether the management operation is complete based at least in part on a first column address of the first memory cell. The memory device may also generate an output signal for performing an error control operation on a third memory cell coupled to the source row based on determining whether the management operation is complete.

Description

[Technical Field]

[0001] [Cross Reference] This patent application claims priority to U.S. patent application Ser. No. 16 / 895,960 by YAMAMOTO et al., entitled "ERROR CONTROL FOR MEMORY DEVICE," filed June 8, 2020, each of which is assigned to the assignee of the present application and each of which is expressly incorporated herein by reference.

[0002] [Technical field] The following relates generally to one or more memory systems, and more particularly to error control for memory devices. [Background technology]

[0003] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells in the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often represented by a logical 1 or a logical 0. In some instances, a single memory cell can support more than two states, any one of which can be stored. To access the stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state into the memory device.

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase change memory (PCM). Memory devices can be volatile or nonvolatile. Nonvolatile memory, such as FeRAM, can maintain its stored logic state for long periods of time, even in the absence of external power. Volatile memory devices, such as DRAM, can lose their stored state if disconnected from external power. FeRAM can achieve similar densities as volatile memory, but possess nonvolatile characteristics due to the use of ferroelectric capacitors as storage devices. [Brief explanation of the drawings]

[0005] [Figure 1] An example of a system for supporting error control for a memory device according to examples as disclosed herein is described. [Figure 2] 1 illustrates an example memory die that supports error control for a memory device according to examples as disclosed herein. [Figure 3] An example of a memory device circuit that supports error control for a memory device according to examples as disclosed herein is described. [Figure 4] An example of a memory device circuit that supports error control for a memory device according to examples as disclosed herein is described. [Figure 5] 1 illustrates an example timing diagram for supporting error control for a memory device according to examples as disclosed herein. [Figure 6] 1 illustrates an example timing diagram for supporting error control for a memory device according to examples as disclosed herein. [Figure 7]1 illustrates a block diagram of a memory device that supports error control for memory devices according to examples as disclosed herein. [Figure 8] 1 shows a flowchart illustrating one or more methods for supporting error control for a memory device according to examples as disclosed herein. [Figure 9] 1 shows a flowchart illustrating one or more methods for supporting error control for a memory device according to examples as disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] Some memory devices may use one or more memory management operations to manage data stored within the memory device. For example, a memory device may use wear leveling, row copy operations, or other types of operations to distribute wear and / or extend the functional lifespan of the memory device. Some of these operations may not include aspects of error control, which may propagate errors and / or introduce new errors into the data during the memory management operation. Some of these operations may be configured to transfer data within the same section of the memory device, which may limit the potential for wear leveling and other data distribution.

[0007] Systems, devices, and techniques are described for using error control operations in memory management operations. In some cases, memory management operations, such as row copy operations, can be configured to include error control operations. A column address counter can be used to track whether each memory cell in a memory source row is subject to error control and stored in a target row. In some cases, memory management operations, such as sense copy operations, can be configured to transfer data between different sections of a memory device. An error correction component can be configured to toggle between the source section and the target section to facilitate the transfer and error control of the information being transferred.

[0008] The disclosed features are first described in the context of memory systems and dies, as described with reference to Figures 1-2. The disclosed features are described in the context of memory device circuits and timing diagrams, as described with reference to Figures 3-6. These and other disclosed features are further illustrated by and described with reference to apparatus diagrams and flow charts relating to error control for memory devices, as described with reference to Figures 7-9.

[0009] 1 illustrates an example of a system 100 that supports error control for memory devices according to examples as disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling host device 105 with memory device 110. Although system 100 may include one or more memory devices 110, aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0010] System 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a mobile phone, a wearable device, an internet-connected device, a vehicle controller, etc. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

[0011] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry in a device that uses memory to execute processes, such as in a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a mobile phone, a wearable device, an internet-connected device, a vehicle controller, or any other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0012] Memory device 110 may be a separate device or component operable to provide a physical memory address / space that can be used or referenced by system 100. In some examples, memory device 110 may be configurable to operate with one or more different types of host device 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for communicating signals, various types of factors for the physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing rules, or other factors.

[0013] Memory device 110 may be operable to store data for components of host device 105. In some examples, memory device 110 may function as a slave-type device to host device 105 (e.g., executing in response to commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0014] The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components, such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0015] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a system-on-a-chip (SoC), among other examples. In some examples, external memory controller 120 may be implemented by or part of processor 125.

[0016] BIOS component 130 may be a software component including a BIOS operating as firmware, which may initialize and execute various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0017] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), each operable to store at least one bit of data. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0018] Device memory controller 155 may include circuitry, logic, or components operable to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions that enable memory device 110 to perform various operations and may be operable to receive, send, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 may be operable to communicate with one or more of external memory controller 120, one or more memory dies 160, or processor 125. In some examples, device memory controller 155, in conjunction with local memory controller 165 of memory die 160, may control the operation of memory device 110 as described herein.

[0019] In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 should store data for host device 105, or a read command indicating that memory device 110 should provide data stored in memory die 160 to the host device.

[0020] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some examples, local memory controller 165 may be operable to communicate (e.g., receive or send data or commands, or both) with device memory controller 155. In some examples, memory device 110 may not include device memory controller 155 and local memory controller 165, or external memory controller 120 may perform various functions described herein. Thus, local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, or processor 125, or a combination thereof. Examples of components that may be included within device memory controller 155 or local memory controller 165, or both, may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating transmitted signals, or various other circuits or controllers operable to support the described operations of device memory controller 155 or local memory controller 165, or both.

[0021] External memory controller 120 may be operable to facilitate communication of one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may replace or translate communications exchanged between components of host device 105 and memory device 110. In some examples, external memory controller 120 or other components of system 100 or host device 105, or its functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some examples, external memory controller 120, or its functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0022] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 is an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive pathway operable to carry a signal. For example, a channel 115 may include a first terminal that includes one or more pins or pads on the host device 105 and one or more pins or pads on the memory device 110. A pin may be an example of a conductive input or output point of a device of the system 100, and the pin may be operable to function as part of a channel.

[0023] Channel 115 (and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling may be communicated over channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be recorded per clock cycle (e.g., on the rising edge or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be recorded per clock cycle (e.g., on both the rising edge and the falling edge of the clock signal).

[0024] Memory device 110 may be configured to perform error control operations during memory management operations. For example, memory device 110 may be configured to perform memory management operations including a row copy operation in which each memory cell of a source row of memory is copied and stored in a target row of memory. The row copy operation (e.g., memory management operation) may include an error control operation to correct bit errors from propagating from the source row to the target row. The row copy operation may further include a column address counter to track whether each memory cell of the source row has been copied, subjected to error control via the error control operation, and stored in the target row.

[0025] Additionally or alternatively, memory device 110 may be configured to perform error control operations in memory management operations, such as sense copy operations. For example, memory device 110 may be configured to perform memory management operations, including sense copy operations, in which data is transferred between different sections of memory device 110 (e.g., between sections of memory array 170, between memory arrays 170, etc.). During a sense copy operation (e.g., a memory management operation), data may be read from a first memory cell in a first section of memory device 110 into a first sense component. The error component may be configured to toggle between the first and second sense components to perform the error control operation and transfer data from the first sense component to the second sense component. Data may then be transferred from the second sense component to a second memory cell in a second section of the memory device.

[0026] FIG. 2 illustrates an example memory die 200 that supports error control for a memory device according to examples as disclosed herein. The memory die 200 may be an example of the memory die 160 described with reference to FIG. 1. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store a different logical state (e.g., programmable to one state of a set of two or more possible states). For example, the memory cells 205 may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cells 205 (e.g., multi-level memory cells) may be operable to store multiple bits of information at a time (e.g., a logic 00, a logic 01, a logic 10, a logic 11). In some examples, the memory cells 205 may be arranged in an array, such as the memory array 170 described with reference to FIG. 1.

[0027] The memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) that represents a programmable state in a capacitor. In an FeRAM architecture, the memory cell 205 may include a capacitor 240 that includes a ferroelectric material for storing the charge and / or polarization that represents the programmable state. The memory cell 205 may include a logic storage component, such as the capacitor 240, and a switching component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled to the switching component 245, and a second node of the capacitor 240 may be coupled to the plate line 220. The switching component 245 may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

[0028] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a pattern, such as a grid-like pattern. The access lines may be conductive lines coupled to the memory cells 205 and may be used to perform access operations on the memory cells 205. In some examples, the word lines 210 may be referred to as row lines. In some examples, the digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or the like, may be interchangeable without loss of understanding or operation. The memory cells 205 may be located at the intersections of the word lines 210, digit lines 215, and / or plate lines 220.

[0029] By activating or selecting access lines, such as word line 210, digit line 215, and / or plate line 220, operations such as read and write may be performed on memory cells 205. By biasing word line 210, digit line 215, and plate line 220 (e.g., applying a voltage to word line 210, digit line 215, or plate line 220), a single memory cell 205 may be accessed at their intersection. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the individual line.

[0030] Access to memory cells 205 may be controlled through row decoder 225, column decoder 230, and plate driver 235. For example, row decoder 225 may receive a row address from local memory controller 265 and activate word line 210 based on the received row address. Column decoder 230 may receive a column address from local memory controller 265 and activate digit line 215 based on the received column address. Plate driver 235 may receive a plate address from local memory controller 265 and activate plate line 220 based on the received plate address.

[0031] Selecting or deselecting memory cell 205 may be achieved by activating or deactivating switching component 245. Capacitor 240 may be in electronic communication with digit line 215 using switching component 245. For example, capacitor 240 may be isolated from digit line 215 when switching component 245 is deactivated, and capacitor 240 may be coupled to digit line 215 when switching component 245 is activated.

[0032] The sense component 250 may determine the state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205 and may determine the logic state of the memory cell 205 based on the detected state. The sense component 250 may include one or more sense amplifiers for amplifying the signal output of the memory cell 205. The sense component 250 may compare the signal received from the memory cell 205 across the digit line 215 with a reference 255 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sense component 250 (e.g., to an input / output 260) and may indicate the detected logic state to another component of the memory device 110 that includes the memory die 200.

[0033] The local memory controller 265 may control operation of the memory cells 205 through various components (e.g., row decoder 225, column decoder 230, plate driver 235, and sense component 250). The local memory controller 265 may be an example of the local memory controller 165 described with reference to FIG. 1. In some examples, one or more of the row decoder 225, column decoder 230, plate driver 235, and sense component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), convert the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 265 may generate row and column address signals to activate the target word line 210, the target digit line 215, and the target plate line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be varied and may be different for the various operations discussed in the operation of the memory die 200.

[0034] The local memory controller 265 may be operable to perform one or more access operations to one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 may be operable to perform other access operations not listed here, or other operations associated with the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0035] The local memory controller 265 may be operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. The local memory controller 265 may identify a target memory cell 205 on which to perform the write operation. The local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled to the target memory cell 205. The local memory controller 265 may activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., by applying a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The local memory controller 265 may apply particular signals (e.g., write pulses) to the digit lines 215 during a write operation to store a particular state (e.g., charge) in the capacitors 240 of the memory cells 205. The pulses used as part of a write operation may include one or more voltage levels for a period of time.

[0036] The local memory controller 265 may be operable to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in the memory cells 205 of the memory die 200 may be determined. The local memory controller 265 may identify a target memory cell 205 on which to perform a read operation. The local memory controller 265 may identify a target word line 210, a target digit line 215, and a target plate line 220 coupled to the target memory cell 205. The local memory controller 265 may activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., by applying a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transfer a signal to the sense component 250 in response to biasing the access line. The sense component 250 may amplify the signal. The local memory controller 265 may activate the sense component 250 (e.g., latch the sense component) so that it can compare the signal received from the memory cell 205 to the reference 255. Based on the comparison, the sense component 250 may determine the logic state stored on the memory cell 205.

[0037] The memory die 200 (e.g., the local memory controller 265) may be configured to perform error control operations during memory management operations. For example, the local memory controller 265 may be configured to perform memory management operations including a row copy operation in which each memory cell 205 of a source row is copied and stored in a memory cell 205 of a target row. The row copy operation (e.g., memory management operation) may include an error control operation to correct bit errors from propagating from the source row to the target row. In this regard, the local memory controller 265 may include, or be communicatively coupled to, an error control component that performs the error control operation on each memory cell 205 during the row copy operation. The row copy operation may include a column address counter for tracking whether each memory cell 205 of the source row has been copied, subjected to error control via the error control operation, and stored in a memory cell 205 of the target row.

[0038] The memory die 200 (e.g., the local memory controller 265) may additionally or alternatively be configured to perform error control operations in memory management operations, such as sense copy operations. For example, the local memory controller 265 may be configured to perform memory management operations, including sense copy operations, in which data is transferred between different sections of the memory die 200 or between a first memory die 200 and a second memory die 200. During a memory management operation (e.g., a sense copy operation), the local memory controller 265 may read data from a first memory cell 205 in the first section into the sense component 250. The error component may be configured to toggle between the sense component 250 and an additional sense component 250 (e.g., an additional sense component of the memory die, or a sense component 250 of an additional memory die) to perform the error control operation and transfer data from the sense component 250 to the additional sense component 250. The data may then be transferred from the additional sense component 250 to a second memory cell 205 in a second section of the memory device. In this regard, data of a first memory cell 205 in a first section of memory die 200 may be copied, subjected to error control via error control operations, and stored in memory cells 205 in a second section of memory die 200. Additionally or alternatively, data of a first memory cell 205 in the first memory die 200 may be copied, subjected to error control via error control operations, and stored in memory cells 205 in a second memory die 200.

[0039] 3 illustrates an example of memory device circuitry 300 that supports error control for a memory device according to examples as disclosed herein. In some examples, memory device circuitry 300 may include circuitry of memory die 200, or some portion thereof (e.g., of local memory controller 265, of memory array 170).

[0040] Some memory devices may use one or more memory management operations to manage data stored within the memory device. Examples of memory management operations may include a row copy operation, a sense copy operation, a garbage collection operation, a wear leveling operation, or other operations to distribute wear and / or extend the functional lifespan of a memory device. During a row copy operation, data stored in one row (e.g., a source row) of a memory array may be copied and written to another row (e.g., a target row) of the memory array. However, some row copy operations may not include aspects of error control, which may propagate errors and / or introduce new errors into the data during the row copy operation. Illustratively, in the context of a DRAM refresh or row copy operation, the data in the memory cells of the source row may already contain one or more errors when the refresh or row copy operation is performed. In such an example, some row copy operations may not be able to detect or correct one or more errors in the data, and therefore, an erroneous memory state may propagate to the target row. Similarly, a row copy operation without error control operations may also introduce new errors into the data during the transfer of information. Error propagation and / or the introduction of new errors may reduce the effectiveness of memory management operations.

[0041] Accordingly, techniques are described herein for using error control operations in memory management operations, such as row copy operations, sense copy operations, garbage collection operations, wear leveling operations, or other operations, or combinations thereof. In some cases, the row copy operation may include an error control operation configured to identify one or more errors in information stored by a source row and correct the determined errors before writing data to memory cells of a target row. The row copy operation may further include techniques for tracking whether each memory cell of the source row has been copied, subjected to an error control operation, and written to the target row. For example, memory device circuit 300 may describe an exemplary circuit that determines when the row copy operation is complete by tracking a column address counter to determine whether each memory cell of the source row has been copied, subjected to error control via an error control operation, and stored in a memory cell of a target row. Such techniques may enable improved row copy operations that prevent propagation of bit errors throughout memory device 110 (e.g., memory die 200), thereby providing improved wear leveling and memory management operations. To implement error control operations during memory management operations, column counters and other control logic may be used to identify when every column of a source row has been read.

[0042] Memory device circuitry 300 may receive a set of input signals for performing a row copy operation. For example, memory device circuitry 300 may receive a write status signal, a column select signal, a refresh signal, and a global command address signal. The input signals to memory device circuitry 300 may be received from host device 105 (e.g., via a CA channel) and may include or be based on a command issued by memory device 110 (e.g., from device memory controller 155 or local memory controller 265). Memory device circuitry 300 may further include a set of logic components (e.g., AND gates, inverting gates, etc.) configured to combine and perform logical commands on the input signals of memory device circuitry 300.

[0043] The memory device circuit 300 may include a counter 305 that may be configured to determine whether a memory management operation is complete. In particular, the counter 305 may be configured to track (e.g., increment) a column address of a source row of a memory management operation (e.g., a row copy operation) to track whether each column of the source row (and therefore each memory cell 205) has been copied, subjected to error control via an error control operation, and written to the target row. In this regard, the counter 305 may receive signals, commands, or other indicators or triggers related to the memory management operation (e.g., a row copy operation). For example, the counter 305 may include an input clock (CLK) signal, an input set signal, and an input reset signal. The set signal and reset signal may load the counter 305 with an initial column address associated with the row copy operation, and the CLK signal may periodically pulse to increment the column address counter 305 to provide a new column latch value until the row copy operation is complete.

[0044] The memory device circuit 300 may further include a latch 310. The latch 310 may be an example of a three-input latch configured to receive a last add signal, an activate signal, and a reset signal. The activate signal may be based on the write state signal and the column select signal and may indicate the start of a next period in which a next scrub may begin. The activate signal may be configured to cause the latch to output a value input to the latch via the last add signal. The last add input signal may be received from the counter 305 and may indicate whether the last column of the source row of the row copy operation has been addressed. The latch 310 may be configured to generate an output signal for the row copy operation. For example, the output of the latch 310 may be used to generate a next scrub signal to trigger a row copy operation on the next column of the source row and to generate a row copy done signal when the row copy operation is complete (e.g., after the last column of the row copy operation has been addressed). In particular, the last add signal may have a first value when the column address is not the last column address of the source row and a second value when the column address is the last column address of the source row, which indicates when the row operation is complete. In this regard, the latch 310 may generate a row copy done signal indicating the end of the row copy operation when the last add input signal indicates the last column of the source row.

[0045] To initiate a row copy operation, host device 105 (e.g., via the CA channel) and / or memory device 110 (e.g., from device memory controller 155 or local memory controller 265) may determine a source row and a target row for the row copy operation. Host device 105, device memory controller 155, and / or local memory controller 265 may initiate a row copy operation (e.g., a management operation) to transfer information from a source row to a target row of memory die 200. Host device 105, device memory controller 155, and / or local memory controller 265 may initiate the row copy operation by generating one or more command signals. The one or more command signals for initiating the row copy operation may include an indication of a first row address associated with the source row and a second row address associated with the target row. The one or more command signals may further include an indication of a first column address indicating a first column of the source address at which the row copy operation is to be initiated.

[0046] One or more command signals used to initiate a row copy operation (e.g., a management operation) may include a column select signal, a write status signal, a tRCDdoneRfsh signal, and a global command address (CA) signal. The global CA signal may include multiple address bits for indicating a column address (e.g., a first column address) of the source row currently being accessed. The row copy operation may be initiated based on generating the tRCDdoneRfsh signal high, the write status signal low, and the column select signal high. The tRCDdoneRfsh signal may indicate that source row data sensing is complete and that copy data has been latched into the source row. When the tRCDdoneRfsh signal transitions from low to high, the reset state of the latch 310 may be released while the output of the latch 310 remains low. The tRCDdoneRfsh signal may be provided to an input of the shot H component 355.

[0047] Shot H component 355 may include a one-shot pulse generator that is generally low and pulses high. Shot H component 355 may detect a rising edge input and generate a high pulse on its output, which is provided to components 325 and 330 (e.g., AND component 325 and AND component 330). Components 325 and 330 may represent multiple devices (e.g., one device for each of multiple global address bits that may be addressed via the global CA signal). Each high global CA bit combined with a high pulse from shot H component 355 in component 325 may cause a corresponding set bit to set an associated output bit from counter 305 high to represent the state of the global CA bit. Each low global CA bit combined with a high pulse from shot H component 355 in component 330 may cause a corresponding reset bit to reset an associated output bit from counter 305 low to represent the state of the global CA bit. Thus, a low-to-high transition of the tRCDdoneRfsh signal may cause the starting column address information from the global CA signal to be indicated by the reference command address signal output from counter 305. The reference command address signal may be provided to component 335 and a column latch (e.g., latch 310). The first column of the source row may be read to the error control logic, and the write status input goes high to write the first column data from the error control logic to the target row.

[0048] The write state signal and the column select signal may be combined via an AND gate 350 or other logic component and further input to a shot L component 320, which outputs a latch signal provided at an activation input to a latch 310. The shot L component 320 may include a normally high, normally low pulse generator, as described in further detail herein. The pulse low at the activation input to the latch 310 may allow the last append output, as decoded from the reference command address signal by component 335, to be received by the latch 310 and appear at the latch output. The output of component 350 may be further combined with the true output of the latch 310 to activate an end row copy signal if the last append input to the latch 310 via the reference command address signal was high. The output of component 350 may be further combined with the complement output of the latch 310 to activate a next scrub signal if the last append input to the latch 310 via the reference command address signal was low. When the next high of the scrub signal indicates the start of another scrub cycle, the signal write state signal will transition to a low state. The inverted write state signal may be combined with the continuous high state of the column select signal in component 315 to create a high edge on the CLK that inputs to counter 305. This high CLK edge may cause the output of counter 305 to count to the next column address via the reference command address signal.

[0049] The reference command address signal may be output as a column latch signal that triggers a row copy operation on the selected memory cell 205 currently being accessed. The column latch signal may include an indication of the column address of the memory cell 205 currently being accessed for the row copy operation. In this regard, the sense component 250 of the memory device may read data from the first memory cell 205 of the source row identified via the first column address indicated by the column latch signal. The error control component may be configured to perform an error control operation on the data stored in the first memory cell 205 based on the column latch signal. During the error control operation, the error control component may determine errors in the data of the first memory cell 205 associated with the first row address and the first column address and correct the errors, if any. Subsequently, the data from the first memory cell 205 of the source row may be written to the memory cell 205 associated with the target row of the memory die 200. The data from the first memory cell 205 of the source row may be written to the memory cell 205 of the target row based on performing the error control operation.

[0050] The final additional signal may be generated by processing the output of counter 305. Counter 305 may output a column address to be used for the current or next copy operation. Component 335 (e.g., an AND gate) may be configured to identify when the last column of a source row is being accessed. In some examples, the AND gate may be configured to combine at least a portion of the bits of the column address. If the bits of the column address are a first value (e.g., a logic "1"), the AND gate may output a first value; otherwise, the AND gate may output a second value (e.g., a logic "0"). Component 335 used to determine whether the last column address is being accessed or has been accessed may be any type of component used to compare information with a reference or threshold. An AND gate is just one example of such a type of component. The reference command address signal may further be input to component 335 or other logic component configured to determine whether the row copy operation is complete based on the column address being accessed (e.g., the first column address). In particular, component 335 may be configured to determine whether the column address meets a threshold associated with the source row. The threshold value associated with the source row may be based on the last column address of the source row. For example, when accessing a first memory cell 205 indicated via a first column address, component 335 may be configured to combine one or more bits of the first column address into a value and compare the value to the threshold value associated with the source row.

[0051] In this regard, component 335 may be configured to receive the reference command address signal and output a final add signal. The final add signal may include an indication of whether the row copy operation is complete. Illustratively, if a value generated by combining one or more bits of the first column address satisfies a threshold associated with the source row, the final add signal may include a logic "1" indicator indicating that the row copy operation is complete. Conversely, if a value generated by combining one or more bits of the first column address does not satisfy the threshold associated with the source row, the final add signal may include a logic "0" indicator indicating that the row copy operation is not complete.

[0052] Latch 310 may receive a final additional signal that includes an indication of whether the row copy operation is complete. Latch 310 may further receive an input latch signal. The input latch signal may be generated based on a column select signal generated by device memory controller 155 or local memory controller 265. In particular, the column select signal, which includes an indication of the column address of the source row currently being accessed, may be input to shot L component 320, which generates an activate signal.

[0053] Latch 310 may output a signal that is provided to AND gate 340 and AND gate 345. AND gate 340 may be configured to receive the output signal from latch 310 and another signal based on the write status signal and the column select signal. If the output signal of latch 310 indicates that the row copy operation is complete (e.g., the last column of the source row has been copied and written to the target row), AND gate 340 may generate a row copy done signal that ends the row copy operation, as will be discussed in more detail herein. AND gate 345 may be configured to receive the output signal from latch 310 and a signal based on the write status signal and the column select signal. If the output signal of latch 310 indicates that the row copy operation is not complete (e.g., the last column of the source row has not been copied and written to the target row), AND gate 345 may generate a next scrub signal.

[0054] The next scrub signal may be configured to trigger the write state signal to retry for a different column address associated with the source row. Additionally or alternatively, the next scrub signal may be configured to increment a column address counter (e.g., counter 305) associated with the source row. In particular, the next scrub signal may be configured to increment a column address counter pointed to via the column select signal. In this regard, the next scrub signal may be configured to trigger the row copy operation to proceed to the next column of the source address if it is determined that the row copy operation is not complete. For example, if the first column address does not meet the threshold associated with the source row, the final add signal generated by component 335 may indicate a “0” indicating that the row copy operation is not complete, causing latch 310 to generate an output signal that triggers AND gate 345 to output the next scrub signal. In this example, the next scrub signal may be configured to activate the write state signal and increment the column address counter pointed to via the column select signal to the next column address of the source row. Illustratively, the next scrub signal may increment the column address counter to the second column address of the source row.

[0055] Reassertion of the write state signal and incrementing the column address counter (indicated via the column select signal) to a second column address may initiate a row copy operation for the next memory cell in the source row associated with the source row address and the second column address. The column select signal may be combined with the write state signal by AND gate 315 and input as the CLK signal to counter 305. The write state signal and column select signal may be additionally combined by AND gate 350, which generates a signal provided to shot L component 320 and AND gate 340.

[0056] The counter 305 may output a reference command address signal (which may include a column address for the current or next column that is part of the row copy operation) based on the CLK signal and the SET signal. The reference command address signal may include an index of the column address of the memory cell 205 of the source row currently being accessed. For example, when performing a row copy operation on the second memory cell 205 of the source row indicated by the second column address count, the reference command address signal may include an index of the second column address.

[0057] The sense component 250 of the memory die 200 may read data stored in the second memory cell 205 at the source row address and the second column address. The error control component may be configured to perform an error control operation on the data stored in the second memory cell 205. During the error control operation, the error control component may determine whether an error exists in the data of the second memory cell 205 associated with the first row address and the second column address, and may correct the error, if any. The data of the second memory cell 205 of the source row may then be written to the second memory cell 205 associated with the target row of the memory die 200. The data of the second memory cell 205 of the source row may be written to the memory cell 205 of the target row based on performing the error control operation.

[0058] The reference command address signal may further be input to component 335 or other logic component configured to determine whether the row copy operation is complete based on the column address being accessed (e.g., the second column address). Component 335 may be configured to determine whether the column address indicated by the reference command address signal satisfies a threshold associated with the source row. The threshold associated with the source row may be based on the last column address of the source row. For example, when accessing the second memory cell 205 indicated via the second column address, component 335 may be configured to combine one or more bits of the second column address into a value and compare it with the value associated with the source row. In this regard, component 335 may be configured to receive the reference command address signal and output a last additional signal. The last additional signal may be used to indicate whether the row copy operation is complete. Illustratively, if the value generated by combining one or more bits of the second column address satisfies the threshold associated with the source row, the last additional signal may include a “1” indicator, indicating that the row copy operation is complete. Conversely, if the value produced by combining one or more bits of the second column address does not satisfy the threshold associated with the source row, the final additional signal may include a “0” indicator indicating that the row copy operation is not complete.

[0059] Latch 310 may receive a final additional signal that includes an indication of whether the row copy operation is complete. Latch 310 may further receive an activation signal that may be based on the column select signal. In particular, the column select signal, which includes an indication of the column address of the currently accessed source row, may be input to shot L component 320, which generates the activation signal. Latch 310 may generate an output signal that is provided to AND gate 340 and AND gate 345.

[0060] AND gate 345 may be configured to receive an output signal from latch 310 and a signal based on the write state signal and the column select signal. If the output of latch 310 indicates that the row copy operation is not complete (e.g., the last column of the source row has not been copied and written to the target row), AND gate 345 may generate a next scrub signal. For example, if the second column address is not the last column address of the source row, latch 310 may generate an output signal that causes AND gate 345 to generate a next scrub signal. The next scrub signal may be configured to re-assert the write state signal and increment a column address counter associated with the source row. In particular, the next scrub signal may be configured to increment the column address counter via the column select signal. In this regard, the next scrub signal may be configured to trigger the row copy operation to proceed to the next column of the source row if it is determined that the row copy operation is not complete. For example, if the second column address does not meet the threshold associated with the source row, the final add signal generated by AND gate 335 may indicate a "0" indicating that the row copy operation is not complete, which may cause latch 310 to generate an output signal that triggers AND gate 345 to output a next scrub signal. In this example, the next scrub signal may be configured to activate the write state signal and increment a column address counter, indicated via the column select signal, to the next column address of the source row. Illustratively, the next scrub signal may increment the column address counter to the third column address of the source row.

[0061] AND gate 340 may be configured to receive the output signal of latch 310 and another signal based on the write status signal and the column select signal. When the output signal of latch 310 indicates that the row copy operation is complete (e.g., the last column of the source row has been copied and written to the target row), AND gate 340 may generate a row copy done signal that ends the row copy operation. For example, when the second column address meets a threshold associated with the source row, the last additional signal may indicate a "1" indicating that the row copy operation is complete, which may cause latch 310 to generate an output signal that triggers AND gate 340 to output the row copy done signal.

[0062] The row copy done signal may indicate that every column of the source row has been addressed by the row copy operation. In this regard, the row copy done signal may indicate the end of the row copy operation for the source row. The row copy done signal may trigger the issuance of a refresh signal (e.g., a tRCD done signal). The refresh signal may be sent to the local memory controller 165 to end the row copy operation.

[0063] After the row copy operation is completed, the target row may be precharged. In some cases, device memory controller 155 and / or local memory controller 265 may generate a signal configured to precharge the target row based on determining that a memory management operation (e.g., a row copy operation) is completed.

[0064] The techniques described herein with respect to memory device circuit 300 may enable improved memory management operations. More specifically, memory device circuit 300 may enable row copy operations that include error control operations configured to prevent the row copy operation from propagating errors from a source row to a target row. Additionally or alternatively, memory device circuit 300 may enable tracking of a column address counter of a source row to ensure that the row copy operation (and error control operation) is performed for each memory cell 205 (e.g., each column address) of the source row.

[0065] 4 illustrates an example of memory device circuitry 400 that supports error control for a memory device according to examples as disclosed herein. In some examples, memory device circuitry 300 may include circuitry of memory die 200, or some portion thereof (e.g., of local memory controller 265, of memory array 170).

[0066] Some memory devices may perform memory management operations, such as sense copy operations, to implement wear leveling and manage data stored within the memory device. During a sense copy operation, data from a first memory cell may be read into a sense component and transferred to a second memory cell different from the first memory cell. However, some sense copy operations may not include error control aspects, which may propagate errors and / or introduce new errors into the data during the sense copy operation. Furthermore, some sense copy operations may be performed through a single sense component and may allow data to be transferred between memory cells within the same section. For example, some sense copy operations may not be capable of transferring data from a first memory cell in a first section of a memory device to a second memory cell in a second section of the memory device. As used herein, the term "section" may be used to refer to any subset of a memory device known in the art. For example, in some cases, a first section may refer to a first set of sense amplifiers that are independently addressable with respect to a second set of sense amplifiers. The second set of sense amplifiers may be within the second section. As another example, a first section may refer to a first region within a memory die, and a second section may refer to a second region within the memory die.

[0067] Techniques are described herein for using a set of error control operations and sense components to perform sense copy operations between sections of a memory device. For example, the sense copy operation may be performed to transfer data between different sections of a memory die 200 or between a first memory die 200 and a second memory die 200. In some cases, the sense copy operation may include an error control operation configured to determine and correct errors in a first memory cell before copying the data of the first memory cell to a second memory cell. During a sense copy operation (e.g., a memory management operation), the local memory controller 265 may read data from a first memory cell 205 in the first section into a sense component 250. The error component may be configured to toggle between the sense component 250 and an additional sense component 250 (e.g., an additional sense component of the memory die 200 or a sense component 250 of an additional memory die 200) associated with an address of interest for the data. The error control component may be configured to perform error control operations to determine and correct bit errors in the data of the first memory cell 205 before transferring the data to the additional sense component 250. The data may then be transferred from the additional sense component 250 to a second memory cell 205 in a second section of the memory device. Such techniques may enable improved sense copy operations that prevent propagation of bit errors throughout the memory device 110 (e.g., memory die 200), thereby providing improved wear leveling and memory management operations. Furthermore, the techniques of this disclosure may enable sense copy operations to be performed between two different sections of the memory device, thereby improving flexibility in wear leveling and data management.

[0068] The memory device circuit 400 may include a first set of memory cells 405 and a second set of memory cells 435. The first set of memory cells 405 may include memory cells 405-a, 405-b, 405-c, and 405-d, and the second set of memory cells 435 may include memory cells 435-a, 435-b, 435-c, and 435-d. The first set of memory cells 405 may be associated (e.g., coupled) with a first word line 440 (e.g., a source word line 440), and the second set of memory cells 435 may be associated with a second word line 445 (e.g., a target word line 445). In some cases, a first section of the memory device 110 may include the first set of memory cells 405, and a second section of the memory device 110 may include the second set of memory cells 435. For example, the first section may include a first set of memory cells 405, and the second section may include a second set of memory cells 435. In some aspects, the first section may be associated with a first section address, and the second section may be associated with a second section address.

[0069] The sense copy operation may be configured to transfer data from the first set of memory cells 405 to the second set of memory cells 435. If the first set of memory cells 405 and the second set of memory cells 435 are located in different sections of the memory device 110 (e.g., different sections of the memory array 170), the sense copy operation may be configured to transfer data from one section of the memory device 110 to another section of the memory device 110. The memory device circuitry 400 may receive one or more input signals for initiating the sense copy operation. The one or more input signals configured to initiate the sense copy operation may be received from the host device 105 (e.g., via the CA channel) or may include or be based on a command issued by the memory device 110 (e.g., from the device memory controller 155 or the local memory controller 265).

[0070] During a sense copy operation, data from the first memory cell 405-a may be read into the first sense component 415-a. In some cases, the first memory cell 405-a and / or the first sense component 415-a may be included within a first section of a memory device. For example, the first memory cell 405-a and the first sense component 415-a may be included within a first section of a memory device and / or memory array. Data may be transferred from the first memory cell 405-a to the first sense component 415-a via a first digit line 410-a associated with the first section. Data may also be read from the first memory cell 405-a to the first sense component 415-a by activating the first sense component 415-a of the first section. In some cases, the first sense component 415-a may be activated by the host device 105, the device memory controller 155, and / or the local memory controller 265.

[0071] The data may then be transferred from the first sense component 415-a to the error control component 420-a. The error control component 420-a may be configured to perform an error control operation on the data. The error control component 420-a may perform the error control operation on the data based on the data being transferred to the error control component 420-a. During the error control operation, the error control component 420-a may determine that the data of the first set of memory cells contains one or more errors and may correct the errors, if any. The error control component 420-a may be located within the first section or the second section of the memory device or memory array. For example, in some cases, the error control component 420-a may be included in the first section along with the first memory cell 405-a and the first sense component 415-a. As another example, in other cases, the error control component 420-a may be included in the second section. In other cases, the error control component 420 may be located within any portion of the memory device and may not be specifically associated with the first section or the second section.

[0072] In some cases, data may be transferred from a first sense component 415-a in the first section to an error control component 420-a via data lines. The data lines may be routed throughout the memory device and / or memory array and may traverse from the first section to the second section. In this regard, data may be transferred from a first sense component 415-a in the first section to an error control component 420-a in the second section via data lines routed from the first section to the second section.

[0073] In some cases, data may be transferred from the first sense component 415-a to the error control component 420-a based on latching a section address of the first sense component 415-a into a first latch. For example, a first section address associated with the first section (e.g., a first section address associated with the first sense component 415-a within the first section) may be stored in the first latch. In this example, data may be transferred from the first sense component 415-a to the error control component 420-a based on storing a first section address associated with the first sense component 415-a in the first latch.

[0074] Data may be transferred from the error control component 420-a to a second sense component 425-a, as shown in Figure 4. The second sense component 425-b may be associated with a second section of the memory device or memory array. In some cases, data may be transferred from the error control component 420-a to the second sense component 425-a in the second section via data lines. The data lines may be routed throughout the memory device 110 and / or memory array 170 and may traverse from the first section to the second section.

[0075] In some aspects, the error control component 420-a may be configured to toggle between the first sense component 415-a and the second sense component 425-a to transfer data between them. For example, data may be read from the first memory cell 405-a to the first sense component 415-a by activating the first sense component 415-a associated with the first section. In this example, the activation of the first sense component 415-a may be maintained to transfer data from the first sense component 415-a to the error control component 420-a and from the error control component 420-a to the second sense component 425-a associated with the second section. In this regard, the error control component 420-a may be configured to toggle between the first sense component 415-a and the second sense component 415-b to transfer data between the two based on maintaining the activation of the first sense component 415-a.

[0076] The second sense component 425-a may be activated to transfer data from the error control component 420-a to the second sense component 425-b. In this regard, data may be transferred from the error control component 420-a to the second sense component 425-a based on activating the second sense component 25-a. In some cases, the second sense component 425-a may be activated based on performing an error control operation by the error control component 420-a. In some cases, the second sense component 425-a may be activated by the host device 105, the device memory controller 155, and / or the local memory controller 265.

[0077] In some cases, data may be transferred from the error control component 420-a to the second sense component 425-a based on latching the section address of the second sense component 425-a into a second latch. For example, a second section address associated with the second section (e.g., a second section address associated with the second sense component 425-a within the second section) may be stored in the second latch. In this example, data may be transferred from the error control component 420-a to the second sense component 425-a based on storing the second section address associated with the second sense component 425-a in the second latch.

[0078] Data may be transferred from the second sense component 425-a to the memory cell 435-a. The memory cell 435-a may be associated with (e.g., located within) a second section of the memory device 110 or the memory array 170. In some cases, data may be transferred from the second sense component 425-a to the memory cell 435-a via a second digit line 430-a associated with the second section.

[0079] Data stored in memory cells 405-b, 405-c, and 405-d can similarly be transferred to memory cells 435-b, 435-c, and 435-d throughout the sense copy operation. In this regard, any description associated with transferring data from memory cell 405-a to memory cell 435-a can further be understood to apply to transferring data between memory cells 405-b, 405-c, and 405-d and memory cells 435-b, 435-c, and 435-d. For example, data in memory cell 405-b can be transferred to memory cell 435-b via digit line 410-b, sense component 415-b, error control component 420-b, sense component 425-b, and digit line 430-b.

[0080] Although sense components 415-a, 415-b, 415-c, and 415-b, sense components 425-a, 425-b, 425-c, and 425-d, and error control components 420-a, 420-b, 420-c, and 420-d are shown and described as comprising separate components, this should not be considered a limitation of the present disclosure unless otherwise noted herein. In this regard, two or more components may be combined into a single component. For example, in some cases, error control components 420-a, 420-b, 420-c, and 420-d may comprise a single error control component configured to perform error control operations for transferring data between each individual memory cell of first set of memory cells 405 and second set of memory cells 435. Similarly, in some cases, sense components 415-a, 415-b, 415-c, and 415-b may include a single sense component associated with a first section, and sense components 425-a, 425-b, 425-c, and 425-d may include a single sense component associated with a second section.

[0081] 5 illustrates an example timing diagram 500 supporting error control for a memory device in accordance with examples as disclosed herein. Timing diagram 500 illustrates an example of sequential disabling and enabling of voltage supplies that may be associated with a sense copy operation. Timing diagram 500 also illustrates an example of sequential disabling and enabling of voltage supplies that may be associated with components or operations of memory die 200. In one example, the voltages of timing diagram 500 may be associated with memory device circuitry 400 described with reference to FIG. 4. However, the described techniques are applicable to other components, configurations, and numbers of voltage supplies of memory die 200.

[0082] When performing a sense copy operation to copy memory cells 205 of a source row in the first section (e.g., memory cell 405) to memory cells 205 of a target row in the target section (e.g., memory cell 435), memory die 200 may activate a source row address associated with the source row by generating a source row address signal. After the source row address is enabled (e.g., activated), a source word line associated with the source row may be activated by generating a WordLineEnable signal. The source row address signal and the WordLineEnable signal may be configured to enable memory die 200 to access the memory cells of the source row to be copied during the sense copy operation.

[0083] After the source row address and word line of memory cell 205 are both activated (e.g., the Source Row Address signal and the WordLineEnable signal are both activated), memory die 200 may activate the sense components (e.g., sense components 415) associated with the source row by generating SenseAmpEnable. At some point after the source row is activated, the sense components (e.g., sense components 415) associated with the source row may be activated to read (e.g., sense) the data in memory cell 205 of the currently accessed source row. Memory die 200 may then latch the source row by generating the SourceSenseAmpLat signal.

[0084] The sense component may remain activated (e.g., the SenseAmpEnable signal remains activated) so that scrubbing can be performed back and forth from the data maintained in the sense component (e.g., sense component 415). In comparison, once the source row is latched and data from memory cells 205 in the source row is read into the sense component, the WordLineEnable signal may go low, thereby deactivating the source word line. In this regard, the WordLineEnable signal may be pulsed low to allow memory die 200 to deactivate the source row address and activate the target row address. After the target row address is activated, the WordLineEnable signal may be activated again. Additionally, after both the target row address and word line are activated, memory die 200 may generate a TargetSenseAmpLat signal to activate and latch the sense component (e.g., sense component 425) associated with the target row.

[0085] The memory die 200 may maintain activation of the source sense component (e.g., sense component 415) and the target sense component (e.g., sense component 425) as described by the SenseAmpEnable signal and the TargetSenseAmpLat signal to scrub (e.g., toggle) back and forth with the error control component 420 between the source sense component 415 and the target sense component 425. In this regard, the error control component may toggle between the source sense component and the target sense component to transfer data from the source sense component to the target sense component.

[0086] 6 illustrates an example of a timing diagram 600 supporting error control for a memory device in accordance with examples as disclosed herein. Timing diagram 600 illustrates an example of sequential disabling and enabling of voltage supplies that may be associated with a sense copy operation. Timing diagram 600 also illustrates an example of sequential disabling and enabling of voltage supplies that may be associated with components or operations of a memory die (e.g., memory die 200). In one example, the voltages of timing diagram 600 may be associated with memory device circuitry 400 described with reference to FIG. 4 and timing diagram 500 described with reference to FIG. 5. However, the described techniques are applicable to other components, configurations, and numbers of voltage supplies of a memory die.

[0087] When performing a sense copy operation, the memory die may generate an activation of a word line of a source row (e.g., source word line 440). Sometime after the word line of the source row is activated, memory die 200 may activate a sense component (e.g., sense component 415) associated with the first row. An initial read of one or more memory cells 205 (e.g., memory cell 405) in the source row to an error control component (e.g., error control component 420) may be performed when both the source word line and the source sense component are activated.

[0088] Thereafter, the source word line may be deactivated, and the memory die may activate the target word line (e.g., target word line 445). The memory die may further activate the target sense component (e.g., sense component 425). The memory die may maintain the source sense component (e.g., sense component 415) activated and the target sense component (e.g., target sense component 425) activated to scrub back and forth with the error control component (e.g., error control component 420) between the source sense component and the target sense component. In this regard, the error control component may toggle between the source sense component and the target sense component to transfer data from the source sense component to the target sense component. During the scrubbing period, the memory die may maintain the target word line (e.g., target word line 445) activated so that data may be transferred from the error control component to the target sense component throughout the scrubbing period. Accordingly, the bolded portion within the scrubbing period may additionally or alternatively describe a write pulse that transfers data to the target sense component and writes data from the target sense component to the target memory cell.

[0089] 7 shows a block diagram 700 of a memory device 705 that supports error control for memory devices according to examples as disclosed herein. The memory device 705 may be an example of an embodiment of a memory device as described with reference to FIGS. 1-6. The memory device 705 may include an error control component 710, an operation manager 715, a command and address manager 720, and a precharge component 725. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0090] The error control component 710 may perform an error control operation on data stored in a first memory cell coupled to a source row of the memory device, the first memory cell being located at a first column address and a first row address of the source row, based on initiating the management operation. In some examples, the error control component 710 may perform the error control operation on the data using the error control component based on transferring the data to the error control component. In some examples, the error control component 710 may read the data of the first memory cell. In some examples, the error control component 710 may determine an error in the data of the first memory cell. In some examples, the error control component 710 may correct the error based on determining the error.

[0091] In some examples, the error control component 710 may toggle between the first sense component of the first section and the second sense component of the second section to transfer a set of data between the first sense component and the second sense component based on transferring the data to the second memory cell. In some examples, the error control component 710 may maintain activation of the first sense component after transferring the data from the first sense component to the error control component, and toggling between the first sense component of the first section and the second sense component of the second section is based on maintaining activation of the first sense component. In some examples, the error control component 710 may transfer data from the error control component to a second sense component associated with a second section of the memory device. In some cases, the first section includes the first memory cell. In some cases, the second section includes the second memory cell.

[0092] The operation manager 715 may initiate management operations to transfer information from a source row to a target row of the memory device. In some examples, the operation manager 715 may write the data to a second memory cell associated with the target row of the memory device based on performing the error control operation on the data.

[0093] In some examples, the operation manager 715 may determine whether the management operation is complete based on the first column address of the first memory cell. In some examples, the operation manager 715 may generate an output signal to perform an error control operation on a third memory cell coupled to the source row based on determining whether the management operation is complete. In some examples, the operation manager 715 may read data from the first memory cell into the first sense component as part of a management operation to transfer information from a first section to a second section of the memory device. In some examples, the operation manager 715 may generate a write status signal and a global command address signal that includes an index to a command address counter.

[0094] In some examples, the operation manager 715 may activate a first sense component of the first section, and reading the data is based on activating the first sense component. In some examples, the operation manager 715 may activate a second sense component of the second section based on performing the error control operation, and transferring the data from the error control component to the second sense component is based on activating the second sense component. In some examples, the operation manager 715 may transfer data from the first memory cell to the first sense component via a first digit line associated with the first section of the memory device.

[0095] The command address manager 720 may determine whether the first column address satisfies a threshold associated with the source row. In some examples, the command address manager 720 may combine one or more bits of the first column address into a value. In some examples, the command address manager 720 may compare the value to a threshold associated with the source row, and determining whether the first column address satisfies the threshold is based on comparing the value to the threshold. In some examples, the command address manager 720 may increment a column address counter associated with the source row based on generating the output signal. In some examples, the command address manager 720 may identify a second column address of a third memory cell based on incrementing the column address counter. In some examples, the command address manager 720 may determine that the management operation is complete based on a third column address associated with the third memory cell. In some examples, the command address manager 720 may determine that the third column address satisfies a threshold associated with the source row.

[0096] The precharge component 725 may precharge the target row based on determining that the management operation is complete.

[0097] FIG. 8 shows a flowchart illustrating one or more methods 800 for supporting error control for a memory device according to examples as disclosed herein. The operations of method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 800 may be performed by a memory device as described with reference to FIG. 7. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0098] At 805, the memory device may initiate a management operation to transfer information from a source row to a target row of the memory device. The operation of 805 may be performed according to methods described herein. In some examples, aspects of the operation of 805 may be performed by an operation manager, as described with reference to FIG. 7.

[0099] At 810, the memory device may perform an error control operation on data stored in a first memory cell coupled to a source row of the memory device, the first memory cell being located at a first column address and a first row address of the source row based on initiating the management operation. The operation of 810 may be performed according to methods described herein. In some examples, aspects of the operation of 810 may be performed by an error control component such as described with reference to FIG. 7.

[0100] At 815, the memory device may write the data to a second memory cell associated with the target row of the memory device based on performing the error control operation on the data. The operation of 815 may be performed according to methods described herein. In some examples, aspects of the operation of 815 may be performed by an operation manager such as described with reference to FIG.

[0101] At 820, the memory device may determine whether the management operation is complete based on the first column address of the first memory cell. The operation of 820 may be performed according to methods described herein. In some examples, aspects of the operation of 820 may be performed by an operation manager such as described with reference to FIG.

[0102] At 825, the memory device may generate an output signal to perform an error control operation on a third memory cell coupled to the source row based on determining whether the management operation is complete. The operation of 825 may be performed according to methods described herein. In some examples, aspects of the operation of 825 may be performed by an operation manager such as described with reference to FIG.

[0103] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include mechanism, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: initiating a management operation to transfer information from a source row to a target row of a memory device; performing an error control operation on data stored in a first memory cell coupled to the source row of the memory device based on initiating the management operation, the first memory cell being located at a first column address and a first row address of the source row; writing the data to a second memory cell coupled to the target row of the memory device based on performing the error control operation on the data; determining whether the management operation is completed based on the first column address of the first memory cell; and generating an output signal to perform the error control operation on a third memory cell coupled to the source row based on determining whether the management operation is completed.

[0104] In some examples of the methods 800 and apparatus described herein, determining whether the management operation can be completed may include an operation, mechanism, means, or instruction for determining whether the first column address satisfies a threshold associated with the source row.

[0105] Some examples of the method 800 and apparatus described herein may further include operations, mechanisms, means, or instructions for combining one or more bits of the first column address into a value and comparing the value to a threshold associated with the source row, wherein determining whether the first column address satisfies the threshold may be based on comparing the value to the threshold.

[0106] In some examples of the methods 800 and apparatus described herein, performing an error control operation on the data stored in the first memory cell may include operations, mechanisms, means, or instructions for reading the data of the first memory cell, determining an error in the data of the first memory cell, and correcting the error based on determining the error.

[0107] Some examples of the method 800 and apparatus described herein may include operations, mechanisms, means, or instructions for incrementing a column address counter associated with the source row based on generating the output signal, and identifying a second column address of a third memory cell based on incrementing the column address counter.

[0108] Some examples of the method 800 and apparatus described herein may further include an operation, mechanism, means, or instruction for determining that a management operation may be completed based on a third column address associated with the third memory cell.

[0109] In some examples of the methods 800 and apparatus described herein, determining that the management operation can be completed may include an operation, mechanism, means, or instruction for determining that the third column address satisfies a threshold associated with the source row.

[0110] Some examples of the method 800 and apparatus described herein may further include an act, mechanism, means, or instruction for precharging the target row based on determining that the maintenance operation may be completed.

[0111] In some examples of the methods 800 and apparatus described herein, initiating a management operation to transfer information from a source row to a target row may include an operation, mechanism, means, or instruction for generating a write status signal and a global command address signal that includes an index to a command address counter.

[0112] 9 shows a flowchart illustrating one or more methods 900 for supporting error control for a memory device according to examples as disclosed herein. The operations of method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 900 may be performed by a memory device as described with reference to FIG. 7. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0113] At 905, the memory device may read data from a first memory cell into a first sense component as part of a management operation to transfer information from a first section to a second section of the memory device. The operation of 905 may be performed according to methods described herein. In some examples, aspects of the operation of 905 may be performed by an operation manager such as described with reference to FIG. 7.

[0114] At 910, the memory device may transfer data from the first sense component to the error control component. The operations of 910 may be performed according to methods described herein. In some examples, aspects of the operations of 910 may be performed by a sense component manager such as described with reference to FIG. 7.

[0115] At 915, the memory device may perform an error control operation on the data using the error control component based on transferring the data to the error control component. The operation of 915 may be performed according to methods described herein. In some examples, aspects of the operation of 915 may be performed by an error control component such as described with reference to FIG. 7.

[0116] At 920, the memory device may transfer data from the error control component to a second sense component associated with a second section of the memory device. The operations of 920 may be performed according to methods described herein. In some examples, aspects of the operations of 920 may be performed by an error control component such as described with reference to FIG. 7.

[0117] At 925, the memory device may transfer data from the second sense component to second memory cells associated with the second section of the memory device. The operations of 925 may be performed according to methods described herein. In some examples, aspects of the operations of 925 may be performed by a sense component manager such as described with reference to FIG. 7.

[0118] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include mechanisms, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for reading data of a first memory cell into a first sense component as part of a management operation for transferring information from a first section of a memory device to a second section, transferring the data from the first sense component to an error control component, performing an error control operation on the data using the error control component based on transferring the data to the error control component, transferring the data from the error control component to a second sense component associated with the second section of the memory device, and transferring the data from the second sense component to a second memory cell associated with the second section of the memory device.

[0119] Some examples of the method 900 and apparatus described herein may further include an operation, mechanism, means, or instruction for toggling by the error control component between the first sense component of the first section and the second sense component of the second section to transfer a set of data between the first sense component and the second sense component based on transferring the data to the second memory cell.

[0120] Some examples of the method 900 and apparatus described herein may further include an operation, mechanism, means, or instruction for maintaining activation of the first sense component after transferring data from the first sense component to the error control component, and wherein toggling between the first sense component of the first section and the second sense component of the second section may be based on maintaining activation of the first sense component.

[0121] Some examples of the method 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for activating a first sense component of the first section, where reading the data may be based on activating the first sense component, and activating a second sense component of the second section based on performing an error control operation, where transferring the data from the error control component to the second sense component may be based on activating the second sense component.

[0122] In some examples of the methods 900 and devices described herein, the first section includes a first memory cell and the second section includes a second memory cell. In some examples of the methods 900 and devices described herein, the first section includes a first sense component and the second section includes a second sense component.

[0123] Some examples of the methods 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for transferring data from a first sense component to an error control component associated with a first section of the memory device, and for transferring data from the error control component to a second sense component associated with a second section of the memory device.

[0124] Some examples of the methods 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for transferring data from a first memory cell to a first sense component via a first digit line associated with a first section of the memory device, and transferring data from a second sense component to a second memory cell via a second digit line associated with a second section of the memory device.

[0125] Some examples of the method 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for storing a first section address associated with a first sense component in a first latch, where transferring data from the first sense component to the error control component may be based on storing the first section address in the first latch, and storing a second section address associated with a second sense component in a second latch, where transferring data from the error control component to the second sense component may be based on storing the second section address in the second latch.

[0126] It should be noted that the methods described herein are possible implementations, that acts and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more methods may be combined.

[0127] An apparatus is described that may include a memory array including a first section and a second section, and a control component associated with the memory array and configured to cause the apparatus to: perform an error control operation on data stored in a first memory cell coupled to a source row of the memory array based on initiating a management operation, the first memory cell being located at a first column address and a first row address of the source row; write the data to a second memory cell coupled to a target row of the memory array based on performing the error control operation on the data; determine whether the management operation is complete based on the first column address of the first memory cell; and generate an output signal to perform the error control operation on a third memory cell coupled to the source row based on determining whether the management operation is complete.

[0128] Some examples may further include determining whether the first column address satisfies a threshold associated with the source row, and determining whether the management operation can be completed may be based on determining whether the first column address satisfies a threshold associated with the source row.

[0129] Some examples may further include combining one or more bits of the first column address into a value and comparing the value to a threshold associated with the source row, wherein determining whether the first column address satisfies the threshold may be based on comparing the value to the threshold.

[0130] Some examples may further include reading data of a first memory cell, determining an error in the data of the first memory cell, and correcting the error based on determining the error, wherein performing an error control operation on the data stored in the first memory cell may be based on reading the data of the first memory cell, determining an error in the data of the first memory cell, and correcting the error.

[0131] An apparatus is described that may include a memory array including a first section and a second section, and a control component associated with the memory array and configured to cause the apparatus to transfer data from a first sense component to an error control component, perform an error control operation on the data using the error control component based on the transfer of the data to the error control component, transfer the data from the error control component to a second sense component associated with a second section of the memory device, and transfer the data from the second sense component to second memory cells associated with the second section of the memory device.

[0132] Some examples may further include toggling by the error control component between the first sense component of the first section and the second sense component of the second section to transfer a set of data between the first sense component and the second sense component based on transferring the data to the second memory cell.

[0133] Some examples may further include maintaining activation of the first sense component after transferring data from the first sense component to the error control component, and wherein toggling between the first sense component of the first section and the second sense component of the second section may be based on maintaining activation of the first sense component.

[0134] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. While some figures may describe signals as a single signal, it will be understood by those skilled in the art that a signal may represent a bus of signals where the bus may have various bit widths.

[0135] The terms “in electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, or connected, or coupled) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact, or connected, or coupled) may be an open circuit or a closed circuit based on the operation of the devices that include the connected components. The conductive path between connected components may be a direct conductive path between the components, or the conductive path between connected components may be an indirect conductive path that may include intervening components such as switches, transistors, or other components. In some cases, the flow of signals between connected components may be temporarily interrupted using one or more intervening components such as, for example, switches or transistors.

[0136] The term "couple" refers to the transition from an open-circuit relationship between components, where signals are not currently able to communicate between the components across conductive paths, to a closed-circuit relationship between the components, where signals can be communicated between the components across conductive paths. When a component, such as a controller, interconnects other components, it initiates changes that allow signals to flow between the other components across conductive paths that previously did not allow such flow.

[0137] The term "isolated" refers to a relationship between components where signals are not currently allowed to flow between them. Components are isolated from one another if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from one another when the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously allowed signals to flow.

[0138] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) is not necessarily absolute, but is close enough to achieve the benefit of the characteristic.

[0139] As used herein, the term "electrode" may refer to an electrical conductor, which in some instances may be used as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, or conductive layer, etc., that provides a conductive path between elements or components of a memory array.

[0140] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, or gallium nitride. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled through doping using various chemical species, including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0141] The switching components or transistors discussed herein may refer to field-effect transistors (FETs) and may include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage equal to or greater than the transistor's threshold voltage is applied to the transistor's gate. When a voltage less than the threshold voltage of a transistor is applied to the gate of the transistor, the transistor can be turned "off" or "deactivated."

[0142] The description set forth herein with reference to the accompanying drawings illustrates exemplary configurations and does not represent every example that may be implemented or fall within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration," not "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. These techniques may, however, be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the content of the described examples.

[0143] In the accompanying figures, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. When only a first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the second reference label.

[0144] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0145] The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0146] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The mechanism implementing the function may also be physically located in various locations, including being distributed so that portions of the function are implemented in different physical locations. Also, as used in this specification, including the claims, "or" as used in a list of items (e.g., a list of items preceded by a phrase such as "at least one" or "one or more of") refers to an inclusive list, such as, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used in this specification, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" will be interpreted in the same manner as the phrase "based at least in part on."

[0147] Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, and without limitation, computer-readable media may include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disk and disc include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where a disc reproduces data optically with a laser, while a disk typically reproduces data magnetically. Combinations of the above are also included within the scope of computer-readable media.

[0148] The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method in a memory device, comprising: the memory device initiating a management operation to transfer information from a source row to a target row of the memory device; Based at least in part on initiating the management operation, the memory device performs an error control operation on data stored in a first memory cell coupled to the source row of the memory device, the first memory cell being located at a first column address and a first row address of the source row; the memory device writing the data to a second memory cell associated with the target row of the memory device based at least in part on performing the error control operation on the data; and determining, based at least in part on the first column address of the first memory cell, whether the management operation is complete; generating an output signal for performing the error control operation on a third memory cell coupled to the source row based at least in part on determining whether the management operation is completed; A method comprising:

2. The memory device determining whether the management operation has been completed comprises: determining whether the first column address satisfies a threshold associated with the source row; The method of claim 1 , comprising:

3. The memory device combining one or more bits of the first column address into a value; the memory device comparing the value to the threshold associated with the source row, wherein the memory device determining whether the first column address satisfies the threshold is based at least in part on the memory device comparing the value to the threshold. The method of claim 2 further comprising:

4. The memory device performing the error control operation on the data stored in the first memory cell comprises: the memory device reading the data of the first memory cell; the memory device determining an error in the data of the first memory cell; correcting the error based at least in part on determining the error. The method of claim 1 , comprising:

5. The method of claim 1, wherein the memory device increments a column address counter associated with the source row based at least in part on the memory device generating the output signal. the memory device identifying a second column address of the third memory cell based at least in part on the memory device incrementing the column address counter. The method of claim 1 further comprising:

6. determining, based at least in part on a third column address associated with the third memory cell, that the memory device has completed the management operation; The method of claim 1 further comprising:

7. The memory device determining that the management operation is completed comprises: the memory device determining that the third column address satisfies a threshold associated with the source row. The method of claim 6, comprising:

8. The method of claim 7, wherein the memory device precharges the target row based at least in part on the memory device determining that the management operation is complete. The method of claim 6 further comprising:

9. The memory device initiating the management operation to transfer the information from the source row to the target row comprises: the memory device generating a write status signal and a global command address signal including an index to a command address counter; The method of claim 1 , comprising:

10. A method in a memory device, comprising: reading data of a first memory cell into a first sense component as part of a management operation by the memory device to transfer information from a first section to a second section of the memory device; the memory device transferring the data from the first sense component to an error control component; performing, by the memory device, an error control operation on the data using the error control component based at least in part on transferring the data to the error control component; and the memory device transferring the data from the error control component to a second sense component associated with the second section of the memory device; the memory device transferring the data from the second sense component to a second memory cell associated with the second section of the memory device; a counter outputting a column address for a column of a row involved in the management operation, the column address being associated with the data; a latch outputting a control signal indicating an end state of the management operation based at least in part on a signal from a logic gate coupled to the counter, the signal indicating whether the column address output by the counter satisfies a threshold value for the row involved in the management operation; the counter outputs a second column address for a second column of the row to the logic gate based at least in part on the control signal output by the latch indicating that the management operation is incomplete, and second data is transferred from the first section to the second section based at least in part on outputting the second column address. A method comprising:

11. The error control component toggling between the first sense component of the first section and the second sense component of the second section to transfer a plurality of data between the first sense component and the second sense component based at least in part on transferring the data to the second memory cell. The method of claim 10 further comprising:

12. and after transferring the data from the first sense component to the error control component, the memory device maintains activation of the first sense component, and the error control component toggling between the first sense component of the first section and the second sense component of the second section is based at least in part on maintaining the activation of the first sense component. The method of claim 11 further comprising:

13. The method of claim 12, wherein the memory device activates the first sense component of the first section, and the memory device reads the data based at least in part on activating the first sense component; the memory device activating the second sense component of the second section based at least in part on performing the error control operation, and the memory device transferring the data from the error control component to the second sense component based at least in part on the memory device activating the second sense component. The method of claim 10 further comprising:

14. the first section includes the first memory cell; the second section includes the second memory cell; The method of claim 10.

15. the first section includes the first sense component; the second section includes the second sense component; 15. The method of claim 14.

16. The memory device transferring the data from the first sense component to the error control component associated with the first section of the memory device; the memory device transferring the data from the error control component to the second sense component associated with the second section of the memory device. The method of claim 10 further comprising:

17. The method of claim 16, wherein the memory device transfers the data from the first memory cell to the first sense component via a first digit line associated with the first section of the memory device; the memory device transferring the data from the second sense component to the second memory cell via a second digit line associated with the second section of the memory device. The method of claim 10 further comprising:

18. The memory device stores a first section address associated with the first sense component in a second latch, and the transferring of the data from the first sense component to the error control component is based at least in part on storing the first section address in the second latch; the memory device storing a second section address associated with the second sense component in a third latch, and wherein transferring the data from the error control component to the second sense component is based at least in part on storing the second section address in the third latch. The method of claim 10 further comprising:

19. a memory array including a first section and a second section; associated with the memory array; initiating a management operation to transfer information from a source row to a target row of the memory array; performing an error control operation on data stored in a first memory cell associated with the source row of the memory array, the first memory cell located at a first column address and a first row address of the source row, based at least in part on initiating the management operation; writing the data to a second memory cell associated with the target row of the memory array based at least in part on performing the error control operation on the data; and determining whether the managing operation is complete based at least in part on the first column address of the first memory cell; generating an output signal for performing the error control operation on a third memory cell coupled to the source row based at least in part on determining whether the management operation is complete; a control component configured to cause the device to An apparatus comprising:

20. The control component determining whether the first column address satisfies a threshold associated with the source row, and determining whether the management operation is complete is based at least in part on determining whether the first column address satisfies the threshold associated with the source row.

20. The apparatus of claim 19, further configured to cause the apparatus to:

21. The control component associated with the memory array includes: combining one or more bits of the first column address into a value; comparing the value to the threshold associated with the source row, and determining whether the first column address satisfies the threshold based at least in part on comparing the value to the threshold.

21. The apparatus of claim 20, further configured to cause the apparatus to:

22. The control component reading the data in the first memory cell; determining an error in the data of the first memory cell; and correcting the error based at least in part on determining the error, wherein performing the error control operation on the data stored in the first memory cell is based at least in part on reading the data of the first memory cell, determining the error in the data of the first memory cell, and correcting the error.

20. The apparatus of claim 19, further configured to cause the apparatus to:

23. a memory array including a first section and a second section; associated with the memory array; reading data of a first memory cell into a first sense component as part of a management operation to transfer information from the first section to the second section of the memory device; transferring the data from the first sense component to an error control component; performing an error control operation on the data using the error control component based at least in part on forwarding the data to the error control component; transferring the data from the error control component to a second sense component associated with the second section of the memory device; transferring the data from the second sense component to a second memory cell associated with the second section of the memory device; outputting, by a counter, a column address for a column of a row involved in the management operation, the column address being associated with the data; outputting a control signal by a latch indicative of an end state of the management operation based at least in part on a signal from a logic gate coupled to the counter, the signal indicating whether the column address output by the counter satisfies a threshold value for the row involved in the management operation; outputting, by the counter, a second column address for a second column of the row to the logic gate based at least in part on the control signal output by the latch indicating that the management operation is incomplete, and transferring second data from the first section to the second section based at least in part on outputting the second column address. a control component configured to cause the device to An apparatus comprising:

24. The control component associated with the memory device includes: toggling by the error control component between the first sense component of the first section and the second sense component of the second section to transfer a plurality of data between the first sense component and the second sense component based at least in part on transferring the data to the second memory cell.

24. The apparatus of claim 23, further configured to cause the apparatus to:

25. The control component associated with the memory device includes: maintaining activation of the first sense component after transferring the data from the first sense component to the error control component, wherein toggling between the first sense component of the first section and the second sense component of the second section is based at least in part on maintaining the activation of the first sense component.

25. The apparatus of claim 24, further configured to cause the apparatus to:

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