Display device

Abstract

To provide a display device configured to improve moisture permeation characteristics without using a plastic substrate.SOLUTION: A display device includes: a first substrate including an active area having a plurality of sub pixels and a non-active area enclosing the active area, the first substrate comprising one of a transparent conductive oxide or an oxide semiconductor; an inorganic layer provided on the first substrate; a planarization layer provided on the inorganic layer; a second substrate provided on the planarization layer, the second substrate having an end located inside the first substrate; a seal member covering a portion of a top of the second substrate; an adhesive layer provided on the second substrate, the adhesive layer being spaced apart from the seal member; and a back cover bonded to the second substrate through the adhesive layer. Bubbles generated due to a step difference between the second substrate and the seal member are blocked, thereby reducing a crack which may be generated in an inorganic layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device that does not use a plastic substrate, has improved moisture permeability, and has improved rigidity by reducing cracking in an inorganic layer. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, flexible display devices, which are manufactured by forming display elements, wiring, etc. on a flexible substrate such as plastic, which can display images even when folded or rolled, have been attracting attention as next-generation display devices. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that does not use a plastic substrate and has improved moisture permeability.

[0006] Another object of the present invention is to provide a display device that reduces the generation of bubbles in the outer periphery.

[0007] Another object of the present invention is to provide a display device having improved rigidity by reducing cracks in an inorganic layer that occur at the outer periphery of the display device.

[0008] Another object of the present invention is to provide a display device having improved rigidity of an outer casing of the display device.

[0009] Another object of the present invention is to provide a display device that does not use a plastic substrate to improve moisture permeability and that reduces cracks in an inorganic film layer.

[0010] The objects of the present invention are not limited to those mentioned above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0011] To achieve the above object, a display device according to an embodiment of the present invention includes a display area including a plurality of sub-pixels and a non-display area surrounding the display area, and includes a first substrate made of one of a transparent conductive oxide and an oxide semiconductor, an inorganic layer disposed on the first substrate, a planarization layer disposed on the inorganic layer, a second substrate disposed on the planarization layer and having an end positioned inside the first substrate, a sealant disposed to cover a portion of an upper surface of the second substrate, an adhesive layer disposed on the second substrate and spaced apart from the sealant, and a back cover disposed on the adhesive layer and attached to the second substrate by the adhesive layer. As a result, moisture permeability of the display device is improved and cracks in the inorganic layer in the outer periphery area are reduced.

[0012] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0013] The present invention can easily control moisture permeability and improve flexibility by using a transparent conductive oxide layer and an oxide semiconductor layer as a substrate for a display device.

[0014] The present invention can reduce the generation of bubbles that may occur in the outer periphery by adjusting the position of the adhesive layer that bonds the display panel and the back cover.

[0015] The present invention can improve the reliability of a display device by minimizing the generation of bubbles and reducing cracks that may occur in inorganic layers and wirings that may occur in the outer periphery.

[0016] According to the present invention, the adhesive layer that bonds the display panel and the back cover is arranged to be spaced apart from the sealing member and is arranged to completely cover the inorganic layer of the display device, thereby improving the rigidity of the display device.

[0017] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a plan view of a display device according to an embodiment of the present invention; [Figure 2] 1 is a schematic cross-sectional view of a display device according to an embodiment of the present invention; [Figure 3] FIG. 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention. [Figure 4] 1 is an enlarged plan view of one pixel of a display device according to an embodiment of the present invention; [Figure 5] FIG. 5 is a cross-sectional view taken along the line VV′ in FIG. [Figure 6a] FIG. 2 is a cross-sectional view taken along line VIa-VIa' in FIG. [Figure 6b] FIG. 6 is a cross-sectional view taken along line VIb-VIb' of FIG. [Figure 6c] FIG. 6 is a cross-sectional view taken along line VIc-VIc′ of FIG. [Figure 7] FIG. 10 is a plan view of a display device according to another embodiment of the present invention. [Figure 8a] FIG. 8 is a cross-sectional view taken along line VIIIa-VIIIa' in FIG. 7. [Figure 8b]FIG. 8 is a cross-sectional view taken along line VIIIb-VIIIb' in FIG. 7. [Figure 8c] FIG. 8 is a cross-sectional view taken along line VIIIc-VIIIc' in FIG. 7. [Figure 9] FIG. 10 is a plan view of a display device according to still another embodiment of the present invention. [Figure 10a] FIG. 10 is a cross-sectional view taken along the line Xa-Xa′ in FIG. 9. [Figure 10b] FIG. 10 is a cross-sectional view taken along the line Xb-Xb' in FIG. [Figure 10c] FIG. 10 is a cross-sectional view taken along the line Xc-Xc′ of FIG. 9. DETAILED DESCRIPTION OF THE INVENTION

[0019] The advantages and features of the present invention, and the methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. These embodiments are provided solely to ensure that this disclosure will be complete and to fully convey the scope of the invention to those skilled in the art.

[0020] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present invention are illustrative only, and the present invention is not limited to the illustrated details. The same reference symbols refer to the same elements throughout the specification. Furthermore, when describing the present invention, if a detailed description of related prior art is deemed to unnecessarily obscure the gist of the present invention, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in the present invention, other parts may be added unless "only" is used. When a component is expressed in the singular, it also includes the plural unless otherwise explicitly stated.

[0021] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0022] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0023] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0024] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of the present invention.

[0025] Like reference numbers refer to like elements throughout the specification.

[0026] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0027] The features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0028] Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0029] Fig. 1 is a plan view of a display device according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention. For convenience of explanation, Fig. 1 shows only a display panel 120, a plurality of flexible films 140, a plurality of printed circuit boards 150, and a seal member 160 among various components of a display device 100. The display device 100 may include other components in addition to the components shown in the drawing.

[0030] 1 and 2, the back cover 110 is disposed on one side of the display panel 120 to support the display panel 120. The back cover 110 may be formed to be larger than the display panel 120 in plan view, thereby protecting other components of the display device 100 from the outside.

[0031] The back cover 110 is formed of a rigid material, but at least a portion of the back cover 110 may have flexibility so that it can be wound or unwound together with the display panel 120. For example, the back cover 110 may be made of a metal material such as SUS (Steel Use Stainless) or Invar, or a material such as plastic. However, the material of the back cover 110 may be variously changed depending on the design as long as it satisfies physical property conditions such as thermal deformation amount, curvature radius, and rigidity, and is not limited thereto. In one embodiment of the present invention, the back cover 110 is shown as being formed as a single unit, but is not limited thereto, and may be made of multiple back covers to accommodate rolling or folding of the display device 100.

[0032] 2, the back cover 110 includes a plurality of openings 111. When the display panel 120 is wound or unwound, the plurality of openings 111 of the back cover 110 may be deformed by stress applied to the display panel 120. Specifically, when the display panel 120 is wound or unwound, the back cover 110 may be deformed as the plurality of openings 111 contract or expand. Furthermore, as the plurality of openings 111 contract or expand, a slip phenomenon of the display panel 120 disposed on the back cover 110 is reduced, and the stress applied to the display panel 120 may be reduced.

[0033] A plurality of sub-pixels including light-emitting elements for displaying images are arranged on the display panel 120. The display panel 120 may be a flexible display panel 120 that can be wound or unwound onto a roller.

[0034] The display panel 120 includes a display area AA and a non-display area NA.

[0035] The display area AA is an area where an image is displayed. A pixel portion PP consisting of a plurality of sub-pixels may be arranged in the display area AA to display an image. For example, the pixel portion PP may be composed of a plurality of sub-pixels each including a light-emitting element and a driving circuit, and may display an image.

[0036] The non-display area NA is an area where no image is displayed, and is an area where various wirings, driving integrated circuits (ICs), etc. for driving the sub-pixels arranged in the display area AA are arranged. For example, various driving ICs such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0037] Referring to FIG. 2, the display panel 120 includes a first substrate 121, an inorganic layer 122, a planarization layer 123, a bank 124, a pixel portion PP, a (second) adhesive layer 125, and a second substrate 126.

[0038] The first substrate 121 is a support member for supporting other components of the display panel 120. The first substrate 121 may be made of either a transparent conductive oxide or an oxide semiconductor. For example, the first substrate 121 may be made of a transparent conducting oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc.

[0039] The first substrate 121 may be made of an oxide semiconductor material containing indium (In) and gallium (Ga), for example, a transparent oxide semiconductor such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), etc. However, the types of transparent conductive oxides and oxide semiconductors are merely examples, and the first substrate 121 may be made of other transparent conductive oxides and oxide semiconductor materials not described herein, and is not limited thereto.

[0040] Meanwhile, the first substrate 121 may be formed by depositing a transparent conductive oxide or oxide semiconductor to a thickness that is much thinner than that of an existing plastic substrate. Thus, the first substrate 121 may have flexibility due to its very thin thickness. A display device 100 including a flexible first substrate 121 may be configured as a flexible display device 100 that can display images even when folded or rolled. For example, if the display device 100 is a foldable display device, the first substrate 121 may be folded or unfolded around a folding axis. As another example, if the display device 100 is a rollable display device, the display device may be stored rolled up on a roller. Therefore, the display device 100 according to an embodiment of the present invention may be configured as a flexible display device 100 such as a foldable display device or a rollable display device using the flexible first substrate 121.

[0041] Furthermore, the display device 100 according to an embodiment of the present invention may perform an LLO (Laser Lift Off) process using the first substrate 121 formed of a transparent conductive oxide or oxide semiconductor. The LLO process refers to a process of separating the first substrate 121 from a temporary substrate below the first substrate 121 using a laser during the manufacturing process of the display device 100. Therefore, the first substrate 121 may also be referred to as a functional thin film, a functional thin film layer, a functional substrate, etc., since it is a layer for an easier LLO process.

[0042] The first substrate 121 includes a display area AA and a non-display area NA.

[0043] The display area AA is an area where an image is displayed. A pixel portion PP consisting of a plurality of sub-pixels may be arranged in the display area AA to display an image. For example, the pixel portion PP may be composed of a plurality of sub-pixels each including a light-emitting element and a driving circuit, and may display an image.

[0044] The non-display area NA is an area where no image is displayed, and is an area where various wirings, driving ICs, etc. for driving the sub-pixels arranged in the display area AA are arranged. For example, various driving ICs, etc. such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0045] A plurality of flexible films 140 are disposed on one end of the first substrate 121. The plurality of flexible films 140 are electrically connected to one end of the first substrate 121. The plurality of flexible films 140 are films in which various components are disposed on a ductile base film and which supply signals to a plurality of sub-pixels in the display area AA. One end of each of the plurality of flexible films 140 is disposed in the non-display area NA of the first substrate 121 and can supply data voltages, etc. to a plurality of sub-pixels in the display area AA. While FIG. 1 illustrates four flexible films 140, the number of flexible films 140 may vary depending on the design and is not limited thereto.

[0046] Meanwhile, driving ICs such as gate driver ICs and data driver ICs may be disposed on the plurality of flexible films 140. The driving ICs are components that process data for displaying images and driving signals for processing the data. Depending on the mounting method, the driving ICs may be disposed in a chip-on-glass (COG) format, a chip-on-film (COF) format, a tape carrier package (TCP) format, or the like. For the sake of convenience, this specification describes the driving ICs as being mounted on the plurality of flexible films 140 in a chip-on-film format, but the present invention is not limited thereto.

[0047] The printed circuit board 150 is connected to a plurality of flexible films 140. The printed circuit board 150 is a component that supplies signals to the driving IC. Various components may be arranged on the printed circuit board 150 to supply various driving signals, such as driving signals and data voltages, to the driving IC. While FIG. 1 illustrates two printed circuit boards 150, the number of printed circuit boards 150 may be varied according to the design and is not limited thereto.

[0048] 2, an inorganic layer 122 is disposed on a first substrate 121. The inorganic layer 122 may be a plurality of inorganic layers including a lower buffer layer 122a, an upper buffer layer 122b, a gate insulating layer 122c, and a passivation layer 122d, which will be described later. The inorganic layer 122 will be described in detail later with reference to FIGS. 4 to 6c.

[0049] A planarization layer 123 and a bank 124 are disposed on the inorganic layer 122. In particular, the planarization layer 123 may be disposed to surround the top and side surfaces of the inorganic layer 122 in the non-display area NA of the first substrate 121. A more detailed description of the planarization layer 123 and the bank 124 will be provided below with reference to FIGS. 4 to 6c.

[0050] A pixel unit PP is disposed on the inorganic layer 122. The pixel unit PP may be disposed to correspond to the display area AA. The pixel unit PP includes a plurality of sub-pixels to display an image. The sub-pixels of the pixel unit PP are the smallest units constituting the display area AA, and each of the sub-pixels may include a light-emitting element and a driving circuit. For example, the light-emitting element of each of the sub-pixels may include, but is not limited to, an organic light-emitting element including an anode, an organic light-emitting layer, and a cathode, or an LED including N-type and P-type semiconductor layers and a light-emitting layer. The driving circuit for driving the sub-pixels may include, but is not limited to, driving elements such as a thin film transistor and a storage capacitor. For convenience of explanation, the following description will be given assuming that the light-emitting element of each of the sub-pixels is an organic light-emitting element, but is not limited to this.

[0051] Meanwhile, the display device 100 may be configured as a top emission or bottom emission type depending on the direction in which light emitted from the light emitting elements is emitted.

[0052] The top emission type is a type in which light emitted from the light emitting element is emitted from above the first substrate 121 on which the light emitting element is disposed. In the case of the top emission type, a reflective layer may be formed below the anode to direct the light emitted from the light emitting element to above the first substrate 121, i.e., toward the cathode.

[0053] The bottom emission type is a type in which light emitted from the light emitting element is emitted to the bottom of the first substrate 121 on which the light emitting element is disposed. In the bottom emission type, in order to propagate the light emitted from the light emitting element to the bottom of the first substrate 121, the anode may be made of only a transparent conductive material, and the cathode may be made of a metal material with high reflectivity.

[0054] For convenience of explanation, the following description will be given assuming that the display device 100 according to the embodiment of the present invention is a bottom emission type, but the present invention is not limited thereto.

[0055] A (second) adhesive layer 125 is disposed to cover the pixel portion PP. The adhesive layer 125 functions to bond the first substrate 121 and the second substrate 126 and seal the pixel portion PP to protect the light emitting element of the pixel portion PP from external moisture, oxygen, impact, etc. The adhesive layer 125 may be configured in a face seal manner. For example, the adhesive layer 125 may be formed by applying an ultraviolet or heat-curing sealant to the front surface of the pixel portion PP. However, the structure of the adhesive layer 125 may be formed using various methods and materials, and is not limited thereto. As shown in FIG. 2, the end of the second substrate 126 may be inserted from the end of the first substrate 121 so that the end of the first substrate 121 extends through the end of the second substrate 126.

[0056] Meanwhile, second substrate 126, made of a metal material with high elasticity and corrosion resistance, is disposed on adhesive layer 125. For example, second substrate 126 may be made of a material with a high elasticity of approximately 200 to 900 MPa, a highly corrosion-resistant material, or a metal material such as aluminum (Al), nickel (Ni), chromium (Cr), or an alloy of iron (Fe) and nickel, which is easily processed into a foil or thin film. Therefore, by forming second substrate 126 from a metal material, second substrate 126 can be configured in an ultra-thin film form, and strong protection against external impacts and scratches can be provided.

[0057] A polarizer 180 is disposed under the first substrate 121. The polarizer 180 selectively transmits light and can reduce reflection of external light incident on the first substrate 121. Specifically, in the display device 100, various metal materials used for semiconductor elements, wiring, light-emitting elements, etc. are formed on the first substrate 121. Therefore, external light incident on the first substrate 121 side may be reflected from the metal materials, and the reflection of the external light may reduce the visibility of the display device 100. In this case, the polarizer 180 that prevents reflection of external light may be disposed under the first substrate 121 to improve the outdoor visibility of the display device 100. However, the polarizer 180 may be omitted depending on the configuration of the display device 100.

[0058] Meanwhile, although not shown in the drawing, a barrier film may be disposed together with the polarizer 180 under the first substrate 121. The barrier film may protect the pixel portion PP including the light-emitting element by reducing the penetration of moisture and oxygen from outside the first substrate 121 into the first substrate 121. However, the barrier film may be omitted depending on the configuration of the display device 100, and is not limited thereto.

[0059] A (first) adhesive layer 130 for adhering the back cover 110 and the second substrate 126 is disposed on the top of the display panel 120 configured as described above. That is, the adhesive layer 130 is disposed between the second substrate 126 of the display panel 120 and the back cover 110. The adhesive layer 130 may be disposed in front of the display area AA, and an end of the adhesive layer 130 disposed in the non-display area NA may be disposed closer to the display area AA than an end of the inorganic layer 122, in an area of the display panel 120 excluding an area where the flexible films 140 are connected. This prevents bubbles from forming in the adhesive layer 130 due to a step between the second substrate 126 and the sealant 160, thereby preventing cracks from occurring due to the bubbles. Such a step occurs because the height of the top surface of the sealant 160 is higher than the height of the top surface of the second substrate 126. The adhesive layer 130 may be made of an adhesive material, for example, double-sided tape (DS tape). A more detailed description of adhesive layer 130 will be provided in detail below with reference to Figures 6a-6c.

[0060] A sealing member 160 is disposed so as to surround the side surface of the display panel 120. The sealing member 160 is positioned on the upper surface of the bank 124, extending to the end of the non-display area NA, and may be disposed up to a portion of the upper side surface of the second substrate 126 while surrounding the side surface of the pixel portion PP. Thus, the sealing member 160 can reduce moisture penetration into the pixel portion PP through the side surface of the display panel 120.

[0061] The sealing member 160 may be made of an elastic, non-conductive material to seal the sides of the display panel 120 and at the same time complement the side rigidity of the display panel 120. The sealing member 160 may also be made of an adhesive material. The sealing member 160 may further include a moisture absorbent to absorb moisture and oxygen from the outside and reduce moisture penetration through the sides of the display panel 120. For example, the sealing member 160 may be made of, but is not limited to, polyimide (PI), polyurethane, epoxy, or acrylic-based materials.

[0062] In the following, reference will be made to both FIGS. 3 to 6c for a more detailed description of the sub-pixels of the pixel portion PP.

[0063] FIG. 3 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present invention.

[0064] 3, a driving circuit for driving the light emitting elements OLED of the plurality of sub-pixels SP includes a first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC. To drive the driving circuit, a plurality of lines including a gate line GL, a data line DL, a high potential power line VDD, a sensing line SL, and a reference line RL are arranged on a first substrate 121.

[0065] Each of the first transistor TR1, the second transistor TR2 and the third transistor TR3 included in the driving circuit of one sub-pixel SP includes a gate electrode, a source electrode and a drain electrode.

[0066] The first transistor TR1, the second transistor TR2, and the third transistor TR3 may be P-type or N-type thin film transistors. For example, in a P-type thin film transistor, holes flow from the source electrode to the drain electrode, so that a current flows from the source electrode to the drain electrode. In an N-type thin film transistor, electrons flow from the source electrode to the drain electrode, so that a current flows from the drain electrode to the source electrode. In the following description, it is assumed that the first transistor TR1, the second transistor TR2, and the third transistor TR3 are N-type thin film transistors in which a current flows from the drain electrode to the source electrode, but the present invention is not limited thereto.

[0067] The first transistor TR1 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to a first node N1, the first source electrode is connected to an anode of the light-emitting element OLED, and the first drain electrode is connected to a high-potential power line VDD. The first transistor TR1 is turned on when the voltage of the first node N1 is higher than a threshold voltage, and is turned off when the voltage of the first node N1 is lower than the threshold voltage. When the first transistor TR1 is turned on, a driving current is transferred to the light-emitting element OLED through the first transistor TR1. Therefore, the first transistor TR1, which controls the driving current transferred to the light-emitting element OLED, may also be referred to as a driving transistor.

[0068] The second transistor TR2 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the gate line GL, the second source electrode is connected to the first node N1, and the second drain electrode is connected to the data line DL. The second transistor TR2 can be turned on or off based on a gate voltage from the gate line GL. When the second transistor TR2 is turned on, it can charge the data voltage from the data line DL to the first node N1. Therefore, the second transistor TR2, which is turned on or off by the gate line GL, can also be referred to as a switching transistor.

[0069] The third transistor TR3 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the sensing line SL, the third source electrode is connected to the second node N2, and the third drain electrode is connected to the reference line RL. The third transistor TR3 may be turned on or off based on a sensing voltage from the sensing line SL. When the third transistor TR3 is turned on, it may transfer a reference voltage from the reference line RL to the second node N2 and the storage capacitor SC. Therefore, the third transistor TR3 may also be referred to as a sensing transistor.

[0070] Meanwhile, in FIG. 3, the gate line GL and the sensing line SL are shown as separate lines, but the gate line GL and the sensing line SL may be configured as one line and are not limited thereto.

[0071] The storage capacitor SC is connected between the first gate electrode and the first source electrode of the first transistor TR1. That is, the storage capacitor SC may be connected between the first node N1 and the second node N2. The storage capacitor SC may maintain a potential difference between the first gate electrode and the first source electrode of the first transistor TR1 while the light emitting element OLED emits light, thereby supplying a constant driving current to the light emitting element OLED. The storage capacitor SC may include a plurality of capacitor electrodes, and, for example, one of the plurality of capacitor electrodes may be connected to the first node N1 and the other may be connected to the second node N2.

[0072] The light emitting element OLED includes an anode, a light emitting layer, and a cathode. The anode of the light emitting element OLED is connected to the second node N2, and the cathode is connected to the low potential power line VSS. The light emitting element OLED emits light by receiving a driving current from the first transistor TR1.

[0073] Meanwhile, in FIG. 3, the driving circuit of the sub-pixel SP of the display device 100 according to one embodiment of the present invention is described as having a 3T1C structure including three transistors and one storage capacitor SC, but the number and connection relationship of the transistors and storage capacitor SC may be variously changed depending on the design and is not limited thereto.

[0074] FIG. 4 is an enlarged plan view of one pixel of a display device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V' in FIG. 4. FIG. 6a is a cross-sectional view taken along line VIa-VIa' in FIG. 1. FIG. 6b is a cross-sectional view taken along line VIb-VIb' in FIG. 1. FIG. 6c is a cross-sectional view taken along line VIc-VIc' in FIG. 1. FIG. 4 is an enlarged plan view of a red subpixel SPR, a white subpixel SPW, a blue subpixel SPB, and a green subpixel SPG that constitute one pixel disposed in a display area AA of a display panel 120. FIG. 4 shows only the display panel 120, and for ease of explanation, the bank 124 is omitted, and the frames of the multiple color filters CF are indicated by thick solid lines. 4 to 6c, the display device 100 according to an embodiment of the present invention includes a first substrate 121, an inorganic layer 122, a planarization layer 123, a bank 124, a first transistor TR1, a second transistor TR2, a third transistor TR3, a storage capacitor SC, a light emitting element OLED, a gate line GL, a sensing line SL, a data line DL, a reference line RL, a high potential power supply line VDD, a plurality of color filters CF, a display panel 120 including a (second) adhesive layer 125 and a second substrate 126, a back cover 110, a (first) adhesive layer 130, a sealing member 160, and (optionally) a polarizer 180.

[0075] 4, the subpixels SP include a red subpixel SPR, a green subpixel SPG, a blue subpixel SPB, and a white subpixel SPW. For example, the red subpixel SPR, the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG may be sequentially arranged along the row direction. However, the arrangement order of the subpixels SP is not limited thereto.

[0076] Each of the subpixels SP includes a light-emitting region and a circuit region. The light-emitting region is a region that can independently emit light of one color and in which a light-emitting element OLED may be disposed. Specifically, the light-emitting region may be defined as a region in an overlapping region of the color filters CF and the anode AN that is exposed from the bank 124 and through which light emitted from the light-emitting element OLED can travel to the outside. For example, referring to both FIGS. 4 and 5 , the light-emitting region of the red subpixel SPR may be a region in an overlapping region of the red color filter CFR and the anode AN that is exposed from the bank 124, the light-emitting region of the green subpixel SPG may be a region in an overlapping region of the green color filter CFG and the anode AN that is exposed from the bank 124, and the light-emitting region of the blue subpixel SPB may be a region in an overlapping region of the blue color filter CF and the anode AN that is exposed from the bank 124 and emits blue light. In this case, the light-emitting region of the white sub-pixel SPW where a separate color filter CF is not disposed may be a white light-emitting region that emits white light and overlaps with a portion of the anode AN exposed from the bank 124.

[0077] The circuit region is the remaining region excluding the light-emitting region, and may include a driving circuit DP for driving a plurality of light-emitting elements OLED and a plurality of wires for transmitting various signals to the driving circuit DP. The circuit region in which the driving circuit DP, the plurality of wires, and the bank 124 are arranged may be a non-light-emitting region. For example, the circuit region may include the driving circuit DP including a first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC, a plurality of high-potential power supply wires VDD, a plurality of data wires DL, a plurality of reference wires RL, a plurality of gate wires GL, a sensing wire SL, and the bank 124.

[0078] 3 to 6c, an inorganic layer 122 is disposed on a first substrate 121. The inorganic layer 122 may include a plurality of layers made of an inorganic material disposed on the first substrate 121. For example, the inorganic layer 122 may include, but is not limited to, a lower buffer layer 122a, an upper buffer layer 122b, a gate insulating layer 122c, and a passivation layer 122d.

[0079] The inorganic layer 122 may be disposed to expose the outermost region of the first substrate 121 in the non-display area NA. That is, the end of the inorganic layer 122 may be located inside the end of the first substrate 121. That is, the end of the inorganic layer 122 may be inserted from the end of the first substrate 121 so that the end of the first substrate 121 extends through the end of the inorganic layer 122.

[0080] Meanwhile, as described above, when the first substrate 121 is made of either a transparent conductive oxide layer or an oxide semiconductor, the first substrate 121 may be disposed over the entire area of the display device 100 for the LLO process. That is, the first substrate 121 may be disposed over the entire display area AA and non-display area NA of the display device 100.

[0081] 6a to 6c, the inorganic layer 122 of the display device 100 according to an embodiment of the present invention may be disposed up to a reference line R of the non-display area NA so that the outermost region of the first substrate 121 is exposed. Here, the reference line R defines the end point of the inorganic layer 122 and may be located between the second non-display area NA2 and the third non-display area NA3. Therefore, the inorganic layer 122 may be exposed in the outermost region, thereby reducing cracks or moisture penetration through the inorganic layer 122.

[0082] For reference, in the display device 100 according to an embodiment of the present invention, the non-display area NA may include a first non-display area NA1, a second non-display area NA2, a third non-display area NA3, and a fourth non-display area NA4. The first non-display area NA1 is a region extending from an end of the display area AA to an end of a conductive material constituting wiring or the like in the non-display area NA; the second non-display area NA2 is a region extending from an end of the first non-display area NA1 to a reference line R; the third non-display area NA3 is a region extending from the reference line R to an inner end of the seal member 160 disposed on the upper surface of the second substrate 126; and the fourth non-display area NA4 is a region extending from an end of the third non-display area NA3 to an end of the first substrate 121, i.e., the outermost region of the first substrate 121. The first non-display area NA1 may be (at least partially) surrounded by the second non-display area NA2, which may be (at least partially) surrounded by the third non-display area NA3. The fourth non-display area NA4 may be (at least partially) surrounded by the first non-display area NA1, the second non-display area NA2, and the third non-display area NA3.

[0083] A lower buffer layer 122a is disposed on the first substrate 121. The lower buffer layer 122a prevents moisture and / or oxygen that has penetrated from the outside of the first substrate 121 from diffusing. The moisture permeability characteristics of the display panel 120 can be controlled by controlling the thickness and stacking structure of the lower buffer layer 122a. In addition, the lower buffer layer 122a can prevent short circuits from occurring when the first substrate 121, which is made of a transparent conductive oxide or oxide semiconductor, comes into contact with other components such as the pixel unit PP. The lower buffer layer 122a may be made of an inorganic material, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0084] A plurality of high-potential power supply lines VDD, a plurality of data lines DL, a plurality of reference lines RL, and a light-shielding layer LS are disposed on the lower buffer layer 122a.

[0085] The plurality of high potential power supply lines VDD, the plurality of data lines DL, the plurality of reference lines RL, and the light-shielding layer LS may be disposed in the same layer on the first substrate 121 and may be made of the same conductive material. For example, the plurality of high potential power supply lines VDD, the plurality of data lines DL, the plurality of reference lines RL, and the light-shielding layer LS may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0086] The plurality of high-potential power supply lines VDD are lines that transmit a high-potential power supply voltage to each of the plurality of subpixels SP. The plurality of high-potential power supply lines VDD may extend in the column direction between the plurality of subpixels SP, and two adjacent subpixels SP in the row direction may share one of the plurality of high-potential power supply lines VDD. For example, one high-potential power supply line VDD may be disposed to the left of the red subpixel SPR and may supply a high-potential power supply voltage to the first transistor TR1 of each of the red subpixel SPR and the white subpixel SPW. Another high-potential power supply line VDD may be disposed to the right of the green subpixel SPG and may supply a high-potential power supply voltage to the first transistor TR1 of each of the blue subpixel SPB and the green subpixel SPG. Referring to FIG. 6c, the ends of the plurality of high-potential power supply lines VDD may be located at the end of the first non-display area NA1 and the start of the second non-display area NA2.

[0087] The data lines DL extend in the column direction between the subpixels SP and transmit data voltages to each of the subpixels SP. The data lines DL include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. The first data line DL1 is disposed between the red subpixel SPR and the white subpixel SPW and can transmit a data voltage to the second transistor TR2 of the red subpixel SPR. The second data line DL2 is disposed between the first data line DL1 and the white subpixel SPW and can transmit a data voltage to the second transistor TR2 of the white subpixel SPW. The third data line DL3 is disposed between the blue subpixel SPB and the green subpixel SPG and can transmit a data voltage to the second transistor TR2 of the blue subpixel SPB. The fourth data line DL4 is disposed between the third data line DL3 and the green subpixel SPG and can transmit a data voltage to the second transistor TR2 of the green subpixel SPG.

[0088] The reference line RL extends in the column direction between the subpixels SP and transmits a reference voltage to each of the subpixels SP. The subpixels SP constituting one pixel can share one reference line RL. For example, one reference line RL is disposed between the white subpixel SPW and the blue subpixel SPB and can transmit a reference voltage to the third transistors TR3 of the red subpixel SPR, the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG.

[0089] 4 and 5, a light-shielding layer LS is disposed on the lower buffer layer 122a. The light-shielding layer LS is disposed to overlap the first active layer ACT1 of at least the first transistor TR1 among the plurality of transistors TR1, TR2, and TR3, and can block light incident on the first active layer ACT1. If light is irradiated onto the first active layer ACT1, leakage current may occur, which may reduce the reliability of the first transistor TR1, which is a driving transistor. In this case, if the light-shielding layer LS is made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, and is disposed to overlap the first active layer ACT1, it can block light incident on the first active layer ACT1 from below the first substrate 121, thereby improving the reliability of the first transistor TR1. However, the light-shielding layer LS is not limited thereto, and may also be disposed to overlap the second active layer ACT2 of the second transistor TR2 and the third active layer ACT3 of the third transistor TR3.

[0090] Although the light-shielding layer LS is shown as a single layer in the drawings, the light-shielding layer LS may be formed of multiple layers. For example, the light-shielding layer LS may be formed of multiple layers arranged to overlap each other with at least one of the inorganic layers 122 sandwiched therebetween, i.e., the lower buffer layer 122a, the upper buffer layer 122b, the gate insulating layer 122c, and the passivation layer 122d.

[0091] An upper buffer layer 122b is disposed on the plurality of high-potential power supply lines VDD, the plurality of data lines DL, the plurality of reference lines RL, and the light-shielding layer LS. The upper buffer layer 122b can reduce the penetration of moisture or impurities through the first substrate 121. For example, the upper buffer layer 122b can be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Furthermore, the upper buffer layer 122b can be omitted depending on the type of first substrate 121 and the type of transistor, but is not limited thereto.

[0092] In each of the sub-pixels SP, a first transistor TR1, a second transistor TR2, a third transistor TR3, and a storage capacitor SC are disposed on the upper buffer layer 122b.

[0093] First, the first transistor TR1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0094] The first active layer ACT1 is disposed on the upper buffer layer 122b. The first active layer ACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, if the first active layer ACT1 is made of an oxide semiconductor, the first active layer ACT1 may include a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0095] A gate insulating layer 122c is disposed on the first active layer ACT1. The gate insulating layer 122c is a layer for insulating the first gate electrode GE1 from the first active layer ACT1 and may be made of an insulating material. For example, the gate insulating layer 122c may be made of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0096] A first gate electrode GE1 is disposed on the gate insulating layer 122c to overlap the first active layer ACT1. The first gate electrode GE1 may be made of a conductive material such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0097] A first source electrode SE1 and a first drain electrode DE1 are disposed on the gate insulating layer 122c and spaced apart from each other. The first source electrode SE1 and the first drain electrode DE1 may be electrically connected to the first active layer ACT1 through contact holes formed in the gate insulating layer 122c. The first source electrode SE1 and the first drain electrode DE1 may be disposed in the same layer as the first gate electrode GE1 and may be formed of the same conductive material, but are not limited thereto. For example, the first source electrode SE1 and the first drain electrode DE1 may be formed of, but are not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0098] The first drain electrodes DE1 are electrically connected to the high potential power line VDD. For example, the first drain electrodes DE1 of the red subpixel SPR and the white subpixel SPW may be electrically connected to the high potential power line VDD on the left side of the red subpixel SPR. The first drain electrodes DE1 of the blue subpixel SPB and the green subpixel SPG may be electrically connected to the high potential power line VDD on the right side of the green subpixel SPG.

[0099] In this case, an auxiliary high potential power line VDDa may be further disposed to electrically connect the first drain electrode DE1 to the high potential power line VDD. One end of the auxiliary high potential power line VDDa may be electrically connected to the high potential power line VDD and the other end may be electrically connected to the first drain electrodes DE1 of the plurality of subpixels SP. For example, if the auxiliary high potential power line VDDa is made of the same material and in the same layer as the first drain electrode DE1, one end of the auxiliary high potential power line VDDa may be electrically connected to the high potential power line VDD through contact holes formed in the gate insulating layer 122c and the upper buffer layer 122b, and the other end of the auxiliary high potential power line VDDa may extend toward the first drain electrode DE1 and be integrated with the first drain electrode DE1.

[0100] In this case, the first drain electrode DE1 of the red subpixel SPR and the first drain electrode DE1 of the white subpixel SPW, which are electrically connected to the same high potential power line VDD, may be connected to the same auxiliary high potential power line VDDa, and the first drain electrode DE1 of the blue subpixel SPB and the first drain electrode DE1 of the green subpixel SPG may also be connected to the same auxiliary high potential power line VDDa, but the first drain electrode DE1 and the high potential power line VDD may be electrically connected in other ways and are not limited thereto.

[0101] The first source electrode SE1 may be electrically connected to the light-shielding layer LS through a contact hole formed in the gate insulating layer 122c and the upper buffer layer 122b. Furthermore, a portion of the first active layer ACT1 connected to the first source electrode SE1 may be electrically connected to the light-shielding layer LS through a contact hole formed in the upper buffer layer 122b. If the light-shielding layer LS is floating, the threshold voltage of the first transistor TR1 may fluctuate, which may affect the operation of the display panel 120. Therefore, by electrically connecting the light-shielding layer LS to the first source electrode SE1, a voltage can be applied to the light-shielding layer LS without affecting the operation of the first transistor TR1. Although both the first active layer ACT1 and the first source electrode SE1 have been described herein as being in contact with the light-shielding layer LS, the present invention is not limited thereto and may include a direct contact between only one of the first source electrode SE1 and the first active layer ACT1 and the light-shielding layer LS.

[0102] Meanwhile, although FIG. 5 shows the gate insulating layer 122c formed on the front surface of the first substrate 121, the gate insulating layer 122c may be patterned to overlap only the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1, and is not limited thereto.

[0103] The second transistor TR2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0104] The second active layer ACT2 is disposed on the upper buffer layer 122b. The second active layer ACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, if the second active layer ACT2 is made of an oxide semiconductor, the second active layer ACT2 may include a channel region, a source region, and a drain region. The source region and the drain region may be conductive regions, but are not limited to this.

[0105] A second source electrode SE2 is disposed on the upper buffer layer 122b. The second source electrode SE2 may be integrated with the second active layer ACT2 and electrically connected to them. For example, a semiconductor material may be formed on the upper buffer layer 122b, and a portion of the semiconductor material may be converted into a conductor to form the second source electrode SE2. The portion of the semiconductor material that is not converted into a conductor may then become the second active layer ACT2, and the portion that is converted into a conductor may become the second source electrode SE2. However, the second active layer ACT2 and the second source electrode SE2 may also be formed separately and are not limited thereto.

[0106] The second source electrode SE2 is electrically connected to the first gate electrode GE1 of the first transistor TR1 through a contact hole formed on the gate insulating layer 122c, and the first transistor TR1 can be turned on or off by a signal from the second transistor TR2.

[0107] A gate insulating layer 122c is disposed on the second active layer ACT2 and the second source electrode SE2, and a second drain electrode DE2 and a second gate electrode GE2 are disposed on the gate insulating layer 122c.

[0108] A second gate electrode GE2 is disposed on the gate insulating layer 122c to overlap the second active layer ACT2. The second gate electrode GE2 may be electrically connected to the gate line GL, and the second transistor TR2 may be turned on or off based on a gate voltage applied to the second gate electrode GE2. The second gate electrode GE2 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0109] Meanwhile, the second gate electrode GE2 may extend from the gate line GL. That is, the second gate electrode GE2 may be integrated with the gate line GL, and the second gate electrode GE2 and the gate line GL may be formed of the same conductive material. For example, the gate line GL may be made of, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0110] The gate line GL is a line that transmits a gate voltage to each of the plurality of subpixels SP and can extend in the row direction across the circuit regions of the plurality of subpixels SP. The gate line GL is arranged extending in the row direction and can intersect with the plurality of high-potential power supply lines VDD, the plurality of data lines DL, and the plurality of reference lines RL that extend in the column direction.

[0111] A second drain electrode DE2 is disposed on the gate insulating layer 122c. The second drain electrode DE2 may be electrically connected to the second active layer ACT2 through a contact hole formed in the gate insulating layer 122c and to one of the plurality of data lines DL through a contact hole formed in the gate insulating layer 122c and the upper buffer layer 122b. For example, the second drain electrode DE2 of the red subpixel SPR may be electrically connected to the first data line DL1, and the second drain electrode DE2 of the white subpixel SPW may be electrically connected to the second data line DL2. For example, the second drain electrode DE2 of the blue subpixel SPB may be electrically connected to the third data line DL3, and the second drain electrode DE2 of the green subpixel SPG may be electrically connected to the fourth data line DL4. The second drain electrode DE2 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. The third transistor TR3 includes a third active layer ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0112] The third active layer ACT3 is disposed on the upper buffer layer 122b. The third active layer ACT3 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon. For example, if the third active layer ACT3 is made of an oxide semiconductor, the third active layer ACT3 may include a channel region, a source region, and a drain region, and the source region and the drain region may be conductive regions, but are not limited to this.

[0113] A gate insulating layer 122c is disposed on the third active layer ACT3, and a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3 are disposed on the gate insulating layer 122c.

[0114] A third gate electrode GE3 is disposed on the gate insulating layer 122c to overlap the third active layer ACT3. The third gate electrode GE3 may be electrically connected to the sensing line SL, and the third transistor TR3 may be turned on or off based on a sensing voltage transmitted to the third transistor TR3. The third gate electrode GE3 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0115] Meanwhile, the third gate electrode GE3 may extend from the sensing line SL. That is, the third gate electrode GE3 may be integrated with the sensing line SL, and the third gate electrode GE3 and the sensing line SL may be formed of the same conductive material. For example, the sensing line SL may be made of, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0116] The sensing line SL is a line that transmits a sensing voltage to each of the sub-pixels SP and extends in the row direction between the sub-pixels SP. For example, the sensing line SL may be extended in the row direction at the boundaries between the sub-pixels SP and intersect with the high potential power supply lines VDD, the data lines DL, and the reference lines RL that extend in the column direction.

[0117] The third source electrode SE3 may be electrically connected to the third active layer ACT3 through a contact hole formed in the gate insulating layer 122c. The third source electrode SE3 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0118] Meanwhile, a portion of the third active layer ACT3 in contact with the third source electrode SE3 may be electrically connected to the light-shielding layer LS through a contact hole formed in the upper buffer layer 122b. That is, the third source electrode SE3 may be electrically connected to the light-shielding layer LS across the third active layer ACT3. Therefore, the third source electrode SE3 and the first source electrode SE1 may be electrically connected to each other through the light-shielding layer LS.

[0119] The third drain electrode DE3 may be electrically connected to the third active layer ACT3 through a contact hole formed in the gate insulating layer 122c. The third drain electrode DE3 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0120] The third drain electrode DE3 may be electrically connected to a reference line RL. For example, the third drain electrodes DE3 of the red subpixel SPR, the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG constituting one pixel may be electrically connected to the same reference line RL. That is, multiple subpixels SP constituting one pixel may share one reference line RL.

[0121] In this case, an auxiliary reference line RLa may be disposed to transmit the reference line RL extending in the column direction to the subpixels SP arranged side by side in the row direction. The auxiliary reference line Rla may extend in the row direction and electrically connect the reference line RL to the third drain electrodes DE3 of the subpixels SP. One end of the auxiliary reference line Rla may be electrically connected to the reference line RL through contact holes formed in the upper buffer layer 122b and the gate insulating layer 122c. The other end of the auxiliary reference line Rla may be electrically connected to the third drain electrodes DE3 of the subpixels SP. In this case, the auxiliary reference line Rla may be integrated with the third drain electrodes DE3 of the subpixels SP, and a reference voltage from the reference line RL may be transmitted to the third drain electrodes DE3 through the auxiliary reference line Rla. However, the auxiliary reference line Rla may be formed separately from the third drain electrodes DE3 and is not limited thereto.

[0122] A storage capacitor SC is disposed in the circuit region of the plurality of sub-pixels SP. The storage capacitor SC stores a voltage between the first gate electrode GE1 and the first source electrode SE1 of the first transistor TR1 so that the light emitting element OLED maintains the same state during one frame. The storage capacitor SC includes a first capacitor electrode SC1 and a second capacitor electrode SC2.

[0123] In each of the plurality of subpixels SP, a first capacitor electrode SC1 is disposed between the lower buffer layer 122a and the upper buffer layer 122b. The first capacitor electrode SC1 may be disposed closest to the first substrate 121 among the conductive components disposed on the first substrate 121. The first capacitor electrode SC1 may be integrated with the light-shielding layer LS and may be electrically connected to the first source electrode SE1 through the light-shielding layer LS.

[0124] An upper buffer layer 122b is disposed on the first capacitor electrode SC1, and a second capacitor electrode SC2 is disposed on the upper buffer layer 122b. The second capacitor electrode SC2 may be disposed to overlap the first capacitor electrode SC1. The second capacitor electrode SC2 may be integrated with the second source electrode SE2 and electrically connected to the first gate electrode GE1. For example, a semiconductor material may be formed on the upper buffer layer 122b, and a portion of the semiconductor material may be conductive to form the second source electrode SE2 and the second capacitor electrode SC2. Therefore, the portion of the semiconductor material that is not conductive functions as the second active layer ACT2, and the portion that is conductive functions as the second source electrode SE2 and the second capacitor electrode SC2. As described above, the first gate electrode GE1 is electrically connected to the second source electrode SE2 through a contact hole formed in the gate insulating layer 122c. Therefore, the second capacitor electrode SC2 may be integral with the second source electrode SE2 and electrically connected to the second source electrode SE2 and the first gate electrode GE1.

[0125] In summary, the first capacitor electrode SC1 of the storage capacitor SC may be integrated with the light-shielding layer LS and electrically connected to the light-shielding layer LS, the first source electrode SE1, and the third source electrode SE3. The second capacitor electrode SC2 is the second source electrode SE2, which may be integrated with the second active layer ACT2 and electrically connected to the second source electrode SE2 and the first gate electrode GE1. Therefore, the first capacitor electrode SC1 and the second capacitor electrode SC2, which overlap with each other with the upper buffer layer 122b interposed therebetween, can maintain a constant voltage across the first gate electrode GE1 and the first source electrode SE1 of the first transistor TR1 while the light-emitting element OLED emits light, thereby maintaining the light-emitting element OLED in a constant state.

[0126] 6a and 6b, a low potential power supply line VSS and a gate driver GD (eg, a conductive element) may be disposed on the gate insulating layer 122c in the non-display area NA.

[0127] 6a, the low potential power supply line VSS may be electrically connected to the cathode CA to supply a low potential voltage to the cathode CA. That is, the low potential power supply line VSS may be electrically connected to the cathode CA through a connection electrode CE that is formed when the anode AN is formed. An end of the low potential power supply line VSS may be located at the boundary between the first non-display area NA1 and the second non-display area NA2.

[0128] Referring to FIG. 6b, a gate driver GD is disposed in the non-display area NA, and the gate driver GD includes a clock line CLK and a stage ST.

[0129] The clock line CLK can transmit a clock signal to the stage ST. The four clock lines CLK as shown in Figure 6b can transmit at least one clock signal having a different phase to the stage ST. In this case, of the four clock lines CLK, the clock line arranged closest to the end of the first substrate 121 may be the boundary between the first non-display area NA1 and the second non-display area NA2. Although Figure 6b shows four clock lines CLK being used, the number of clock lines CLK is not limited to this.

[0130] The stage ST is disposed between the display area AA and the clock wiring CLK, and can output a scan signal in response to the drive signal. Although the stage ST is shown as a single conductive layer in Figure 6b, this is for convenience of explanation only, and the stage ST may be composed of various transistors and / or capacitors.

[0131] 6c, high-potential power supply wiring VDD is arranged in the non-display area NA. Ends of the high-potential power supply wiring VDD may be at the boundary between the first non-display area NA1 and the second non-display area NA2.

[0132] A passivation layer 122d is disposed on the first transistor TR1, the second transistor TR2, the third transistor TR3, and the storage capacitor SC in the display area AA, and on the low-potential power supply line VSS, the high-potential power supply line VDD, and the gate driver GD in the non-display area NA. The passivation layer 122d is an insulating layer for protecting the components below the passivation layer 122d. For example, the passivation layer 122d may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. The passivation layer 122d may also be omitted depending on the embodiment.

[0133] A plurality of color filters CF are disposed on the passivation layer 122d in the light-emitting regions of the sub-pixels SP. As described above, the display device 100 according to an embodiment of the present invention is a bottom emission type in which light emitted from the light-emitting element OLED is directed toward the bottom of the light-emitting element OLED and the first substrate 121, so a plurality of color filters CF may be disposed below the light-emitting element OLED. The light emitted from the light-emitting element OLED passes through the plurality of color filters CF and may be configured into light of various colors.

[0134] The plurality of color filters CF include a red color filter CFR, a blue color filter CFB, and a green color filter CFG. The red color filter CFR may be disposed in an emitting region of a red subpixel SPR among the plurality of subpixels SP, the blue color filter CFB may be disposed in an emitting region of a blue subpixel SPB, and the green color filter CFG may be disposed in an emitting region of a green subpixel SPG.

[0135] A planarization layer 123 is disposed on the passivation layer 122d and the plurality of color filters CF.

[0136] The planarization layer 123 is an insulating layer that planarizes the upper surface of the first substrate 121 on which the first transistor TR1, the second transistor TR2, the third transistor TR3, the storage capacitor SC, the plurality of high potential power supply lines VDD, the plurality of data lines DL, the plurality of reference lines RL, the plurality of gate lines GL, and the plurality of sensing lines SL are arranged. The planarization layer 123 may be arranged on the front surface of the first substrate 121. That is, the planarization layer 123 may be arranged not only in the display area AA but also up to the end of the first substrate 121 while surrounding the end of the inorganic layer 122 located in the non-display area NA. Therefore, in the display device 100 according to an embodiment of the present invention, the planarization layer 123 is arranged to cover the end of the inorganic layer 122, thereby reducing damage to the inorganic layer 122.

[0137] A light-emitting element OLED is disposed in the light-emitting region of each of the sub-pixels SP. The light-emitting element OLED is disposed on the planarization layer 123 of each of the sub-pixels SP. The light-emitting element OLED includes an anode AN, an emitting layer EL, and a cathode CA.

[0138] An anode AN is disposed on the planarization layer 123 in the light-emitting region. The anode AN supplies holes to the light-emitting layer EL and is therefore made of a conductive material with a high work function. The anode AN may be formed of a transparent conductive material such as, but not limited to, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0139] Meanwhile, the anode AN may extend toward the circuit region. A portion of the anode AN may extend from the light-emitting region toward the first source electrode SE1 in the circuit region and be electrically connected to the first source electrode SE1 through a contact hole formed in the planarization layer 123 and the passivation layer 122d. Thus, the anode AN of the light-emitting element OLED may extend toward the circuit region and be electrically connected to the first source electrode SE1 of the first transistor TR1 and the second capacitor electrode SC2 of the storage capacitor SC.

[0140] An emitting layer EL is disposed on the anode AN in the emitting region and the circuit region. The emitting layer EL may be formed as a single layer across the plurality of subpixels SP. That is, the emitting layers EL of the plurality of subpixels SP may be connected to each other to form an integrated structure. The emitting layer EL may be composed of a single emitting layer, or may have a structure in which a plurality of emitting layers emitting light of different colors are stacked. The emitting layer EL may further include organic layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0141] A cathode CA is disposed on the light-emitting layer EL in the light-emitting region and the circuit region. The cathode CA supplies electrons to the light-emitting layer EL and may be made of a conductive material with a low work function. The cathode CA may be formed as a single layer across the plurality of subpixels SP. That is, the cathodes CA of the plurality of subpixels SP may be connected to each other and integrated. The cathode CA may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an ytterbium (Yb) alloy, and may further include a metal doping layer, but is not limited thereto.

[0142] Banks 124 are disposed on the planarization layer 123 and the anode AN. That is, the banks 124 are disposed in front of the display area AA and the non-display area NA of the first substrate 121. In the display area AA, the banks 124 are disposed between the anode AN and the light-emitting layer EL so as to cover the edge of the anode AN. The banks 124 are disposed at the boundaries between adjacent sub-pixels SP to reduce color mixing of light emitted from the light-emitting elements OLED of the sub-pixels SP. In the non-display area NA, the banks 124 may extend from the display area AA and be disposed on the planarization layer 123. The banks 124 may be made of an insulating material, for example, but not limited to, polyimide.

[0143] A cathode CA may be disposed on the bank 124, and an adhesion layer 125 may be disposed on the cathode CA.

[0144] The second substrate 126 is disposed on the adhesive layer 125. The second substrate 126, together with the adhesive layer 125, can protect the light-emitting element OLED from external moisture, oxygen, and impact. For example, the second substrate 126 can be made of a material having a high elastic modulus of about 200 to 900 MPa, and can be made of a metal material such as aluminum (Al), nickel (Ni), chromium (Cr), or an alloy of iron (Fe) and nickel, which has strong corrosion resistance and can be easily processed into a foil or thin film. By forming the second substrate 126 from a metal material, it can be configured into an ultra-thin film and can provide strong protection against external impacts and scratches.

[0145] The second substrate 126 is arranged not to overlap the front surface of the first substrate 121 but to cover a portion of the non-display area NA. In this case, the second substrate 126 may be arranged to protrude outward from the adhesive layer 125.

[0146] On the second substrate 126, a (first) adhesive layer 130 for attaching the back cover 110 is disposed.

[0147] Generally, in conventional technology, an adhesive layer for bonding the display panel and back cover is disposed on the front surface of the display device. That is, an adhesive layer is disposed not only on the front surface of the second substrate but also on the front surface of the upper surface of the sealing member. The back cover is disposed on the adhesive layer disposed in this manner to bond the display panel and back cover, and then a polarizer is disposed below the display panel to manufacture the display device. Here, as described above, because the sealing member is disposed to cover a portion of the upper surface of the second substrate, a step occurs between the sealing member and the second substrate.

[0148] When adhesive layers are formed on the front surface of the upper sealant and the front surface of the second substrate, air bubbles can form due to the difference in level between the sealant and the second substrate, causing cracks. More specifically, after the upper surface of the display panel and the back cover are attached with the adhesive layer, a polarizer is attached to the lower surface of the display panel using a roller lamination method. However, air bubbles formed due to the difference in level between the sealant and the second substrate can affect the inorganic layers of the display panel, i.e., the lower buffer layer, upper buffer layer, gate insulating layer, and passivation layer, causing cracks in the inorganic layers. However, because a conductive adhesive layer (ACF) is disposed in the area where the display panel and multiple flexible films are connected, the conductive adhesive layer acts to fix the inorganic layer. Therefore, cracks do not occur even when an adhesive layer is disposed on the front surface in the area where the display panel and multiple flexible films are connected.

[0149] 6A to 6C, in the display device 100 according to an embodiment of the present invention, the adhesive layer 130, which bonds the display panel 120 and the back cover 110, is disposed apart from the sealing member 160 except for an area where the flexible films 140 are connected to the display panel 120. That is, the adhesive layer 130 does not overlap the sealing member 160. An end of the adhesive layer 130 may be located between the second non-display area NA2 and the reference line R in the non-display area NA. More specifically, the end of the adhesive layer 130 may be located between the ends of the low voltage wiring VSS, the gate driver GD, and the high voltage wiring VDD and the end of the inorganic layer 122 in the non-display area NA. That is, the adhesive layer 130 may be disposed to cover the conductive material disposed on the inorganic layer 122. That is, the end of the adhesive layer 130 may be inserted from the end of the inorganic layer 122 so as to extend through any one end of the high voltage wiring, the low voltage wiring, and the gate driver.

[0150] As such, in the display device 100 according to one embodiment of the present invention, the adhesive layer 130 that bonds the display panel 120 and the back cover 110 is positioned at a certain distance from the sealing member 160, thereby preventing the generation of bubbles due to the step between the sealing member 160 and the second substrate 126 and reducing the occurrence of cracks due to the bubbles.

[0151] In addition, in the display device 100 according to one embodiment of the present invention, the adhesive layer 130 is arranged to be spaced apart from the sealing member 160, and the adhesive layer 130 covers (e.g., overlaps) the ends of the conductive material arranged on the inorganic layer 122, i.e., the low-potential power wiring VSS, the gate driver GD, and the high-potential power wiring VDD, so that the ends of the adhesive layer 130 are positioned beyond the ends of the conductive material, thereby reducing the possibility of cracks occurring in wiring, etc. formed of conductive material.

[0152] Furthermore, in the display device 100 according to an embodiment of the present invention, the first substrate 121 may be formed of either a transparent conductive oxide or an oxide semiconductor, thereby reducing the thickness of the display device 100. Conventionally, plastic substrates have been primarily used as display device substrates. However, plastic substrates are formed by coating and curing a substrate material at high temperatures, which takes a long time and makes it difficult to form a substrate thin enough to a certain thickness. In contrast, transparent conductive oxides and oxide semiconductors can be formed to a very thin thickness through a deposition process such as sputtering. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 121, which supports various components of the display panel 120, is formed of a transparent conductive oxide layer or an oxide semiconductor layer, thereby reducing the thickness of the display device 100 and achieving a slim design.

[0153] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of a transparent conductive oxide or an oxide semiconductor, thereby improving the flexibility of the display device 100 and reducing stress generated when the display device 100 is deformed. Specifically, when the first substrate 121 is formed of a transparent conductive oxide layer or an oxide semiconductor, the first substrate 121 can be formed as a very thin film. In this case, the first substrate 121 may also be referred to as a first transparent thin film layer. Therefore, the display device 100 including the first substrate 121 has high flexibility and can be easily bent or rolled. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of either a transparent conductive oxide layer or an oxide semiconductor layer, thereby improving the flexibility of the display device 100 and reducing stress generated when the display device 100 is deformed, thereby reducing the occurrence of cracks, etc. in the display device 100.

[0154] Furthermore, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of either a transparent conductive oxide layer or an oxide semiconductor layer, thereby reducing the possibility of static electricity generation in the first substrate 121. If the first substrate 121 were made of plastic and static electricity were generated, the static electricity could damage various wiring and driving elements on the first substrate 121 or affect driving, thereby reducing display quality. Instead, if the first substrate 121 is formed of a transparent conductive oxide layer or an oxide semiconductor layer, the generation of static electricity in the first substrate 121 can be reduced, and the configuration for blocking and discharging static electricity can be simplified. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of either a transparent conductive oxide layer or an oxide semiconductor layer, which are less likely to generate static electricity, thereby reducing damage and degradation of display quality due to static electricity.

[0155] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of one of a transparent conductive oxide and an oxide semiconductor, thereby reducing the penetration of external moisture, oxygen, etc. into the display device 100 through the first substrate 121. When the first substrate 121 is formed of a transparent conductive oxide layer or an oxide semiconductor, the first substrate 121 is formed in a vacuum environment, which significantly reduces the possibility of foreign matter being generated. Furthermore, even if foreign matter is generated, the size of the foreign matter is very small, thereby reducing the penetration of moisture and oxygen into the display device 100. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of a transparent conductive oxide or an oxide semiconductor that is less likely to generate foreign matter and has excellent moisture permeability, thereby improving the reliability of the light emitting device OLED including the organic layer and the display device 100.

[0156] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 121 may be formed of either a transparent conductive oxide or an oxide semiconductor, and a thin, inexpensive barrier film may be attached to the lower surface of the first substrate 121. If the first substrate 121 is made of a material with low moisture permeability, such as plastic, a thick, expensive, high-performance barrier film may be attached to enhance the moisture permeability. However, in the display device 100 according to an embodiment of the present invention, the first substrate 121 is formed of either a transparent conductive oxide or an oxide semiconductor with excellent moisture permeability, and therefore a thin, inexpensive barrier film may be attached to the lower surface of the first substrate 121. Therefore, in the display device 100 according to an embodiment of the present invention, the first substrate 121 may be formed of either a transparent conductive oxide or an oxide semiconductor with excellent moisture permeability, thereby reducing the manufacturing cost of the display device.

[0157] In addition, in the display device 100 according to an embodiment of the present invention, the first substrate 121 may be formed of either a transparent conductive oxide or an oxide semiconductor, and an LLO (Laser Lift Off) process may be performed. During the manufacturing of the display device 100, a temporary substrate having a sacrificial layer formed thereon may be attached below the first substrate 121, and then the pixel unit PP may be formed on the first substrate 121. The sacrificial layer may be, for example, hydrogenated amorphous silicon or amorphous silicon that has been hydrogenated and doped with impurities. After the manufacturing of the display device 100 is completed, a laser may be irradiated from below the temporary substrate to dehydrogenate the hydrogen in the sacrificial layer, thereby separating the sacrificial layer and the temporary substrate from the first substrate 121. Here, transparent conductive oxides and oxide semiconductors are materials that can be subjected to the LLO process with the sacrificial layer and the temporary substrate. Therefore, even if the first substrate 121 is formed of either a transparent conductive oxide or an oxide semiconductor, the first substrate 121 and the temporary substrate may be easily separated. Therefore, in the display device 100 according to one embodiment of the present invention, the first substrate 121 is composed of one of a transparent conductive oxide layer or an oxide semiconductor that can be subjected to the LLO process, so that the display device 100 can be easily manufactured using existing processes and equipment.

[0158] Figure 7 is a plan view of a display device according to another embodiment of the present invention. Figure 8a is a cross-sectional view taken along line VIIIa-VIIIa' in Figure 7. Figure 8b is a cross-sectional view taken along line VIIIb-VIIIb' in Figure 7. Figure 8c is a cross-sectional view taken along line VIIIc-VIIIc' in Figure 7. The display device 700 of Figures 7 to 8c is different from the display device 100 of Figures 1 to 6c only in that the adhesive layer 730 is different, and other configurations are substantially the same, so duplicated explanations will be omitted.

[0159] 7 to 8c, in a display device 700 according to another embodiment of the present invention, an adhesive layer 730 for adhering the display panel 120 and the back cover 110 may be disposed apart from the sealant 160, and an end of the adhesive layer 730 may be positioned to align with an end of the inorganic layer 122. That is, the end of the adhesive layer 730 may be positioned in accordance with the reference line R of the non-display area NA, and the end of the adhesive layer 730 may overlap with an end of the inorganic layer 122. Therefore, the adhesive layer 730 of the display device 700 according to another embodiment of the present invention may be positioned to completely cover and completely overlap the inorganic layer 122.

[0160] In the display device 700 according to another embodiment of the present invention, an adhesive layer 730 that bonds the display panel 120 to the back cover 110 in an area other than the area where the display panel 120 and the plurality of flexible films 140 are connected may be disposed spaced apart from the sealing member 160, and an end of the adhesive layer 730 may be disposed to overlap with an end of the inorganic layer 122. Therefore, in the display device 700 according to another embodiment of the present invention, the adhesive layer 730 that bonds the display panel 120 to the back cover 110 is disposed spaced apart from the sealing member 160 by a certain distance, thereby preventing bubbles from being generated due to a step between the sealing member 160 and the second substrate 126 and reducing the generation of cracks due to the bubbles.

[0161] In addition, in a display device 700 according to another embodiment of the present invention, the adhesive layer 730 is arranged to be spaced apart from the sealing member 160, and covers the ends of the conductive material arranged on the inorganic layer 122, i.e., the low potential power wiring VSS, the gate driver GD, and the high potential power wiring VDD, so that the ends of the adhesive layer 730 are positioned beyond the ends of the conductive material, thereby reducing the occurrence of cracks in wiring, etc. formed of conductive material.

[0162] Furthermore, in the display device 700 according to another embodiment of the present invention, an end of the adhesive layer 730 may be disposed so as to correspond to and overlap an end of the inorganic layer 122. Thus, by disposing the adhesive layer 730 so as to completely cover the inorganic layer 122, the adhesive layer 730 can absorb stress applied to the inorganic layer 122, thereby reducing cracking of the inorganic layer 122.

[0163] Figure 9 is a plan view of a display device according to yet another embodiment of the present invention. Figure 10a is a cross-sectional view taken along Xa-Xa' in Figure 9. Figure 10b is a cross-sectional view taken along Xb-Xb' in Figure 9. Figure 10c is a cross-sectional view taken along Xc-Xc' in Figure 9. The display device 900 of Figures 9 to 10c is different from the display device 100 of Figures 1 to 6c only in that the adhesive layer 930 is different, and the other configurations are substantially the same, so duplicated explanations will be omitted.

[0164] 9 to 10c, in a display device 900 according to another embodiment of the present invention, an adhesive layer 930 for adhering a display panel 120 and a back cover 110 may be disposed spaced apart from the sealant 160, and an end of the adhesive layer 930 may be located in the third non-display area NA3. That is, the end of the adhesive layer 930 may be spaced apart from the sealant 160 and located outside the reference line R, which is the end of the inorganic layer 122.

[0165] In the display device 900 according to another embodiment of the present invention, an adhesive layer 930 that bonds the display panel 120 and the back cover 110 to each other outside the region where the display panel 120 and the plurality of flexible films 140 are connected may be disposed spaced apart from the sealing member 160, and an end of the adhesive layer 930 may be disposed in the third non-display region NA3. Therefore, in the display device 900 according to another embodiment of the present invention, the adhesive layer 930 that bonds the display panel 120 and the back cover 110 is disposed spaced apart from the sealing member 160 by a predetermined distance, thereby preventing bubbles from being generated due to a step between the sealing member 160 and the second substrate 126 and reducing the generation of cracks due to the bubbles.

[0166] In addition, in a display device 900 according to another embodiment of the present invention, the adhesive layer 930 is arranged to be spaced apart from the sealing member 160, and covers the ends of the conductive material arranged on the inorganic layer 122, i.e., the low potential power wiring VSS, the gate driver GD, and the high potential power wiring VDD, so that the ends of the adhesive layer 930 extend beyond the ends of the conductive material, thereby minimizing the occurrence of cracks in wiring, etc., formed of conductive material.

[0167] Furthermore, in a display device 900 according to still another embodiment of the present invention, an end of the adhesive layer 930 may be disposed so as to cover an end of the inorganic layer 122 and protrude beyond the end of the inorganic layer 122. Thus, by disposing the adhesive layer 930 so as to completely cover the inorganic layer 122, the adhesive layer 930 can absorb stress applied to the inorganic layer 122, thereby reducing cracking of the inorganic layer 122.

[0168] A display device according to an embodiment of the present invention can be described as follows.

[0169] A display device according to an embodiment of the present invention includes a display area including a plurality of sub-pixels and a non-display area surrounding the display area, and includes a first substrate made of one of a transparent conductive oxide and an oxide semiconductor, an inorganic layer disposed on the first substrate, a planarization layer disposed on the inorganic layer, a second substrate disposed on the planarization layer, a sealing member disposed to cover a portion of an upper portion of the second substrate, an adhesive layer disposed on the second substrate and spaced apart from the sealing member, and a back cover disposed on the adhesive layer and attached to the second substrate by the adhesive layer.

[0170] According to another feature of the present invention, an end of the inorganic layer may be located inside an end of the first substrate in the non-display area.

[0171] According to another feature of the present invention, the inorganic layer is composed of a plurality of layers made of inorganic materials, and at least one of a high potential power supply wiring, a low potential power supply wiring, and a gate driver may be disposed on at least one of the plurality of layers in the non-display area.

[0172] According to another aspect of the present invention, an end of the adhesive layer may be located between an end of the inorganic layer and an end of any one of the high potential power supply wiring, the low potential power supply wiring, and the gate driver.

[0173] According to another feature of the present invention, an end of the adhesive layer may be positioned to overlap an end of the inorganic layer.

[0174] According to another feature of the present invention, the end of the adhesive layer may be located between the seal member and the end of the inorganic layer.

[0175] According to yet another feature of the present invention, a planarization layer may be disposed on the front surface of the first substrate, covering the ends of the inorganic layer.

[0176] According to yet another feature of the present invention, the adhesive layer may be a double-sided tape.

[0177] According to another feature of the present invention, the display device may further include a plurality of flexible films disposed on one end of the first substrate, and the adhesive layer may be spaced apart from the sealing member in areas other than the area where the plurality of flexible films are disposed.

[0178] According to yet another feature of the present invention, an adhesive layer may be disposed on the seal member in the area where the plurality of flexible films are disposed.

[0179] Although the present invention has been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present invention. Therefore, the disclosed embodiments are for illustrative purposes only and do not limit the technical concept of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of the present invention should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0180] 100 display device 110 Back Cover 111 Opening 120 Display Panel 121 First board 122 Inorganic layer 123 Planarization layer 124 banks 125 Adhesive layer 126 Second board 130 Adhesive layer 140 Flexible Film 150 Printed Circuit Board 160 Sealing material 180 Polarizing Plate AA display area NA hidden area PP pixel section R Reference Line

Claims

1. a first substrate including a display area including a plurality of sub-pixels and a non-display area surrounding the display area, the first substrate being made of one of a transparent conductive oxide and an oxide semiconductor; an inorganic layer on the first substrate; a planarization layer on the inorganic layer; a second substrate disposed on the planarization layer, the second substrate having an end positioned inside an end of the first substrate such that an end of the first substrate extends through an end of the second substrate; a sealing member covering a portion of the second substrate; an adhesive layer disposed on the second substrate; a back cover disposed on the adhesive layer and bonded to the second substrate by the adhesive layer; a plurality of flexible films disposed on one end of the first substrate; Including, the adhesive layer is spaced apart from the sealing member in an area other than an area where the plurality of flexible films are disposed; In the region including the plurality of flexible films, the adhesive layer is disposed on the seal member. Display device.

2. The display device of claim 1 , wherein an edge of the inorganic layer is located inside an edge of the first substrate in the non-display area.

3. the inorganic layer includes a plurality of inorganic layers, The display device of claim 2 , wherein at least one of a high-potential power supply line, a low-potential power supply line, and a gate driver is disposed on at least one of the inorganic layers in the non-display area.

4. A display device as described in Claim 3, wherein in the area excluding the area in which the multiple flexible films are arranged, the end of the adhesive layer extends through the end of one of the high-potential power supply wiring, the low-potential power supply wiring and the gate driving unit, and is located inside the end of the inorganic layer.

5. A display device as described in Claim 3, wherein in the area excluding the area in which the multiple flexible films are arranged, the end of the adhesive layer is positioned so as to be aligned with the end of the inorganic layer.

6. A display device as described in Claim 3, wherein in the area excluding the area in which the multiple flexible films are arranged, the end of the adhesive layer extends through the end of the inorganic layer and does not extend to the sealing member.

7. The display device according to claim 2 , wherein the planarization layer overlaps an end of the inorganic layer and is disposed on the front surface of the first substrate.

8. The display device of claim 1 , wherein the adhesive layer includes a double-sided tape.

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