Oscillation period detection circuit, method, and semiconductor memory

Abstract

The present disclosure provides an oscillation period detection circuit, a method, and a semiconductor memory. The oscillation period detection circuit includes: an oscillator module including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal based on the enable signal; a control module configured to receive the enable signal and the oscillation clock signal, perform a valid time reset process based on the oscillation clock signal and the enable signal, and determine a target time; and a counting module configured to receive the enable signal and the oscillation clock signal, perform a period counting process based on the enable signal and the oscillation clock signal, and determine a target period number. The oscillation period of the target oscillator is calculated based on the target time and the target period number.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on August 27, 2021, bearing application number 202110993836.6 and entitled "Oscillation Period Detection Circuit, Method and Semiconductor Memory," the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of electronic measurement technology, and more particularly to oscillation period detection circuits, methods, and semiconductor memories. [Background technology]

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of multiple overlapping memory cells. DRAM requires an oscillator to generate a regular sequence signal, which controls the multiple memory cells. Therefore, detecting the oscillator period is an important part of chip quality verification.

[0004] However, the detection method of the oscillation period time length in the related art still has some shortcomings, so the detection accuracy rate and detection efficiency are low. Summary of the Invention

[0005] The present disclosure provides an oscillation period detection circuit, method, and semiconductor memory, which can improve the accuracy and efficiency of oscillation period detection.

[0006] The technical solution of the present disclosure is realized as follows:

[0007] According to a first aspect, an embodiment of the present disclosure provides an oscillation period detection circuit, the oscillation period detection circuit comprising: an oscillator module including a target oscillator and configured to receive an enable signal and, based on the enable signal, control the target oscillator to output an oscillating clock signal; a control module configured to receive an enable signal and an oscillating clock signal, and perform a valid time reset process based on the oscillating clock signal and the enable signal to determine a target time; a counting module configured to receive an enable signal and an oscillating clock signal, perform a period counting process based on the enable signal and the oscillating clock signal, and determine a target number of periods; The oscillation period of the target oscillator is calculated based on the target time and the target number of periods.

[0008] According to a second aspect, an embodiment of the present disclosure provides an oscillation period detection method applied to an oscillation period detection circuit including a target oscillator, the method comprising: controlling the target oscillator to output an oscillating clock signal based on an enable signal; performing a valid time resetting process based on the oscillation clock signal and the enable signal to determine a target time; performing a period counting process based on the enable signal and the oscillation clock signal to determine a target number of periods; performing a calculation on the target time and the target number of periods to determine an oscillation period of the target oscillator.

[0009] According to a third aspect, an embodiment of the present disclosure provides a semiconductor memory including at least the oscillation period detection circuit according to the first aspect.

[0010] The embodiments of the present disclosure provide an oscillation period detection circuit, method, and semiconductor memory. The oscillation period detection circuit includes an oscillator module including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal based on the enable signal; a control module configured to receive the enable signal and the oscillation clock signal, perform a valid time reset process based on the oscillation clock signal and the enable signal to determine a target time; and a counting module configured to receive the enable signal and the oscillation clock signal, perform a period counting process based on the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated based on the target time and the target period number. In this way, the enable signal and the oscillation clock signal determine the target time through the valid time reset process, and the enable signal and the oscillation clock signal determine the target period number by counting the periods. The oscillation period is then calculated based on the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a structural schematic diagram of an example of an oscillation periodic circuit provided in an embodiment of the present disclosure. [Figure 2] FIG. 10 is a structural schematic diagram of another example of an oscillation periodic circuit provided in an embodiment of the present disclosure. [Figure 3] FIG. 2 is a schematic diagram of a signal waveform of an example of an oscillation periodic circuit provided in an embodiment of the present disclosure. [Figure 4] FIG. 10 is a schematic diagram of a simulated verification of an example of an oscillation period circuit provided in an embodiment of the present disclosure. [Figure 5] 1 is a flowchart of an example of an oscillation period detection method provided in an embodiment of the present disclosure. [Figure 6] 1 is a structural schematic diagram of an example of a semiconductor memory provided in an embodiment of the present disclosure; DETAILED DESCRIPTION OF THE INVENTION

[0012] The following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only for the purpose of explaining the present application, and are not intended to limit the present application. It should be noted that, for ease of explanation, only parts relevant to the present application are shown in the drawings.

[0013] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

[0014] Where "some embodiments" are mentioned below, any subset of the possible embodiments is described, but it should be understood that "some embodiments" may be the same or different subsets of all possible embodiments, and may be combined with each other where not inconsistent.

[0015] Furthermore, the terms "first / second / third" in the embodiments of the present disclosure do not limit a specific order but are used to distinguish between similar objects. It is understood that "first / second / third" can be used to change the specific order or order in some cases, and therefore the embodiments of the present application described herein can be implemented in an order other than the order shown or described.

[0016] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of multiple overlapping memory cells. DRAM requires an oscillator to generate a regular sequence signal, which controls the multiple memory cells. Therefore, detecting the oscillator period is an important part of memory chip quality verification.

[0017] There are various methods for detecting the oscillator inside a memory chip, but they can be roughly divided into two types. One is direct verification, in which the oscillator's output clock is output to a verification device. This verification method is suitable for low-speed clocks. The other is a method in which the internal clock period is output by the control logic, and the oscillator period is calculated based on the operating time of the oscillator.

[0018] However, the detection method of the oscillation period time length in the related art still has some shortcomings, so the detection accuracy rate and detection efficiency are low.

[0019] Based on this, an embodiment of the present disclosure provides an oscillation period detection circuit, the basic concept of which is as follows: the oscillation period detection circuit includes an oscillator module including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal based on the enable signal; a control module configured to receive the enable signal and the oscillation clock signal, perform a valid time reset process based on the oscillation clock signal and the enable signal to determine a target time; and a counting module configured to receive the enable signal and the oscillation clock signal, perform a period counting process based on the enable signal and the oscillation clock signal to determine a target number of periods, whereby the oscillation period of the target oscillator is calculated based on the target time and the target number of periods. In this way, the enable signal and the oscillation clock signal determine the target time through the valid time reset process, and the enable signal and the oscillation clock signal determine the target number of periods by counting the periods. The oscillation period is then calculated based on the target time and the target number of periods, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0020] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[0021] In one embodiment of the present disclosure, referring to FIG. 1, FIG. 1 shows a structural schematic diagram of an example of an oscillation period detection circuit 10 provided in an embodiment of the present disclosure. As shown in FIG. 1, the oscillation period detection circuit 10 includes: an oscillator module 101 including a target oscillator 1011, the oscillator module 101 being configured to receive an enable signal and, based on the enable signal, control the target oscillator 1011 to output an oscillating clock signal; a control module 102 configured to receive an enable signal and an oscillating clock signal, and perform an effective time resetting process based on the oscillating clock signal and the enable signal to determine a target time; a counting module 103 configured to receive an enable signal and an oscillating clock signal, perform a period counting process based on the enable signal and the oscillating clock signal, and determine a target period quantity; The oscillation period of the target oscillator 1011 is calculated based on the target time and the number of target periods.

[0022] It should be noted that the oscillation period detection circuit provided in the embodiments of the present disclosure can be applied to any electronic device related to an oscillator, such as a dynamic random memory, a static random memory, etc.

[0023] In the embodiment of the present disclosure, the basic principle of the oscillation period detection circuit 10 is to output the internal clock period quantity through the control logic, and calculate the period of the oscillator based on the operating time of the oscillator.

[0024] Specifically, the oscillation period detection circuit includes an oscillator module 101, a control module 102, and a counting module 103. The target oscillator 1011 in the oscillator module 101 outputs an oscillation clock signal based on an enable signal. The control module 102 resets the effective time for the enable signal based on the oscillation clock signal and outputs a target time. The counting module 103 counts the periods of the oscillation clock signal based on the enable signal and determines the number of target periods. In this way, the oscillation period of the target oscillator 1011 can be obtained by calculation based on the target time and the number of target periods.

[0025] 2, in some embodiments, reference is made to FIG. 2, which shows a structural schematic diagram of another example of the oscillation period detection circuit 10 provided in the embodiments of the present disclosure. As shown in FIG. 2, the control module 102 includes a first flip-flop 1021, a second flip-flop 1022, and a third flip-flop 1023, wherein the input terminal (D) of the first flip-flop 1021 is for receiving an enable signal, the input terminal (D) of the second flip-flop 1022 is connected to the output terminal (Q) of the first flip-flop 1021, the input terminal (D) of the third flip-flop 1023 is connected to the output terminal (Q) of the second flip-flop 1022, and the clock terminal (CK) of the first flip-flop 1021, the clock terminal (CK) of the second flip-flop 1022, and the clock terminal (CK) of the third flip-flop 1023 are all for receiving an oscillation clock signal.

[0026] The first flip-flop 1021 performs sampling processing on the enable signal based on the oscillation clock signal and outputs a first control signal. The second flip-flop 1022 performs sampling processing on the first control signal based on the oscillation clock signal and outputs a second control signal. The third flip-flop 1023 performs sampling processing on the second control signal based on the oscillation clock signal and outputs a third control signal.

[0027] Here, the duration of time that the first control signal is in the first level state is for determining the target time, and the target time is an integer multiple of the oscillation period of the target oscillator, the second control signal is for performing a latch process on the target period quantity when the first level state is reversed to the second level state, and the third control signal is for performing a clear process on the counting module 103 when the first level state is reversed to the second level state.

[0028] It should be noted that the control module 102 comprises a first flip-flop 1021, a second flip-flop 1022 and a third flip-flop 1023, the specific connection relationship of which is shown in Figure 2. A flip-flop is a common electronic device in a logic circuit, which includes a clock terminal and an input terminal, receives an oscillating clock signal through the clock terminal, and samples the signal at the input terminal according to the oscillating clock signal.

[0029] The first flip-flop 1021, the second flip-flop 1022, and the third flip-flop 1023 may be flip-flops based on various principles, and those skilled in the art may select them according to the actual application. For example, the first flip-flop 1021, the second flip-flop 1022, and the third flip-flop 1023 may all be D-type flip-flops. The D-type flip-flop can sample the signal at the input terminal at the rising edge of the oscillation clock signal.

[0030] The first flip-flop 1021 samples the enable signal at the rising edge of the oscillation clock signal, thereby outputting a first control signal. Referring to FIG. 3, FIG. 3 shows a schematic diagram of a signal waveform of an example of an oscillation cycle circuit provided in an embodiment of the present disclosure. As shown in FIG. 3, since the first flip-flop 1021 samples only at the rising edge of the oscillation clock signal, the first control signal can only change its level state at the rising edge of the oscillation clock signal. Therefore, the duration of the first control signal in the first level state is always an integer multiple of the oscillation period of the target oscillator 1011. That is, the first flip-flop 1021 is mainly used to reset the effective time of the enable signal to an integer multiple of the oscillation period (of the target oscillator), thereby determining the target time.

[0031] The second flip-flop 1022 samples the first control signal at the rising edge of the oscillation clock signal, and outputs it as the second control signal. As shown in Figure 3, the effective time of the second control signal (the duration of the first level state) is delayed by one oscillation period (of the target oscillator) compared to the first control signal. The second control signal is mainly used to latch the target period quantity.

[0032] The third flip-flop 1023 samples the second control signal at the rising edge of the oscillation clock signal, and outputs the third control signal. As shown in Figure 3, the effective time of the third control signal (the duration of the first level state) is delayed by one oscillation period (of the target oscillator) compared to the second control signal. The third control signal is mainly used to perform a clearing process for the counting module 103.

[0033] Furthermore, in some embodiments, the oscillator module 101 is configured to receive the enable signal and the third control signal, and control the target oscillator 1011 to output an oscillating clock signal when the enable signal is in a first level state or the third control signal is in a first level state, and control the target oscillator 1011 to stop outputting the oscillating clock signal when the enable signal and the third control signal are both in a second level state. In this way, the enable signal and the third control signal are simultaneously employed to control the target oscillator, thereby avoiding errors in the measurement process caused by the target oscillator stopping oscillation prematurely.

[0034] Therefore, in some embodiments, as shown in FIG. 2, the oscillator module 101 further includes a NOR gate 1012 and a NOT gate 1013; The NOR gate 1012 performs a NOR operation on the third control signal and the enable signal to obtain a signal after the operation. The NOT gate 1013 performs a NOT operation on the signal after the operation to obtain an enable control signal. The target oscillator 1011 is for receiving an enable control signal and outputting an oscillating clock signal based on the enable control signal.

[0035] It should be noted that the third control signal and the enable signal perform a NOR operation and a NOT operation in turn to obtain an enable control signal, which is for controlling the target oscillator 1011 to output a target oscillation signal.

[0036] Further, in some embodiments, as shown in FIG. 2 , the counting module 103 includes a counter 1031, and the input end, the clock end and the reset end of the counter 1031 are respectively connected to an enable signal, an oscillating clock signal and a third control signal; The counter 1031 is for performing period counting processing on the oscillation clock signal and outputting a period counting signal when the enable signal is in the first level state, and the period counting signal indicates the target number of periods. The counter 1031 is further for performing a clearing process when the third control signal is inverted from the first level state to the second level state.

[0037] It should be noted that the counting module 103 mainly includes a counter 1031. For the counter 1031, the enable signal plays the role of gate control. When the enable signal is valid (in the first level state), the counter 1031 counts the periods of the oscillation clock signal and outputs a period counting signal. In addition, for the counter 1031, the third control signal is a reset signal, and when the third control signal reverses from the first level state to the second level state, the count value of the counter 1031 is cleared.

[0038] Furthermore, in some embodiments, the oscillation period detection circuit 10 further includes a latch 104, two inputs of which are respectively connected to the period count signal and the second control signal; The latch 104 is for latching the period count signal to realize the latching of the target period quantity when the second control signal is inverted from the first level state to the second level state.

[0039] It should be noted that the input terminal of the latch 104 receives the period count signal output from the counter 1031, and further receives a second control signal, and latches the period count signal at the falling edge of the second control signal.

[0040] As can be seen from the above, when the enable signal is in the first level state, the counter 1031 counts the period of the oscillating clock signal. At the falling edge of the second control signal, the latch 104 latches the period count signal output from the counter 1031, thereby obtaining the target period number. At the falling edge of the third control signal, the count value of the counter 1031 is cleared.

[0041] It should be further explained that the first level state is a high level state and the second level state is a low level state, however, this is not intended to limit the embodiments of the present disclosure.

[0042] Referring to FIG. 4, FIG. 4 shows a schematic diagram of an example of a pseudo-verification of an oscillation period circuit provided in an embodiment of the present disclosure. As shown in FIG. 4, the embodiment of the present disclosure employs two pseudo-verifications. In the first pseudo-verification, the target time is 1000 nanoseconds, and the period number is a pseudo result of 592 (binary number is 0000 0010 0101 0000), thereby calculating an oscillation period of 1.69 nanoseconds. In the second pseudo-verification, the oscillation period is a pseudo result of 1.687 nanoseconds, and thereby calculating a period number of 593 (binary number is 0000 0010 0101 0001). As can be seen from the above, the results of the oscillation period circuit provided in the embodiment of the present disclosure are relatively accurate.

[0043] [Table 1]

[0044] An embodiment of the present disclosure provides an oscillation period detection circuit, the oscillation period detection circuit including: an oscillator module including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal based on the enable signal; a control module configured to receive the enable signal and the oscillation clock signal, perform a valid time reset process based on the oscillation clock signal and the enable signal to determine a target time; and a counting module configured to receive the enable signal and the oscillation clock signal, perform a period counting process based on the enable signal and the oscillation clock signal to determine a target period number, wherein the oscillation period of the target oscillator is calculated based on the target time and the target period number. Thus, the embodiment of the present disclosure provides a novel circuit control structure, which is mainly applied to detecting the period of an oscillator within a chip, and can also be used as an auxiliary circuit for verifying propagation delay time (Tpd) in wafer level test (WAT). Specifically, the enable signal and the oscillation clock signal determine the target time through an effective time reset process, and the enable signal and the oscillation clock signal determine the target period number through period counting.Then, the oscillation period is calculated according to the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.In addition, the oscillation period detection circuit provided in the embodiments of the present disclosure is suitable for both high-speed and low-speed clocks and has a wide range of application scenarios.

[0045] In another embodiment of the present disclosure, referring to Fig. 5, Fig. 5 shows a flowchart of an example of an oscillation period detection method provided in an embodiment of the present disclosure. As shown in Fig. 5, the method may include the following steps:

[0046] In step S201, the target oscillator is controlled to output an oscillation clock signal based on the enable signal.

[0047] It should be noted that the oscillation period detection method in the embodiment of the present disclosure is applied to the above oscillation period detection circuit, and the oscillation period detection circuit includes a target oscillator, where the target oscillator can output an oscillation clock signal according to an enable signal, that is, the purpose of the oscillation period detection method provided in the embodiment of the present disclosure is to detect the period of the oscillation clock signal.

[0048] In step S202, a valid time resetting process is performed based on the oscillation clock signal and the enable signal, and a target time is determined.

[0049] In step S203, a period counting process is performed based on the enable signal and the oscillation clock signal to determine the target number of periods.

[0050] It should be noted that the oscillation clock signal is used to perform an effective clock resetting process on the enable signal, resetting the effective time of the enable signal to an integer multiple of the oscillation period, thereby obtaining a target time, and the enable signal is used to perform a period counting process on the oscillation clock signal, thereby obtaining a target period quantity.

[0051] Specifically, in some embodiments, the oscillation period detection circuit may include a first flip-flop, a second flip-flop, and a third flip-flop. receiving an enable signal and an oscillation clock signal by a first flip-flop, performing sampling processing according to the oscillation clock signal and the enable signal, and outputting a first control signal; receiving the first control signal and the oscillation clock signal by a second flip-flop, performing sampling processing on the first control signal according to the oscillation clock signal, and outputting a second control signal; The method may include receiving the second control signal and the oscillation clock signal by a third flip-flop, performing a sampling process on the second control signal based on the oscillation clock signal, and outputting a third control signal.

[0052] It should be noted that the first flip-flop mainly samples the enable signal at the rising edge of the oscillation clock signal to obtain the first control signal, thereby resetting the effective time of the enable signal to an integer multiple of the oscillation period of the target oscillator, and facilitating subsequent calculation, that is, the duration length of the first control signal in the first level state is used to determine the target time, and the target time is an integer multiple of the oscillation period of the target oscillator.

[0053] The second flip-flop mainly samples the first control signal at the rising edge of the oscillation clock signal to obtain the second control signal. The effective time of the second control signal is delayed by one oscillation period (of the target oscillator) compared to the first control signal, thereby latching the target period number. That is, the second control signal is used to latch the target period number when the first level state is reversed to the second level state.

[0054] The third flip-flop mainly samples the second control signal at the rising edge of the oscillation clock signal to obtain the third control signal. The effective time of the third control signal is delayed by one oscillation period (of the target oscillator) compared to the second control signal, and the third control signal is used to perform a clearing process on the counting module. That is, the third control signal is used to perform a clearing process when the counting module is reversed from the first level state to the second level state.

[0055] In the above description, the valid time of a signal is the time that the signal is in a first level state.

[0056] Furthermore, in some embodiments, the step of controlling the target oscillator to output the oscillating clock signal based on the enable signal comprises: controlling the target oscillator to output an oscillating clock signal when the enable signal is in a first level state or the third control signal is in a first level state; and controlling the target oscillator to stop outputting the oscillating clock signal when the enable signal and the third control signal are both in the second level state.

[0057] It should be noted that the enable signal and the third control signal are simultaneously employed to control the target oscillator, to avoid errors in the measurement process caused by the target oscillator stopping oscillation too early.

[0058] In one specific embodiment, the oscillation period detection circuit further includes a counter and a latch. Correspondingly, the step of performing period counting processing on the oscillation clock signal according to the enable signal to determine the target period number includes: When the enable signal is in a first level state, performing a period counting process on the oscillation clock signal by a counter and outputting a period counting signal, the period counting signal being for indicating a target number of periods; When the second control signal is inverted from the first level state to the second level state, latching the period count signal by the latch can be included, thereby realizing latching of the target number of periods.

[0059] Illustratively, when the enable signal is valid, the counter counts periods of the oscillating clock signal and outputs a period count signal, and at the same time, at the falling edge of the second control signal, the latch latches the period count signal to obtain a target period quantity.

[0060] Illustratively, the reset end of the counter is connected to a third control signal. Therefore, in some embodiments, the method further comprises: The method may include controlling the counter to perform a clearing process when the third control signal is inverted from the first level state to the second level state.

[0061] In this way, after each verification is completed, the count value of the counter is cleared and the system waits for the next verification.

[0062] Furthermore, in some embodiments, the step of controlling the target oscillator to output the oscillating clock signal based on the enable signal comprises: performing a NOR operation on the third control signal and the enable signal to obtain a signal after the operation; performing a not operation on the operated signal to obtain an enable control signal; controlling the target oscillator to output the oscillating clock signal based on the enable control signal.

[0063] It should be noted that the third control signal and the enable signal are for controlling the oscillation clock signal after NOR and NOT operations. Thus, when the third control signal and the enable signal are both at the second level, the enable control signal is at the second level, and the target oscillator stops outputting the target oscillation signal. When the third control signal is at the first level or the enable signal is at the first level, the enable control signal is at the first level, and the target oscillator outputs the target oscillation signal.

[0064] In this way, the above process makes it possible to obtain the target number of cycles of the oscillation clock signal within the target time.

[0065] In step S204, calculations are performed on the target time and the target number of cycles to determine the oscillation cycle of the target oscillator.

[0066] It should be noted that after obtaining the target time and the target number of periods, a simple calculation can be performed to determine the oscillation period of the target oscillator.

[0067] Specifically, the step of calculating the target time and the target number of cycles to determine the oscillation cycle of the target oscillator includes: The step may include dividing the target time by the target number of periods to obtain the oscillation period of the target oscillator.

[0068] It should be noted that the oscillation period of a target oscillator is the quantity target time / target period.

[0069] In another embodiment, since the first count value of the counter is 0, the exact number of periods of the oscillation period signal is actually (target number of periods + 1), that is, the exact oscillation period is target time / (target number of periods + 1). However, in a single test, the number of oscillation periods is generally large, so the target number of periods can be used to calculate (target number of periods + 1) instead, and the error is within the allowable range.

[0070] It should be further explained that the first level state is a high level state and the second level state is a low level state.

[0071] An embodiment of the present disclosure provides an oscillation period detection method. The target oscillator is controlled to output an oscillation clock signal based on an enable signal. A target time is determined by performing an effective time reset process based on the oscillation clock signal and the enable signal. A period counting process is performed based on the enable signal and the oscillation clock signal to determine a target period number. A calculation is performed on the target time and the target period number to determine the oscillation period of the target oscillator. In this way, the enable signal and the oscillation clock signal determine the target time through an effective time reset process, and the enable signal and the oscillation clock signal determine the target period number by period counting. The oscillation period is then calculated based on the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0072] In yet another embodiment of the present disclosure, reference is made to Fig. 6, which shows an example of a semiconductor memory 30 provided in an embodiment of the present disclosure. The semiconductor memory 30 includes at least the oscillation period detection circuit 10 described above.

[0073] Since the semiconductor memory 30 includes the oscillation period detection circuit 10, during the oscillation period detection process, the enable signal and the oscillation clock signal are used to perform a valid time reset process to determine the target time, and the enable signal and the oscillation clock signal are used to count the periods to determine the target period number, and then the oscillation period is calculated according to the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0074] In yet another embodiment of the present disclosure, an electronic device is provided, which includes at least the semiconductor memory 30 described above.

[0075] Since the electronic device includes a semiconductor memory 30, during the process of detecting the oscillation period, the enable signal and the oscillation clock signal are used to perform a valid time reset process, thereby determining the target time, and the enable signal and the oscillation clock signal are used to count the period to determine the target period number, and then the oscillation period is calculated according to the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

[0076] The above contents are merely the best examples of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0077] It should be explained that in this disclosure, the term "comprises," or any other variation thereof, is intended to cover a non-exclusive inclusion, whereby a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also other elements not expressly listed or inherent elements of such process, method, article, or apparatus. Unless otherwise limited, an element defined with the phrase "comprises..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

[0078] The numbers of the above-mentioned embodiments of the present disclosure do not indicate the superiority or inferiority of the embodiments, but are used for convenience of explanation.

[0079] The methods disclosed in the several method embodiments provided in this disclosure can be combined in any non-conflicting manner to obtain new method embodiments.

[0080] The features disclosed in the several product embodiments provided in this disclosure may be combined in any non-conflicting manner to obtain new product embodiments.

[0081] The features disclosed in any method or apparatus embodiment provided in this disclosure may be combined in any non-conflicting manner to produce new method or apparatus embodiments.

[0082] The above content is merely a specific embodiment of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any modifications or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims. [Industrial Applicability]

[0083] The embodiments of the present disclosure provide an oscillation period detection circuit, method, and semiconductor memory. The oscillation period detection circuit includes an oscillator module including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal based on the enable signal; a control module configured to receive the enable signal and the oscillation clock signal, perform a valid time reset process based on the oscillation clock signal and the enable signal to determine a target time; and a counting module configured to receive the enable signal and the oscillation clock signal, perform a period counting process based on the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated based on the target time and the target period number. In this way, the enable signal and the oscillation clock signal determine the target time through the valid time reset process, and the enable signal and the oscillation clock signal determine the target period number by counting the periods. The oscillation period is then calculated based on the target time and the target period number, thereby improving the detection accuracy and detection efficiency of the oscillation period.

Claims

1. An oscillation period detection circuit, an oscillator module including a target oscillator, the oscillator module configured to receive an enable signal and, based on the enable signal, control the target oscillator to output an oscillating clock signal; a control module configured to receive the enable signal and the oscillating clock signal, and perform a valid time reset process based on the oscillating clock signal and the enable signal to determine a target time; a counting module configured to receive the enable signal and the oscillating clock signal, and perform a period counting process based on the enable signal and the oscillating clock signal to obtain a number of periods of the oscillating clock signal within the target time, and set the number of periods of the oscillating clock signal obtained by the period counting process as a target number of periods; The oscillation period of the target oscillator to be detected is calculated based on the target time and the target number of periods, the control module includes a first flip-flop, a second flip-flop, and a third flip-flop, an input terminal (D) of the first flip-flop is for receiving the enable signal, an input terminal (D) of the second flip-flop is connected to an output terminal (Q) of the first flip-flop, an input terminal (D) of the third flip-flop is connected to an output terminal (Q) of the second flip-flop, and a clock terminal (CK) of the first flip-flop, a clock terminal (CK) of the second flip-flop, and a clock terminal (CK) of the third flip-flop are all for receiving the oscillation clock signal; the first flip-flop is configured to perform sampling processing on the enable signal based on the oscillation clock signal and output a first control signal; the second flip-flop is configured to perform sampling processing on the first control signal based on the oscillation clock signal and output a second control signal; the third flip-flop is configured to perform sampling processing on the second control signal based on the oscillation clock signal and output a third control signal; The duration of time during which the first control signal is in the first level state is set as the target time, and the target time is an integer multiple of the oscillation period of the target oscillator; the second control signal, when it is reversed from the first level state to the second level state, is for performing a latch process on the target period quantity; and the third control signal, when it is reversed from the first level state to the second level state, is for performing a clear process on the counting module. Oscillation period detection circuit.

2. the oscillator module is configured to receive the enable signal and the third control signal, and control the target oscillator to output the oscillating clock signal when the enable signal is in a first level state or the third control signal is in a first level state, and control the target oscillator to stop outputting the oscillating clock signal when both the enable signal and the third control signal are in a second level state; 2. The oscillation period detection circuit according to claim 1.

3. The counting module includes a counter, and an input end, a clock end, and a reset end of the counter are respectively connected to the enable signal, the oscillating clock signal, and the third control signal; the counter is for counting the number of periods of the oscillation clock signal when the enable signal is in a first level state, and outputting a period count signal, the period count signal being for indicating the target number of periods; and the counter is further for performing a clearing process when the third control signal is inverted from the first level state to a second level state.

3. The oscillation period detection circuit according to claim 2.

4. the oscillation period detection circuit further includes a latch, two input terminals of which are respectively connected to the period count signal and the second control signal; the latch is for latching the period count signal to realize the latching of the target period number when the second control signal is inverted from a first level state to a second level state; 4. The oscillation period detection circuit according to claim 3.

5. the oscillator module further includes a NOR gate and a NOT gate; the NOR gate performs a NOR operation on the third control signal and the enable signal to obtain a signal after the operation; the NOT gate performs a NOT operation on the signal after the operation to obtain an enable control signal; the target oscillator is for receiving the enable control signal and outputting the oscillating clock signal based on the enable control signal; 3. The oscillation period detection circuit according to claim 2.

6. the first flip-flop, the second flip-flop, and the third flip-flop are all D-type flip-flops; 2. The oscillation period detection circuit according to claim 1.

7. The first level state is a high level state, and the second level state is a low level state.

7. The oscillation period detection circuit according to claim 1.

8. 1. An oscillation period detection method applied to an oscillation period detection circuit including a target oscillator, comprising: controlling the target oscillator to output an oscillating clock signal based on an enable signal; performing a valid time resetting process based on the oscillation clock signal and the enable signal to determine a target time; performing a period counting process based on the enable signal and the oscillation clock signal to obtain the number of periods of the oscillation clock signal within the target time, and setting the number of periods of the oscillation clock signal obtained by the period counting process as a target number of periods; performing a calculation on the target time and the target number of periods to determine the oscillation period of the target oscillator to be detected; The oscillation period detection circuit includes a first flip-flop, a second flip-flop, and a third flip-flop, and the oscillation period detection method further includes: receiving the enable signal and the oscillating clock signal by the first flip-flop, sampling the enable signal based on the oscillating clock signal, and outputting a first control signal; receiving the first control signal and the oscillation clock signal by the second flip-flop, performing sampling processing on the first control signal based on the oscillation clock signal, and outputting a second control signal; receiving the second control signal and the oscillation clock signal by the third flip-flop, performing sampling processing on the second control signal based on the oscillation clock signal, and outputting a third control signal; The duration of time during which the first control signal is in the first level state is set as the target time, and the target time is an integer multiple of the oscillation period of the target oscillator, the second control signal is for performing a latch process on the target period number when the first level state is reversed to the second level state, and the third control signal is for performing a clear process when the first level state is reversed to the second level state. Oscillation period detection method.

9. controlling the target oscillator to output an oscillating clock signal based on an enable signal, controlling the target oscillator to output the oscillating clock signal when the enable signal is in a first level state or the third control signal is in a first level state; and controlling the target oscillator to stop outputting the oscillating clock signal when the enable signal and the third control signal are both in a second level state. The oscillation period detection method according to claim 8.

10. The oscillation period detection circuit includes a counter and a latch, and performs a period counting process based on the enable signal and the oscillation clock signal to obtain the number of periods of the oscillation clock signal within the target time, and the step of setting the number of periods of the oscillation clock signal obtained by the period counting process as a target number of periods includes: When the enable signal is in a first level state, counting the number of periods of the oscillating clock signal by the counter and outputting a period count signal, the period count signal being for indicating the target number of periods; when the second control signal is inverted from a first level state to a second level state, latching the period count signal by the latch, thereby realizing latching of the target number of periods; The oscillation period detection method according to claim 9.

11. The oscillation period detection method further comprises: controlling the counter to perform a clearing process when the third control signal is inverted from a first level state to a second level state; The oscillation period detection method according to claim 10.

12. controlling the target oscillator to output an oscillating clock signal based on an enable signal, performing a NOR operation on the third control signal and the enable signal to obtain a signal after the operation; performing a not operation on the signal after the operation to obtain an enable control signal; and controlling the target oscillator to output the oscillating clock signal based on the enable control signal. The oscillation period detection method according to claim 10.

13. The step of calculating the target time and the target number of cycles to determine the target oscillation cycle of the oscillator includes: dividing the target time by the target number of periods to obtain an oscillation period of the target oscillator; The oscillation period detection method according to any one of claims 9 to 12.

14. The first level state is a high level state, and the second level state is a low level state. The oscillation period detection method according to any one of claims 8 to 13.

15. A semiconductor memory comprising at least the oscillation period detection circuit according to any one of claims 1 to 7.

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