Fast offset voltage calibration device for dynamic comparators

Abstract

This invention discloses a rapid offset voltage calibration device for dynamic comparators, primarily addressing the problems of long calibration cycles and poor calibration accuracy in existing comparator offset calibration techniques. The device includes a comparator, a calibration voltage control circuit, a calibration control logic circuit, and a calibration input circuit. In calibration mode, the comparator outputs the comparison result. The calibration control logic circuit stores and processes the comparison result and outputs different control signals to the calibration voltage control circuit based on the number of consecutive comparisons. The calibration voltage control circuit adjusts the step size of the calibration voltage according to the different control signals and transmits this information to the calibration transistor in the calibration input circuit. The calibration transistor in the calibration input circuit rapidly calibrates the comparator's offset voltage to the convergence range as the calibration voltage changes. This invention dynamically adjusts the calibration step size, reduces the comparison and compensation cycle, and improves calibration speed while maintaining calibration accuracy. It can be used for calibrating dynamic comparators.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to an offset voltage calibration device for a dynamic comparator, which can be used to quickly calibrate the offset voltage of a dynamic comparator, dynamically adjust the calibration step size, and improve the convergence speed of calibration while meeting the calibration accuracy requirements. Background Technology

[0002] With the ever-increasing demand for faster information processing speeds in modern digital systems such as digital signal processing chips and communication infrastructure, analog-to-digital converters (ADCs), as core components of these systems, face increasingly stringent performance requirements. As a fundamental module of the ADC, the circuit design and performance optimization of the comparator also significantly impact its overall performance. Dynamic comparators, with their advantages of low power consumption, high speed, and good process compatibility, are widely used in high-performance ADC circuit design. Although the speed, power consumption, and area of ​​dynamic comparators have increased with the continuous shrinking of CMOS process dimensions, this size reduction has led to more severe device mismatch, resulting in larger offsets and severely limiting their application in high-performance ADCs. The simplest way to reduce the offset of dynamic comparators is to increase the device size, but this contradicts the goal of reducing area and power consumption. Another approach is to use offset calibration techniques, which store or measure the offset voltage and then cancel it out, thus achieving higher comparator accuracy with a smaller area. Dynamic comparators can achieve offset voltage calibration under certain timing constraints and power consumption requirements through additional calibration auxiliary circuits and calibration logic.

[0003] Currently, there are two main types of comparator offset calibration methods: load capacitance adjustment offset calibration and input stage current adjustment offset calibration. Load capacitance adjustment adjusts the load capacitance at the differential output of the comparator's pre-amplification stage, causing different charging and discharging rates at the differential output during the initial amplification phase, thus offsetting the comparator's offset voltage. The load capacitance can be adjusted using a configurable capacitor array or a voltage-controlled MOS capacitor. A capacitor array consists of multiple capacitors connected in series with a switch, with different sized load capacitors connected to the differential output via a selector switch. A voltage-controlled MOS capacitor is implemented using a MOSFET whose gate is connected to the differential output, and whose source, drain, and body terminals are both connected to an auxiliary calibration voltage. Calibration is achieved by controlling the switch or calibration voltage with calibration information stored in memory during calibration mode. The offset voltage calibration range and accuracy of this method depend on the number of capacitors; more capacitors result in better calibration performance, but require additional storage units and control logic. This calibration method requires no additional power consumption after calibration, but increasing the load capacitance reduces the comparator speed.

[0004] Input stage current regulation compensates for the comparator's offset voltage by adjusting the current in the differential input branch of the comparator. Several methods exist for this current regulation, such as adjusting the substrate voltage of the input transistor pair, adding an adjustable input transistor array, and adjusting the gate voltage of the calibration input transistor. However, adjusting the substrate voltage requires additional process costs and carries the risk of the transistor failing to turn off due to excessively high substrate voltage. Adjustable input transistor arrays, by controlling the number of differential input transistors, create differences in the current in the differential branch, which can improve comparator speed to some extent, but this increases the parasitic capacitance of the comparator to the preceding circuitry, hindering overall performance improvement. Therefore, by adjusting the gate voltage of the calibration input transistor pair—one transistor gate connected to a fixed voltage, and the other gate connected to a calibration capacitor controlled by the calibration input circuit—the comparator offset voltage is compensated. In calibration mode, all comparator inputs are connected to a common-mode signal, amplifying and comparing the comparator's offset voltage. The voltage across the calibration capacitor is controlled based on this comparison result, causing a current mismatch in the calibration input transistor pair, thus compensating for the comparator's offset. This method does not affect the comparator speed or increase the parasitic capacitance of the preceding stage, but it requires multiple cycles of comparison and compensation to bring the offset to a smaller range.

[0005] Patent application CN201610933177.6 discloses a dynamic comparator and its offset calibration method. This method stores offset charge in calibration mode by connecting a charge storage capacitor in series at the input of the dynamic comparator and using a charge / discharge switch, a common-mode switch, a first calibration control switch, and a second calibration control switch. This offset voltage is then canceled out during normal comparison. While this method does not require the entire comparator to participate in calibration, the presence of an offset charge storage capacitor in series at the comparator input affects the operation of the pre-amplifier circuitry, thus impacting the overall performance of the ADC. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the prior art by proposing a comparator offset calibration device based on adjusting the gate voltage of the calibration input transistor, thereby reducing the comparison and compensation cycle, accelerating the offset calibration speed, and ensuring the performance of the entire analog-to-digital converter (ADC).

[0007] The technical solution to achieve the purpose of this invention is as follows: by adjusting the gate voltage of the calibration input transistor and simultaneously using the overall trend of the comparison results of the comparator in calibration mode, the gate voltage change step size of the calibration input transistor is adjusted to reduce the comparison and compensation cycle; by connecting an additional calibration input transistor in parallel at the input of the comparator and adding a calibration capacitor only at the gate of the calibration transistor, the performance of the comparator pre-stage circuit is guaranteed.

[0008] Based on the above ideas, the present invention provides an offset calibration device based on calibration input transistor gate voltage adjustment, comprising a comparator, a calibration voltage control circuit, a calibration control logic circuit, and a calibration input circuit, characterized in that:

[0009] The calibration voltage control circuit is used to dynamically adjust the step size of the calibration voltage change. It includes a calibration capacitor, a calibration enable AND gate, a NAND gate, a step size charge / discharge inverter array, and a calibration step size control capacitor array. The calibration capacitor is connected to the calibration input circuit. The calibration enable AND gate and NAND gate are both connected to the output of the comparator. The input of the step size charge / discharge inverter array is connected to the output of the calibration control logic. The step size control capacitor array is connected to the calibration capacitor through the step size charge / discharge inverter array.

[0010] The calibration control logic circuit is used to generate enable control signals of different step lengths in the calibration voltage control circuit. It includes an output result register chain, a calibration enable control AND gate array, a step size control NAND gate array, and a step size control AND gate array. The input terminal of the output result register chain is connected to a comparator, the reset terminal is connected to the calibration enable control AND gate array, and the output terminal is connected to the input terminal of the step size control NAND gate array and the step size control AND gate array. The output terminal of the step size control NAND gate array and the step size control AND gate array is connected to the input terminal of the calibration voltage control circuit. The calibration enable control AND gate array is connected to the output terminal of the comparator.

[0011] Furthermore, the step-size charge / discharge inverter array includes eight inverters for charging and discharging the calibration step-size control capacitor.

[0012] The first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 are all connected to the power supply at their power supply terminals, and their ground terminals are all connected to the gate of transistor MC2 in the calibration input circuit. Their input terminals are respectively connected to the output terminal of the calibration enable AND gate and the three output terminals of the step control AND gate array. Their output terminals are all connected to the calibration step control capacitor.

[0013] The ground terminals of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8 are all connected to the power supply ground. Their power supply terminals are all connected to the gate of transistor MC2 in the calibration input circuit. Their input terminals are respectively connected to the output terminal of the calibration enable AND gate and the three output terminals of the step size control AND gate array. Their output terminals are all connected to the calibration step size control capacitor.

[0014] Furthermore, the calibration step size control capacitor array includes eight capacitors for storing calibration charge;

[0015] The first capacitor C1, the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7 are all connected to ground at one end, and the other end is connected to the output terminal of the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 respectively.

[0016] The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 each have one end connected to ground, and the other end connected to the output terminals of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8, respectively.

[0017] Furthermore, the output result register chain includes 10 D flip-flops for storing the comparison results of the comparator;

[0018] The inputs of the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 are respectively connected to the power supply and the outputs of the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, and the fourth flip-flop D4. Their clock inputs are all connected to the comparator's positive output signal OUTP. The reset terminal of the first flip-flop D1 is connected to the calibration enable control AND gate array. The reset terminals of the second flip-flop D2, the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 are connected to the output of the first flip-flop D1.

[0019] The inputs of the sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 are connected to the power supply and the outputs of the sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8, and the ninth flip-flop D9, respectively. Their clock inputs are all connected to the inverted output signal OUTN of the comparator. The reset terminal of the sixth flip-flop D6 is connected to the calibration enable control AND gate array, and the reset terminals of the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 are connected to the output of the sixth flip-flop D6.

[0020] Furthermore, the step size control NAND gate array includes three NAND gates, which are used to control the step size charge / discharge inverter array in the calibration step size control circuit;

[0021] The first NAND gate NAND1, the second NAND gate NAND2, and the third NAND gate NAND3 each have two inputs. One input is connected to the inverted output of the comparator, and the other input is connected to the outputs of the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 in the register chain, respectively. Their outputs are connected to the inputs of the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8, respectively.

[0022] Furthermore, the step size control AND gate array includes three AND gates, which are used to control the step size charge / discharge inverter in the calibration step size control circuit;

[0023] The first AND gate AND1, the second AND gate AND2, and the third AND gate AND3 each have two input terminals. One input terminal is connected to the non-inverting output terminal of the comparator, and the other input terminal is connected to the output terminals of the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 in the register chain, respectively. The output terminals of these three AND gates are connected to the input terminals of the third inverter INV3, the fifth inverter INV5, and the seventh inverter INV7, respectively.

[0024] Furthermore, the calibration enable control AND gate array includes two AND gates used to control the reset terminal of the output result register chain;

[0025] The fourth AND gate AND4 has two inputs. One input is connected to the calibration enable signal CAL_EN, and the other input is connected to the inverted signal of the comparator's inverted output OUTN. Its output is connected to the reset terminal of the first flip-flop D1. The fifth AND gate AND5 has two inputs. One input is connected to the calibration enable signal CAL_EN, and the other input is connected to the inverted signal of the comparator's non-inverted output OUTP. Its output is connected to the reset terminal of the sixth flip-flop D6.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] Firstly, this invention designs an offset calibration device that includes a calibration control logic circuit and a calibration voltage control circuit. The comparison result of the comparator is stored in the register chain in the calibration control logic circuit, and after processing by the step size control AND gate and NAND gate array, different control signals are output and transmitted to the calibration voltage control circuit to adjust the calibration voltage. This not only speeds up the change of the calibration voltage, but also greatly improves the offset calibration speed of the circuit.

[0028] Secondly, this invention receives the comparison result of the comparator in calibration mode through the calibration voltage control circuit, and connects the capacitors with different potentials in the step size control capacitor array to the calibration capacitor, so that the charge on the step size control capacitor and the calibration capacitor share the charge to control the change of calibration voltage, without the need for an additional current source, thus saving the power consumption of the calibration circuit and ensuring the accuracy of offset calibration. Attached Figure Description

[0029] Figure 1 This is the overall circuit block diagram of the present invention;

[0030] Figure 2 This is a schematic diagram of the dynamic comparator and calibration input circuit in this invention;

[0031] Figure 3 This is a circuit diagram of the calibration voltage control circuit in this invention;

[0032] Figure 4 This is a circuit diagram of the calibration control logic in this invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0034] Reference Figure 1 This example is a comparator offset calibration device based on adjusting the gate voltage of the calibration input transistor. It includes a comparator 1, a calibration voltage control circuit 2, a calibration control logic circuit 3, and a calibration input circuit 4. The non-inverting and inverting outputs of the comparator 1 are simultaneously connected to the first and second inputs of the calibration voltage control circuit 2 and the first and second inputs of the calibration control logic circuit 3. The third to eighth inputs of the calibration voltage control circuit 2 are connected to the first to sixth outputs of the calibration control logic circuit 3. The output of the calibration voltage control circuit 2 is connected to the input of the calibration input circuit 4. The output of the calibration input circuit 4 is connected to the input of the comparator 1. Wherein:

[0035] Comparator 1 adopts a pre-amplified dynamic comparator architecture, including a pre-amplifier circuit 11 and an output latch circuit 12. The pre-amplifier circuit 11 is used to initially amplify the input signal. Its input terminal is connected to a set of differential voltage signals INP and INN. Its output terminal is connected to the output terminal of the calibration input circuit 4 and together they are connected to the input terminal of the output latch circuit 12. The output latch circuit 12 is used to latch the comparison result of the comparator and output the comparison result to the input terminal of the calibration step size control circuit 2 and the calibration control logic circuit 3.

[0036] The calibration voltage control circuit 2 includes a calibration capacitor 21, a calibration enable AND gate 22, a NAND gate 23, a step-size charge / discharge inverter array 24, and a calibration step-size control capacitor array 25. The calibration capacitor 21 is connected to the input terminal of the calibration input circuit 4. The calibration enable AND gate 22 has two input terminals: one connected to the calibration enable signal CAL_EN, and the other connected to the comparator's positive output OUTP. Its output is connected to the first input terminal of the step-size control inverter array 24. The calibration enable NAND gate 23 has two input terminals: one connected to the calibration enable signal CAL_EN, and the other connected to the comparator's inverted output OUTN. Its output is connected to the second input terminal of the step-size control inverter array 24. The third to eighth input terminals of the step-size charge / discharge inverter array 24 are also connected to the first to sixth output terminals of the calibration control logic circuit 3. The step-size control capacitor array 25 is connected to the calibration capacitor 21 through the step-size charge / discharge inverter array 24.

[0037] The calibration control logic circuit 3 includes an output result register chain 31, a calibration enable control AND gate array 32, a step size control NAND gate array 33, and a step size control AND gate array 34. The two inputs of the register chain 31 are connected to the two outputs of the comparator 1 to store the comparison result of the comparator 1 and transmit the comparison result to the step size control NAND gate array 33 and the AND gate array 34. The output of this array is connected to the input of the calibration voltage control circuit 2. The calibration enable control AND gate array 32 has three inputs. One input is connected to the calibration enable signal CAL_EN, and the other two inputs are connected to the inverted signals of the two outputs of the comparator 1. Its output is connected to the reset terminal of the register chain 31.

[0038] The calibration input circuit 4 includes two transistors MC1 and MC2. The input terminal of transistor MC1 is connected to the common-mode voltage VCM, and the input terminal of transistor MC2 is connected to the output terminal of the calibration voltage control circuit 2. Transistors MC1 and MC2 are used to convert the calibration voltage output by the calibration control circuit 2 into an offset compensation current. This offset compensation current is connected to the output terminals FN and FP of the pre-amplification circuit 11 in comparator 1 through the output terminals of transistors MC1 and MC2 to cancel the offset voltage of the comparator.

[0039] The working principle of the above comparator offset calibration device is as follows:

[0040] Set the calibration enable signal CAL_EN to high level to enter calibration mode, connect all input terminals of comparator 1 to the common-mode voltage VCM, and charge the gates of calibration transistors MC1 and MC2 in calibration input circuit 4 to the common-mode voltage VCM; set the clock signal CLK of comparator 1 to enter the comparison state, and compare it with the common-mode voltage VCM. The comparison result is transmitted to calibration voltage control circuit 2 and calibration control logic circuit 3.

[0041] The output result register chain 31 in the calibration control logic circuit 3 stores the comparison result of the comparator 1. The register chain 31 transmits the stored result to the step size control NAND gate array 33 and the step size control AND gate array 34. The step size control NAND gate array 33 and the NAND gate array 34 process the stored comparison result and output different control signals to the calibration voltage control circuit 2.

[0042] The step charge-discharge inverter array 24 in the calibration voltage control circuit 2 receives the comparison result of the comparator 1 and the control signal of the calibration control logic circuit 3, thereby connecting with different capacitors in the calibration step control capacitor array 25 to adjust the step size of the calibration voltage change and transmit it to the calibration transistor MC2 in the calibration input circuit 4.

[0043] As the calibration voltage changes, the calibration transistor MC2 in the calibration input circuit 4 quickly calibrates the offset voltage of comparator 1 to the convergence range, interrupting the continuous comparison result of comparator 1, and transmitting a reset signal to the register chain 31 in the calibration control logic circuit 3.

[0044] After register chain 31 in calibration control logic circuit 3 enters the reset state, it outputs a control signal to calibration voltage control circuit 2, so that the calibration voltage step size is restored to the initial step size. After a period of calibration time, it reaches the final high calibration accuracy and completes the offset calibration.

[0045] The following are examples of the circuit structures in a comparator offset calibration device:

[0046] Example 1: Circuit structure of comparator 1 and calibration input circuit 4.

[0047] Reference Figure 2 The pre-amplifier circuit 11, output latch circuit 12, and calibration input circuit 4 in comparator 1 of this example have the following structures:

[0048] The pre-amplifier circuit 11 includes two differential input transistors M2 and M3, a first tail current transistor M1, and two reset transistors M4 and M5. The gates of the differential input transistors M2 and M3 are connected to the input terminals INP and INN, respectively, and their drains are connected to the drains of the two reset transistors M4 and M5, respectively. Their sources are both connected to the drain of the first tail current transistor M1. The gate of the first tail current transistor M1 is connected to the comparator input clock CLK, and its source is grounded. The gates of the reset transistors M4 and M5 are both connected to the clock signal CLK, and their sources are connected to the power supply.

[0049] The output latch circuit 12 includes a second tail current transistor M6, four latch transistors M7-M10, and two latch input transistors M11 and M12. The gate of the second tail current transistor M6 is connected to the inverted clock signal CLKB, the source is connected to the power supply, and the drain is connected to the source of the first latch transistor M7 and the second latch transistor M8. The drains of the first latch transistor M7 and the second latch transistor M8 are connected to the drains of the third latch transistor M9 and the fourth latch transistor M10, respectively. The source and drain of the first latch input transistor M11 and the second latch input transistor M12 are connected to the source and drain of the third latch transistor M9 and the fourth latch transistor M10, respectively, and their sources are all grounded.

[0050] The drain of the first latching input transistor M11 of the output latch circuit 12 is connected to the drain of the second differential input transistor M3 of the pre-amplifier circuit 11; the drain of the second latching input transistor M12 of the output latch circuit 12 is connected to the drain of the first differential input transistor M2 of the pre-amplifier circuit 11.

[0051] The calibration input circuit 4 includes two calibration transistors MC1 and MC2; the first calibration transistor MC1 is connected to the common-mode voltage VCM, and the gate of the second calibration transistor MC2 is connected to the calibration voltage VCARN. The sources of both calibration transistors are connected to the drain of the first tail current transistor M1; the drain of the first calibration transistor MC1 is connected to the output terminal FN of the pre-amplifier circuit 11, and the drain of the second calibration transistor MC2 is connected to the output terminal FP of the pre-amplifier circuit 11.

[0052] Example 2: Circuit structure of calibration voltage control circuit 2.

[0053] Reference Figure 3 The calibration voltage control circuit 2 in this example includes a step-size charge / discharge inverter array 24 and a calibration step-size control capacitor array 25, the structures of which are as follows:

[0054] The step-size charge / discharge inverter array 24 includes inverters INV1 to INV8. The power supply terminals of inverters INV1, INV3, INV5, and INV7 are all connected to a power source, their ground terminals are all connected to the gate of the second calibration transistor MC2 in the calibration input circuit 4, and their output terminals are all connected to the calibration step-size control capacitor 25. The input terminal of inverter INV1 is connected to the output terminal of the calibration enable AND gate 22. The input terminals of inverters INV3, INV5, and INV7 are respectively connected to the calibration control... The third to fifth output terminals of logic circuit 3 are connected; the ground terminals of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8 are all connected to the power supply ground, and their power supply terminals are all connected to the gate of the second calibration transistor MC2 in the calibration input circuit 4. Their output terminals are all connected to the calibration step size control capacitor 25; the input terminal of the second inverter INV2 is connected to the output terminal of the calibration enable NAND gate 23; the input terminals of the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8 are respectively connected to the sixth to eighth output terminals of the calibration control logic circuit 3.

[0055] The calibration step size control capacitor array 25 includes a first capacitor C1 to an eighth capacitor C8; one end of the first capacitor C1, the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7 are all connected to ground, and the other end is connected to the output terminal of the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 respectively; one end of the second capacitor C2, the fourth capacitor C4, the sixth capacitor C6 and the eighth capacitor C8 are all connected to ground, and the other end is connected to the output terminal of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6 and the eighth inverter INV8 respectively.

[0056] Example 3: Circuit structure of calibration control logic circuit 3.

[0057] Reference Figure 4 The calibration control logic circuit 3 in this example includes an output result register chain 31, a calibration enable control AND gate array 32, a step size control AND-NOT gate array 33, and a step size control AND gate array 34, the structures of which are as follows:

[0058] The output result register chain 31 includes the first flip-flop D1 to the tenth flip-flop D10; the input terminals of the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 are respectively connected to the power supply, the output terminals of the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, and the fourth flip-flop D4, and their clock inputs are all connected to the positive output signal OUTP of comparator 1; the reset terminal of the first flip-flop D1 is connected to the calibration enable signal; the reset terminals of the second flip-flop D2, the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 are also connected to the power supply, the output terminals of the first flip-flop D2, the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 are also connected to the power supply, the output terminals of the first flip-flop D2, the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 are also connected to the power supply, the output terminals of the first flip-flop D1, the output terminals of the second ... The input terminals of the sixth, seventh, eighth, ninth, and tenth flip-flops D6, D7, D8, D9, and D10 are respectively connected to the power supply and the output terminals of the sixth, seventh, eighth, and ninth flip-flops D9. Their clock inputs are all connected to the inverted output signal OUTN of the comparator. The reset terminal of the sixth flip-flop D6 is connected to the calibration enable signal, and the reset terminals of the seventh, eighth, ninth, and tenth flip-flops D9 are connected to the output terminal of the sixth flip-flop D6.

[0059] The step-size control NAND gate array 33 includes a first NAND gate NAND1, a second NAND gate NAND2, and a third NAND gate NAND3. Each of the first, second, and third NAND gates NAND1, NAND2, and NAND3 has two input terminals. One input terminal is connected to the inverting output terminal of a comparator, and the other input terminal is connected to the output terminals of the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 in the register chain 31, respectively. Its output terminals are connected to the input terminals of the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8, respectively.

[0060] The step-size control AND gate array 34 includes a first AND gate AND1, a second AND gate AND2, and a third AND gate AND3. Each of the first AND gate AND1, the second AND gate AND2, and the third AND gate AND3 has two input terminals. One input terminal is connected to the non-inverting output terminal of the comparator, and the other input terminal is connected to the output terminals of the third flip-flop D3, the fourth flip-flop D4, and the fifth flip-flop D5 in the register chain 31, respectively. The output terminals of these three AND gates are connected to the input terminals of the third inverter INV3, the fifth inverter INV5, and the seventh inverter INV7, respectively.

[0061] The calibration enable control AND gate array 32 includes a fourth AND gate AND4 and a fifth AND gate AND5. The fourth AND gate AND4 has two input terminals: one input terminal is connected to the calibration enable signal CAL_EN, and the other input terminal is connected to the inverted signal of the inverted output terminal OUTN of comparator 1. Its output terminal is connected to the reset terminal of the first flip-flop D1. The fifth AND gate AND5 has two input terminals: one input terminal is connected to the calibration enable signal CAL_EN, and the other input terminal is connected to the inverted signal of the non-inverted output terminal OUTP of comparator 1. Its output terminal is connected to the reset terminal of the sixth flip-flop D6.

[0062] Example 4: A method for comparator misalignment calibration based on the above-described device.

[0063] The calibration enable signal CAL_EN is set to a high level and transmitted to the calibration enable AND gate 22, calibration enable NAND gate 23 in the calibration voltage control circuit 2 and the calibration enable control AND gate array 32 in the calibration control logic circuit 3, so that the offset calibration device enters the calibration mode.

[0064] The input of comparator 1 is connected to the common-mode voltage VCM, and the gates of calibration transistors MC1 and MC2 in calibration input circuit 4 are charged to the common-mode voltage VCM. The clock signal CLK of comparator 1 is set to enter the comparison state, and the common-mode voltage VCM is compared. The comparison result is transmitted to calibration voltage control circuit 2 and calibration control logic circuit 3. Due to the existence of offset voltage, the comparison result of comparator 1 will always be high or low.

[0065] When the number of consecutive high-level comparisons is 3, 4, and 5, respectively, the third D flip-flop D3, the fourth D flip-flop D4, and the fifth D flip-flop D5 in register chain 31 of calibration control logic circuit 3 output high levels in sequence, which are transmitted to step control AND gate array 34. This causes the first AND gate AND1, the second AND gate AND2, and the third AND gate AND3 in it to output high-level control signals in sequence, which are transmitted to step charge-discharge inverter array 24 in calibration voltage control circuit 2. This causes the third inverter INV3, the fifth inverter INV5, and the seventh inverter INV7 in it to connect the third capacitor C3, the fifth capacitor C5, and the seventh capacitor C7 in sequence, thereby increasing the calibration voltage at the gate of the second calibration transistor MC2 in calibration input circuit 4 and increasing the speed of calibration voltage change.

[0066] When the comparison result shows a continuous low level for 3, 4, and 5 times respectively, the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 of the register chain 31 in the calibration control logic circuit 3 output high levels in sequence, which are transmitted to the step control NAND gate array 33. This causes the first NAND gate NAND1, the second NAND gate NAND2, and the third NAND gate NAND3 to output high-level control signals in sequence, which are then transmitted to the step charge-discharge inverter array 24 in the calibration voltage control circuit 2. This causes the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8 to connect the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 in sequence, thereby reducing the calibration voltage at the gate of the second calibration transistor MC2 in the calibration input circuit 4 and increasing the speed of calibration voltage change.

[0067] As the calibration voltage changes, the second calibration transistor MC2 of the calibration input circuit 4 quickly calibrates the offset voltage of comparator 1 to the convergence range, interrupting the continuous comparison result of comparator 1. This comparison result is converted into a reset signal by the calibration enable control AND gate array 32 in the calibration control logic circuit 3, and resets the output result register chain 31 therein. After the register chain 31 enters the reset state, it outputs a control signal to the calibration voltage control circuit 2, so that the calibration voltage step size is restored to the initial step size. After a period of calibration time, it reaches the final high calibration accuracy, completing the offset calibration.

[0068] The above descriptions are merely a few specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. For example, in addition to the 8 units given in this example, the number of units in the step-size control inverter array can be increased or decreased; in addition to the 8 units given in this example, the number of units in the step-size control capacitor array can be increased or decreased; in addition to the 10 units given in this example, the number of units in the output result register chain can be increased or decreased; in addition to the unit ratio given in this example, the ratio of the step-size control capacitor array can be modified; and the connection relationships of the components in each circuit can be other than those given in this example. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A comparator offset calibration device based on adjusting the gate voltage of a calibration input transistor, comprising a comparator (1), a calibration voltage control circuit (2), a calibration control logic circuit (3), and a calibration input circuit (4), characterized in that: The calibration voltage control circuit (2) is used to dynamically adjust the step size of the calibration voltage change. It includes a calibration capacitor (21), a calibration enable AND gate (22), a NAND gate (23), a step size charge / discharge inverter array (24), and a calibration step size control capacitor array (25). The calibration capacitor (21) is connected to the calibration input circuit (4). The calibration enable AND gate (22) and the NAND gate (23) are both connected to the output of the comparator (1). The input of the step size charge / discharge inverter array (24) is connected to the output of the calibration control logic (3). The step size control capacitor array (25) is connected to the calibration capacitor (21) through the step size charge / discharge inverter array (24). The calibration control logic circuit (3) is used to generate enable control signals of different step lengths in the calibration voltage control circuit. It includes an output result register chain (31), a calibration enable control AND gate array (32), a step size control AND gate array (33), and a step size control AND gate array (34). The input terminal of the output result register chain (31) is connected to the comparator (1), the reset terminal is connected to the calibration enable control AND gate array (32), and the output terminal is connected to the input terminals of the step size control AND gate array (33) and the step size control AND gate array (34). The output terminals of the step size control AND gate array (33) and the step size control AND gate array (34) are connected to the input terminal of the calibration voltage control circuit (2). The calibration enable control AND gate array (32) is connected to the output terminal of the comparator (1). The step-size charge / discharge inverter array (24) includes eight inverters INV1 to INV8, which are used to charge and discharge the calibration step-size control capacitor. The first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 are all connected to the power supply, and their ground terminals are all connected to the gate of transistor MC2 in the calibration input circuit. Their input terminals are respectively connected to the output terminal of the calibration enable AND gate (22) and the three output terminals of the step-size control AND gate array (34). Their output terminals are all connected to the calibration step-size control capacitor. The output result register chain (31) includes 10 D flip-flops D1~D10, used to store the comparison results of the comparator; the input terminals of the first flip-flop D1, the second flip-flop D2, the third flip-flop D3, the fourth flip-flop D4 and the fifth flip-flop D5 are respectively connected to the power supply, the output terminals of the first flip-flop D1, the second flip-flop D2, the third flip-flop D3 and the fourth flip-flop D4, and their clock inputs are all connected to the comparator's positive output signal OUTP; the reset terminal of the first flip-flop D1 is connected to the calibration enable control AND gate array (32); the reset terminals of the second flip-flop D2, the third flip-flop D3, the fourth flip-flop D4 and the fifth flip-flop D5 are connected to the output terminal of the first flip-flop D1; The step size control AND gate array (34) includes three AND gates AND1~AND3, which are used to control the step size charge and discharge inverter (24) in the calibration step size control circuit. The first AND gate AND1, the second AND gate AND2 and the third AND gate AND3 each have two input terminals, and one input terminal is connected to the positive output terminal of the comparator (1), and the other input terminal is connected to the output terminals of the third flip-flop D3, the fourth flip-flop D4 and the fifth flip-flop D5 in the register chain (31), respectively. The output terminals of these three AND gates are connected to the input terminals of the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7, respectively.

2. The apparatus according to claim 1, characterized in that: The ground terminals of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8 are all connected to the power supply ground. Their power supply terminals are all connected to the gate of transistor MC2 in the calibration input circuit. Their input terminals are respectively connected to the output terminal of the calibration enable NAND gate (23) and the three output terminals of the step size control NAND gate array (33). Their output terminals are all connected to the calibration step size control capacitor.

3. The apparatus according to claim 1, characterized in that, The calibration step size control capacitor array (25) contains eight capacitors C1 to C8 for storing calibration charge; The first capacitor C1, the third capacitor C3, the fifth capacitor C5 and the seventh capacitor C7 are all connected to ground at one end, and the other end is connected to the output terminal of the first inverter INV1, the third inverter INV3, the fifth inverter INV5 and the seventh inverter INV7 respectively. The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 each have one end connected to ground, and the other end connected to the output terminals of the second inverter INV2, the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8, respectively.

4. The apparatus according to claim 1, characterized in that: The input terminals of the sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 are respectively connected to the power supply and the output terminals of the sixth flip-flop D6, the seventh flip-flop D7, the eighth flip-flop D8, and the ninth flip-flop D9. Their clock inputs are all connected to the inverted output signal OUTN of the comparator. The reset terminal of the sixth flip-flop D6 is connected to the calibration enable control AND gate array (32), and the reset terminals of the seventh flip-flop D7, the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 are connected to the output terminal of the sixth flip-flop D6.

5. The apparatus according to any one of claims 1-4, characterized in that, The step size control NAND gate array (33) includes three NAND gates NAND1 to NAND3, which are used to control the step size charge and discharge inverter array (24) in the calibration step size control circuit. The first NAND gate NAND1, the second NAND gate NAND2, and the third NAND gate NAND3 each have two input terminals. One input terminal is connected to the inverted output terminal of the comparator (1), and the other input terminal is connected to the output terminals of the eighth flip-flop D8, the ninth flip-flop D9, and the tenth flip-flop D10 in the register chain (31), respectively. Their output terminals are connected to the input terminals of the fourth inverter INV4, the sixth inverter INV6, and the eighth inverter INV8, respectively.

6. The apparatus according to any one of claims 1-4, characterized in that, The calibration enable control AND gate array (32) includes two AND gates, a fourth AND gate AND4 and a fifth AND gate AND5, which are used to control the reset terminal of the output result register chain (31). The fourth AND gate AND4 has two input terminals. One input terminal is connected to the calibration enable signal CAL_EN, and the other input terminal is connected to the inverted signal of the inverted output terminal of the comparator (1). Its output terminal is connected to the reset terminal of the first flip-flop D1. The fifth AND gate AND5 has two input terminals. One input terminal is connected to the calibration enable signal CAL_EN, and the other input terminal is connected to the inverted signal of the non-inverted output terminal of the comparator (1). Its output terminal is connected to the reset terminal of the sixth flip-flop D6.

7. The offset calibration device according to claim 1, characterized in that, The comparator (1) employs a pre-amplified dynamic comparator, which includes: The pre-amplifier circuit (11) is used to initially amplify the comparator input signal and reduce the comparator input noise; The output latch circuit (12) is used to latch the comparison result of the comparator and output it to the calibration voltage control circuit (2).

8. The offset calibration device according to claim 7, characterized in that: The pre-amplification circuit (11) includes input transistors M2 and M3, tail current transistor M1, and transistors M4 and M5; the gates of M2 and M3 are connected to the input terminals INP and INN respectively, and their drains are connected to the drains of M4 and M5 respectively; the gate of the tail current transistor M1 is connected to the comparator input clock CLK, and its source is grounded; the gates of transistors M4 and M5 are connected to CLK, and their sources are connected to the power supply; The output latch circuit (12) includes a tail current transistor M6 and transistors M7-M12. The gate of the tail current transistor M6 is connected to the inverted CLKB of the clock CLK, the source is connected to the power supply, and the drain is connected to the source of transistors M7 and M8. The drains of transistors M7 and M8 are connected to the output nodes OUTN and OUTP of the comparator, respectively. The source and drain of transistors M11 and M12 are connected to the source and drain of M9 and M10, respectively, and the source is grounded. The gate of transistor M12 in the output latch circuit (12) is connected to the drain of transistor M2 in the pre-amplifier circuit (11). The gate of transistor M11 in the output latch circuit (12) is connected to the drain of transistor M3 in the pre-amplifier circuit (11).

9. The offset calibration device according to claim 1, characterized in that, The calibration input circuit (4) includes two transistors MC1 and MC2, which are used to cancel the offset voltage of the comparator. The sources of transistors MC1 and MC2 are connected to the drain of transistor M1 in the pre-amplifier circuit (11), and their drains are connected to the output terminals FN and FP of the pre-amplifier circuit (11) respectively. Their gates are connected to the output terminals VCALP and VCARN of the calibration voltage control circuit (2) respectively.

10. A method for comparator misalignment calibration using the apparatus of claim 1, characterized in that, Including the following: Set the calibration enable signal CAL_EN to a high level to enter the calibration mode, connect the input of comparator (1) to the common mode voltage VCM, and charge the gates of transistors MC1 and MC2 of the calibration input circuit (4) to the common mode voltage VCM. Set the clock signal CLK of comparator (1) to make it enter the comparison state, compare it with the common mode voltage VCM, and output a high level or low level to the calibration control logic circuit (3). The calibration control logic circuit (3) stores and processes the comparison result of the comparator (1), and outputs different control signals to the calibration voltage control circuit (2) according to the number of consecutive comparison results. The calibration voltage control circuit (2) adjusts the step size of the calibration voltage according to different control signals and transmits it to the transistor MC2 in the calibration input circuit (4); As the calibration voltage changes, transistor MC2 in the calibration input circuit (4) quickly calibrates the offset voltage of comparator (1) to the convergence range, interrupting the comparison result of comparator (1) and transmitting a reset signal to the register chain (31) in the calibration control logic circuit (3). After the register chain (31) in the calibration control logic circuit (3) enters the reset state, it outputs a control signal to the calibration voltage control circuit (2) to restore the calibration voltage step size to the initial step size. After a period of calibration time, it achieves the final high calibration accuracy and completes the offset calibration.

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