Pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection

Abstract

The present application relates to a kind of pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection, belong to analog integrated circuit technical field.After the residual error signal is obtained in the first stage SAR ADC quantization, pseudo-random sequence is injected in the residual error signal, the superimposed signal is sampled and converted by the later stage ADC, finally cause nonlinear error in digital code output code, then the sequence input and digital output code are correlated to obtain the error information of non-ideal factor in circuit, finally the actual interstage gain value in circuit is approximated by variable step iterative algorithm for digital code reconstruction analog signal, finally reach the effect of calibration.The present application can avoid the influence of step on speed and accuracy in iterative process, be used to calibrate the interstage gain error caused by capacitor mismatch and the limited gain of operational amplifier, and in the iterative process of calibration, better speed and accuracy are realized, the performance of ADC is obviously improved, and signal-to-noise ratio and spurious-free dynamic range are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog integrated circuits, and relates to a pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection. BACKGROUND

[0002] Analog to Digital Converter (ADC) is an indispensable part of signal conversion link in modern electronic systems, and is one of the research hotspots in the field of integrated circuits in recent years. There are various types of analog to digital converters. The traditional pipeline analog to digital converter (Pipeline ADC) has the advantages of high speed and high precision, but has the problem of high power consumption; the successive approximation register analog to digital converter (SAR ADC) can meet the low power consumption requirement, but the speed and precision are limited to 100MS / s and 10-bit precision or less. The pipeline SAR ADC is a new type of structure combining SAR ADC and Pipeline ADC together. Compared with the traditional SAR ADC, the pipeline SAR ADC can have higher speed and precision, and compared with the traditional Pipeline ADC, the pipeline SAR ADC has lower power consumption, integrating the advantages of both. The structure of the pipeline SAR ADC is to connect multiple SAR ADCs in series, and insert a residue amplifier between each two sub-ADCs to amplify the residue value generated after the quantization of the previous stage sub-ADC, and send it to the next stage sub-ADC for continuous quantization.

[0003] There are various non-ideal factors in ADC, which will affect the noise and linearity of ADC and limit the performance of ADC, so it is necessary to use calibration technology to calibrate the errors caused by non-ideal factors in the pipeline SAR ADC. ADC calibration technology is mainly divided into analog domain and digital domain calibration. The analog domain calibration mainly achieves the purpose of calibration by increasing or modifying the specific circuit structure in the analog circuit. This method usually greatly improves the complexity of the circuit structure and the complexity of the circuit working timing, and the working speed of the ADC is also limited to a certain extent. The digital domain calibration mainly places the calibration module in the digital circuit, and the modification of the analog circuit structure is less. Generally, only a simple auxiliary structure needs to be added in the analog circuit. The basic principle is to estimate the error of the analog circuit system caused by non-ideal factors according to the final digital output signal, and then perform error extraction and other processing on the digital output signal, finally achieving the purpose of calibrating the error. With the progress of technology, the feature size of the tube is reduced, and the adaptability and portability of the digital domain calibration are stronger, and the integration is also higher.

[0004] The digital calibration technique mainly contains two core stages: error measurement and signal calibration. According to the difference of the execution process, the technique can be divided into two categories: foreground calibration and background calibration. Among them, the foreground calibration follows the principle of sequential execution, first the error measurement is carried out, and then the signal is calibrated; while the background calibration adopts the parallel processing mode, that is, the error measurement and the signal calibration are carried out at the same time. When the foreground calibration mode is adopted, the circuit system generally needs to add an independent calibration period, and the calibration process in this period cannot be synchronized with the conversion process of the ADC. The specific work flow is as follows: once the circuit is switched to the calibration mode, the first step is to introduce the calibration signal, then the calibration DAC will undertake the task of detecting the capacitance mismatch error, and store the detected data in a special memory. After completing this calibration step, the system immediately enters the normal quantization link, in which the ADC will perform corresponding compensation processing according to the previously stored capacitance mismatch error information, and finally achieve the intended goal of calibration. When the background calibration mode is adopted, it does not need an additional clock signal control, nor will it interrupt the normal conversion work of the ADC. This feature greatly improves the conversion rate of the ADC, so the background digital calibration technique is widely used in various types of analog-to-digital converters. The background digital calibration technique can be divided into LMS algorithm of adaptive filter, pseudo-random sequence injection calibration algorithm, signal-related pseudo-random sequence injection calibration algorithm, code domain equalization background digital calibration algorithm and time interleaving-based background digital calibration algorithm, etc.

[0005] However, the problem faced by the digital calibration technique is that in the actual ADC circuit, due to the process reasons, there is a manufacturing deviation between the two capacitors, that is, the capacitance mismatch, which will cause the inter-stage gain error in the pipeline SAR ADC. Secondly, the design of the operational amplifier is the key of the pipeline SAR ADC design. In theoretical analysis, it is often assumed that the gain of the operational amplifier is infinite, but in the actual circuit, the gain of the operational amplifier is limited. Compared with the ideal transmission characteristics, it will introduce an error coefficient. With the proportional reduction of the process size, the intrinsic gain of the transistor also decreases, making it more and more difficult to design a high-gain operational amplifier, thereby producing a larger error coefficient. These two factors will cause the inter-stage gain error, so the traditional digital calibration method is not suitable for the error calibration of the smaller size pipeline SAR ADC. SUMMARY

[0006] Therefore, the purpose of the present application is to provide a pipeline SAR ADC digital background calibration method based on pseudo-random sequence (i.e. Pseudo-random Noise, PN) injection, which is used to calibrate the inter-stage gain error caused by capacitance mismatch and limited gain of the operational amplifier, and to achieve better speed and accuracy in the iteration process of calibration.

[0007] To achieve the above object, the present application provides the following technical solutions:

[0008] A pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection, wherein the pipeline SAR ADC comprises a first-stage SAR ADC, a residue amplifier, and a second-stage SAR ADC, and the method comprises the following steps:

[0009] S1, sending an analog input signal to be processed into the first-stage SAR ADC. In this stage, the SAR ADC uses its binary search algorithm to accurately sample the input signal and convert it into a digital code.

[0010] S2, when the first-stage SAR ADC completes the conversion, a PN sequence (commonly known as an m-sequence or maximum length sequence) generated by a linear feedback shift register is superimposed on the residual signal generated in the conversion process of the first-stage SAR ADC. This superimposing operation aims to introduce a known but random disturbance to facilitate the identification and correction of potential errors in subsequent processing.

[0011] S3, the m-sequence modulated residual signal is sent to the second-stage SAR ADC for further sampling and conversion. This stage of ADC also uses the successive approximation method. After the conversion is completed, a digital code is obtained.

[0012] S4, in the digital domain, the overall digital output D out (composed of the digital codes output by the first-stage and second-stage SAR ADCs) of the pipeline SAR ADC is processed for correlation analysis with the previously introduced PN sequence.

[0013] Since the PN sequence is not corrected in the analog-to-digital converter, it will eventually cause a non-linear error in the final digital output code. This error contains the results of the non-ideal factors in the circuit acting on the PN signal. Under the condition that the PN sequence is long enough, this error is only related to the PN signal and has nothing to do with the input signal. Therefore, according to the characteristics of the PN sequence signal, only the correlation operation between the input PN sequence and the digital output code D out is needed to obtain the error information of the non-ideal factors in the circuit, which is represented by the correlation coefficient Ecor.

[0014] S5. Given the inter-stage gain error problem that pipelined SAR ADCs may encounter in practical applications, these errors can cause the actual gain to deviate from the ideal value, and this deviation is often unpredictable. To address this issue, an iterative method is used to estimate and adjust the gain value. Specifically, based on the correlation coefficient calculated in step S4, an iterative process is used to gradually approximate the estimated gain value rG to the true gain value. Furthermore, a logarithmic sigmoid function is introduced during the iteration process to dynamically adjust the iteration step size, ensuring that the convergence process is both fast and stable.

[0015] S6. Finally, the gain estimate rG obtained through iterative optimization is applied to the digital code reconstruction process of the pipeline SAR ADC. rG is used to correct the digital code output by the ADC, thereby reconstructing a more accurate analog signal.

[0016] In an ideal scenario, the interstage gain of a pipelined SAR ADC is a power of 2. The codewords from each stage are then added together by shifting the order of the outputs to synthesize the final digital code. However, when there is an interstage gain error, the interstage gain is no longer a power of 2. In this case, it is necessary to calculate the weights corresponding to each sub-stage digital code and sum the products of each stage's digital code and the weights to obtain the final digital output. In the final step of the calibration process, when reconstructing the analog signal from the digital code, the estimated value rG of the actual gain is used to calculate the weights at this time for the ADC's final digital output, which is then used to reconstruct the analog signal.

[0017] Furthermore, in step S4, for D out Correlation operations with PN sequences are generally performed by accumulating the data and then taking the average. The more times the data is accumulated, the closer the average is to the expected value. However, this method has high computational complexity and consumes a lot of resources in circuit implementation. Therefore, in the implementation, the sign bit is taken instead of the product value for accumulation, i.e., sign[D] out The update process of the correlation coefficient [(i)*PN(i)] can be expressed as:

[0018] Ecor = Ecor + sign[D] out (i)*PN(i)]

[0019] In the formula, Ecor represents the correlation coefficient, sign(·) represents the sign function, and D out This represents the final digital signal output by the pipelined SAR ADC, where PN represents the pseudo-random sequence and i represents the number of calibration samples.

[0020] Furthermore, in step S5, the iterative process of gradually approximating the estimated gain value rG to the true gain value is represented by the following equation:

[0021] rG(k+1) = rG(k) - step(k) * Ecor(k)

[0022] Wherein, step represents the iteration step, and k represents the number of calibration cycles.

[0023] Further, the convergence time and the misadjustment accuracy of the algorithm are controlled by the step, and the iteration step is an extremely important parameter, the convergence time is inversely proportional to the step, and the misadjustment accuracy is proportional to the step, that is, the smaller the step, the longer the convergence time, and the smaller the misadjustment, the larger the step, the shorter the convergence time, and the larger the misadjustment.

[0024] Therefore, in step S5, in the iteration process of realizing the convergence of the estimated value rG of the gain to the actual gain value, the step is adjusted through a logarithmic sigmoid function according to the number of calibration cycles, so as to realize the trade-off between the iteration process speed and the accuracy, the step is larger in the initial stage of calibration, so as to quickly approach the target value, and with the progress of the calibration cycle, the step gradually decreases, so that the calibration becomes more accurate.

[0025] Wherein, the logarithmic sigmoid function can be expressed as:

[0026] step(k) = 2beta {1.4 + log [1 + exp(|Ecor(k)| -2 ]}

[0027] Wherein, alpha and beta represent control coefficients, alpha is used to control the shape of the function, and beta is used to control the value range of the function.

[0028] The present application has the advantages that the present application can avoid the influence of the iteration process step on the speed and the accuracy, is used for calibrating the inter-stage gain error caused by the capacitor mismatch and the limited gain of the operational amplifier, realizes the better speed and the accuracy in the iteration process of the calibration, obviously improves the performance of the ADC, and improves the signal-to-noise ratio and the spurious-free dynamic range.

[0029] Other advantages, objects, and features of the present application will be apparent to those skilled in the art from the following specification, and will be learned from the practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the following specification. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to make the objects, technical solutions and advantages of the present application clearer, the preferred detailed description of the present application will be combined with the drawings, and the drawings are as follows:

[0031] Figure 1 The flowchart of the method of the present application is shown in the figure;

[0032] Figure 2 Fig. 1 is a schematic diagram of the principle of generating m sequence;

[0033] Figure 3 Fig. 2 is a schematic diagram of simulation of logarithmic sigmoid function;

[0034] Figure 4 Fig. 3 is a comparison diagram of FFT simulation before and after calibration, Figure 4 (a) is a simulation result before calibration, Figure 4 (b) is a simulation result after calibration. DETAILED DESCRIPTION

[0035] The present application is described and explained with additional specificity and detail through the use of the accompanying drawings in which:

[0036] The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the application and, together with the description, serve to explain the principles of the application. In the drawings:

[0037] The same or similar components in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only for illustrative purposes, and cannot be understood as a limitation of the present application, for those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0038] The application is directed to an inter-stage gain error caused by a capacitor mismatch and a limited gain of an operational amplifier, and proposes a pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection. The pseudo-random sequence, i.e. pseudo-random noise, is a carefully designed and highly characteristic sequence, and its uniqueness is reflected in two main aspects. First, it has predictability and repeatability, i.e. these sequences are not randomly generated, but are generated according to certain deterministic rules or algorithms, so that each element of the sequence can be calculated in advance under the condition of knowing the rules or algorithms, and the sequence can also be repeatedly generated and copied as needed without losing its original structure and characteristics. Second, the pseudo-random sequence also exhibits a random characteristic similar to a truly random sequence, mainly in its statistical characteristics, such as the expectation E[PN] = 0, the variance σ[PN] = 1, the autocorrelation characteristic cross-correlation characteristic Most pseudo-random sequences are generated by shift register feedback, which has a simple structure, is easy to implement, and can easily generate sequences with a very long period. Commonly used pseudo-random sequences include m-sequences, M-sequences, and Gold sequences, and the currently widely used pseudo-random sequence is the m-sequence. Meanwhile, the embodiment also uses the m-sequence.

[0039] An m-sequence is mainly composed of elements 0 and 1 or 1 and -1. In an m-sequence, the probability of occurrence of two different elements (such as 0 and 1, or 1 and -1) for any bit is equal, and the distribution of this probability is independent and does not affect each other between different bits, which is called the balance of the m-sequence. The m-sequence also has a very important autocorrelation characteristic. In addition, when the m-sequence is long enough, its power spectrum characteristic tends to that of white noise, so the m-sequence also has a cross-correlation characteristic that is not related to other signals. An m-sequence is generally generated by a linear feedback shift register, which is composed of multiple registers, and the output of each register is used as the input of the next register to form a shift chain. The feedback line (C0, C1, …, Cn) is connected to the input of the register to form a feedback loop, and when Ci is 1, it indicates that the i-th register is connected to the feedback loop, and when it is 0, it indicates that the i-th register is not connected to the feedback loop. Generally, the values of C0 and Cn are determined to be 1. The feedback connection state of the linear feedback shift register is described by a characteristic polynomial, and when designing the characteristic polynomial to generate the m-sequence, a specific primitive polynomial is generally selected.

[0040] For a two-stage pipeline SAR ADC using MDAC modulation, as shown in Figure 1 , a pseudo-random sequence is injected at the first stage residual error, and the corresponding digital ideal value of the final output is represented as:

[0041]

[0042] Wherein D1 is the digital code generated by the first stage SAR ADC quantization, V res is the input signal of the back end, r is the coefficient of PN sequence, since the inter-stage gain value in the actual circuit is unknown, the gain estimation value is used. Figure 1 D2 is the digital code generated by the second stage ADC actual quantization, D1 and D2 are expressed in the analog domain as:

[0043] D1=V in -Q1

[0044] D2=V res +Q2=G·(Q1+r·PN)+Q2

[0045] Wherein Q1 is the quantization error of the first stage, Q2 is the error generated by the second stage quantization, G is the equivalent inter-stage gain value related to the open loop gain of the operational amplifier and the ratio of capacitance, and V res D1 can be expressed as: out Also can be expressed as:

[0046]

[0047] D1 is replaced by D out Correlation processing with the PN sequence is performed, that is According to the autocorrelation characteristics and cross-correlation characteristics of the PN sequence, the following is obtained: In the algorithm implementation, the sign function is used instead of multiplication to solve the problems of large amount of operation and high resource consumption, and finally the correlation result is used as an error coefficient (or correlation coefficient), and the process of gradually converging the gain estimation value to the actual gain value is realized through the iterative method, that is:

[0048]

[0049] Based on this, an embodiment of the present application performs error calibration on a pipeline SAR ADC as shown in Figure 1 The pipeline SAR ADC is a 12-bit 100MS / S pipeline ADC, adopts a 12V power supply voltage, includes a 6-bit sub-stage SAR ADC and a 7-bit sub-stage SAR ADC, a residual error amplifier, and a digital code reconstruction analog signal module. The pipeline ADC adopts one inter-stage redundancy, if the same reference voltage is used to design the two-stage SAR ADC, 32 times of inter-stage gain is needed, in order to reduce the difficulty in circuit design, the reference voltage of the second stage is reduced by half, and only 16 times of inter-stage gain is needed.

[0050] Figure 1In the embodiment, the residual error signal is obtained after the analog signal is sampled and converted by the first sub-stage SAR ADC, at this time, the pseudo-random sequence is injected at the P terminal and the N terminal, and the pseudo-random sequence is an m-sequence generated by the linear feedback shift register shown in the formula (1). Figure 2 The feedback shift register is composed of a plurality of registers connected in series, and the output of each register is directly supplied to the input of the subsequent register to form a data shift chain. The system also includes a set of feedback lines (C0, C1, …, Cn), and each feedback line determines whether the output of a specific register is fed back to the starting input of the chain according to its own state (1 represents connection, and 0 represents no connection), thereby forming a feedback loop. This feedback connection mode can be accurately described by a characteristic polynomial, which can reflect whether the register participates in the feedback process. In the construction of the linear feedback shift register for generating the m-sequence, a specific primitive polynomial is usually selected as the characteristic polynomial to ensure the optimal properties of the generated sequence. In the embodiment, the linear shift register contains 16 registers in total, and the maximum length of the pseudo-random sequence generated is (2 16 -1) bits. There are 6 sets of such linear shift registers, and the primitive polynomials of these linear shift registers are the same, but the initial values are different. Therefore, the pseudo-random sequences generated are also different and uncorrelated. Any one of the 6 sets of linear shift registers can generate an m-sequence.

[0051] The residual error signal superimposed with the PN signal is amplified and then enters the second sub-stage SAR ADC for sampling and quantization. Since the PN signal is not corrected during the operation of the analog-to-digital converter, it will eventually cause nonlinear errors in the final digital output code. These errors include the results caused by the non-ideal factors in the circuit acting on the PN signal.

[0052] The digital code reconstruction analog signal module of the pipeline SAR ADC is divided into two reconstruction modules, one for subtracting the PN signal from the digital code, and the other for calculating the actual weight of the capacitor for calibration. Finally, the results of the two modules are used to compare the calibration effect of the PN signal. After obtaining the digital code output of the pipeline SAR ADC, the correlation coefficient (correlation coefficient) is obtained by using the sign function to correlate the digital code with the PN signal, and then the iteration process of converging the gain estimation value rG of the residual error amplifier of the pipeline SAR ADC to the actual gain value is performed:

[0053] rG(k+1)=rG(k)-step(k)*Ecor(k)

[0054] Specifically, the pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection provided by the present application includes the following steps:

[0055] Step 1: The analog input signal to be processed is sent into the first stage 6-bit SAR ADC. At this stage, the SAR ADC uses its binary search algorithm to accurately sample the input signal and convert it into a 6-bit digital code D 1,i , where i is the bit index, ranging from 1 to 6, representing each bit in the 6-bit digital code.

[0056] Step 2: Next, after the first stage SAR ADC completes its conversion task, the system enters the next step of processing. At this time, the m-sequence generated by the linear feedback shift register is superimposed on the residual error signal generated in the first stage conversion process.

[0057] Step 3: The m-sequence modulated residual error signal is sent into the second stage 7-bit SAR ADC for further sampling and conversion, which also uses the successive approximation method. After conversion, a 7-bit digital code D 2,j is obtained, where j is the bit index, ranging from 1 to 7, representing each bit of the 7-bit quantization result of the second stage SAR ADC.

[0058] Step 4: The overall digital output D out of the pipeline SAR ADC is processed in the digital domain for correlation analysis with the previously introduced PN sequence. This step is achieved by calculating the correlation coefficient between D out and the PN sequence, which actually serves as an error parameter reflecting the nonlinear errors and other issues in the pipeline SAR ADC system.

[0059] Step 5: The gain value is estimated and adjusted through iteration. Specifically, based on the correlation coefficient calculated in step 4, the iteration process is started, and the estimated gain value rG gradually approaches the true gain value.

[0060] Step 6: Finally, the gain estimate rG obtained through iteration optimization is applied to the digital code reconstruction process of the pipeline SAR ADC. This step uses rG to correct the digital code of the ADC output, thereby reconstructing a digital code closer to the original analog signal.

[0061] In step 5, the invention proposes using a logarithmic Sigmoid function to control the iteration step size step, ensuring that the convergence process is both fast and stable. Specifically, based on the advantages of fast convergence and simple calculation of the series LMS algorithm based on the clevis line, starting from the step size adjustment function u(k) = β[1-exp(-α|e(k)| 2 )], the control parameter β in this step size adjustment function is first separated to obtain a single parameter control compensation adjustment function u(k) = 1-exp(-α|e(k)| 2), and after taking the negative logarithm operation (keeping the original function characteristics) u(k) = -log[1-exp(-a|e(k)| 2 ] is obtained. In combination with the monotonic convergence characteristics of the logarithm function, the exponential part is taken to the opposite to obtain u(k) = -log[1+exp(-a|e(k)| 2 ]. In order to make the new adjustment function comply with the step size adjustment principle of the variable step size adaptive LMS (VSSA LMS) algorithm, the reciprocal of the independent variable part is taken to obtain a new nonlinear function model: u(k) = -log[1+exp(-a|e(k)| -2 ]. By flipping and shifting and introducing β again, the shape of the function can be controlled, and the sigmoid step size change control function model after the logarithm function is strengthened is: u(k) = 2β{1.4+log[1+exp(-a|e(k)| -2 ]}.

[0062] Therefore, by replacing e(k) in the sigmoid step size change control function model with the correlation coefficient Ecor(k) and replacing u(k) in the function model with step(k), a function model is obtained:

[0063] step(k) = 2β{1.4+log[1+exp(-a|Ecor(k)| -2 ]}

[0064] In the iteration process of realizing the convergence of the estimated value rG of the gain to the actual gain value through the function model, the step size value is dynamically adjusted, so that the speed and accuracy in the iteration process are compromised, that is, the step size step is large in the preliminary stage of calibration, so as to quickly approach the target value, and as the calibration cycle progresses, step gradually decreases, so that the calibration becomes more accurate.

[0065] As shown in Figure 3 The function simulation diagram of controlling the step size is shown. When the absolute value of the independent variable correlation coefficient en is large, the dependent variable step size u is also large, and in the process that the absolute value of en gradually approaches 0, the value of u also gradually decreases, which realizes that the step size is large when the error coefficient is large in the preliminary stage of calibration, at this time the convergence speed is fast, and when the error coefficient gradually decreases in the later period, the step size also decreases, at this time the accuracy is higher.

[0066] In the pipeline SAR ADC module, the capacitor mismatch and the finite gain, and the offset voltage of the amplifier are added, Figure 4 indicate the output spectrum of the pipeline SAR ADC before and after calibration, wherein, Figure 4 (a) is the simulation result before calibration, Figure 4(b) is the simulation result after calibration. It can be seen that, without calibration, the SNDR is 54.71dB, the SFDR is 75.01dB, and the ENOB is 8.8bit, and after calibration, the SNDR is improved to 70.68dB, the SFDR is improved to 75.86dB, and the ENOB is up to 11.45bit.

[0067] In conclusion, the pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection provided by the application can verify that the capacitor mismatch and limited gain error in the pipeline SAR ADC can be calibrated on MATLAB, the performance of the ADC is obviously improved, and the signal-to-noise ratio and the non-aliasing dynamic range are improved.

[0068] Finally, it should be explained that the above embodiments are only used to illustrate the technical solutions of the application and are not limited. Although the application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the application can be modified or replaced equivalently without departing from the purpose and scope of the technical solutions, which should be covered in the scope of the claims of the application.

Claims

1. A method for digital background calibration of a pipelined SAR ADC based on pseudo-random sequence injection, said pipelined SAR ADC comprising a first stage SAR ADC and a second stage SAR ADC, said first stage SAR ADC and said second stage SAR ADC being connected by a residue amplifier, characterized in that, The method comprises: sampling an input analog signal by a first-stage SAR ADC, and converting the sampled input signal into a digital code; after the conversion of the first-stage SAR ADC is completed, superimposing a pseudo-random sequence generated by a linear feedback shift register into a residual error signal of the first-stage SAR ADC; amplifying the residual error signal superimposed with the pseudo-random sequence and inputting the amplified signal into a second-stage SAR ADC for sampling and conversion to obtain a quantized digital code; in a digital domain, performing a correlation operation between a digital signal finally output by the pipeline SAR ADC and the pseudo-random sequence to obtain a correlation coefficient; the correlation operation between the digital signal finally output by the pipeline SAR ADC and the pseudo-random sequence is realized by taking a sign bit and accumulating, and is shown in the following formula: wherein denotes a correlation coefficient, denotes a sign function, denotes a digital signal of the final output of the pipelined SAR ADC, denotes a pseudo-random sequence, denotes a number of calibration samples; according to the correlation coefficient, converging an estimated value of the inter-stage gain to an actual value of the inter-stage gain by an iterative method; in the iterative process, an iterative step is dynamically adjusted by a logarithmic sigmoid function; the logarithmic sigmoid function is shown in the following formula: wherein and denotes a control coefficient, for controlling the shape of the function, for controlling the range of values of the function, denotes a correlation coefficient, denotes the number of calibration cycles; using the estimated value of the inter-stage gain obtained by the iteration to obtain a final digital code output of the pipeline SAR ADC.

2. The method of claim 1, wherein: the process of converging the estimated value of the inter-stage gain to the actual value of the inter-stage gain by the iterative method is shown in the following formula: wherein denotes an estimate of the inter-stage gain, denotes an iteration step size, denotes a correlation coefficient, denotes a number of calibration cycles.

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