Wireline receiver with improved timing and associated margins

Abstract

To provide a wireline receiver with improved timing and associated margins. [Solution] A wireline receiver comprising a data sampler sa0, a first edge sampler sa1, a second edge sampler sa2, a base phase detection circuit 222, an additional phase detection circuit 224, a clock circuit 240, and a phase shift circuit 250, wherein the data sampler, the first edge sampler, and the second edge sampler, when triggered by the data clock, the first edge clock, and the second edge clock, respectively, sample and compare the receiver signal to determine whether the receiver signal exceeds the data threshold level, the first threshold level, and the second threshold level, thereby providing a basis for phase detection. In response to phase detection, the clock circuit provides the first edge clock and the data clock, and the phase shift circuit provides the second edge clock by phase shift.

Description

Technical Field

[0001] The present disclosure relates to a wireline receiver having improved timing and associated margins; more specifically, it includes a wireline receiver that may include a data sampler, a first edge sampler and / or a third edge sampler, a second edge sampler, a base phase detection circuit, an additional phase detection circuit, a clock circuit, and a phase shift circuit; the data sampler may sample and compare a receiver signal when triggered by a data clock to determine whether the receiver signal exceeds a data threshold level, and may contribute to forming a data signal accordingly; the first edge sampler and the third edge sampler may sample and compare the receiver signal when triggered by a first edge clock to determine whether the receiver signal exceeds a first threshold level and a third threshold level respectively, and may provide a first edge signal and a third edge signal accordingly; the second edge sampler may sample and compare the receiver signal when triggered by a second edge clock to determine whether the receiver signal exceeds a second threshold level, and may provide a second edge signal accordingly; the base phase detection circuit may provide a base timing control signal according to the data signal, the second edge signal, and at least one of the first edge signal and the third edge signal; the additional phase detection circuit may provide an additional timing control signal according to the data signal and at least one of the first edge signal to the third edge signal; the clock circuit may provide the data clock and the first edge clock according to the base timing control signal, and the phase shift circuit may provide the second edge clock by performing a phase shift according to the additional timing control signal.

Background Art

[0002] Wireline receivers, which can receive high-speed (high-frequency, high-rate) signals via physical conductive wires, are an essential and fundamental component of modern semiconductor integrated circuits. Disclosure of prior art / References

[0003] In relation to this disclosure, the Intellectual Property Office of Taiwan, in its Examination Opinion Notice No. 11420268390 (dated March 12, 2025), refers to CN 105391537, TW I779853, and US 10243571. [Overview of the project]

[0004] The object of this disclosure is to provide a wireline receiver (e.g., 100 in Figure 1a) having improved timing and associated margins; the wireline receiver comprises a sampler block (e.g., 110, 210, 310, 510, 1400 or 1500 in Figures 1a, 2a, 3a, 5a, 14, or 15a), a phase detection circuit block (e.g., Figure 1a, The system may include 120, 220, 320, 420, 520, 620, 720, 820, 920, 1020, 1120, 1220, or 1520 in Figures 2a, 3a, 4a, 5a, 6a, 7a, 8a, 9a, 10a, 11a, 12a, or 15b, and a clock circuit block (130, 230, or 1530 in Figures 1a, 2a, or 15c). The sampler block may include a data sampler (e.g., sa0 in Figure 2a, or one of sa01 to sa04 in Figure 15a), a first edge sampler (e.g., sa1 in Figure 2a, or one of sa1e and sa1o in Figure 15a), and a second edge sampler (e.g., sa2 in Figure 2a, or one of sa2e and sa2o in Figure 15a). The phase detection circuit block may include a base phase detection circuit (e.g., 222, 322, 422, 522, 622, or 1522 in Figures 2a, 3a, 4a, 5a, 6a, or 15b) and additional phase detection circuits (e.g., 224, 324, 424, 524, 624, 724, 824, 924, 1024, 1124, 1224, or 1524 in Figures 2a, 3a, 4a, 5a, 6a, 7a, 8a, 9a, 10a, 11a, 12a, or 15b). The clock circuit block may include a clock circuit (e.g., 240 or 1540 in Figure 2a or 15c) and a phase shift circuit (e.g., 250 or 1550 in Figure 2a or 15c).A data sampler, when triggered by a data clock (e.g., ck0 in Figure 2a, or one of ck0e and ck0o in Figure 15a), may sample and compare a receiver signal (e.g., sr1 in Figure 2a, or one of sr1e and sr1o in Figure 15a) to determine whether the receiver signal exceeds a data threshold level (e.g., L0 in Figure 2a, or one of +h_1 and -h_1 in Figure 15a), and accordingly contribute to the formation of a data signal (e.g., sd1 in Figure 2a or Figure 15a). When triggered by a first edge clock (e.g., cke1 in Figure 2a, or one of cke1e and cke1o in Figure 15a), the first edge sampler may sample and compare the receiver signal to determine whether the receiver signal exceeds a first threshold level (e.g., L1 in Figure 2a or Figure 15a), and accordingly provide a first edge signal (e.g., x1 in Figure 2a, or one of x1e and x1o in Figure 15a). When triggered by a second edge clock (e.g., cke2 in Figure 2a, or one of cke2e or cke2o in Figure 15a), the second edge sampler may sample and compare the receiver signal to determine whether it exceeds a second threshold level (e.g., L2 in Figure 2a or Figure 15a), and accordingly provide a second edge signal (e.g., x2 in Figure 2a, or one of x2e and x2o in Figure 15a). A base phase detection circuit may be coupled to the data sampler, the first edge sampler, and the second edge sampler, and may provide a base timing control signal (e.g., scr1 in Figure 2a or Figure 15b) in response to the data signal, the first edge signal, and the second edge signal. An additional phase detection circuit may provide an additional timing control signal (e.g., scr2 in Figure 2a or Figure 15b) in response to the data signal and at least one of the first edge signal and the second edge signal. A clock circuit may be coupled to the base phase detection circuit, and may provide a first edge clock and a data clock in response to the base timing control signal, and may make the phase difference between the data clock and the first edge clock substantially equal to a predetermined base offset value (e.g., d_p0 in Figure 2b or Figure 15d).The phase shift circuit may be coupled to an additional phase detection circuit, which may provide a second edge clock by phase shifting, and the phase difference between the second edge clock and the first edge clock may be made substantially equal to an additional offset value (e.g., d_phi in Figure 2b or Figure 15d). The first and second threshold levels may be different, and the additional offset value may be controlled by an additional timing control signal.

[0005] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), the base phase detection circuit may include a first pattern phase detection unit (for example, pd1 in Figure 2a, or one of pd1e and pd1o in Figure 15b). When a base phase detection circuit provides a base timing control signal in response to a data signal, a first edge signal, and a second edge signal, if the data signal matches a first pattern (e.g., p1 in Figure 2a or Figure 15b), the first pattern phase detection unit may assert a speed-up message (e.g., UP in Figure 2c) or a speed-down message (e.g., DN in Figure 2c) in the base timing control signal, depending on the current signal value of the first edge signal (e.g., x1[i] in Figure 2b, or one of x1e[i] and x1o[i] in Figure 15d); if the data signal does not match the first pattern, the first pattern phase detection unit does not need to assert a speed-up message or a speed-down message in the base timing control signal.

[0006] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), if three consecutive signal values ​​of the data signal (for example, sd1[i-1], sd1[i] and sd1[i+1] in Figure 2b, or sd1[2i-1], sd1[2i] and sd1[2i+1] in Figure 15d, or sd1[2i-2], sd1[2i-1] and sd1[2i] in Figure 15d) are equal to a first defined value (for example, H in Figure 2a), a first defined value, and a second defined value (for example, L in Figure 2a), the data signal matches a first pattern. When a data signal matches a first pattern and the first pattern phase detection unit asserts a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the first edge signal, the first pattern phase detection unit may assert a speed-up message in the base timing control signal if the current signal value of the first edge signal is equal to a second defined value; otherwise, the first pattern phase detection unit may assert a speed-down message in the base timing control signal.

[0007] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), when a data sampler samples and compares a receiver signal to determine whether the receiver signal exceeds a data threshold level according to a trigger of a data clock, and contributes to the formation of a data signal accordingly, if it is determined that the receiver signal exceeds a data threshold level, the data sampler may make the current signal value of the data signal (for example, sd1[i] in Figure 2b, sd1[2i] in Figure 15d, or sd1[2i-1] in Figure 15d) equal to a first defined value; otherwise, the data sampler may make the current signal value of the data signal equal to a second defined value.

[0008] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), the wireline receiver may further include a third edge sampler (for example, sa3 in Figure 2a, or one of sa3e and sa3o in Figure 15a); the third edge sampler may, when triggered by the first edge clock, sample and compare the receiver signal to determine whether the receiver signal exceeds a third threshold level (for example, L3 in Figure 2a or Figure 15a), and accordingly provide a third edge signal (for example, x3 in Figure 2a, or one of x3e and x3o in Figure 15a). The third threshold level may be different from the first threshold level and different from the second threshold level. When a base phase detection circuit provides a base timing control signal in response to a data signal, a first edge signal, and a second edge signal, the base phase detection circuit may provide a base timing control signal in response to a data signal, a first edge signal, a second edge signal, and a third edge signal. When an additional phase detection circuit provides an additional timing control signal in response to a data signal and at least one of the first edge signal and the second edge signal, the additional phase detection circuit may provide an additional timing control signal in response to a data signal and at least one of the first edge signal, the second edge signal, and the third edge signal.

[0009] In one embodiment (for example, Figure 2b), the second threshold level may be substantially equal to the average of the first threshold level and the third threshold level.

[0010] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), the base phase detection circuit may further include a third pattern phase detection unit (for example, pd3 in Figure 2a, or one of pd3e and pd3o in Figure 15b). When the base phase detection circuit provides a base timing control signal in response to a data signal, a first edge signal, a second edge signal, and a third edge signal, if the data signal matches a third pattern (for example, p3 in Figure 2a or Figure 15b), the third pattern phase detection unit may assert a speed-up message or a speed-down message in the base timing control signal in response to the current signal value of the third edge signal (for example, x3[i] in Figure 2b, or one of x3e[i] and x3o[i] in Figure 15d); if the data signal does not match a third pattern, the third pattern phase detection unit does not need to assert a speed-up message or a speed-down message in the base timing control signal.

[0011] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), if three consecutive signal values ​​of the data signal (for example, sd1[i-1] to sd1[i+1] in Figure 2b, sd1[2i-1] to sd1[2i+1] in Figure 15d, or sd1[2i-2] to sd1[2i] in Figure 15d) are equal to the second defined value, the second defined value, and the first defined value, respectively, then the data signal matches the third pattern. When a data signal matches a third pattern and the third pattern phase detection unit asserts a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the third edge signal, the third pattern phase detection unit may assert a speed-up message in the base timing control signal if the current signal value of the third edge signal is equal to a first defined value; otherwise, the third pattern phase detection unit may assert a speed-down message in the base timing control signal.

[0012] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), the base phase detection circuit may further include a second pattern phase detection unit (for example, pd2 in Figure 2a, or one of pd2e and pd2o in Figure 15b). When the base phase detection circuit provides a base timing control signal in response to a data signal, a first edge signal, and a second edge signal, if the data signal matches a second pattern (for example, p2 in Figure 2a or Figure 15b), the second pattern phase detection unit may assert a speed-up message or a speed-down message in the base timing control signal in response to the current signal value of the second edge signal (for example, x2[i] in Figure 2b, or one of x2e[i] and x2o[i] in Figure 15d); if the data signal does not match a second pattern, the second pattern phase detection unit does not need to assert a speed-up message or a speed-down message in the base timing control signal.

[0013] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), if three consecutive signal values ​​of the data signal (for example, sd1[i-1] to sd1[i+1] in Figure 2b, sd1[2i-1] to sd1[2i+1] in Figure 15d, or sd1[2i-2] to sd1[2i] in Figure 15d) are equal to the first defined value, the second defined value, and the first defined value, respectively, then the data signal matches the second pattern. When a data signal matches a second pattern and the second pattern phase detection unit asserts a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the second edge signal, the second pattern phase detection unit may assert a speed-up message in the base timing control signal if the current signal value of the second edge signal is equal to a first defined value; otherwise, the second pattern phase detection unit may assert a speed-down message in the base timing control signal.

[0014] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), the base phase detection circuit may further include a fourth pattern phase detection unit (for example, pd4 in Figure 2a, or one of pd4e and pd4o in Figure 15b). When the base phase detection circuit provides a base timing control signal in response to a data signal, a first edge signal, and a second edge signal, if the data signal matches a fourth pattern (for example, p4), the fourth pattern phase detection unit may assert a speed-up message or a speed-down message in the base timing control signal in response to the current signal value of the second edge signal (for example, x2[i] in Figure 2b, or one of x2e[i] and x2o[i] in Figure 15d); if the data signal does not match a fourth pattern, the fourth pattern phase detection unit does not need to assert a speed-up message or a speed-down message in the base timing control signal.

[0015] In one embodiment (for example, Figures 2a to 2f, or Figures 15a to 15d), if three consecutive signal values ​​of the data signal (for example, sd1[i-1] to sd1[i+1] in Figure 2b, sd1[2i-1] to sd1[2i+1] in Figure 15d, or sd1[2i-2] to sd1[2i] in Figure 15d) are equal to the second defined value, the first defined value, and the second defined value, respectively, then the data signal matches the fourth pattern. When a data signal matches a fourth pattern and the fourth pattern phase detection unit asserts a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the second edge signal, the fourth pattern phase detection unit may assert a speed-up message in the base timing control signal if the current signal value of the second edge signal is equal to a second defined value; otherwise, the fourth pattern phase detection unit may assert a speed-down message in the base timing control signal.

[0016] In one embodiment, the data threshold level and the first threshold level may be substantially equal. In one embodiment, the base offset value may be orthogonal to the data clock and the first edge clock; for example, the base offset value may be such that the data clock is substantially an inverted version of the first edge clock.

[0017] In one embodiment (for example, Figure 9a), an additional phase detection circuit (for example, 924) may include a first counting circuit (for example, 961). The data signal matches a first pattern (for example, p1) if, in response to the current signal value of a first edge signal (for example, x1[i]), three associated signal values ​​of the data signal (for example, sd1[i-1] to sd1[i+1]) are equal to a first defined value, a first defined value, and a second defined value, respectively. When the data signal matches a first pattern and the current signal value of the first edge signal is equal to a second defined value, the first counting circuit may increment a first speed-up cumulative count; when the data signal matches a first pattern and the current signal value of the first edge signal is equal to a first defined value, the first counting circuit may increment a first speed-down cumulative count. When the data signal does not match the first pattern, the first counting circuit may leave the first speed-up cumulative count and the first speed-down cumulative count unchanged. When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, the additional phase detection circuit may increase the additional offset value and reset each of the first speed-up cumulative count and the first speed-down cumulative count to the reset value. When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, the additional phase detection circuit may decrease the additional offset value and reset each of the first speed-up cumulative count and the first speed-down cumulative count to the reset value. When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed a first preset positive value, and the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed a third preset positive value, the additional phase detection circuit may leave the additional offset value unchanged and does not need to reset the first speed-up cumulative count and the first speed-down cumulative count.

[0018] In one embodiment (for example, Figure 7a), an additional phase detection circuit (e.g., 724) may include a first counting circuit (e.g., 761). In response to the current signal value of the first edge signal (e.g., x1[i]), if three associated signal values ​​of the data signal (e.g., sd1[i-1] to sd1[i+1]) are equal to a first defined value, a first defined value, and a second defined value, respectively, the data signal matches a first pattern (e.g., p1). If three associated signal values ​​of the data signal are equal to a second defined value, a second defined value, and a first defined value, respectively, the data signal matches a third pattern (e.g., p3). When a data signal matches a first pattern and the current signal value of a first edge signal is equal to a second defined value, the first counting circuit may increment a first speed-up cumulative count; when a data signal matches a first pattern and the current signal value of a first edge signal is equal to a first defined value, the first counting circuit may increment a first speed-down cumulative count. When a data signal matches a third pattern and the current signal value of a third edge signal (e.g., x3[i]) is equal to a first defined value, the first counting circuit may increment a first speed-up cumulative count; when a data signal matches a third pattern and the current signal value of a third edge signal is equal to a second defined value, the first counting circuit may increment a first speed-down cumulative count. When the data signal does not match the first pattern and does not match the third pattern, the first counting circuit may leave the first speed-up cumulative count and the first speed-down cumulative count unchanged. When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, the additional phase detection circuit may increase the additional offset value and reset the first speed-up cumulative count and the first speed-down cumulative count to their respective reset values.If the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, the additional phase detection circuit may decrease the additional offset value and reset the first speed-up cumulative count and the first speed-down cumulative count to their respective reset values. If the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed a first preset positive value, and the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed a third preset positive value, the additional phase detection circuit may leave the additional offset value unchanged and does not reset the first speed-up cumulative count and the first speed-down cumulative count.

[0019] In one embodiment (for example, Figure 10a), an additional phase detection circuit (e.g., 1024) may include a second counting circuit (e.g., 1062). The data signal matches a second pattern (e.g., p2) if, in response to the current signal value of the second edge signal (e.g., x2[i]), three associated signal values ​​of the data signal (e.g., sd1[i-1] to sd1[i+1]) are equal to a first defined value, a second defined value, and a first defined value, respectively. When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit may increment a second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit may increment a second speed-down cumulative count. When the data signal does not match the second pattern, the second counting circuit may leave the second speed-up cumulative count and the second speed-down cumulative count unchanged. When the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit may decrease the additional offset value and reset each of the second speed-up cumulative count and the second speed-down cumulative count to their reset values. When the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit may increase the additional offset value and reset each of the second speed-up cumulative count and the second speed-down cumulative count to their reset values. When the difference between the second speed-up cumulative count and the second speed-down cumulative count does not exceed a second preset positive value, and the difference between the second speed-down cumulative count and the second speed-up cumulative count does not exceed a fourth preset positive value, the additional phase detection circuit may leave the additional offset value unchanged and does not need to reset the second speed-up cumulative count and the second speed-down cumulative count.

[0020] In one embodiment (for example, Figure 8a), an additional phase detection circuit (e.g., 824) may include a second counting circuit (e.g., 862). In response to the current signal value of the second edge signal (e.g., x2[i]), if three associated signal values ​​of the data signal (e.g., sd1[i-1] to sd1[i+1]) are equal to a first defined value, a second defined value, and a first defined value, respectively, the data signal matches a second pattern (e.g., p2). If three associated signal values ​​of the data signal are equal to a second defined value, a first defined value, and a second defined value, respectively, the data signal matches a fourth pattern (p4). When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit may increment the second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit may increment the second speed-down cumulative count. When the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit may increment the second speed-up cumulative count; when the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit may increment the second speed-down cumulative count. When the data signal does not match the second pattern and does not match the fourth pattern, the second counting circuit may leave the second speed-up cumulative count and the second speed-down cumulative count unchanged. If the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit may reduce the additional offset value and reset the second speed-up cumulative count and the second speed-down cumulative count to their respective reset values.If the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit may increase the additional offset value and reset the second speed-up cumulative count and the second speed-down cumulative count to their respective reset values. If the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed a second preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed a fourth preset positive value, the additional phase detection circuit may leave the additional offset value unchanged and does not reset the second speed-up cumulative count and the second speed-down cumulative count.

[0021] In one embodiment (for example, Figure 3a), an additional phase detection circuit (e.g., 324) may include a first counting circuit (e.g., 361) and a second counting circuit (e.g., 362). The data signal matches a first pattern (e.g., p1) if, in response to the current signal value of a first edge signal (e.g., x1[i]), three associated signal values ​​of the data signal (e.g., sd1[i-1], sd1[i], sd1[i+1]) are equal to a first defined value, a first defined value, and a second defined value, respectively. When the data signal matches a first pattern and the current signal value of the first edge signal is equal to a second defined value, the first counting circuit may increment a first speed-up cumulative count; when the data signal matches a first pattern and the current signal value of the first edge signal is equal to a first defined value, the first counting circuit may increment a first speed-down cumulative count. When the data signal does not match the first pattern, the first counting circuit may leave the first speed-up cumulative count and the first speed-down cumulative count unchanged. The data signal matches the second pattern (e.g., p2) if, in response to the current signal value of the second edge signal (e.g., x2[i]), the three associated signal values ​​of the data signal (e.g., sd1[i-1] to sd1[i+1]) are equal to a third defined value (e.g., H), a fourth defined value (e.g., L), and a third defined value, respectively. When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the third defined value, the second counting circuit may increment the second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the fourth defined value, the second counting circuit may increment the second speed-down cumulative count. When the data signal does not match the second pattern, the second counting circuit may leave the second speed-up cumulative count and the second speed-down cumulative count unchanged.When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit may increase the additional offset value and reset each of the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count to their reset values. When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, and the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit may decrease the additional offset value and reset each of the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count to their reset values. When a situation other than the two described above occurs, the additional phase detection circuit may leave the additional offset value unchanged and does not need to reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count.In other words, when the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed a third preset positive value, or when the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed a first preset positive value, or when the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed a second preset positive value, or when the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed a fourth preset positive value, the additional phase detection circuit may leave the additional offset value unchanged and does not need to reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count.

[0022] In one embodiment (for example, Figure 2a), an additional phase detection circuit (for example, 224) may include a first counting circuit (for example, 261) and a second counting circuit (for example, 262). In response to the current signal value of the first edge signal (for example, x1[i]), if three associated signal values ​​of the data signal (for example, sd1[i-1], sd1[i], sd1[i+1]) are equal to a first defined value, a first defined value, and a second defined value, respectively, the data signal matches a first pattern (for example, p1); if three associated signal values ​​of the data signal are equal to a second defined value, a second defined value, and a first defined value, respectively, the data signal matches a third pattern (for example, p3). When a data signal matches a first pattern and the current signal value of a first edge signal is equal to a second defined value, the first counting circuit may increment a first speed-up cumulative count; when a data signal matches a first pattern and the current signal value of a first edge signal is equal to a first defined value, the first counting circuit may increment a first speed-down cumulative count. When a data signal matches a third pattern and the current signal value of a third edge signal (e.g., x3[i]) is equal to a first defined value, the first counting circuit may increment a first speed-up cumulative count; when a data signal matches a third pattern and the current signal value of a third edge signal is equal to a second defined value, the first counting circuit may increment a first speed-down cumulative count. When the data signal does not match the first pattern and does not match the third pattern, the first counting circuit may leave the first speed-up cumulative count and the first speed-down cumulative count unchanged.Furthermore, in response to the current signal value of the second edge signal (e.g., x2[i]), if the three associated signal values ​​of the data signal (e.g., sd1[i-1], sd1[i], sd1[i+1]) are equal to the first defined value, the second defined value, and the first defined value, respectively, the data signal matches the second pattern (e.g., p2); if the three associated signal values ​​of the data signal are equal to the second defined value, the first defined value, and the second defined value, respectively, the data signal matches the fourth pattern (e.g., p4). When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit may increment the second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit may increment the second speed-down cumulative count. When the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit may increment the second speed-up cumulative count; when the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit may increment the second speed-down cumulative count. When the data signal does not match the second pattern and does not match the fourth pattern, the second counting circuit may leave the second speed-up cumulative count and the second speed-down cumulative count unchanged. When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit may increase the additional offset value and reset each of the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count to their reset values.When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, and the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit may decrease the additional offset value and reset each of the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count to their reset values. When a situation other than the two described above occurs, the additional phase detection circuit may leave the additional offset value unchanged and does not need to reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count. In other words, when the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed a third preset positive value, or when the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed a first preset positive value, or when the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed a second preset positive value, or when the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed a fourth preset positive value, the additional phase detection circuit may leave the additional offset value unchanged and does not need to reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count.

[0023] The object of this disclosure is to provide a method applicable to a wireline receiver for improved timing and associated margins; the method may comprise the following operations: data sampling, at least one of first edge sampling and third edge sampling, second edge sampling, at least one of first to fourth pattern phase detection, base phase detection, additional phase detection, base timing adjustment, and additional timing adjustment. Data sampling may comprise the following: when triggered by one or more data clocks (e.g., ck0 in Figure 2a, or ck0e and ck0o in Figure 15a), sampling and comparing one or more receiver signals (e.g., sr1 in Figure 2a, or sr1e and sr1o in Figure 15a) to determine whether one or more receiver signals each exceed one or more data threshold levels (e.g., L0 in Figure 2a, or +h_1 and -h_1 in Figure 15a), and providing a data signal (e.g., sd1) accordingly. The first edge sampling may have the following characteristics: when triggered by one or more first edge clocks (e.g., cke1 in Figure 2a, or cke1e and cke1o in Figure 15a), it samples and compares one or more receiver signals to determine whether one or more receiver signals exceed a first threshold level (e.g., L1), and accordingly provides one or more first edge signals (e.g., x1 in Figure 2a, or x1e and x1o in Figure 15a). The second edge sampling may have the following characteristics: when triggered by one or more second edge clocks (e.g., cke2 in Figure 2a, or cke2e and cke2o in Figure 15a), it samples and compares one or more receiver signals to determine whether one or more receiver signals exceed a second threshold level (e.g., L2), and accordingly provides one or more second edge signals (e.g., x2 in Figure 2a, or x2e and x2o in Figure 15a).The third edge sampling may include: when triggered by one or more of the first edge clocks, sampling and comparing one or more receiver signals to determine whether one or more receiver signals exceed a third threshold level (e.g., L3), and providing one or more third edge signals accordingly (e.g., x3 in Figure 2a, or x3e and x3o in Figure 15a). The first threshold level, the second threshold level, and the third threshold level do not have to be equal.

[0024] One or more first edge signals (e.g., x1 in Figure 2a, or x1e and x1o in Figure 15a) may be associated with one or more first pattern phase detection signals (e.g., ud1 in Figure 2a, or ud1e and ud1o in Figure 15a), and the first pattern phase detection may have the following: in response to the current signal value (e.g., x1[i], x1e[i], or x1o[i]) of a particular first edge signal (e.g., x1, x1e, or x1o) among the one or more first edge signals, a plurality of associated signal values ​​of the data signal (e.g., sd1[i-1]~sd1[i+1], sd1[2i-1]~sd1[2i+1], or sd1[2i-2]~ If sd1[2i]) matches one of several first constituent values ​​(e.g., three defined values ​​H, H, L) included in the first pattern phase detection signal associated with a particular first edge signal, assert a speed-up message or a speed-down message depending on whether the current signal value of the particular first edge signal is equal to the last of the several first constituent values; if the several associated signal values ​​of the data signal do not match the several first constituent values, do not assert either a speed-up message or a speed-down message in the first pattern phase detection signal associated with a particular first edge signal.

[0025] One or more second edge signals (e.g., x2 in Figure 2a, or x2e and x2o in Figure 15a) may be associated with one or more second pattern phase detection signals (e.g., ud2 in Figure 2a, or ud2e and ud2o in Figure 15a), and may also be associated with one or more fourth pattern phase detection signals (e.g., ud4 in Figure 2a, or ud4e and ud4o in Figure 15a). The second pattern phase detection may have the following: In response to the current signal value (e.g., x2[i], x2e[i], or x2o[i]) of a particular second edge signal (e.g., x2, x2e, or x2o) among one or more second edge signals, if a certain number of associated signal values ​​of the data signal (e.g., sd1[i-1]~sd1[i+1] or sd1[2i-1]~sd1[2i+1], or sd1[2i-2]~sd1[2i]) match a number of second constituent values ​​(e.g., three defined values ​​H, L, H) contained in the second pattern, then a particular number In a second pattern phase detection signal associated with an edge signal, assert a speed-up message or a speed-down message depending on whether the current signal value of a particular second edge signal is equal to the last of the plurality of second constituent values; if the plurality of associated signal values ​​of the data signal do not match the plurality of second constituent values, do not assert either a speed-up message or a speed-down message in the second pattern phase detection signal associated with a particular second edge signal.The fourth pattern phase detection may have the following: in response to the current signal value of a particular second edge signal, if multiple associated signal values ​​of a data signal match multiple fourth constituent values ​​(e.g., three defined values ​​L, H, L) that the fourth pattern phase detection signal associated with the particular second edge signal asserts a speed-up message or a speed-down message depending on whether the current signal value of the particular second edge signal is equal to the last of the multiple fourth constituent values; if multiple associated signal values ​​of the data signal do not match multiple fourth constituent values, the fourth pattern phase detection signal associated with the particular second edge signal does not assert either a speed-up message or a speed-down message.

[0026] One or more third edge signals (e.g., x3 in Figure 2a, or x3e and x3o in Figure 15a) may be associated with one or more third pattern phase detection signals (e.g., ud3 in Figure 2a, or ud3e and ud3o in Figure 15a), and the third pattern phase detection may have: in response to the current signal value (e.g., x3[i], x3e[i], or x3o[i]) of a particular third edge signal (e.g., x3, x3e, or x3o) among the one or more third edge signals, a plurality of associated signal values ​​of the data signal (e.g., sd1[i-1]~sd1[i+1], sd1[2i-1]~sd1[2i+1], or sd1[2i-2]) If ~sd1[2i]) matches one of several third configuration values ​​(e.g., three defined values ​​L, L, H) included in the third pattern, assert a speed-up message or a speed-down message in the third pattern phase detection signal associated with a particular third edge signal, depending on whether the current signal value of the particular third edge signal is equal to the last of the several third configuration values; if none of the several associated signal values ​​of the data signal match any of the several third configuration values, do not assert either a speed-up message or a speed-down message in the third pattern phase detection signal associated with a particular third edge signal.

[0027] Base phase detection may be associated with a base signal subset; the base signal subset may comprise at least one of one or more first pattern phase detection signals and one or more third pattern phase detection signals, and may further comprise at least one of one or more second pattern phase detection signals and one or more fourth pattern phase detection signals. Base phase detection may have the following: if the speed-up message is asserted in any one of the base signal subsets, asserting the corresponding speed-up message in the base timing control signal (e.g., scr1); if the speed-down message is asserted in any one of the base signal subsets, asserting the corresponding speed-down message in the base timing control signal. One or more data clocks may each be associated with one or more first edge clocks. Base timing adjustment may have the following: one or more data clocks and one or more first edge clocks may be of substantially the same frequency controlled by the base timing control signal, and providing one or more data clocks and one or more first edge clocks according to the base timing control signal such that the phase difference between each data clock and its associated first edge clock may be substantially equal to a predetermined base offset value (e.g., d_p0).

[0028] One or more second edge clocks may each be associated with one or more first edge clocks. Additional timing adjustment may have the following: performing a phase shift and providing one or more second edge clocks such that one or more second edge clocks and one or more first edge clocks may be of substantially the same frequency, and the phase difference between each of the second edge clocks and its associated first edge clock may be substantially equal to an additional offset value (e.g., d_phi).

[0029] The additional phase detection may comprise one or both of a first count operation and a second count operation, and may further comprise additional internal operations. The first count operation may be associated with a first signal subset, which may comprise at least one of one or more first pattern phase detection signals and one or more third pattern phase detection signals. The first count operation may have the following: if the speed-up message is asserted in any one of the first signal subsets, increment the first count (e.g., cnt1) by a step value (e.g., d1); if the speed-down message is asserted in any one of the first signal subsets, decrement the first count by a step value; and leave the first count unchanged if the speed-up message and the speed-down message are not asserted in each of the first signal subsets. The second counting operation may be associated with a second signal subset, which may comprise at least one of one or more second pattern phase detection signals and one or more fourth pattern phase detection signals. The second counting operation may have the following characteristics: if the speed-up message is asserted in any one of the second signal subsets, increment the second count (e.g., cnt2) by a step value; if the speed-down message is asserted in any one of the second signal subsets, decrement the second count by a step value; and leave the second count unchanged if the speed-up message and the speed-down message are not asserted in each of the second signal subsets.

[0030] In one embodiment (e.g., FIGS. 7a, 9a, or 11a), additional internal operations (e.g., FIG. 7c) may include: when a first count is greater than an upper limit value (e.g., c_U in FIG. 2f), increasing an additional offset value and resetting the first count to an initial value (e.g., c_0 in FIG. 2f); when the first count is less than a lower limit value (e.g., c_D in FIG. 2f), decreasing the additional offset value and resetting the first count to the initial value; when the first count is not greater than the upper limit value and not less than the lower limit value, holding the additional offset value without change and not resetting the first count. In another embodiment (e.g., FIGS. 8a, 10a, or 12a), additional internal operations (e.g., FIG. 8c) may include: when a second count is less than the lower limit value, increasing the additional offset value and resetting the second count to the initial value; when the second count is greater than the upper limit value, decreasing the additional offset value and resetting the second count to the initial value; when the second count is not greater than the upper limit value and not less than the lower limit value, holding the additional offset value without change and not resetting the second count.

[0031] In yet another embodiment (for example, Figures 2a, 3a, 4a, 5a, or 6a), additional internal operations (for example, Figure 2e) may include: increasing the additional offset value and resetting the first and second counts to their initial values ​​when the first count is greater than the upper limit and the second count is less than the lower limit; decreasing the additional offset value and resetting the first and second counts to their initial values ​​when the first count is less than the lower limit and the second count is greater than the upper limit; and keeping the additional offset value unchanged and not resetting the first and second counts when any other scenario occurs. The upper limit may be greater than the initial value, and the initial value may be greater than the lower limit; furthermore, the aforementioned second preset positive value may be equal to the first preset positive value, the fourth preset positive value may be equal to the third preset positive value, the upper limit may be equal to the initial value multiplied by the step value and the first preset positive value (for example, c_U = c_0 + d1 * pv1, where pv1 represents the first preset positive value), and the lower limit may be equal to the initial value minus the product of the step value and the third preset positive value (for example, c_D = c_0 - d1 * pv3, where pv3 represents the third preset positive value).

[0032] Many of the purposes, features, and advantages of this disclosure will become readily apparent upon reading the following detailed description of embodiments of this disclosure in conjunction with the accompanying drawings. However, the drawings used herein are for illustrative purposes only and should not be considered limiting. [Brief explanation of the drawing]

[0033] The purposes and advantages of this disclosure described above will become more readily apparent to those skilled in the art after reviewing the detailed description and accompanying drawings below.

[0034] [Figure 1]Figure 1a shows a wireline receiver according to one embodiment of the present disclosure, which may include a sampler block, a phase detection circuit block, and a clock circuit block, etc. Figure 1b shows an eye diagram of the received signal.

[0035]

[0036] [Figure 2-1] Figure 2a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the sampler block, phase detection circuit block, and clock circuit block shown in Figure 1a, respectively, according to one embodiment of the present disclosure, where the phase detection circuit block in Figure 2a may include a base phase detection circuit and an additional phase detection circuit.

[0037] [Figure 2-2] Figure 2b shows embodiments of the waveforms and timings of the related signals and clocks shown in Figure 2a.

[0038] [Figure 2-3] Figure 2c shows an embodiment of the operation of the base phase detection circuit shown in Figure 2a. Figure 2d shows an embodiment of the operation of the additional phase detection circuit shown in Figure 2a.

[0039] [Figure 2-4] Figure 2e shows an embodiment of the operation of the additional phase detection circuit shown in Figure 2a.

[0040] [Figure 2-5] Figure 2f shows an example of the operation of the additional phase detection circuit shown in Figure 2a.

[0041] [Figure 3-1]Figure 3a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, according to one embodiment of the present disclosure, where the phase detection circuit block in Figure 3a may comprise a base phase detection circuit and additional phase detection circuits.

[0042] [Figure 3-2] Figure 3b shows an embodiment of the operation of the base phase detection circuit shown in Figure 3a. Figure 3c shows an embodiment of the operation of the additional phase detection circuit shown in Figure 3a.

[0043]

[0044] [Figure 4-1] Figure 4a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, according to one embodiment of the present disclosure, wherein the phase detection circuit block shown in Figure 4a may comprise a base phase detection circuit and additional phase detection circuits.

[0045] [Figure 4-2] Figure 4b shows an embodiment of the operation of the base phase detection circuit shown in Figure 4a. Figure 4c shows an embodiment of the operation of the additional phase detection circuit shown in Figure 4a.

[0046]

[0047] [Figure 5-1] Figure 5a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, according to one embodiment of the present disclosure, wherein the phase detection circuit block shown in Figure 5a may comprise a base phase detection circuit and additional phase detection circuits.

[0048] [Figure 5-2]Figure 5b shows an embodiment of the operation of the base phase detection circuit shown in Figure 5a. Figure 5c shows an embodiment of the operation of the additional phase detection circuit shown in Figure 5a.

[0049]

[0050] [Figure 6-1] Figure 6a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, according to one embodiment of the present disclosure, wherein the phase detection circuit block shown in Figure 6a may comprise a base phase detection circuit and additional phase detection circuits.

[0051] [Figure 6-2] Figure 6b shows an embodiment of the operation of the base phase detection circuit shown in Figure 6a. Figure 6c shows an embodiment of the operation of the additional phase detection circuit shown in Figure 6a.

[0052]

[0053] [Figure 7-1] Figure 7a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, according to one embodiment of the present disclosure, wherein the phase detection circuit block shown in Figure 7a may comprise a base phase detection circuit and additional phase detection circuits.

[0054] [Figure 7-2] Figures 7b and 7c illustrate an embodiment of the operation of the additional phase detection circuit shown in Figure 7a.

[0055] [Figure 8-1]Figure 8a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, according to one embodiment of the present disclosure, wherein the phase detection circuit block shown in Figure 8a may comprise a base phase detection circuit and additional phase detection circuits.

[0056] [Figure 8-2] Figures 8b and 8c illustrate an embodiment of the operation of the additional phase detection circuit shown in Figure 8a.

[0057] [Figure 9a] Figure 9a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, respectively, where the phase detection circuit block shown in Figure 9a may include a base phase detection circuit and additional phase detection circuits.

[0058] [Figure 9b] Figure 9a shows an embodiment of the operation of the additional phase detection circuit.

[0059] [Figure 10a] Figure 10a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, where the phase detection circuit block shown in Figure 10a may include a base phase detection circuit and additional phase detection circuits.

[0060] [Figure 10b] Figure 10a shows an embodiment of the operation of the additional phase detection circuit.

[0061] [Figure 11a]One embodiment of the present disclosure shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, where the phase detection circuit block shown in Figure 11a may comprise a base phase detection circuit and additional phase detection circuits.

[0062] [Figure 11b] Figure 11a shows an embodiment of the operation of the additional phase detection circuit.

[0063] [Figure 12a] Figure 12a shows a sampler block, a phase detection circuit block, and a clock circuit block that may implement the corresponding blocks in the wireline receiver shown in Figure 1a, where the phase detection circuit block shown in Figure 12a may include a base phase detection circuit and additional phase detection circuits.

[0064] [Figure 12b] Figure 12a shows an embodiment of the operation of the additional phase detection circuit.

[0065] [Figure 13-1] Figures 13a and 13b show clock circuit blocks according to different embodiments of the present disclosure. [Figure 13-2] Figure 13c shows a clock circuit block according to a different embodiment of the present disclosure.

[0066] [Figure 14] Figure 1a shows a circuit block that may implement the relevant block in the wireline receiver shown in one embodiment of the present disclosure.

[0067] [Figure 15a] Figure 1a shows a circuit block that may implement the relevant block in the wireline receiver shown in one embodiment of the present disclosure.

[0068] [Figure 15b] A phase detection circuit block that may implement the corresponding block in the wireline receiver shown in Figure 1a, according to one embodiment of the present disclosure, is shown.

[0069] [Figure 15c] A clock circuit block that may implement the corresponding block in the wireline receiver shown in Figure 1a, according to one embodiment of the present disclosure, is shown.

[0070] [Figure 15d] The waveforms and timings of the relevant signals and clocks shown in Figure 15a are illustrated. [Modes for carrying out the invention]

[0071] Figure 1a shows a wireline transceiver system 10 according to one embodiment of the present disclosure; the wireline transceiver system 10 may comprise a wireline transmitter 20, a transmission line 30, and a wireline receiver 100. The transmission line 30 may comprise one or more physical conductive wires. When transmitting data, the wireline transmitter 20 may drive a voltage change on the transmission line 30 in accordance with the serial symbol of the data, thereby forming an electrical signal s1; the signal s1 may be transmitted to the wireline receiver 100 via the transmission line 30 to form a signal s2. The wireline receiver 100 may receive the signal s2, recognize (restore) the symbol of the data in the received signal, and provide a data signal D1 accordingly. In one embodiment, the wireline transceiver system 10 may be an embedded clock data transceiver system; that is, the wireline transmitter 20 does not have to provide any data clock for the timing of individual symbols for the wireline receiver 100, and consequently, the wireline receiver 100 may have to implement clock and data reconstruction in order to reconstruct the data clock from the received signal and to distinguish each symbol from the received signal by sampling according to the trigger of the data clock.

[0072] In one embodiment, the wireline transmitter 20 and the wireline receiver 100 may each reside in two semiconductor devices in two different packages; the two semiconductor devices may be arranged on a printed circuit board, and conductive wiring on the printed circuit board may function as the transmission line 30. In another embodiment, the wireline transmitter 20 and the wireline receiver 100 may each be two semiconductor circuits packaged in the same package (for example, packaged in the same system chip).

[0073] Due to the channel characteristics of the transmission line 30, the received signal of the wireline receiver 100 is plagued not only by noise and jitter, but also by interference such as intersymbol interference. In terms of data transmission efficiency, the wireline transmitter 20 may transmit high-speed electrical signals, but high-speed electrical signals are more susceptible to noise, jitter, and interference. Therefore, how the wireline receiver 100 can effectively overcome noise, jitter, and interference that degrade the reception of high-speed signals is crucial for the development of semiconductor circuit technology in recent years.

[0074] Figure 1b shows an eye diagram of a received signal, where the horizontal axis represents time and the vertical axis represents the signal value (e.g., voltage). In Figure 1b, the shaded area represents the region through which the waveform of the received signal may pass, and the curves c011, c100, c101, and c110 represent various possible waveforms of the received signal. For example, if three consecutive symbols of the received signal are binary 1, 1, and 0, the waveform of the received signal may look like curve c110; if three consecutive symbols of the received signal are 1, 0, and 1, the waveform of the received signal may look like curve c101. In Figure 1b, points cp1, cp2, cp3, and cp4 represent the intersections of the four curves described above. From Figure 1b, curves c011, c100, c101, and c110 enclose an eye-shaped region at four points cp1 to cp4; note that the eye-shaped region has its center at time point ts1 along the horizontal time axis, meaning that time point ts1 is a preferred time point for data sampling. That is, when the wireline receiver 100 reconstructs a data clock from the received signal and distinguishes symbols by sampling according to the trigger of the data clock, if the timing of the data clock is aligned with time point ts1, the accuracy of symbol distinction will effectively increase, jitter will decrease, and the margins related to timing and margins related to signal values ​​(e.g., margins along the vertical axis of the eye diagram) will also be expanded. However, with currently known prior art, it is difficult to align the timing of the data clock with time point ts1 when reconstructing the data clock. For example, as shown in Figure 1b, when a data clock is reconstructed using conventional techniques, the resulting data clock may trigger sampling at time point ts2, i.e., at the center of two time points tz1 and tz2, where time points tz1 and tz2 are located at points cp2 and cp3 along the time axis, respectively. As shown in Figure 1b, time point ts2 is off from the preferred sampling time point ts1, and therefore conventional techniques suffer from high jitter and narrow margins related to timing and signal values.

[0075] As shown in Figure 1a, to implement the present disclosure, the wireline receiver 100 may comprise a front-end circuit block 102, a sampler block 110, a phase detection circuit block 120, and a clock circuit block 130. The front-end circuit block 102 may perform pre-signal processing on the signal s2 (e.g., filtering and amplification) and, accordingly, provide the signal sr1; for example, the front-end circuit block 102 may comprise a linear equalizer (e.g., a continuous-time linear equalizer) and / or a variable-gain amplifier. The structure and operation of the sampler block 110, the phase detection circuit block 120, and the clock circuit block 130 are described by the embodiments below.

[0076] Figure 2a shows a sampler block 210, a phase detection circuit block 220, and a clock circuit block 230 according to one embodiment of the present disclosure; the sampler block 210, the phase detection circuit block 220, and the clock circuit block 230 may implement the sampler block 110, the phase detection circuit block 120, and the clock circuit block 130 shown in Figure 1a, respectively. As shown in Figure 2a, the sampler block 210 may comprise four samplers sa0 to sa3. Sampler sa0 may comprise a signal input terminal, a clock input terminal, a threshold level input terminal, and an output terminal, each coupled to two nodes n1 and n5, a threshold level L0, and another node n2, respectively. Sampler sa1 may comprise a signal input terminal, a clock input terminal, a threshold level input terminal, and an output terminal, each coupled to node n1, node n6, a threshold level L1, and another node a1, respectively. Sampler sa2 may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals connected to nodes n1, n7, threshold level L2, and another node a2, respectively. Sampler sa3 may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals connected to nodes n1, n6, threshold level L3, and another node a3, respectively. Node n1 may be further connected to signal sr1 (also shown in Figure 1a).

[0077] As shown in Figure 2a, the phase detection circuit block 220 may comprise two phase detection circuits 222 and 224. The phase detection circuit 222 may comprise four pattern phase detection units pd1 to pd4 and an internal circuit 2221. Pattern phase detection unit pd1 may comprise a data input terminal, a signal input terminal, and an output terminal, each connected to node n2, node a1, and another node b1, respectively. Pattern phase detection unit pd2 may comprise a data input terminal, a signal input terminal, and an output terminal, each connected to node n2, node a2, and another node b2, respectively. Pattern phase detection unit pd3 may comprise a data input terminal, a signal input terminal, and an output terminal, each connected to node n2, node a3, and another node b3, respectively. Pattern phase detection unit pd4 may comprise a data input terminal, a signal input terminal, and an output terminal, each connected to node n2, node a2, and another node b4, respectively. Internal circuit 2221 may have four input and output terminals connected to nodes b1 to b4 and another node n3, respectively. Phase detection circuit 224 may have two counting circuits 261 and 262 and three internal circuits 2241, 2242, and 2243. Internal circuit 2241 may have two input and output terminals connected to node b1, node b3, and counting circuit 261, respectively. Internal circuit 2242 may have two input and output terminals connected to node b2, node b4, and counting circuit 262, respectively. Internal circuit 2243 may be connected to counting circuit 261, counting circuit 262, and node n4.

[0078] As shown in Figure 2a, the clock circuit block 230 may include a clock circuit 240 and a phase shift circuit 250. The clock circuit 240 may include control input terminals and two clock output terminals coupled to nodes n3, n5, and n6, respectively. The phase shift circuit 250 may include control input terminals and clock output terminals coupled to nodes n4 and n7, respectively. The clock circuit 240 may be controlled by a signal scr1 at node n3, and may provide two clocks ck0 and cke1 at nodes n5 and n6 in response to the signal scr1. When the clock circuit 240 provides clocks ck0 and cke1, the clock circuit 240 may make the frequencies of clocks ck0 and cke1 equal, and may make the phase difference between clocks ck0 and cke1 equal to a predetermined offset value d_p0. In one embodiment, the clock circuit 240 may control the frequency (and / or phase) of clock cke1 according to the signal value of signal scr1, and may shift the phase of clock cke1 to form clock ck0; for example, the clock circuit 240 may invert clock cke1 to form clock ck0 so that clocks ck0 and cke1 are in inverted phase. In one embodiment, the clock circuit 240 may control the frequency (and / or phase) of clock ck0 according to the signal value of signal scr1, and may shift the phase of clock ck0 to form clock cke1; for example, the clock circuit 240 may invert clock cke1 to form clock cke1. The phase shift circuit 250 may be controlled by signal scr2 at node n4, and may provide clock cke2 by phase shifting. When the phase shift circuit 250 provides the clock cke2, the phase shift circuit 250 may make the frequencies of clocks cke1 and cke2 equal, and may make the phase difference between clocks cke2 and cke1 equal to the offset value d_phi, where the offset value d_phi may be controlled by the signal scr2.

[0079] Following Figure 2a, Figure 2b shows examples of the timing and waveforms of the related signals and clocks shown in Figure 2a. As shown in Figure 2b, each of the clocks ck0, cke1, and cke2 from the clock circuit block 230 may periodically alternate between two levels vc0 and vc1, where time points t0[i-1], t0[i], and t0[i+1] may represent three time points where three consecutive effective edges of clock ck0 occur (e.g., an edge where the level changes from vc0 to vc1), and the interval between two consecutive effective edge time points t0[i] and t0[i+1] may be the period T0[i] of clock ck0. Furthermore, the time points t1[i-2], t1[i-1], t1[i], and t1[i+1] may represent four consecutive effective edges of clock cke1, and the interval between two consecutive effective edge time points t1[i] and t1[i+1] may be the period T1[i] of clock cke1. Furthermore, the time points t2[i-1], t2[i], and t2[i+1] may represent three consecutive effective edges of clock cke2, and the interval between two consecutive effective edge time points t2[i] and t2[i+1] may be the period T2[i] of clock cke2. As mentioned above, in one embodiment, the clock circuit 240 may have clocks ck0 and cke1 with equal periods (for example, the time spans of periods T0[i] and T1[i] may be equal), and the phase difference between the two clocks may be equal to an offset value d_p0, for example, 180 degrees. Also, the periods of clocks cke2 and cke1 may be equal, for example, the time spans of periods T2[i] and T1[i] may be equal.

[0080] Returning to Figure 2a; in sampler block 210, sampler sa0 may, when triggered by clock ck0, sample and compare signal sr1 to determine whether signal sr1 exceeds threshold level L0, and accordingly provide signal sd1 at node n2. In one embodiment, sampler sa0 may sample and compare signal sr1 at each effective edge of clock ck0 (for example, at each of the time points t0[i-1], t0[i], and t0[i+1] shown in Figure 2b) to determine whether it is higher than threshold level L0, and accordingly determine the corresponding signal value of signal sd1 (for example, each of the signal values ​​sd1[i-1], sd1[i], and sd1[i+1] shown in Figure 2b). For example, at the effective edge time point t0[i] of clock ck0, if sampler sa0 samples that signal sr1 is higher (greater) than threshold level L0, sampler sa0 may make the corresponding signal value sd1[i] of signal sd1 equal to a defined value H (e.g., logical 1); if sampler sa0 samples that signal sr1 is lower (smaller) than threshold level L0, sampler sa0 may make the signal value sd1[i] of signal sd1 equal to another defined value L (e.g., logical 0). In one embodiment, when performing sampling and comparison, sampler sa0 may first sample signal sr1 and then compare whether the sampled result exceeds threshold level L0; in another embodiment, when performing sampling and comparison, sampler sa0 may continuously compare whether signal sr1 exceeds threshold level L0 to generate a continuous time comparison result, and then sample the comparison result.

[0081] As shown in Figure 2b, the swing range of signal sr1 may extend upward (to become positive) and downward (to become negative) along the vertical axis from the central level v0 (e.g., zero volts), for example, signal sr1 may be obtained from the subtraction of a pair of differential signals. In one embodiment, the threshold level L0 may be equal to level (v0 + vh1) or level (v0 - vh1), where level vh1 may be a constant level. At the effective edge time point t0[i-1] of clock ck0, sampler sa0 may sample and compare whether signal sr1 exceeds the threshold level L0; in the example shown in Figure 2b, signal sr1 is higher than the threshold level L0 at time point t0[i-1], and therefore sampler sa0 may make the corresponding signal value sd1[i-1] of signal sd1 equal to the defined value H. At the next valid edge time point t0[i] of clock ck0, sampler sa0 may again sample and compare whether signal sr1 is above the threshold level L0; in the example shown in Figure 2b, signal sr1 is still above the threshold level L0 at time point t0[i], and therefore sampler sa0 may make the corresponding signal value sd1[i] of signal sd1 equal to the defined value H. Thereafter, at the next valid edge time point t0[i+1] of clock ck0, sampler sa0 may again sample and compare whether signal sr1 is above the threshold level L0; in the example shown in Figure 2b, signal sr1 is below the threshold level L0 at time point t0[i+1], and therefore sampler sa0 may change the corresponding signal value sd1[i+1] of signal sd1 to the defined value L. The signal value of signal sd1 may represent a symbol distinguished from signal sr1 by the wireline receiver 100 (Figure 1a); that is, the wireline receiver 100 shown in Figure 1a may provide a data signal D1 (Figure 1a) corresponding to signal sd1.

[0082] In the sampler block 210 shown in Figure 2a, sampler sa1 may, when triggered by clock cke1, sample and compare signal sr1 to determine whether signal sr1 exceeds threshold level L1, and accordingly provide signal x1 at node a1. In one embodiment, sampler sa1 may sample and compare whether signal sr1 is higher than threshold level L1 at each effective edge of clock cke1 (for example, at each of the time points t1[i-2], t1[i-1], and t1[i] shown in Figure 2b), and accordingly determine the corresponding signal value of signal x1 (for example, each of the signal values ​​x1[i-2], x1[i-1], and x1[i] shown in Figure 2b). For example, at the effective edge time point t1[i] of clock cke1, if sampler sa1 samples that signal sr1 is higher than threshold level L1, sampler sa1 may make the corresponding signal value x1[i] of signal x1 equal to the defined value H; if sampler sa1 samples that signal sr1 is lower than threshold level L1, sampler sa1 may make the signal value x1[i] of signal x1 equal to the defined value L.

[0083] In the sampler block 210, when triggered by the clock cke2, sampler sa2 may sample and compare signal sr1 to determine whether signal sr1 exceeds threshold level L2, and accordingly provide signal x2 at node a2. In one embodiment, sampler sa2 may sample and compare whether signal sr1 is higher than threshold level L2 at each effective edge of clock cke2 (for example, at each of the time points t2[i-2], t2[i-1], and t2[i] shown in Figure 2b), and accordingly determine the corresponding signal value of signal x2 (for example, each of the signal values ​​x2[i-2], x2[i-1], and x2[i] shown in Figure 2b). For example, at the effective edge time point t2[i] of cke2, if sampler sa2 samples that signal sr1 is higher than threshold level L2, sampler sa2 may make the corresponding signal value x2[i] of signal x2 equal to the defined value H; if sampler sa2 samples that signal sr1 is lower than threshold level L2, sampler sa2 may make the signal value x2[i] of signal x2 equal to the defined value L.

[0084] In the sampler block 210, when triggered by the clock cke1, sampler sa3 may sample and compare signal sr1 to determine whether signal sr1 exceeds threshold level L3, and accordingly provide signal x3 at node a3. In one embodiment, sampler sa3 may sample and compare whether signal sr1 is higher than threshold level L3 at each effective edge of clock cke1 (for example, at each of the time points t1[i-2], t1[i-1], and t1[i] shown in Figure 2b), and accordingly determine the corresponding signal value of signal x3 (for example, each of the signal values ​​x3[i-2], x3[i-1], and x3[i] shown in Figure 2b). For example, at the effective edge time point t1[i] of clock cke1, if sampler sa3 samples that signal sr1 is higher than threshold level L3, sampler sa3 may make the corresponding signal value x3[i] of signal x3 equal to the defined value H; if sampler sa3 samples that signal sr1 is lower than threshold level L3, sampler sa3 may make the signal value x3[i] of signal x3 equal to the defined value L.

[0085] In one embodiment, the threshold levels L1, L2, and L3 of samplers sa1, sa2, and sa3 may be different; in one embodiment, threshold level L1 may be higher than threshold level L2, and threshold level L2 may be higher than threshold level L3. In one embodiment, threshold level L2 may be equal to the average of threshold levels L1 and L3 (i.e., L2 = (L1 + L3) / 2). In one embodiment, threshold level L0 of sampler sa0 may be equal to threshold level L1 or L3. As shown in Figure 2b, in one embodiment, threshold levels L1, L2, and L3 may be equal to levels (v0 + vh1), v0, and (v0 - vh1), respectively.

[0086] In the phase detection circuit block 220 shown in Figure 2a, the phase detection circuit 222 may provide signal scr1 at node n3 in response to signals sd1 and x1 to x3, and the phase detection circuit 224 may provide signal scr2 at node n4 in response to signals sd1 and x1 to x3. Following Figure 2a, Figure 2c shows an embodiment of the operation of the phase detection circuit 222 by list. In the phase detection circuit 222, the pattern phase detection unit pd1 may compare whether signal sd1 matches pattern p1, and may provide signal ud1 at node b1 in response to the pattern comparison result and the signal value of signal x1. Pattern p1 may include three constituent values ​​equal to the defined values ​​H, H, and L, respectively. In response to the current signal value x1[i] of signal x1, if the three associated signal values ​​sd1[i-1], sd1[i], and sd1[i+1] of signal sd1 are equal to the three defined values ​​H, H, and L of pattern p1, respectively, then the pattern phase detection unit pd1 may determine that signal sd1 matches pattern p1, and depending on whether the current signal value x1[i] is equal to the defined value L or H, the signal ud1 will display either a speed-up message UP or a speed-down message DN (Figure 2). c) may be asserted; on the other hand, if the three associated signal values ​​of signal sd1, sd1[i-1], sd1[i], and sd1[i+1] are not equal to the three defined values ​​H, H, and L of pattern p1, the pattern phase detection unit pd1 may determine that signal sd1 does not match pattern p1, and regardless of what the signal value x1[i] is equal to, neither the speed-up message UP nor the speed-down message DN is asserted in signal ud1.

[0087] In the phase detection circuit 222, the pattern phase detection unit pd2 may compare whether signal sd1 matches pattern p2, and may provide signal ud2 at node b2 according to the pattern comparison result and the signal value of signal x2. In one embodiment, pattern p2 may include three constituent values ​​equal to the defined values ​​H, L, and H, respectively. In response to the current signal value x2[i] of signal x2, if the three associated signal values ​​sd1[i-1], sd1[i], and sd1[i+1] of signal sd1 are equal to the three defined values ​​H, L, and H of pattern p2, respectively, the pattern phase detection unit pd2 may determine that signal sd1 matches pattern p2, and depending on whether the current signal value x2[i] is equal to the defined value H or L, it may provide the speed-up message UP or the speed-down message DN in signal ud2. The pattern phase detection unit pd2 may assert the above; on the other hand, if the three associated signal values ​​of signal sd1, sd1[i-1], sd1[i], and sd1[i+1] are not equal to the three defined values ​​H, L, and H of pattern p2, the pattern phase detection unit pd2 may determine that signal sd1 does not match pattern p2, and regardless of what the current signal value x2[i] is equal to, it does not need to assert either the speed-up message UP or the speed-down message DN in signal ud2.

[0088] In the phase detection circuit 222, the pattern phase detection unit pd3 may compare whether signal sd1 matches pattern p3, and may provide signal ud3 at node b3 according to the pattern comparison result and the signal value of signal x3. In one embodiment, pattern p3 may include three constituent values ​​equal to the defined values ​​L, L, and H, respectively. In response to the current signal value x3[i] of signal x3, if the three associated signal values ​​sd1[i-1], sd1[i], and sd1[i+1] of signal sd1 are equal to the three defined values ​​L, L, and H of pattern p3, respectively, the pattern phase detection unit pd3 may determine that signal sd1 matches pattern p3, and depending on whether the current signal value x3[i] is equal to the defined value H or L, it may provide the speed-up message UP or the speed-down message DN in signal ud3. The pattern phase detection unit pd3 may assert that the signal sd1 does not match pattern p3, and does not have to assert either the speed-up message UP or the speed-down message DN in the signal ud3, regardless of what the current signal value x3[i] is equal to.

[0089] In the phase detection circuit 222, the pattern phase detection unit pd4 may compare whether signal sd1 matches pattern p4, and may provide signal ud4 at node b4 according to the pattern comparison result and the signal value of signal x2. In one embodiment, pattern p4 may include three constituent values ​​equal to the defined values ​​L, H, and L, respectively. In response to the current signal value x2[i] of signal x2, if the three associated signal values ​​sd1[i-1], sd1[i], and sd1[i+1] of signal sd1 are equal to the three defined values ​​L, H, and L of pattern p4, respectively, the pattern phase detection unit pd4 may determine that signal sd1 matches pattern p4, and depending on whether the current signal value x2[i] is equal to the defined value L or H, it may provide the speed-up message UP or the speed-down message D in signal ud4. N may be asserted; on the other hand, if the three associated signal values ​​of signal sd1, sd1[i-1], sd1[i], and sd1[i+1], are not equal to the three defined values ​​L, H, and L of pattern p4, the pattern phase detection unit pd4 may determine that signal sd1 does not match pattern p4, and regardless of what the signal value x2[i] is equal to, neither the speed-up message UP nor the speed-down message DN may be asserted in signal ud4.

[0090] In the phase detection circuit 222, the internal circuit 2221 may control signal scr1 in accordance with signals ud1 to ud4. When the speed-up message UP is asserted in any one of signals ud1 to ud4, the internal circuit 2221 may respond by asserting the speed-up message UP in signal scr1; when the speed-down message DN is asserted in any one of signals ud1 to ud4, the internal circuit 2221 may respond by asserting the speed-down message DN in signal scr1. In other words, internal circuit 2221 may aggregate signals ud1 to ud4 into signal scr1; internal circuit 2221 may, when signal sd1 matches pattern p1, assert the speed-up message UP or the speed-down message DN in signal scr1 depending on what the signal value of signal x1 is equal to; pattern phase detection unit pd2 may, when signal sd1 matches pattern p2, assert the speed-up message UP or the speed-down message DN in signal scr1 depending on what the signal value of signal x2 is equal to; pattern phase detection unit pd3 may, when signal sd1 matches pattern p3 Depending on what the signal value of signal x3 is equal to, the speed-up message UP or the speed-down message DN may be asserted in signal scr1. When signal sd1 matches pattern p4, the pattern phase detection unit pd4 may assert the speed-up message UP or the speed-down message DN in signal scr1 depending on what the signal value of signal x2 is equal to; on the other hand, if signal sd1 does not match any of patterns p1 to p4, all pattern phase detection units pd1 to pd4 do not need to assert either the speed-up message UP or the speed-down message DN in signal scr1.

[0091] As shown by rows (horizontal lists) r201a and r201b in Figure 2c, when signal sd1 matches pattern p1, pattern phase detection unit pd1 in phase detection circuit 222 may assert speed-up message UP or speed-down message DN in signal ud1, depending on whether the current signal value of signal x1 is equal to the defined value L or H, and consequently may cause internal circuit 2221 to assert speed-up message UP or speed-down message DN in signal scr1; on the other hand, since signal sd1 does not match patterns p2 to p4, pattern phase detection units pd2 to pd4 may not assert either speed-up message UP or speed-down message DN in signals ud2 to ud4, regardless of what the signal values ​​of signals x2 and x3 are equal to (in Figure 2c, "x" indicates "irrelevant") (in Figure 2c, "-" indicates "not asserted").

[0092] Similarly, as shown by rows r202a and r202b in Figure 2c, when signal sd1 matches pattern p2, pattern phase detection unit pd2 in phase detection circuit 222 may assert a speed-up message UP or a speed-down message DN in signal ud2, depending on whether the current signal value of signal x2 is equal to the defined value H or L, and consequently cause internal circuit 2221 to assert a speed-up message UP or a speed-down message DN in signal scr1; on the other hand, since signal sd1 does not match patterns p1, p3, and p4, pattern phase detection units pd1, pd3, and pd4 may not assert either a speed-up message UP or a speed-down message DN in signals ud1, ud3, and ud4, respectively, regardless of what the signal values ​​of signals x1, x2, and x3 are equal to.

[0093] As shown by rows r203a and r203b in Figure 2c, when signal sd1 matches pattern p3, the pattern phase detection unit pd3 in the phase detection circuit 222 may assert a speed-up message UP or a speed-down message DN in signal ud3, depending on whether the current signal value of signal x3 is equal to the defined value H or L, and consequently cause the internal circuit 2221 to assert a speed-up message UP or a speed-down message DN in signal scr1; on the other hand, since signal sd1 does not match patterns p1, p2, and p4, the pattern phase detection units pd1, pd2, and pd4 may not assert either a speed-up message UP or a speed-down message DN in signals ud1, ud2, and ud4, respectively, regardless of what the signal values ​​of signals x1 and x2 are equal to.

[0094] As shown by rows r204a and r204b in Figure 2c, when signal sd1 matches pattern p4, the pattern phase detection unit pd4 in the phase detection circuit 222 may assert a speed-up message UP or a speed-down message DN in signal ud4, depending on whether the current signal value of signal x2 is equal to the defined value L or H, and consequently, may cause the internal circuit 2221 to assert a speed-up message UP or a speed-down message DN in signal scr1; on the other hand, since signal sd1 does not match patterns p1 to p3, the pattern phase detection units pd1 to pd3 do not have to assert either a speed-up message UP or a speed-down message DN in signals ud1 to ud3, regardless of what the signal values ​​of signals x1, x2, and x3 are equal to.

[0095] As shown by row r205 in Figure 2c, when signal sd1 does not match any of patterns p1 to p4, regardless of what the signal values ​​of signals x1 to x3 are equal to, the pattern phase detection units pd1 to pd4 do not need to assert either the speed-up message UP or the speed-down message DN for signals ud1 to ud4, respectively, and consequently, the internal circuit 2221 does not need to assert either the speed-up message UP or the speed-down message DN for signal scr1.

[0096] In the phase detection circuit 224, the internal circuit 2241 may control the counting circuit 261 in accordance with signals ud1 and ud3 in order to accumulate the total number of times the speed-up message UP is asserted in signals ud1 and ud3 (hereinafter referred to as the first speed-up cumulative count), and the total number of times the speed-down message DN is asserted in signals ud1 and ud3 (hereinafter referred to as the first speed-down cumulative count). When the speed-up message UP is asserted in signal ud1, the internal circuit 2241 may cause the counting circuit 261 to increment the first speed-up cumulative count by 1; when the speed-down message DN is asserted in signal ud1, the internal circuit 2241 may cause the counting circuit 261 to increment the first speed-down cumulative count by 1. Furthermore, when the speed-up message UP is asserted in signal ud3, the internal circuit 2241 may cause the counting circuit 261 to increment the first speed-up cumulative count by 1; when the speed-down message DN is asserted in signal ud3, the internal circuit 2241 may cause the counting circuit 261 to increment the first speed-down cumulative count by 1. In other words, each time the speed-up message UP is asserted in either signal ud1 or ud3, the counting circuit 261 may increment the first speed-up cumulative count by 1; each time the speed-down message DN is asserted in either signal ud1 or ud3, the counting circuit 261 may increment the first speed-down cumulative count by 1. On the other hand, if neither the speed-up message UP nor the speed-down message DN is asserted in either of the signals ud1 or ud3, the counting circuit 261 may leave the first speed-up cumulative count and the first speed-down cumulative count unchanged.

[0097] In the phase detection circuit 224, the internal circuit 2242 may control the counting circuit 262 in accordance with signals ud2 and ud4 in order to accumulate the total number of times the speed-up message UP is asserted in signals ud2 and ud4 (hereinafter referred to as the second speed-up cumulative count), and the total number of times the speed-down message DN is asserted in signals ud2 and ud4 (hereinafter referred to as the second speed-down cumulative count). When the speed-up message UP is asserted in signal ud2, the internal circuit 2242 may cause the counting circuit 262 to increment the second speed-up cumulative count by 1; when the speed-down message DN is asserted in signal ud2, the internal circuit 2242 may cause the counting circuit 262 to increment the second speed-down cumulative count by 1. Furthermore, when the speed-up message UP is asserted in signal ud4, the internal circuit 2242 may cause the counting circuit 262 to increment the second speed-up cumulative count by 1; when the speed-down message DN is asserted in signal ud4, the internal circuit 2242 may cause the counting circuit 262 to increment the second speed-down cumulative count by 1. In other words, each time the speed-up message UP is asserted in either signal ud2 or ud4, the counting circuit 262 may increment the second speed-up cumulative count by 1; each time the speed-down message DN is asserted in either signal ud2 or ud4, the counting circuit 262 may increment the second speed-down cumulative count by 1. On the other hand, if neither the speed-up message UP nor the speed-down message DN is asserted in either signal ud2 or ud4, the counting circuit 262 may leave the second speed-up cumulative count and the second speed-down cumulative count unchanged.

[0098] In the phase detection circuit 224, the internal circuit 2243 may control the offset value d_phi of the phase shift circuit 250 according to the cumulative results of the counting circuits 261 and 262. If the value obtained by subtracting the first speed-down cumulative count of the counting circuit 261 (i.e., the total number of times the speed-up message UP was asserted in signals ud1 and ud3) from the first speed-up cumulative count of the counting circuit 261 (i.e., the total number of times the speed-down message DN was asserted in signals ud1 and ud3) exceeds a first preset positive value, then the value obtained by subtracting the second speed-down cumulative count of the counting circuit 262 (i.e., the total number of times the speed-down message DN was asserted in signals ud2 and ud4) If the value obtained by subtracting the second speed-up cumulative count of the counting circuit 262 (i.e., the total number of times the speed-up message UP has been asserted in signals ud2 and ud4) exceeds a fourth preset positive value, the internal circuit 2243 may increment the offset value d_phi and reset each of the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count of the counting circuits 261 and 262 to a reset value (e.g., zero). Furthermore, if the value obtained by subtracting the first speed-up cumulative count of the counting circuit 261 from the first speed-down cumulative count of the counting circuit 261 exceeds a third preset positive value, and the value obtained by subtracting the second speed-down cumulative count of the counting circuit 262 from the second speed-up cumulative count of the counting circuit 262 exceeds a second preset positive value, the internal circuit 2243 may decrement the offset value d_phi and reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count of the counting circuits 261 and 262 to their respective reset values.On the other hand, if the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed a first preset positive value, or if the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed a third preset positive value, then regardless of what the second speed-up cumulative count and the second speed-down cumulative count are equal to, the internal circuit 2243 may leave the offset value d_phi unchanged; and the internal circuit 2243 may not reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count. Similarly, if the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed a fourth preset positive value, or if the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed a second preset positive value, then regardless of what the first speed-up cumulative count and the first speed-down cumulative count are equal to, the internal circuit 2243 may leave the offset value d_phi unchanged; and the internal circuit 2243 may not reset the first speed-up cumulative count, the first speed-down cumulative count, the second speed-up cumulative count, and the second speed-down cumulative count.

[0099] Following Figures 2a and 2c, Figure 2d shows embodiments of the operation of counting circuits 261 and 262 by list. As shown by rows r211a and r213a of Figure 2d, in one embodiment of the present disclosure, whenever the speed-up message UP is asserted in either of the signals ud1 and ud3, the internal circuit 2241 may cause the counting circuit 261 to increment the count cnt1 by a predetermined step value d1 (a positive value, which may be +1); as shown by rows r211b and r213b of Figure 2d, whenever the speed-down message DN is asserted in either of the signals ud1 and ud3, the internal circuit 2241 may cause the counting circuit 261 to decrement the count cnt1 by a step value d1. Furthermore, as shown by rows r212a, r212b, r214a, r214b, and r215 in Figure 2d, when neither the speed-up message UP nor the speed-down message DN is asserted in signals ud1 and ud3, the counting circuit 261 may leave the count cnt1 unchanged (indicated by "-" in Figure 2d). Therefore, the count cnt1 may reflect the value obtained by subtracting the total number of times the speed-down message DN is asserted in signals ud1 and ud3 from the total number of times the speed-up message UP is asserted in signals ud1 and ud3, i.e., the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count.

[0100] Similarly, as shown by rows r212a and r214a of Figure 2d, in one embodiment of the present disclosure, whenever the speed-up message UP is asserted in either signal ud2 or ud4, the internal circuit 2242 may cause the counting circuit 262 to increment the count cnt2 by step value d1; as shown by rows r212b and r214b of Figure 2d, whenever the speed-down message DN is asserted in either signal ud2 or ud4, the internal circuit 2242 may cause the counting circuit 262 to decrement the count cnt2 by step value d1. Furthermore, as shown by rows r211a, r211b, r213a, r213b, and r215 of Figure 2d, when neither the speed-up message UP nor the speed-down message DN is asserted in signals ud2 or ud4, the counting circuit 262 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the total number of times the speed-up message DN was asserted in signals ud2 and ud4 from the total number of times the speed-up message UP was asserted in signals ud2 and ud4, that is, the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count.

[0101] Following Figures 2a to 2d, Figure 2e shows an embodiment of the operation of the internal circuit 2243 in the phase detection circuit 224. As shown in Figure 2e, the internal circuit 2243 may further determine the state of count cnt1 according to the value of count cnt1; when count cnt1 is greater than a predetermined upper limit c_U, the internal circuit 2243 may set the state of count cnt1 to equal state cnt_UP; when count cnt1 is less than a predetermined lower limit c_D, the internal circuit 2243 may set the state of count cnt1 to equal another state cnt_DN; when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 2243 may set the state of count cnt1 to yet another state cnt_normal. Similarly, the internal circuit 2243 may further determine the state of count cnt2 according to the value of count cnt2; when count cnt2 is greater than the upper limit c_U, the internal circuit 2243 may set the state of count cnt2 to state cnt_UP; when count cnt2 is less than the lower limit c_D, the internal circuit 2243 may set the state of count cnt2 to state cnt_DN; when count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 2243 may set the state of count cnt2 to state cnt_normal. The upper limit c_U may be greater than the lower limit c_D.

[0102] As shown in Figure 2e, in one embodiment, the internal circuit 2243 in the phase detection circuit 224 may further adjust the offset value d_phi of the phase shift circuit 250 depending on the state of counts cnt1 and cnt2. As shown by row r221c in Figure 2e, when the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively, the internal circuit 2243 may increase the offset value d_phi of the phase shift circuit 250 via signal scr2, and reset each of counts cnt1 and cnt2 to a predetermined initial value c_0. The initial value c_0 may be greater than the lower limit c_D and less than the upper limit c_U; therefore, when counts cnt1 and cnt2 are reset to the initial value c_0, the states of counts cnt1 and cnt2 may return to equal to state cnt_normal.

[0103] On the other hand, as shown by rows r221a and r221b in Figure 2e, when the state of count cnt1 is equal to state cnt_UP, and the state of count cnt2 is equal to state cnt_UP or cnt_normal, the internal circuit 2243 may leave the offset value d_phi of the phase shift circuit 250 unchanged via signal scr2 (indicated by "-" in Figure 2e), and does not need to reset counts cnt1 and cnt2. Furthermore, as shown by row r223a in Figure 2e, when the states of counts cnt1 and cnt2 are equal to states cnt_DN and cnt_UP, respectively, the internal circuit 2243 may decrease the offset value d_phi of the phase shift circuit 250 via signal scr2, and may reset counts cnt1 and cnt2 to their initial value c_0 so that the state of counts cnt1 and cnt2 may return to state cnt_normal. On the other hand, as shown by rows r223b and r223c in Figure 2e, when the state of count cnt1 is equal to state cnt_DN, and the state of count cnt2 is equal to state cnt_DN or cnt_normal, the internal circuit 2243 may leave the offset value d_phi unchanged and does not need to reset counts cnt1 and cnt2. As shown by rows r221b, r222a to r222c and r223b in Figure 2e, when the state of either one of counts cnt1 or cnt2 is equal to state cnt_normal, the internal circuit 2243 may leave the offset value d_phi unchanged and does not need to reset counts cnt1 and cnt2.

[0104] Following Figures 2a to 2e, Figure 2f shows an example of the change in the values ​​of counts cnt1 and cnt2. In the example shown in Figure 2f, between two time points ta0 and ta1, the speed-down message DN is asserted in signal ud2 or ud4; therefore, at time point ta1, count cnt2 may be decremented by step value d1, and count cnt1 may remain unchanged; at this point, both counts cnt1 and cnt2 may be between the upper limit c_U and the lower limit c_D, and therefore the state of both counts cnt1 and cnt2 may be equal to the state cnt_normal, and the internal circuit 2243 may maintain the offset value d_phi unchanged. Between time point ta1 and the subsequent time point ta2, the speed-down message DN is asserted again by signal ud2 or ud4; therefore, at time point ta2, count cnt2 may be decremented again by step value d1, count cnt1 may remain unchanged, and the states of counts cnt1 and cnt2 may remain equal to the state cnt_normal. Next, between time point ta2 and the subsequent time point ta3, the speed-up message UP is asserted by signal ud1 or ud3; therefore, at time point ta3, count cnt1 may be incremented by step value d1, count cnt2 may remain unchanged, and the states of counts cnt1 and cnt2 may remain equal to the state cnt_normal. Between time point ta3 and the subsequent time point ta4, the speeddown message DN is asserted in signal ud2 or ud4; therefore, at time point ta4, count cnt2 may be decremented to equal the lower limit c_D, count cnt1 may remain unchanged, and the states of counts cnt1 and cnt2 may remain equal to the state cnt_normal.Between time point ta4 and the subsequent time point ta5, the speed-up message UP is asserted in signal ud1 or ud3; therefore, at time point ta5, count cnt1 may be incremented to equal the upper limit c_U, while count cnt2 may remain unchanged.

[0105] Between time point ta5 and the subsequent time point ta6, the speed-up message UP is asserted again in signal ud1 or ud3; therefore, at time point ta6, count cnt1 may be incremented to a value higher than the upper limit c_U, while count cnt2 may remain unchanged; at this point, the state of count cnt1 may change to state cnt_UP, while the state of count cnt2 may still be equal to state cnt_normal, and therefore the internal circuit 2243 does not need to change the offset value d_phi. Between time point ta6 and the subsequent time point ta7, the speed-up message UP is asserted again in signal ud1 or ud3; therefore, at time point ta7, count cnt1 may be incremented again by step value d1, while count cnt2 may remain unchanged; at this point, the states of count cnt1 and cnt2 may be equal to states cnt_UP and cnt_normal, respectively. Between time point ta7 and the subsequent time point ta8, neither the speed-up message UP nor the speed-down message DN is asserted in any of the signals ud1 to ud4; therefore, at time point ta8, counts cnt1 and cnt2 may remain unchanged. Between time point ta8 and the subsequent time point ta9, the speed-down message DN is asserted in either signal ud2 or ud4; therefore, at time point ta9, count cnt2 may decrement to a value lower than the lower limit c_D; and since count cnt2 is below the lower limit c_D, the state of count cnt2 may change to state cnt_DN. At time point ta9, the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively. Therefore, the internal circuit 2243 may operate according to row r221c in Figure 2e and increase the offset value d_phi of the phase shift circuit 250 via signal scr2. At the subsequent time point ta10, counts cnt1 and cnt2 may be reset to their initial value c_0 so that the states of counts cnt1 and cnt2 can return to state cnt_normal.After time point ta10, count cnt1 may be incremented or decremented again because the speed-up message UP or the speed-down message DN is asserted in either signal ud1 or ud3, and count cnt2 may be incremented or decremented again because the speed-up message UP or the speed-down message DN is asserted in either signal ud2 or ud4. In the time points ta0 to ta10 shown in Figure 2f, the time span between every two consecutive time points (for example, between time points ta0 and ta1, between time points ta1 and ta2, etc.) may be equal to the period of clock cke1.

[0106] Returning to Figure 2a, when the clock circuit 240 provides clocks cke1 and ck0 in response to the signal scr1 of the phase detection circuit 222, the clock circuit 240 may adjust the frequency (and / or phase) of clocks cke1 and ck0 in response to the count of the number of times the speed-up message UP has been asserted in signal scr1 and the count of the number of times the speed-down message DN has been asserted in signal scr1. For example, if the count of times the speed-up message UP has been asserted in signal scr1 is greater than the count of times the speed-down message DN has been asserted by a predetermined first tolerance value, the clock circuit 240 may accelerate the timing of clocks cke1 and ck0, for example, by increasing (incrementing) the frequencies of clocks cke1 and ck0; furthermore, the clock circuit 240 may reset the count of times the speed-up message UP has been asserted in signal scr1 to its original value, and may reset the count of times the speed-down message DN has been asserted in signal scr1 to its original value; On the other hand, if the count of times the speed-down message DN has been asserted in signal scr1 is greater than the count of times the speed-up message UP has been asserted by a predetermined second tolerance value, the clock circuit 240 may decelerate the timing of clocks cke1 and ck0, for example, by decreasing (decrementing) the frequencies of clocks cke1 and ck0; furthermore, the clock circuit 240 may reset the count of times the speed-up message UP has been asserted in signal scr1 to its original value, and may also reset the count of times the speed-down message DN has been asserted in signal scr1 to its original value.As shown in Figure 2c, each time the speed-up message UP is asserted in any one of the signals ud1 to ud4, the internal circuit 2221 of the phase detection circuit 222 may assert the speed-up message UP in signal scr1. Therefore, the count of the number of times the speed-up message UP is asserted in signal scr1 may be equal to the total number of times the speed-up message UP is asserted in signals ud1 to ud4. Furthermore, each time the speed-down message DN is asserted in any one of the signals ud1 to ud4, the internal circuit 2221 of the phase detection circuit 222 may assert the speed-down message DN in signal scr1. Therefore, the count of the number of times the speed-down message DN is asserted in signal scr1 may be equal to the total number of times the speed-down message DN is asserted in signals ud1 to ud4. In short, the operating principle of the clock circuit 240 is to balance the count of the number of times the speed-up message UP is asserted on signal scr1 and the count of the number of times the speed-down message DN is asserted on signal scr1 by adjusting the timing of clocks cke1 and ck0.

[0107] In the circuit configuration shown in Figure 2a, the clock circuit 240 may adjust the timing of clocks cke1 and ck0 in accordance with the signal scr1 from the phase detection circuit 222, while the phase shift circuit 250 may adjust the offset value d_phi in accordance with the signal scr2 from the phase detection circuit 224, thereby adjusting the timing of clock cke2. The timing adjustment of the clock circuit 240 and the timing adjustment of the phase shift circuit 250 may be based on different principles. For example, as explained earlier, during the time points ta0 to ta10 shown in Figure 2f, the states of count cnt1 (related to signals ud1 and ud3 of pattern phase detection units pd1 and pd3) and count cnt2 (related to signals ud2 and ud4 of pattern phase detection units pd2 and pd4) change from state cnt_normal to state cnt_UP and cnt_DN, respectively, so the phase shift circuit 250 may adjust (increase) the offset value d_phi. On the other hand, during the time points ta0 to ta10 shown in Figure 2f, the count of times the speed-up message UP is asserted in signal scr1 is equal to the count of times the speed-down message DN is asserted in signal scr1, so the clock circuit 240 does not need to adjust the timing of clocks cke1 and ck0; in signal scr1, the count of times the speed-up message UP is asserted is provided by signals ud1 and ud3 of pattern phase detection units pd1 and pd3, while the count of times the speed-down message DN is asserted is equal to the count of times the speed-down message DN is asserted. The count is provided by signals ud2 and ud4 of the other two pattern phase detection units pd2 and pd4, but the phase detection circuit 222 that provides signal scr1 does not need to be concerned with which of the pattern phase detection units pd1 to pd4 causes each of the speed-up messages UP and each of the speed-down messages DN to assert; therefore, the timing adjustments performed by the clock circuit 240 on the clocks ck0 and cke1 may not need to be able to determine what caused the speed-up messages UP and speed-down messages DN.

[0108] In Figure 2a, signal sr1 may be referred to as the receiver signal; when the circuit configuration shown in Figure 2a operates to distinguish each symbol in signal sr1 (for example, symbols sr1[i-1], sr1[i], and sr1[i+1] shown in Figure 2b), the active edges of clocks cke1 and cke2 may track (and / or reflect) the edges of the symbols, and thus clocks cke1 and cke2 may be referred to as the first edge clock and the second edge clock, respectively; in addition, the active edges of clock ck0 may track (and / or reflect) the time axis center of the symbols, and thus clock ck0 may be referred to as the data clock; sampler sa0 triggered by clock ck0 may be referred to as the data sampler; threshold level L0 utilized by sampler sa0 may be referred to as the data threshold level; and signal sd1 provided by sampler sa0 may be referred to as the data signal. Furthermore, samplers sa1, sa2, and sa3 may be referred to as the first edge sampler, the second edge sampler, and the third edge sampler, respectively, and threshold levels L1, L2, and L3 may be referred to as the first threshold level, the second threshold level, and the third threshold level, respectively.

[0109] In Figure 2a, the signal x1 provided by sampler sa1 may be referred to as the first edge signal; when signal sd1 matches pattern p1 (equal to the defined values ​​H, H, L), the signal value of signal x1 may reflect whether the corresponding active edge of clock cke1 is earlier or later than the associated edge of signal sd1 changing from the defined value H to L (i.e., when signal sd1 crosses the threshold level L1). When signal sd1 matches pattern p1, the situation in which the signal value of signal x1 is equal to the defined value H may indicate that the corresponding active edge of clock cke1 is earlier than the associated edge of signal sd1 changing from the defined value H to L, and therefore the pattern phase detection unit pd1 may assert the speed-down message DN in signal ud1, as shown by line r201b in Figure 2c. On the other hand, when signal sd1 matches pattern p1, the moment when the signal value of signal x1 is equal to the defined value L occurs later than the corresponding effective edge of clock cke1, which changes from the defined value H to L, and therefore the pattern phase detection unit pd1 may assert the speed-up message UP in signal ud1, as shown by row r201a in Figure 2c.

[0110] In Figure 2a, the signal x2 provided by sampler sa2 may be referred to as the second edge signal; when signal sd1 matches pattern p2 (equal to the defined values ​​H, L, H), the signal value of signal x2 may reflect whether the corresponding active edge of clock cke2 is earlier or later than the associated edge of signal sd1 changing from the defined value L to H (i.e., when signal sd1 crosses the threshold level L2). When signal sd1 matches pattern p2, the situation in which the signal value of signal x2 is equal to the defined value L means that the corresponding active edge of clock cke2 is earlier than the associated edge of signal sd1 changing from the defined value L to H, and therefore the pattern phase detection unit pd2 may assert the speed-down message DN in signal ud2, as shown by line r202b in Figure 2c. On the other hand, when signal sd1 matches pattern p2, the moment when the signal value of signal x2 is equal to the defined value H occurs later than the corresponding effective edge of clock cke2, which is associated with signal sd1, when the signal changes from the defined value L to H. Therefore, the pattern phase detection unit pd2 may assert the speed-up message UP in signal ud2, as shown by row r202a in Figure 2c.

[0111] In Figure 2a, the signal x3 provided by sampler sa3 may be referred to as the third edge signal; when signal sd1 matches pattern p3 (equal to the defined values ​​L, L, H), the signal value of signal x3 may reflect whether the corresponding active edge of clock cke1 is earlier or later than the associated edge of signal sd1 changing from the defined value L to H (i.e., when signal sd1 crosses the threshold level L3). When signal sd1 matches pattern p3, the situation in which the signal value of signal x3 is equal to the defined value L is earlier than the corresponding active edge of clock cke1 changing from the defined value L to H, and therefore the pattern phase detection unit pd3 may assert the speed-down message DN in signal ud3, as shown by line r203b in Figure 2c. On the other hand, when signal sd1 matches pattern p3, the moment when the signal value of signal x3 is equal to the defined value H occurs later than the corresponding effective edge of clock cke1, which changes from the defined value L to H, and therefore the pattern phase detection unit pd3 may assert the speed-up message UP in signal ud3, as shown by row r203a in Figure 2c.

[0112] In addition, when signal sd1 matches pattern p4 (equal to the defined values ​​L, H, L), the signal value of signal x2 may reflect whether the corresponding effective edge of clock cke2 changes earlier or later than the associated edge of signal sd1 where the defined value changes from H to L (i.e., when signal sd1 crosses the threshold level L2). When signal sd1 matches pattern p4, the situation in which the signal value of signal x2 is equal to the defined value H means that the corresponding effective edge of clock cke2 changes earlier than the associated edge of signal sd1 where the defined value changes from H to L, and therefore the pattern phase detection unit pd4 may assert the speed-down message DN in signal ud4, as shown by row r204b in Figure 2c. On the other hand, when signal sd1 matches pattern p4, the moment when the signal value of signal x2 is equal to the defined value L occurs later than the corresponding effective edge of clock cke2, which changes from the defined value H to L, and therefore the pattern phase detection unit pd4 may assert the speed-up message UP in signal ud4, as shown by row r204a in Figure 2c.

[0113] In Figure 2a, patterns p1 to p4 may be referred to as the first pattern to the fourth pattern, respectively. In the three component values ​​of pattern p1 (equal to defined values ​​H, H, L) and the three component values ​​of pattern p3 (equal to defined values ​​L, L, H), the first component value and the second component value may be equal, so patterns p1 and p3 may be referred to as low-frequency patterns. In the three component values ​​of pattern p2 (equal to defined values ​​H, L, H) and the three component values ​​of pattern p4 (equal to defined values ​​L, H, L), the first component value may be different from the second component value, and the second component value may be different from the third component value, so patterns p2 and p4 may be referred to as high-frequency patterns. In Figure 2a, the phase detection circuits 222 and 224 may be referred to as the base phase detection circuit and the additional phase detection circuit, respectively; the signals scr1 and scr2 may be referred to as the base timing control signal and the additional timing control signal, respectively; and the offset values ​​d_p0 and d_phi may be referred to as the base offset value and the additional offset value, respectively.

[0114] Following Figures 1a and 2a, Figure 3a shows a sampler block 310 and a phase detection circuit block 320 according to one embodiment of the present disclosure; the sampler block 310 and the phase detection circuit block 320 may work in conjunction with the clock circuit block 230 shown in Figure 2a (also shown in Figure 3a) to implement the sampler block 110, the phase detection circuit block 120, and the clock circuit block 130 shown in Figure 1a, respectively. As shown in Figure 3a, the sampler block 310 may comprise samplers sa0 to sa2 (as already described when referring to Figure 2a), and the phase detection circuit block 320 may comprise two phase detection circuits 322 and 324. The phase detection circuit 322 may be a base phase detection circuit and may comprise pattern phase detection units pd1 and pd2 (as already described when referring to Figure 2a), as well as an internal circuit 3221. The phase detection circuit 324 may be an additional phase detection circuit and may comprise three internal circuits 3241, 3242, and 3243 and two counting circuits 361 and 362.

[0115] In the phase detection circuit 322, the internal circuit 3221 may have two input terminals and an output terminal connected to nodes b1, b2, and n3, respectively. In the phase detection circuit 324, the internal circuit 3241 may have input terminals and an output terminal connected to node b1 and counting circuit 361, respectively, and the internal circuit 3242 may have input terminals and an output terminal connected to node b2 and counting circuit 362, respectively. The internal circuit 3243 may be connected to counting circuits 361, 362, and node n4.

[0116] In Figure 3a, the phase detection circuit 322 may provide signal scr1 at node n3 in response to signals sd1, x1, and x2, and the phase detection circuit 324 may likewise provide signal scr2 at node n4 in response to signals sd1, x1, and x2. When the speed-up message UP is asserted in either one of signals ud1 and ud2, the internal circuit 3221 may respond by asserting the speed-up message UP in signal scr1; when the speed-down message DN is asserted in either one of signals ud1 and ud2, the internal circuit 3221 may respond by asserting the speed-down message DN in signal scr1.

[0117] Following Figure 3a, Figure 3b lists embodiments of the operation of the phase detection circuit 322. As shown by rows r301a and r301b in Figure 3b, when signal sd1 matches pattern p1, and therefore pattern phase detection unit pd1 asserts a speed-up message UP or a speed-down message DN in signal ud1 according to the signal value of signal x1, the internal circuit 3221 in the phase detection circuit 322 may subsequently assert a speed-up message UP or a speed-down message DN in signal scr1. As shown by rows r302a and r302b in Figure 3b, when signal sd1 matches pattern p2, and therefore pattern phase detection unit pd2 asserts a speed-up message UP or a speed-down message DN in signal ud2 according to the signal value of signal x2, the internal circuit 3221 in the phase detection circuit 322 may subsequently assert a speed-up message UP or a speed-down message DN in signal scr1. As shown by row r303 in Figure 3b, when signal sd1 does not match either of patterns p1 and p2, and therefore pattern phase detection units pd1 and pd2 do not assert any speed-up message UP and no speed-down message DN, the internal circuit 3221 in the phase detection circuit 322 does not need to assert either the speed-up message UP or the speed-down message DN for signal scr1.

[0118] Following Figures 3a and 3b, Figure 3c lists embodiments of the operation of counting circuits 361 and 362. As shown by row r311a in Figure 3c, whenever the speed-up message UP is asserted in signal ud1, the internal circuit 3241 may cause the counting circuit 361 to increment the count cnt1 by step value d1; as shown by row r311b in Figure 3c, whenever the speed-down message DN is asserted in signal ud1, the internal circuit 3241 may cause the counting circuit 361 to decrement the count cnt1 by step value d1. Furthermore, as shown by rows r312a, r312b, and r313, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud1, the counting circuit 361 may leave the count cnt1 unchanged. Therefore, the count cnt1 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud1 from the number of times the speed-up message UP was asserted in signal ud1.

[0119] Similarly, as shown by row r312a in Figure 3c, whenever the speed-up message UP is asserted in signal ud2, the internal circuit 3242 may cause the counting circuit 362 to increment the count cnt2 by step value d1; as shown by row r312b in Figure 3c, whenever the speed-down message DN is asserted in signal ud2, the internal circuit 3242 may cause the counting circuit 362 to decrement the count cnt2 by step value d1. Furthermore, as shown by rows r311a, r311b, and r313, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud2, the counting circuit 362 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the number of times the speed-down message DN is asserted in signal ud2 from the number of times the speed-up message UP is asserted in signal ud2.

[0120] In the phase detection circuit 324 shown in Figure 3a, the operation of the internal circuit 3243 may be the same as the operation of the internal circuit 2243 shown in Figure 2a, as shown in Figure 2e. In one embodiment, the internal circuit 3243 may determine the states of counts cnt1 and cnt2 according to the values ​​of counts cnt1 and cnt2, respectively, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the states of the two counts. When count cnt1 exceeds the upper limit c_U (Figure 2e), the internal circuit 3243 may set the state of count cnt1 to equal state cnt_UP; when count cnt1 falls below the lower limit c_D, the internal circuit 3243 may set the state of count cnt1 to equal state cnt_DN; and when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 3243 may set the state of count cnt1 to equal state cnt_normal. Similarly, when the count cnt2 exceeds the upper limit c_U, the internal circuit 3243 may set the state of the count cnt2 to equal the state cnt_UP; when the count cnt2 falls below the lower limit c_D, the internal circuit 3243 may set the state of the count cnt2 to equal the state cnt_DN; and when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 3243 may set the state of the count cnt2 to equal the state cnt_normal.

[0121] When the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively, the internal circuit 3243 in the phase detection circuit 324 may increase the offset value d_phi and reset counts cnt1 and cnt2 to their initial value c_0 so that the states of counts cnt1 and cnt2 may return to state cnt_normal; when the states of counts cnt1 and cnt2 are equal to states cnt_DN and cnt_UP, respectively, the internal circuit 3243 may decrease the offset value d_phi and reset counts cnt1 and cnt2 to their initial value c_0 so that the states of counts cnt1 and cnt2 may return to state cnt_normal; in all other cases, the internal circuit 3243 may leave the offset value d_phi unchanged and not reset counts cnt1 and cnt2.

[0122] Following Figures 1a, 2a, and 3a, Figure 4a shows a phase detection circuit block 420 according to one embodiment of the present disclosure; the phase detection circuit block 420 may work in conjunction with the clock circuit block 230 shown in Figure 2a (also shown in Figure 4a) and the sampler block 310 shown in Figure 3a (also shown in Figure 4a) to implement the phase detection circuit block 120, clock circuit block 130, and sampler block 110 shown in Figure 1a, respectively. As shown in Figure 4a, the phase detection circuit block 420 may comprise two phase detection circuits 422 and 424. Phase detection circuit 422 may be a base phase detection circuit and may comprise pattern phase detection units pd1 and pd4 (already described when referring to Figure 2a), as well as an internal circuit 4221. The phase detection circuit 424 may be an additional phase detection circuit and may comprise three internal circuits 4241, 4242, and 4243, and two counting circuits 461 and 462.

[0123] In the phase detection circuit 422, the internal circuit 4221 may have two input terminals and an output terminal connected to nodes b1, b4, and n3, respectively. In the phase detection circuit 424, the internal circuit 4241 may have input terminals and an output terminal connected to node b1 and counting circuit 461, respectively, and the internal circuit 4242 may have input terminals and an output terminal connected to node b4 and counting circuit 462, respectively. The internal circuit 4243 may be connected to counting circuit 461, counting circuit 462, and node n4.

[0124] In Figure 4a, the phase detection circuit 422 may provide signal scr1 at node n3 in response to signals sd1, x1, and x2, and the phase detection circuit 424 may similarly provide signal scr2 at node n4 in response to signals sd1, x1, and x2. When the speed-up message UP is asserted in either one of signals ud1 and ud4, the internal circuit 4221 may respond by asserting the speed-up message UP in signal scr1; when the speed-down message DN is asserted in either one of signals ud1 and ud4, the internal circuit 4221 may respond by asserting the speed-down message DN in signal scr1.

[0125] Following Figure 4a, Figure 4b lists embodiments of the operation of the phase detection circuit 422. As shown by rows r401a and r401b in Figure 4b, when signal sd1 matches pattern p1, and therefore pattern phase detection unit pd1 asserts a speed-up message UP or a speed-down message DN in signal ud1 according to the signal value of signal x1, the internal circuit 4221 in the phase detection circuit 4222 may subsequently assert a speed-up message UP or a speed-down message DN in signal scr1. As shown by rows r402a and r402b in Figure 4b, when signal sd1 matches pattern p4, and therefore pattern phase detection unit pd4 asserts a speed-up message UP or a speed-down message DN in signal ud4 according to the signal value of signal x2, the internal circuit 4221 in the phase detection circuit 4222 may subsequently assert a speed-up message UP or a speed-down message DN in signal scr1. As shown by row r403 in Figure 4b, when signal sd1 does not match either of patterns p1 and p4, and therefore pattern phase detection units pd1 and pd4 do not assert any speed-up message UP and no speed-down message DN, the internal circuit 4221 in the phase detection circuit 422 does not have to assert either the speed-up message UP or the speed-down message DN in signal scr1.

[0126] Following Figures 4a and 4b, Figure 4c lists embodiments of the operation of counting circuits 461 and 462. As shown by row r411a in Figure 4c, whenever the speed-up message UP is asserted in signal ud1, the internal circuit 4241 of the phase detection circuit 424 may cause the counting circuit 461 to increment the count cnt1 by step value d1; as shown by row r411b in Figure 4c, whenever the speed-down message DN is asserted in signal ud1, the internal circuit 4241 may cause the counting circuit 461 to decrement the count cnt1 by step value d1. Furthermore, as shown by rows r412a, r412b and r413, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud1, the counting circuit 461 may leave the count cnt1 unchanged. Therefore, the count cnt1 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud1 from the number of times the speed-up message UP was asserted in signal ud1.

[0127] Similarly, as shown by row r412a in Figure 4c, whenever the speed-up message UP is asserted in signal ud4, the internal circuit 4242 may cause the counting circuit 462 to increment the count cnt2 by step value d1; as shown by row r412b in Figure 4c, whenever the speed-down message DN is asserted in signal ud4, the internal circuit 4242 may cause the counting circuit 462 to decrement the count cnt2 by step value d1. Furthermore, as shown by rows r411a, r411b and r413, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud4, the counting circuit 462 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the number of times the speed-down message DN is asserted in signal ud4 from the number of times the speed-up message UP is asserted in signal ud4.

[0128] In the phase detection circuit 424 shown in Figure 4a, the operation of the internal circuit 2243 shown in Figure 2a and the operation of the internal circuit 4243 may be the same as shown in Figure 2e. In one embodiment, the internal circuit 4243 may determine the states of counts cnt1 and cnt2 according to the values ​​of counts cnt1 and cnt2, respectively, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the states of the two counts. When count cnt1 is greater than the upper limit c_U (Figure 2e), the internal circuit 4243 may set the state of count cnt1 to equal the state cnt_UP; when count cnt1 is less than the lower limit c_D, the internal circuit 4243 may set the state of count cnt1 to equal the state cnt_DN; when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 4243 may set the state of count cnt1 to equal the state cnt_normal. Similarly, when the count cnt2 is greater than the upper limit c_U, the internal circuit 4243 may set the state of the count cnt2 to equal the state cnt_UP; when the count cnt2 is less than the lower limit c_D, the internal circuit 4243 may set the state of the count cnt2 to equal the state cnt_DN; and when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 4243 may set the state of the count cnt2 to equal the state cnt_normal.

[0129] When the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively, the internal circuit 4243 of the phase detection circuit 424 may increase the offset value d_phi of the phase shift circuit 250 via the signal scr2, and reset counts cnt1 and cnt2 to their initial value c_0 so that the states of counts cnt1 and cnt2 may return to state cnt_normal; when the states of counts cnt1 and cnt2 are equal to states cnt_DN and cnt_UP, respectively, the internal circuit 4243 may decrease the offset value d_phi, and reset counts cnt1 and cnt2 to their initial value c_0 so that the states of counts cnt1 and cnt2 may return to state cnt_normal; in situations other than the two above, the internal circuit 4243 may leave the offset value d_phi unchanged and not reset counts cnt1 and cnt2.

[0130] Following Figures 1a and 2a, Figure 5a shows a sampler block 510 and a phase detection circuit block 520 according to one embodiment of the present disclosure; the sampler block 510 and the phase detection circuit block 520 may work in conjunction with the clock circuit block 230 shown in Figure 2a (also shown in Figure 5a) to implement the sampler block 110, the phase detection circuit block 120, and the clock circuit block 130 shown in Figure 1a, respectively. As shown in Figure 5a, the sampler block 510 may include samplers sa0, sa2, and sa3 (as already described when referring to Figure 2a), and the phase detection circuit block 520 may comprise two phase detection circuits 522 and 524. The phase detection circuit 522 may be a base phase detection circuit and may comprise pattern phase detection units pd2 and pd3 (as already described when referring to Figure 2a) in addition to the internal circuit 5221. The phase detection circuit 524 may be an additional phase detection circuit and may include internal circuits 5241, 5242, and 5243 and two counting circuits 561 and 562.

[0131] In the phase detection circuit 522, the internal circuit 5221 may have two input terminals and an output terminal connected to nodes b2, b3, and n3, respectively. In the phase detection circuit 524, the internal circuit 5241 may include input terminals and an output terminal connected to node b3 and counting circuit 561, respectively, and the internal circuit 5242 may have input terminals and an output terminal connected to node b2 and counting circuit 562, respectively. The internal circuit 5243 may be connected to counting circuits 561, 562, and node n4.

[0132] In Figure 5a, the phase detection circuit 522 may provide signal scr1 at node n3 in response to signals sd1, x2, and x3, and the phase detection circuit 524 may similarly provide signal scr2 at node n4 in response to signals sd1, x2, and x3. When the speed-up message UP is asserted in either one of signals ud2 and ud3, the internal circuit 5221 may respond by asserting the speed-up message UP in signal scr1; when the speed-down message DN is asserted in either one of signals ud2 and ud3, the internal circuit 5221 may respond by asserting the speed-down message DN in signal scr1.

[0133] Following Figure 5a, Figure 5b lists embodiments of the operation of the phase detection circuit 522. As shown by rows r501a and r501b in Figure 5b, when signal sd1 matches pattern p2, and therefore pattern phase detection unit pd2 asserts speed-up message UP or speed-down message DN in signal ud2 according to the signal value of signal x2, the internal circuit 5221 in the phase detection circuit 522 may subsequently assert speed-up message UP or speed-down message DN in signal scr1. As shown by rows r502a and r502b in Figure 5b, when signal sd1 matches pattern p3, and therefore pattern phase detection unit pd3 asserts speed-up message UP or speed-down message DN in signal ud3 according to the signal value of signal x3, the internal circuit 5221 in the phase detection circuit 522 may subsequently assert speed-up message UP or speed-down message DN in signal scr1. As shown by row r503 in Figure 5b, when signal sd1 does not match either of patterns p2 and p3, and therefore pattern phase detection units pd2 and pd3 do not assert any speed-up message UP and no speed-down message DN, the internal circuit 5221 in the phase detection circuit 522 does not need to assert either the speed-up message UP or the speed-down message DN for signal scr1.

[0134] Following Figures 5a and 5b, Figure 5c lists embodiments of the operation of counting circuits 561 and 562. As shown by row r512a in Figure 5c, whenever the speed-up message UP is asserted in signal ud3, the internal circuit 5241 may cause the counting circuit 561 to increment the count cnt1 by step value d1; as shown by row r512b in Figure 5c, whenever the speed-down message DN is asserted in signal ud3, the internal circuit 5241 may cause the counting circuit 561 to decrement the count cnt1 by step value d1. Furthermore, as shown by rows r511a, r511b and r513, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud3, the counting circuit 561 may leave the count cnt1 unchanged. Therefore, the count cnt1 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud3 from the number of times the speed-up message UP was asserted in signal ud3.

[0135] Similarly, as shown by row r511a in Figure 5c, whenever the speed-up message UP is asserted in signal ud2, the internal circuit 5242 may cause the counting circuit 562 to increment the count cnt2 by step value d1; as shown by row r511b in Figure 5c, whenever the speed-down message DN is asserted in signal ud2, the internal circuit 5242 may cause the counting circuit 562 to decrement the count cnt2 by step value d1. Furthermore, as shown by rows r512a, r512b and r513, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud2, the counting circuit 562 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the number of times the speed-down message DN is asserted in signal ud2 from the number of times the speed-up message UP is asserted in signal ud2.

[0136] In the phase detection circuit 524 shown in Figure 5a, the operation of the internal circuit 2243 shown in Figure 2a and the operation of the internal circuit 5243 may be the same as shown in Figure 2e. In one embodiment, the internal circuit 5243 may determine the states of counts cnt1 and cnt2 according to the values ​​of counts cnt1 and cnt2, respectively, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the states of the two counts. When count cnt1 is greater than the upper limit c_U (Figure 2e), the internal circuit 5243 may set the state of count cnt1 to equal state cnt_UP; when count cnt1 is less than the lower limit c_D, the internal circuit 5243 may set the state of count cnt1 to equal state cnt_DN; when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 5243 may set the state of count cnt1 to equal state cnt_normal. Similarly, when the count cnt2 is greater than the upper limit c_U, the internal circuit 5243 may set the state of the count cnt2 to equal the state cnt_UP; when the count cnt2 is less than the lower limit c_D, the internal circuit 5243 may set the state of the count cnt2 to equal the state cnt_DN; and when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 5243 may set the state of the count cnt2 to equal the state cnt_normal.

[0137] When the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively, the internal circuit 5243 in the phase detection circuit 524 may increase the offset value d_phi of the phase shift circuit 250 via the signal scr2, and reset counts cnt1 and cnt2 to their initial value c_0 so that the states of counts cnt1 and cnt2 may return to state cnt_normal; when the states of counts cnt1 and cnt2 are equal to states cnt_DN and cnt_UP, respectively, the internal circuit 5243 may decrease the offset value d_phi, and reset counts cnt1 and cnt2 to their initial value c_0 so that the states of counts cnt1 and cnt2 may return to state cnt_normal; in all other cases, the internal circuit 5243 may leave the offset value d_phi unchanged and not reset counts cnt1 and cnt2.

[0138] Following Figures 1a, 2a, and 5a, Figure 6a shows a phase detection circuit block 620 according to one embodiment of the present disclosure; the phase detection circuit block 620 may work in conjunction with the clock circuit block 230 shown in Figure 2a (also shown in Figure 6a) and the sampler block 510 shown in Figure 5a (also shown in Figure 6a) to implement the phase detection circuit block 120, clock circuit block 130, and sampler block 110 shown in Figure 1a, respectively. As shown in Figure 6a, the phase detection circuit block 620 may comprise two phase detection circuits 622 and 624. The phase detection circuit 622 may be a base phase detection circuit and may comprise pattern phase detection units pd3 and pd4 (already described when referring to Figure 2a) in addition to the internal circuit 6221. The phase detection circuit 624 may be an additional phase detection circuit and may comprise three internal circuits 6241, 6242, and 6243, and two counting circuits 661 and 662.

[0139] In the phase detection circuit 622, the internal circuit 6221 may have two input terminals and an output terminal connected to nodes b3, b4, and n3, respectively. In the phase detection circuit 624, the internal circuit 6241 may include input terminals and an output terminal connected to node b3 and counting circuit 661, respectively, and the internal circuit 6242 may have input terminals and an output terminal connected to node b4 and counting circuit 662, respectively. The internal circuit 6243 may be connected to counting circuits 661, 662, and node n4.

[0140] In Figure 6a, the phase detection circuit 622 may provide signal scr1 at node n3 in response to signals sd1, x2, and x3, and the phase detection circuit 624 may similarly provide signal scr2 at node n4 in response to signals sd1, x2, and x3. When the speed-up message UP is asserted in either one of signals ud3 and ud4, the internal circuit 6221 may respond by asserting the speed-up message UP in signal scr1; when the speed-down message DN is asserted in either one of signals ud3 and ud4, the internal circuit 6221 may respond by asserting the speed-down message DN in signal scr1.

[0141] Following Figure 6a, Figure 6b lists embodiments of the operation of the phase detection circuit 622. As shown by rows r601a and r601b in Figure 6b, when signal sd1 matches pattern p3, and therefore pattern phase detection unit pd3 asserts a speed-up message UP or a speed-down message DN in signal ud3 according to the signal value of signal x3, the internal circuit 6221 in the phase detection circuit 622 may assert a speed-up message UP or a speed-down message DN in signal scr1 in correspondence. As shown by rows r602a and r602b in Figure 6b, when signal sd1 matches pattern p4, and therefore pattern phase detection unit pd4 asserts a speed-up message UP or a speed-down message DN in signal ud4 according to the signal value of signal x2, the internal circuit 6221 in the phase detection circuit 622 may assert a speed-up message UP or a speed-down message DN in signal scr1 in correspondence. As shown by row r603 in Figure 6b, when signal sd1 does not match either of patterns p3 and p4, and therefore pattern phase detection units pd3 and pd4 do not assert any speed-up message UP and no speed-down message DN, the internal circuit 6221 in the phase detection circuit 622 does not need to assert either the speed-up message UP or the speed-down message DN in signal scr1.

[0142] Following Figures 6a and 6b, Figure 6c lists embodiments of the operation of counting circuits 661 and 662. As shown by row r611a in Figure 6c, whenever the speed-up message UP is asserted in signal ud3, the internal circuit 6241 may cause the counting circuit 661 to increment the count cnt1 by step value d1; as shown by row r611b in Figure 6c, whenever the speed-down message DN is asserted in signal ud3, the internal circuit 6241 may cause the counting circuit 661 to decrement the count cnt1 by step value d1. Furthermore, as shown by rows r612a, r612b and r613, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud3, the counting circuit 661 may leave the count cnt1 unchanged. Therefore, the count cnt1 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud3 from the number of times the speed-up message UP was asserted in signal ud3.

[0143] Similarly, as shown by line r612a in Figure 6c, whenever the speed-up message UP is asserted in signal ud4, the internal circuit 6242 may cause the counting circuit 662 to increment the count cnt2 by step value d1; as shown by line r612b in Figure 6c, whenever the speed-down message DN is asserted in signal ud4, the internal circuit 6242 may cause the counting circuit 662 to decrement the count cnt2 by step value d1. Furthermore, as shown by lines r611a, r611b and r613, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud4, the counting circuit 662 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the number of times the speed-down message DN is asserted in signal ud4 from the number of times the speed-up message UP is asserted in signal ud4.

[0144] In the phase detection circuit 624 shown in Figure 6a, the operation of the internal circuit 2243 shown in Figure 2a and the operation of the internal circuit 6243 may be the same as shown in Figure 2e. In one embodiment, the internal circuit 6243 may determine the states of counts cnt1 and cnt2 according to the values ​​of counts cnt1 and cnt2, respectively, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the states of the two counts. When count cnt1 is greater than the upper limit c_U (Figure 2e), the internal circuit 6243 may set the state of count cnt1 to equal the state cnt_UP; when count cnt1 is less than the lower limit c_D, the internal circuit 6243 may set the state of count cnt1 to equal the state cnt_DN; when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 6243 may set the state of count cnt1 to equal the state cnt_normal. Similarly, when the count cnt2 is greater than the upper limit c_U, the internal circuit 6243 may set the state of the count cnt2 to equal the state cnt_UP; when the count cnt2 is less than the lower limit c_D, the internal circuit 6243 may set the state of the count cnt2 to equal the state cnt_DN; and when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 6243 may set the state of the count cnt2 to equal the state cnt_normal.

[0145] When the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively, the internal circuit 6243 of the phase detection circuit 624 may increase the offset value d_phi of the phase shift circuit 250 via signal scr2, reset counts cnt1 and cnt2 to their initial value c_0, and thereby return the states of counts cnt1 and cnt2 to state cnt_normal; when the states of counts cnt1 and cnt2 are equal to states cnt_DN and cnt_UP, respectively, the internal circuit 6243 may decrease the offset value d_phi, reset counts cnt1 and cnt2 to their initial value c_0, and thereby return the states of counts cnt1 and cnt2 to state cnt_normal; in situations other than the two above, the internal circuit 6243 may leave the offset value d_phi unchanged and not reset counts cnt1 and cnt2.

[0146] Although not shown, any one of the phase detection circuits 324, 424, 524, and 624 (shown in Figures 3a, 4a, 5a, and 6a, respectively) may replace the phase detection circuit 224 shown in Figure 2a to form another embodiment of the present disclosure. That is, the base phase detection circuit 222 shown in Figure 2a may provide all four signals ud1 to ud4, but the accompanying additional phase detection circuits may adjust the offset value d_phi in response to only one of signals ud1 and ud3 and only one of signals ud2 and ud4, as shown in the phase detection circuits 324, 424, 524, and 624 shown in Figures 3a to 6a, respectively.

[0147] Following Figures 1a and 2a, Figure 7a shows a phase detection circuit block 720 according to one embodiment of the present disclosure; the phase detection circuit block 720 may, in conjunction with the sampler block 210 and clock circuit block 230 shown in Figure 2a (also shown in Figure 7a), implement the phase detection circuit block 120, sampler block 110, and clock circuit block 130 shown in Figure 1a, respectively. The phase detection circuit block 720 may comprise a phase detection circuit 222 (already described when referring to Figure 2a) and another phase detection circuit 724. The phase detection circuit 724 may be an additional phase detection circuit that provides signal scr2 at node n4 in response to signals sd1, x1, and x3, and may comprise two internal circuits 7241 and 7243 and a counting circuit 761. The internal circuit 7241 may comprise two input and output terminals coupled to nodes b1, b3 and the counting circuit 761, respectively. The internal circuit 7243 may be connected to the counting circuit 761 and node n4.

[0148] Following Figure 7a, Figure 7b lists embodiments of the operation of the counting circuit 761. As shown by rows r701a and r702a in Figure 7b, whenever the speed-up message UP is asserted in signal ud1 or ud3, the internal circuit 7241 may cause the counting circuit 761 to increment the count cnt1 by step value d1; as shown by rows r701b and r702b in Figure 7b, whenever the speed-down message DN is asserted in signal ud1 or ud3, the internal circuit 7241 may cause the counting circuit 761 to decrement the count cnt1 by step value d1. Furthermore, as shown by row r703, when the speed-up message UP and the speed-down message DN are not asserted in signals ud1 and ud3, the counting circuit 761 may leave the count cnt1 unchanged. Therefore, the count cnt1 may reflect the total number of times the speed-up message UP is asserted in signals ud1 and ud3, minus the total number of times the speed-down message DN is asserted in signals ud1 and ud3.

[0149] In the phase detection circuit 724, the internal circuit 7243 may determine the state of count cnt1 according to the value of count cnt1, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the state of count cnt1. Following Figures 7a and 7b, Figure 7c lists embodiments of the operation of the internal circuit 7243. As shown in Figure 7c, when count cnt1 is greater than the upper limit c_U, the internal circuit 7243 may set the state of count cnt1 to equal state cnt_UP; when count cnt1 is less than the lower limit c_D, the internal circuit 7243 may set the state of count cnt1 to equal state cnt_DN; and when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 7243 may set the state of count cnt1 to equal state cnt_normal. As shown by line r711a, when the state of count cnt1 is equal to state cnt_UP, the internal circuit 7243 in the phase detection circuit 724 may increase the offset value d_phi of the phase shift circuit 250 via signal scr2, resetting count cnt1 to its initial value c_0, and thereby returning the state of count cnt1 to state cnt_normal; as shown by line r711c, when the state of count cnt1 is equal to state cnt_DN, the internal circuit 7243 may decrease the offset value d_phi, resetting count cnt1 to its initial value c_0, and thereby returning the state of count cnt1 to state cnt_normal; as shown by line r711b, when the state of count cnt1 is equal to state cnt_normal, the internal circuit 7243 may leave the offset value d_phi unchanged and not reset count cnt1.

[0150] Following Figures 1a and 2a, Figure 8a shows a phase detection circuit block 820 according to one embodiment of the present disclosure; the phase detection circuit block 820 may, in conjunction with the sampler block 210 and clock circuit block 230 (also shown in Figure 8a) shown in Figure 2a, implement the phase detection circuit block 120, sampler block 110, and clock circuit block 130 shown in Figure 1a, respectively. The phase detection circuit block 820 may comprise a phase detection circuit 222 (already described when referring to Figure 2a) and another phase detection circuit 824. The phase detection circuit 824 may be an additional phase detection circuit that provides the signal scr2 at node n4 in response to signals sd1 and x2, and may comprise two internal circuits 8242 and 8243 and a counting circuit 862. The internal circuit 8242 may comprise two input and output terminals coupled to nodes b2, b4, and the counting circuit 862, respectively. The internal circuit 8243 may be connected to the counting circuit 862 and node n4.

[0151] Following Figure 8a, Figure 8b lists embodiments of the operation of the counting circuit 862. As shown by rows r801a and r802a in Figure 8b, whenever the speed-up message UP is asserted in signal ud2 or ud4, the internal circuit 8242 may cause the counting circuit 862 to increment the count cnt2 by step value d1; as shown by rows r801b and r802b in Figure 8b, whenever the speed-down message DN is asserted in signal ud2 or ud4, the internal circuit 8242 may cause the counting circuit 862 to decrement the count cnt2 by step value d1. Furthermore, as shown by row r803, when the speed-up message UP and the speed-down message DN are not asserted in signals ud2 and ud4, the counting circuit 862 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the total number of times the speed-up message DN was asserted in signals ud2 and ud4 from the total number of times the speed-up message UP was asserted in signals ud2 and ud4.

[0152] In the phase detection circuit 824, the internal circuit 8243 may determine the state of count cnt2 according to the value of count cnt2, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the state of count cnt2. Following Figures 8a and 8b, Figure 8c lists embodiments of the operation of the internal circuit 8243. As shown in Figure 8c, when the count cnt2 is greater than the upper limit c_U, the internal circuit 8243 may set the state of count cnt2 to equal state cnt_UP; when the count cnt2 is less than the lower limit c_D, the internal circuit 8243 may set the state of count cnt2 to equal state cnt_DN; and when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 8243 may set the state of count cnt2 to equal state cnt_normal. As shown by line r811a, when the state of count cnt2 is equal to state cnt_UP, the internal circuit 8243 in the phase detection circuit 824 may decrease the offset value d_phi of the phase shift circuit 250 via signal scr2, reset count cnt2 to its initial value c_0, and thereby return the state of count cnt2 to state cnt_normal; as shown by line r811c, when the state of count cnt2 is equal to state cnt_DN, the internal circuit 8243 may increase the offset value d_phi, reset count cnt2 to its initial value c_0, and thereby return the state of count cnt2 to state cnt_normal; as shown by line r811b, when the state of count cnt2 is equal to state cnt_normal, the internal circuit 8243 may leave the offset value d_phi unchanged and not reset count cnt2.

[0153] Following Figures 1a, 2a, and 3a, Figure 9a shows a phase detection circuit block 920 according to one embodiment of the present disclosure; the phase detection circuit block 920 may, in conjunction with the sampler block 310 shown in Figure 3a and the clock circuit block 230 shown in Figure 2a (also shown in Figure 9a), implement the phase detection circuit block 120, sampler block 110, and clock circuit block 130 shown in Figure 1a, respectively. The phase detection circuit block 920 may comprise a phase detection circuit 322 (already described when referring to Figure 3a) and another phase detection circuit 924. The phase detection circuit 924 may be an additional phase detection circuit that provides a signal scr2 at node n4 in response to signals sd1 and x1, and may comprise two internal circuits 9241 and 9243 and a counting circuit 961. The internal circuit 9241 may comprise input and output terminals coupled to node b1 and the counting circuit 961, respectively. The internal circuit 9243 may be connected to the counting circuit 961 and node n4.

[0154] Following Figure 9a, Figure 9b lists embodiments of the operation of the counting circuit 961. As shown by line r901a in Figure 9b, whenever the speed-up message UP is asserted in signal ud1, the internal circuit 9241 may cause the counting circuit 961 to increment the count cnt1 by step value d1; as shown by line r901b in Figure 9b, whenever the speed-down message DN is asserted in signal ud1, the internal circuit 9241 may cause the counting circuit 961 to decrement the count cnt1 by step value d1. Furthermore, as shown by line r902, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud1, the counting circuit 961 may leave the count cnt1 unchanged.

[0155] In the phase detection circuit 924, the internal circuit 9243 may determine the state of count cnt1 according to the value of count cnt1, and may dynamically adjust the offset value d_phi of the phase shift circuit 250 according to the state of count cnt1. In one embodiment, the operation of the internal circuit 9243 shown in Figure 9a and the operation of the internal circuit 7243 shown in Figure 7a may be the same as shown in Figure 7c. When count cnt1 is greater than the upper limit c_U, the internal circuit 9243 may set the state of count cnt1 to equal state cnt_UP; when count cnt1 is less than the lower limit c_D, the internal circuit 9243 may set the state of count cnt1 to equal state cnt_DN; when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 9243 may set the state of count cnt1 to equal state cnt_normal. When the state of count cnt1 is equal to state cnt_UP, the internal circuit 9243 in the phase detection circuit 924 may increase the offset value d_phi of the phase shift circuit 250 via signal scr2, reset count cnt1 to its initial value c_0, and thereby return the state of count cnt1 to state cnt_normal; when the state of count cnt1 is equal to state cnt_DN, the internal circuit 9243 may decrease the offset value d_phi, reset count cnt1 to its initial value c_0, and thereby return the state of count cnt1 to state cnt_normal; when the state of count cnt1 is equal to state cnt_normal, the internal circuit 9243 may leave the offset value d_phi unchanged and not reset count cnt1.

[0156] Following Figures 1a, 2a, and 3a, Figure 10a shows a phase detection circuit block 1020 according to one embodiment of the present disclosure; the phase detection circuit block 1020 may work in conjunction with the sampler block 310 shown in Figure 3a and the clock circuit block 230 shown in Figure 2a (also shown in Figure 10a) to implement the phase detection circuit block 120, sampler block 110, and clock circuit block 130 shown in Figure 1a, respectively. The phase detection circuit block 1020 may comprise a phase detection circuit 322 (already described when referring to Figure 3a) and another phase detection circuit 1024. The phase detection circuit 1024 may be an additional phase detection circuit that provides a signal scr2 at node n4 in response to signals sd1 and x2, and may comprise two internal circuits 10242 and 10243 and a counting circuit 1062. Internal circuit 10242 may have input and output terminals connected to node b2 and counting circuit 1062, respectively. Internal circuit 10243 may be connected to counting circuit 1062 and node n4.

[0157] Following Figure 10a, Figure 10b lists embodiments of the operation of the counting circuit 1062. As shown by line r1001a in Figure 10b, whenever the speed-up message UP is asserted in signal ud2, the internal circuit 10242 may cause the counting circuit 1062 to increment the count cnt2 by step value d1; as shown by line r1001b in Figure 10b, whenever the speed-down message DN is asserted in signal ud2, the internal circuit 10242 may cause the counting circuit 1062 to decrement the count cnt2 by step value d1. Furthermore, as shown by line r1002, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud2, the counting circuit 1062 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud2 from the number of times the speed-up message UP was asserted in signal ud2.

[0158] In the phase detection circuit 1024, the internal circuit 10243 may determine the state of count cnt2 according to the value of count cnt2, and may dynamically tune the offset value d_phi of the phase shift circuit 250 according to the state of count cnt2. In one embodiment, the operation of the internal circuit 10243 shown in Figure 10a and the operation of the internal circuit 8243 shown in Figure 8a may be the same, as shown in Figure 8c. When the count cnt2 is greater than the upper limit c_U, the internal circuit 10243 may set the state of count cnt2 to equal the state cnt_UP; when the count cnt2 is less than the lower limit c_D, the internal circuit 10243 may set the state of count cnt2 to equal the state cnt_DN; when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 10243 may set the state of count cnt2 to equal the state cnt_normal. When the state of count cnt2 is equal to state cnt_UP, the internal circuit 10243 in the phase detection circuit 1024 may decrease the offset value d_phi of the phase shift circuit 250 via signal scr2, reset count cnt2 to its initial value c_0, and thereby return the state of count cnt2 to state cnt_normal; when the state of count cnt2 is equal to state cnt_DN, the internal circuit 10243 may increase the offset value d_phi, reset count cnt2 to its initial value c_0, and thereby return the state of count cnt2 to state cnt_normal; when the state of count cnt2 is equal to state cnt_normal, the internal circuit 10243 may leave the offset value d_phi unchanged and not reset count cnt2.

[0159] Following Figures 1a, 2a, 5a, and 6a, Figure 11a shows a phase detection circuit block 1120 according to one embodiment of the present disclosure; the phase detection circuit block 1120 may work in conjunction with the sampler block 510 shown in Figure 5a and the clock circuit block 230 shown in Figure 2a (also shown in Figure 11a) to implement the phase detection circuit block 120, sampler block 110, and clock circuit block 130 shown in Figure 1a, respectively. The phase detection circuit block 1120 may comprise a phase detection circuit 622 (already described when referring to Figure 6a) and another phase detection circuit 1124. The phase detection circuit 1124 may be an additional phase detection circuit that may provide a signal scr2 at node n4 in response to signals sd1 and x3, and may include two internal circuits 11241 and 11243 and a counting circuit 1161. Internal circuit 11241 may have input and output terminals connected to node b3 and counting circuit 1161, respectively. Internal circuit 11243 may be connected to counting circuit 1161 and node n4.

[0160] Following Figure 11a, Figure 11b lists embodiments of the operation of the counting circuit 1161. As shown by line r1101a in Figure 11b, whenever the speed-up message UP is asserted in signal ud3, the internal circuit 11241 may cause the counting circuit 1161 to increment the count cnt1 by step value d1; as shown by line r1101b in Figure 11b, whenever the speed-down message DN is asserted in signal ud3, the internal circuit 11241 may cause the counting circuit 1161 to decrement the count cnt1 by step value d1. Furthermore, as shown by line r1102, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud3, the counting circuit 1161 may leave the count cnt1 unchanged. Therefore, the count cnt1 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud3 from the number of times the speed-up message UP was asserted in signal ud3.

[0161] In the phase detection circuit 1124, the internal circuit 11243 may determine the state of count cnt1 according to the value of count cnt1, and may dynamically tune the offset value d_phi of the phase shift circuit 250 according to the state of count cnt1. In one embodiment, the operation of the internal circuit 11243 shown in Figure 11a, the operation of the internal circuit 7243 shown in Figure 7a, and the operation of the internal circuit 9243 shown in Figure 9a may be the same, as shown in Figure 7c. When count cnt1 exceeds the upper limit c_U, the internal circuit 11243 may set the state of count cnt1 to equal state cnt_UP; when count cnt1 falls below the lower limit c_D, the internal circuit 11243 may set the state of count cnt1 to equal state cnt_DN; and when count cnt1 is between the upper limit c_U and the lower limit c_D, the internal circuit 11243 may set the state of count cnt1 to equal state cnt_normal. When the state of count cnt1 is state cnt_UP, the internal circuit 11243 in the phase detection circuit 1124 may increase the offset value d_phi of the phase shift circuit 250 via the signal scr2 and reset count cnt1 to its initial value c_0 so that the state of count cnt1 may return to state cnt_normal; when the state of count cnt1 is state cnt_DN, the internal circuit 11243 may decrease the offset value d_phi and reset count cnt1 to its initial value c_0 so that the state of count cnt1 may return to state cnt_normal; when the state of count cnt1 is state cnt_normal, the internal circuit 11243 may leave the offset value d_phi unchanged and not reset count cnt1.

[0162] Following Figures 1a, 2a, 5a, and 6a, Figure 12a shows a phase detection circuit block 1220 according to one embodiment of the present disclosure; the phase detection circuit block 1220 may work in conjunction with the sampler block 510 shown in Figure 5a and the clock circuit block 230 shown in Figure 2a (also shown in Figure 12a) to implement the phase detection circuit block 120, sampler block 110, and clock circuit block 130 shown in Figure 1a, respectively. The phase detection circuit block 1220 may comprise a phase detection circuit 622 (already described when referring to Figure 6a) and another phase detection circuit 1224. The phase detection circuit 1224 may be an additional phase detection circuit that provides a signal scr2 at node n4 in response to signals sd1 and x2, and may include two internal circuits 12242 and 12243 and a counting circuit 1262. Internal circuit 12242 may have input and output terminals connected to node b4 and counting circuit 1262, respectively. Internal circuit 12243 may be connected to counting circuit 1262 and node n4.

[0163] Following Figure 12a, Figure 12b lists embodiments of the operation of the counting circuit 1262. As shown by line r1201a in Figure 12b, whenever the speed-up message UP is asserted in signal ud4, the internal circuit 12242 may cause the counting circuit 1262 to increment the count cnt2 by step value d1; as shown by line r1201b in Figure 12b, whenever the speed-down message DN is asserted in signal ud4, the internal circuit 12242 may cause the counting circuit 1262 to decrement the count cnt2 by step value d1. Furthermore, as shown by line r1202, when neither the speed-up message UP nor the speed-down message DN is asserted in signal ud4, the counting circuit 1262 may leave the count cnt2 unchanged. Therefore, the count cnt2 may reflect the value obtained by subtracting the number of times the speed-down message DN was asserted in signal ud4 from the number of times the speed-up message UP was asserted in signal ud4.

[0164] In the phase detection circuit 1224, the internal circuit 12243 may determine the state of count cnt2 according to the value of count cnt2, and may dynamically tune the offset value d_phi of the phase shift circuit 250 according to the state of count cnt2. In one embodiment, the operation of the internal circuit 12243 shown in Figure 12a, the operation of the internal circuit 10243 shown in Figure 10a, and the operation of the internal circuit 8243 shown in Figure 8a may be the same as shown in Figure 8c. When the count cnt2 exceeds the upper limit c_U, the internal circuit 12243 may set the state of count cnt2 to equal state cnt_UP; when the count cnt2 falls below the lower limit c_D, the internal circuit 12243 may set the state of count cnt2 to equal state cnt_DN; and when the count cnt2 is between the upper limit c_U and the lower limit c_D, the internal circuit 12243 may set the state of count cnt2 to equal state cnt_normal. When the state of count cnt2 is state cnt_UP, the internal circuit 12243 in the phase detection circuit 1224 may decrease the offset value d_phi of the phase shift circuit 250 via the signal scr2 and reset count cnt2 to its initial value c_0 so that the state of count cnt2 may return to state cnt_normal; when the state of count cnt2 is state cnt_DN, the internal circuit 12243 may increase the offset value d_phi and reset count cnt2 to its initial value c_0 so that the state of count cnt2 may return to state cnt_normal; when the state of count cnt2 is state cnt_normal, the internal circuit 12243 may leave the offset value d_phi unchanged and not reset count cnt2.

[0165] Although not shown, the phase detection circuit 924 shown in Figure 9a may replace the phase detection circuit 224 shown in Figure 2a or the phase detection circuit 424 shown in Figure 4a to form another embodiment of the present disclosure. Although not shown, the phase detection circuit 1024 shown in Figure 10a may replace the phase detection circuit 224 shown in Figure 2a or the phase detection circuit 524 shown in Figure 5a to form another embodiment of the present disclosure. Although not shown, the phase detection circuit 1124 shown in Figure 11a may replace the phase detection circuit 224 shown in Figure 2a or the phase detection circuit 524 shown in Figure 5a to form another embodiment of the present disclosure. Although not shown, the phase detection circuit 1224 shown in Figure 12a may replace the phase detection circuit 224 shown in Figure 2a or the phase detection circuit 424 shown in Figure 4a to form another embodiment of the present disclosure. In other words, each of the base phase detection circuits 222, 322, 422, 522, and 622 shown in Figures 2a to 6a may provide at least one of signals ud1 and ud3 as a first set of phase detection results, and at least one of signals ud2 and ud4 as a second set of phase detection results, but an additional accompanying phase detection circuit may adjust the offset value d_phi according to only one subset of the first set and the second set of phase detection results.For example, the base phase detection circuit 222 shown in Figure 2a may provide signals ud1 and ud3 as a first set of phase detection results, and signals ud1 and ud4 as a second set of phase detection results; however, an accompanying additional phase detection circuit may adjust the offset value d_phi according to signals ud1 and ud3 only, as in the additional phase detection circuit 724 shown in Figure 7a, or an accompanying additional phase detection circuit may adjust the offset value d_phi according to only one of signals ud1 and ud3, as in the additional phase detection circuit 924 or 1124 shown in Figure 9a or Figure 11a; similarly, an accompanying additional phase detection circuit may adjust the offset value d_phi according to signals ud2 and ud4 only, as in the additional phase detection circuit 824 shown in Figure 8a; or an accompanying additional phase detection circuit may adjust the offset value d_phi according to only one of signals ud2 and ud4, as in the additional phase detection circuit 1024 or 1224 shown in Figure 10a or Figure 12a.

[0166] Following Figure 2a, Figures 13a, 13b, and 13c illustrate various embodiments of the clock circuit block 230. As shown in Figure 13a, in one embodiment of the present disclosure, the clock circuit 240 may comprise a filter 1301 and an oscillator 1302. The filter 1301 may be coupled between node n3 and oscillator 1302 and may filter signal scr1 to generate signal sf1. Oscillator 1302 may be a controlled oscillator such as a voltage-controlled oscillator or a digitally controlled oscillator; under the control of signal sf1, oscillator 1302 may generate clocks cke1 and ck0 of the same frequency but different phases. Oscillator 1302 may allow the timing (frequency and / or phase) of clocks cke1 and ck0 to be controlled by signal scr1, and the relative phase difference between clocks ck0 and cke1 may be substantially equal to a predetermined offset value d_p0. In the embodiment shown in Figure 13a, the phase shift circuit 250 may be a controllable delay line and may further include a clock input terminal coupled to clock cke1 at node n6. The phase shift circuit 250 shown in Figure 13a may shift (delay) the phase of clock cke1 by an offset value d_phi such that the phase difference between clock cke2 and cke1 is substantially equal to the offset value d_phi, thereby forming clock cke2, where the offset value d_phi may be controlled by the signal scr2.

[0167] In the embodiment shown in Figure 13b, the clock circuit 240 may include a filter 1303 and an oscillator 1304. The filter 1303 may be coupled between node n3 and oscillator 1304 and may filter signal scr1 to generate signal sf2. The oscillator 1304 may be a controlled oscillator and may generate a plurality of clocks ck_0 to ck_Q of the same frequency and constant mutual phase difference under the control of signal sf2. The oscillator 1304 may control the timing (frequency and / or phase) of clocks ck_0 to ck_Q by signal sf2 (and therefore signal scr1) and may make the mutual phase difference between any two of the clocks ck_0 to ck_Q equal to a predetermined phase difference (e.g., a constant phase angle). The clocks cke1 and ck0 provided by the clock circuit 240 may be any two of the clocks ck_0 to ck_Q, and the mutual phase difference between the two clocks may be equal to a predetermined offset value d_p0. In the embodiment shown in Figure 13b, the phase shift circuit 250 may be a controlled variable phase interpolator and may further include two clock input terminals coupled to two clocks ck_q1 and ck_q2 at two nodes n8a and n8b, respectively; clocks ck_q1 and ck_q2 may be any two of clocks ck_0 to ck_Q. The phase shift circuit 250 may perform phase interpolation between clocks ck_q1 and ck_q2 to form clock cke2, and may make the phase difference between clocks cke2 and cke1 equal to an offset value d_phi; the phase interpolation performed by the phase shift circuit 250 may be controlled by a signal scr2, and therefore the offset value d_phi may be controlled by the signal scr2. For example, in one embodiment, the clocks ck_0 to ck_Q provided by the oscillator 1304 may be four clocks ck_0, ck_90, ck_180, and ck_270 with a mutual phase difference equal to 90 degrees; clocks ck0 and cke1 may be clocks ck_0 and ck_180, and the phase shift circuit 250 may perform phase interpolation between clocks ck_180 and ck_270 to form clock cke2.

[0168] In the embodiment shown in Figure 13c, the clock circuit 240 and the phase shift circuit 250 may be two controllable phase interpolators. The clock circuit 240 may further include two clock input terminals coupled to two clocks ck_q3 and ck_q4 at two nodes n9a and n9b, respectively. The phase shift circuit 250 may further include two clock input terminals coupled to two clocks ck_q1 and ck_q2 at two nodes n8a and n8b, respectively. The clocks ck_q1, ck_q2, ck_q3, and ck_q4 may be four clocks of the same frequency and a constant mutual phase difference. Under the control of signal scr1, the clock circuit 240 may perform phase interpolation between clocks ck_q3 and ck_q4 to generate clocks ck0 and cke1, and the mutual phase difference between clocks ck0 and cke1 may be substantially equal to the offset value d_p0. Under the control of signal scr2, the phase shift circuit 250 may perform phase interpolation between clocks ck_q1 and ck_q2 to generate clock cke2, and may make the mutual phase difference between clocks cke2 and cke1 equal to the offset value d_phi. Since the phase interpolation performed by the phase shift circuit 250 is controlled by signal scr2, the offset value d_phi may therefore be controlled by signal scr2.

[0169] This disclosure may be implemented within a decision feedback equalizer; following Figures 1a and 2a, Figure 14 shows a circuit block 1400 according to one embodiment of this disclosure; the circuit block 1400 may implement the front-end circuit block 102 and sampler block 110 shown in Figure 1a by the architecture of the decision feedback equalizer. Similar to the sampler block 210 shown in Figure 2a, the circuit block 1400 shown in Figure 14 may comprise samplers sa0 to sa3 (already described when referring to Figure 2a), and may also comprise a front-end circuit 1401, an adder 1402, and a feedback circuit 1403. The front-end circuit 1401 may be coupled between a received signal s2 (Figure 1a) and node n0, and may comprise a linear equalizer and / or a variable gain amplifier (not shown), which may perform signal processing on the received signal s2 to provide a signal sr0 at node n0 accordingly. The adder 1402 may be coupled between nodes n0, n1 and the feedback circuit 1403, and may sum signal sr0 and a certain number of M signals s_1 to s_M, and provide signal sr1 at node n1 accordingly, where M may be an integer greater than or equal to 1. The feedback circuit 1403 may be coupled between node n2 and the adder 1402, and may provide signals s_1 to s_M as feedback signals at node n2 according to signal sd1 and one or more predetermined coefficients h_1 to h_M. For example, in one embodiment, the feedback circuit 1403 may form a signal s_1 by multiplying a coefficient h_1 by the result of delaying signal sd1 by one unit duration, form a signal s_2 by multiplying a coefficient h_2 by the result of delaying signal sd1 by two of the above unit durations, form a signal s_M by multiplying a coefficient h_M by the result of delaying signal sd1 by several M of the above unit durations; the unit duration may be equal to the period of the clock ck0. In one embodiment, the coefficient h_1 may be a positive value, the threshold level L1 may be equal to the coefficient h_1, and the threshold level L3 may be equal to a negative value of the coefficient h_1 (i.e., -h_1).

[0170] Although not shown, the circuit block 1400 shown in Figure 14 may work in conjunction with the phase detection circuit block 220 and the clock circuit block 230 shown in Figure 2a to implement the wireline receiver 100 shown in Figure 1a. In addition to the clock circuit block 230, the circuit block 1400 shown in Figure 14 may work in conjunction with the phase detection circuit blocks 320, 420, 520, 620, 720, 820, 920, 1020, 1120, or 1220 shown in Figures 3a, 4a, 5a, 6a, 7a, 8a, 9a, 10a, 11a, or 12a, respectively, to implement the wireline receiver 100 shown in Figure 1a.

[0171] Similar to Figures 3a, 4a, 9a, or 10a, the circuit block 1400 shown in Figure 14 may omit the sampler sa3 and, in conjunction with the phase detection circuit blocks 320, 420, 920, or 1020 shown in Figures 3a, 4a, 9a, or 10a respectively, implement the wireline receiver 100 shown in Figure 1a in addition to the clock circuit block 230. In addition, similar to Figures 5a, 6a, 11a, or 12a, the circuit block 1400 may omit the sampler sa1 and, in conjunction with the phase detection circuit blocks 520, 620, 1120, or 1220 shown in Figures 5a, 6a, 11a, or 12a respectively, implement the wireline receiver 100 shown in Figure 1a in addition to the clock circuit block 230.

[0172] Following Figures 1a, 2a, and 14, Figure 15a shows a circuit block 1500 according to one embodiment of the present disclosure, Figure 15b shows a phase detection circuit block 1520 according to one embodiment of the present disclosure, Figure 15c shows a clock circuit block 1530 according to one embodiment of the present disclosure, and Figure 15d shows embodiments of the timing and waveforms of the associated signals and clock shown in Figure 15a. The circuit block 1500 shown in Figure 15a may implement the front-end circuit block 102 and sampler block 110 shown in Figure 1a by a half-rate loop-unrolled decision feedback equalizer architecture; in conjunction with circuit block 1500, the phase detection circuit block 1520 shown in Figure 15b and the clock circuit block 1530 shown in Figure 15c may implement the phase detection circuit block 120 and clock circuit block 130 shown in Figure 1a, respectively.

[0173] As shown in Figure 15a, the circuit block 1500 may comprise a front-end circuit 1501, two adders 1502e and 1502o, a feedback circuit 1503, two multiplexers 1504e and 1504o, and a plurality of samplers sa01 to sa04, sa1e to sa3e, and sa1o to sa3o. The front-end circuit 1501 may be coupled between the received signal s2 and node n0 and may comprise a linear equalizer and / or a variable gain amplifier (not shown) which may perform signal processing on the signal s2 to form the signal sr0 at node n0 accordingly. An adder 1502e may be coupled between node n0, another node n1e, and a feedback circuit 1503, and may sum signal sr0 and one or more signals se_2~se_M, thereby forming signal sr1e at node n1e, where the number M may be an integer greater than or equal to 2. Sampler sa01 may include a signal input terminal, a clock input terminal, a threshold level input terminal, and an output terminal coupled to node n1e, clock ck0e, a positive coefficient +h_1, and node n11, respectively. Sampler sa02 may include a signal input terminal, a clock input terminal, a threshold level input terminal, and an output terminal coupled to node n1e, clock ck0e, a negative coefficient -h_1 (sign inverted of the positive coefficient h_1), and node n12, respectively. Sampler sa1e may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals connected to node n1e, clock cke1e, threshold level L1, and node a1e, respectively. Sampler sa2e may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals connected to node n1e, clock cke2e, threshold level L2, and node a2e, respectively. Sampler sa3e may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals connected to node n1e, clock cke1e, threshold level L3, and node a3e, respectively. Multiplexer 1504e has two signal input terminals, a control input terminal, and an output terminal, and may be connected to nodes n11, n12, and two other nodes, nodes n2o and n2e, respectively.

[0174] In circuit block 1500, adder 1502o may be coupled between node n0, another node n1o, and feedback circuit 1503, and may sum signal sr0 and one or more signals so_2 to so_M, thereby forming signal sr1o at node n1o. Sampler sa03 may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals coupled to node n1o, clock ck0o, positive coefficient +h_1, and node n13, respectively. Sampler sa04 may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals coupled to node n1o, clock ck0o, negative coefficient -h_1, and node n14, respectively. Sampler sa1o may have signal input terminals, clock input terminals, threshold level input terminals, and output terminals coupled to node n1o, clock cke1o, threshold level L1, and node a1o, respectively. Sampler sa2o may have signal input terminals, a clock input terminal, a threshold level input terminal, and an output terminal connected to node n1o, clock cke2o, threshold level L2, and node a2o, respectively. Sampler sa3o may have signal input terminals, a clock input terminal, a threshold level input terminal, and an output terminal connected to node n1o, clock cke1o, threshold level L3, and node a3o, respectively. Multiplexer 1504o may have two signal input terminals, a control input terminal, and an output terminal, and may be connected to nodes n13, n14, n2e, and n2o, respectively.

[0175] In circuit block 1500, when triggered by clock ck0e, sampler sa01 may sample and compare signal sr1e to determine if signal sr1e exceeds a positive coefficient +h_1, and accordingly provide signal sd11 at node n11. When triggered by clock ck0e, sampler sa02 may sample and compare signal sr1e to determine if signal sr1e exceeds a negative coefficient -h_1, and accordingly provide signal sd12 at node n12. When triggered by clock ck0o, sampler sa03 may sample and compare signal sr1o to determine if signal sr1o exceeds a positive coefficient +h_1, and accordingly provide signal sd13 at node n13. When triggered by the clock ck0o, sampler sa04 may sample and compare signal sr1o to determine whether signal sr1o exceeds a negative coefficient -h_1, and accordingly provide signal sd14 at node n14.

[0176] In circuit block 1500, multiplexers 1504e and 1504o may provide two signals, sd1e and sd1o, at nodes n2e and n2o, respectively. When the signal value at node n2o is equal to the defined value H, multiplexer 1504e may conduct (electrically connect) node n11 to node n2e (instead of node n12); when the signal value at node n2o is equal to the defined value L, multiplexer 1504e may conduct node n12 to node n2e (instead of node n11). When the signal value at node n2e is equal to the defined value H, the multiplexer 1504o may conduct (electrically connect) node n13 to node n2o (instead of node n14); when the signal value at node n2e is equal to the defined value L, the multiplexer 1504o may conduct (instead of node n13) node n14 to node n2o.

[0177] In circuit block 1500, adder 1502e, samplers sa01, sa02, sa1e~sa3e, and multiplexer 1504e may constitute circuit branch 1510e, which may distinguish even symbols of signal sr0 (e.g., symbols sr0[2i-2] and sr0[2i] shown in Figure 15d) and provide signal sd1e accordingly; the signal values ​​of signal sd1e (e.g., consecutive signal values ​​sd1[2i-2] and sd1[2i] shown in Figure 15d) may therefore represent even symbols distinguished from signal sr0 by circuit block 1500. On the other hand, in circuit block 1500, the adder 1502o, samplers sa03, sa04, sa1o~sa3o, and multiplexer 1504o may constitute another circuit branch 1510o which may distinguish odd symbols of signal sr0 (e.g., symbols sr0[2i-1] and sr0[2i+1] shown in Figure 15d) and provide signal sd1o accordingly; the signal values ​​of signal sd1o (e.g., consecutive signal values ​​sd1[2i-1] and sd1[2i+1] shown in Figure 15d) may therefore represent odd symbols distinguished from signal sr0 by circuit block 1500. A complete data signal sd1 may be formed by integrating the signal values ​​corresponding to even symbols from signal sd1e and the signal values ​​corresponding to odd symbols from signal sd1o, and the signal values ​​of the data signal sd1 (e.g., signal values ​​sd1[2i-2], sd1[2i-1], sd1[2i], sd1[2i+1]) may represent complete symbols distinguished from signal sr0 by circuit block 1500.

[0178] As shown in Figure 15c, the clock circuit block 1530 may include a clock circuit 1540 and a phase shift circuit 1550. The clock circuit 1540 may provide clocks cke1e, cke1o, ck0e and ck0o in response to a signal scr1; when providing clocks cke1e, cke1o, ck0e and ck0o, the clock circuit 1540 may ensure that the frequencies of the clocks cke1e, cke1o, ck0e and ck0o are equal and controlled by the signal scr1, the phase difference between clocks cke0e and cke1e may be equal to a predetermined offset value d_p0, the phase difference between clocks cke0o and cke1o may be equal to an offset value d_p0, and the phase difference between clocks cke1e and cke1o may be equal to an offset value d_p0. In one embodiment, the offset value d_p0 may be 180 degrees; that is, clocks cke1e and cke0e may be inverted relative to each other, clocks cke1o and cke0o may be inverted relative to each other, and clocks cke1e and cke1o may be inverted relative to each other. The phase shift circuit 1550 may provide clocks cke2e and cke2o by performing a phase shift in accordance with the signal scr2; when providing clocks cke2e and cke2o, the phase shift circuit 1550 may make the frequencies of clocks cke1e and cke2e equal to each other, and make the phase difference between clocks cke2e and cke1e equal to the offset value d_phi; also, the phase shift circuit 1550 may make the frequencies of clocks cke1o and cke2o equal to each other, and make the phase difference between clocks cke2o and cke1o equal to the offset value d_phi, where the offset value d_phi may be controlled by the signal scr2.

[0179] As shown in Figure 15d, each of the clocks ck0e, cke1e, cke2e, ck0o, cke1o, and cke2o may be a periodic clock that alternates between two levels, vc1 and vc0, and the period of these clocks may be equal to the period T22. The effective edges of clocks cke1e and cke2e (edges that change from level vc0 to vc1) may track (reflect) the symbol edges of signal sr1e, and the effective edges of clock ck0e may track (reflect) the time axis center of the symbol of signal sr1e. Furthermore, the effective edges of clocks cke1o and cke2o may track (reflect) the symbol edges of signal sr1o, and the effective edges of clock ck0o may track (reflect) the time axis center of the symbol of signal sr1o.

[0180] In the circuit block 1500 shown in Figure 15a, the feedback circuit 1503 may provide signals se_2 to se_M and signals so_2 to so_M depending on signals sd1e and sd1o and one or more coefficients h_2 to h_M; for example, the feedback circuit 1503 may form signal se_2 by multiplying coefficient h_2 and signal sd1e by the result of delaying by two unit intervals, form signal so_2 by multiplying coefficient h_2 and signal sd1o by the result of delaying by two of the above unit intervals, form signal se_3 by multiplying coefficient h_3 and signal sd1o by the result of delaying by four of the above unit intervals, form signal so_3 by multiplying coefficient h_3 and signal sd1e by the result of delaying by four of the above unit intervals, and so on. The time span of the two above unit intervals may be equal to the period T22 (Figure 15d).

[0181] As shown in Figure 15b, the phase detection circuit block 1520 may comprise two phase detection circuits 1522 and 1524, which may be a base phase detection circuit and an additional phase detection circuit, respectively. The phase detection circuit 1522 may comprise a plurality of pattern phase detection units pd1e to pd4e and pd1o to pd4o, and an internal circuit 15221. The pattern phase detection unit pd1e may be coupled to nodes n2e, n2o, a1e, and another node b1e, respectively, and comprise two data input terminals, a signal input terminal, and an output terminal. The pattern phase detection unit pd2e may be coupled to nodes n2e, n2o, a2e, and another node b2e, respectively, and comprise two data input terminals, a signal input terminal, and an output terminal. The pattern phase detection unit pd3e may have two data input terminals, a signal input terminal, and an output terminal connected to nodes n2e, n2o, a3e, and another node b3e, respectively. The pattern phase detection unit pd4e may have two data input terminals, a signal input terminal, and an output terminal connected to nodes n2e, n2o, a2e, and another node b4e, respectively. The pattern phase detection unit pd1o may have two data input terminals, a signal input terminal, and an output terminal connected to nodes n2e, n2o, a1o, and another node b1o, respectively. The pattern phase detection unit pd2o may have two data input terminals, a signal input terminal, and an output terminal connected to nodes n2e, n2o, a2o, and another node b2o, respectively. The pattern phase detection unit pd3o may have two data input terminals, a signal input terminal, and an output terminal connected to nodes n2e, n2o, a3o, and another node b3o, respectively. The pattern phase detection unit pd4o may have two data input terminals, a signal input terminal, and an output terminal connected to nodes n2e, n2o, a2o, and another node b4o, respectively. The pattern phase detection units pd1e~pd4e and pd1o~pd4o may provide signals ud1e~ud4e and ud1o~ud4o at nodes b1e~b4e and b1o~b4o, respectively.

[0182] In response to the signal value x1e[i] of signal x1e (Figure 15d), the pattern phase detection unit pd1e may compare the three associated signal values ​​sd1[2i-1], sd1[2i], and sd1[2i+1] of signals sd1e and sd1o to see if they match pattern p1. If the comparison of pattern p1 matches, the signal ud1e may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x1e[i] is equal to the defined value L or H. If the comparison of pattern p1 does not match, the signal ud1e does not need to assert either the speed-up message UP or the speed-down message DN. In response to the signal value x2e[i] of signal x2e (Figure 15d), the pattern phase detection unit pd2e may compare the three associated signal values ​​sd1[2i-1], sd1[2i], and sd1[2i+1] of signals sd1e and sd1o to see if they match pattern p2. If the comparison of pattern p2 matches, the signal ud2e may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x2e[i] is equal to the defined value H or L. If the comparison of pattern p2 does not match, the signal ud2e does not need to assert either the speed-up message UP or the speed-down message DN. In response to the signal value x3e[i] of signal x3e (Figure 15d), the pattern phase detection unit pd3e may compare the three associated signal values ​​sd1[2i-1], sd1[2i], and sd1[2i+1] of signals sd1e and sd1o to see if they match pattern p3. If the comparison of pattern p3 matches, the signal ud3e may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x3e[i] is equal to the defined value H or L. If the comparison of pattern p3 does not match, the signal ud3e does not need to assert either the speed-up message UP or the speed-down message DN.In response to the signal value x2e[i] of signal x2e (Figure 15d), the pattern phase detection unit pd4e may compare the three associated signal values ​​sd1[2i-1], sd1[2i], and sd1[2i+1] of signals sd1e and sd1o to see if they match pattern p4. If the comparison of pattern p4 matches, the signal ud4e may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x2e[i] is equal to the defined value L or H. If the comparison of pattern p4 does not match, neither the speed-up message UP nor the speed-down message DN may be asserted in signal ud4e.

[0183] In response to the signal value x1o[i] of signal x1o (Figure 15d), the pattern phase detection unit pd1o may compare the three associated signal values ​​sd1[2i-2], sd1[2i-1], and sd1[2i] of signals sd1e and sd1o to see if they match pattern p1. If the comparison of pattern p1 matches, the signal ud1o may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x1o[i] is equal to the defined value L or H. If the comparison of pattern p1 does not match, the signal ud1o does not need to assert either the speed-up message UP or the speed-down message DN. In response to the signal value x2o[i] of signal x2o (Figure 15d), the pattern phase detection unit pd2o may compare the three associated signal values ​​sd1[2i-2], sd1[2i-1], and sd1[2i] of signals sd1e and sd1o to see if they match pattern p2. If the comparison of pattern p2 matches, the signal ud2o may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x2o[i] is equal to the defined value H or L. If the comparison of pattern p2 does not match, the signal ud2o does not need to assert either the speed-up message UP or the speed-down message DN. In response to the signal value x3o[i] of signal x3o (Figure 15d), the pattern phase detection unit pd3o may compare the three associated signal values ​​sd1[2i-2], sd1[2i-1], and sd1[2i] of signals sd1e and sd1o to see if they match pattern p3. If the comparison of pattern p3 matches, the signal ud3o may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x3o[i] is equal to the defined value H or L. If the comparison of pattern p3 does not match, the signal ud3o does not need to assert either the speed-up message UP or the speed-down message DN.In response to the signal value x2o[i] of signal x2o (Figure 15d), the pattern phase detection unit pd4o may compare the three associated signal values ​​sd1[2i-2], sd1[2i-1], and sd1[2i] of signals sd1e and sd1o to see if they match pattern p4. If the comparison of pattern p4 matches, the signal ud4o may assert the speed-up message UP or the speed-down message DN depending on whether the signal value x2o[i] is equal to the defined value L or H. If the comparison of pattern p4 does not match, the signal ud4o does not need to assert either the speed-up message UP or the speed-down message DN.

[0184] In the phase detection circuit 1522, the internal circuit 15221 may provide signal scr1 at node n3 in accordance with signals ud1e~ud4e and ud1o~ud4o. When the speed-up message UP is asserted in either one of signals ud1e~ud4e or ud1o~ud4o, the internal circuit 15221 may assert the speed-up message UP in signal scr1 in correspondence; when the speed-down message DN is asserted in either one of signals ud1e~ud4e or ud1o~ud4o, the internal circuit 15221 may assert the speed-down message DN in signal scr1 in correspondence.

[0185] As shown in Figure 15b, the phase detection circuit 1524 may comprise three internal circuits 15241, 15242, and 15243, and two counting circuits 1561 and 1562. When the speed-up message UP is asserted in any one of the signals ud1e, ud3e, ud1o, and ud3o, the internal circuit 15241 may cause the counting circuit 1561 to increment the count cnt1 by step value d1; when the speed-down message DN is asserted in any one of the signals ud1e, ud3e, ud1o, and ud3o, the internal circuit 15241 may cause the counting circuit 1561 to decrement the count cnt1 by step value d1. When the speed-up message UP and the speed-down message DN are not asserted in any one of the signals ud1e, ud3e, ud1o, and ud3o, the internal circuit 15241 may leave the count cnt1 of the counting circuit 1561 unchanged.

[0186] When the speed-up message UP is asserted in any one of signals ud2e, ud4e, ud2o, and ud4o, the internal circuit 15242 may cause the counting circuit 1562 to increment another count cnt2 by step value d1; when the speed-down message DN is asserted in any one of signals ud2e, ud4e, ud2o, and ud4o, the internal circuit 15242 may cause the counting circuit 1562 to decrement count cnt2 by step value d1. When neither the speed-up message UP nor the speed-down message DN is asserted in any one of signals ud2e, ud4e, ud2o, and ud4o, the internal circuit 15242 may leave the count cnt2 of the counting circuit 1562 unchanged. The internal circuit 15243 may determine the states of counts cnt1 and cnt2 according to the values ​​of counts cnt1 and cnt2, and may control the offset value d_phi of the phase shift circuit 1550 according to the states of counts cnt1 and cnt2 via the signal scr2. When count cnt1 is between the upper limit c_U and the lower limit c_D, its state may be equal to the state cnt_normal; when count cnt1 is greater than the upper limit c_U or less than the lower limit c_D, its state may be equal to the state cnt_UP or cnt_DN. When count cnt2 is between the upper limit c_U and the lower limit c_D, its state may be equal to the state cnt_normal; when count cnt2 is greater than the upper limit c_U or less than the lower limit c_D, its state may be equal to the state cnt_UP or cnt_DN. As shown in Figure 2e, when the states of counts cnt1 and cnt2 are equal to states cnt_UP and cnt_DN, respectively, the internal circuit 15243 may increase the offset value d_phi of the phase shift circuit 1550 via the signal scr2, and reset counts cnt1 and cnt2 to their initial value c_0.When the states of counts cnt1 and cnt2 are equal to states cnt_DN and cnt_UP, respectively, the internal circuit 15243 may decrease the offset value d_phi of the phase shift circuit 1550 via the signal scr2, and reset counts cnt1 and cnt2 to their initial value c_0. In all other situations, the internal circuit 15243 may leave the offset value d_phi unchanged and not reset counts cnt1 and cnt2.

[0187] In one embodiment, the threshold levels L1 and L3 shown in Figure 15a may be equal to a positive coefficient +h_1 and a negative value -h_1 of the coefficient, respectively; in addition, clocks ck0e and cke1e may be inverting relationships with each other, and clocks cke1o and cke1e may be inverting relationships with each other, and therefore the phases of clocks ck0e and cke1o may be the same. From the above two points, it should be understood that the operation of samplers sa01 and sa02 and the operation of samplers sa1o and sa3o may be the same, and therefore samplers sa1o and sa3o may be omitted; the signals x1o and x3o of samplers sa1o and sa3o at nodes a1o and a3o may be replaced by the signals sd11 and sd12 of samplers sa01 and sa02 at nodes n11 and n12, respectively. Similarly, samplers sa1e and sa3e may be omitted; the signals x1e and x3e of samplers sa1e and sa3e at nodes a1e and a3e may be replaced by the signals sd13 and sd14 of samplers sa03 and sa04 at nodes n13 and n14, respectively.

[0188] Although not shown, the phase detection circuit 1522 shown in Figure 15b does not have to include all of the pattern phase detection units pd1e~pd4e and pd1o~pd4o; and / or, the phase detection circuit 1524 does not have to include both of the internal circuits 15241 and 15242 and both of the counting circuits 1561 and 1562. For example, in one embodiment not shown, the phase detection circuit 1522 may include the pattern phase detection units pd1e~pd4e but not the pattern phase detection units pd1o~pd4o; and the internal circuit 15221 does not have to assert either the speed-up message UP or the speed-down message DN in signal scr1 unless either of the speed-up message UP or the speed-down message DN is asserted in any one of the signals ud1e~ud4e. In conjunction with the simplified phase detection circuit 1522, the phase detection circuit 1524 may include all of the internal circuits 15241 to 15243 and counting circuits 1561 and 1562, where the internal circuit 15241 does not need to increment or decrement the count cnt1 by step value d1 unless the speed-up message UP or the speed-down message DN is asserted in either of the signals ud1e and ud3e, and the internal circuit 15242 does not need to increment or decrement the count cnt2 by step value d1 unless the speed-up message UP or the speed-down message DN is asserted in either of the signals ud2e and ud4e. In conjunction with the simplified phase detection circuit 1522, the phase detection circuit 1524 may omit the internal circuit 15242 and the counting circuit 1562, similar to the phase detection circuit 724 shown in Figure 7a. Furthermore, in conjunction with the simplified phase detection circuit 1522, the phase detection circuit 1524 may omit the internal circuit 15241 and the counting circuit 1561, similar to the phase detection circuit 824 shown in Figure 8a.

[0189] In one embodiment not shown, the phase detection circuit 1522 may include pattern phase detection units pd1e and pd2o, but may not include other pattern phase detection units; the internal circuit 15221 may not assert either the speed-up message UP or the speed-down message DN in signal scr1 unless either of the speed-up message UP or the speed-down message DN is asserted in either of the signals ud1e and ud2o. In conjunction with such a simplified phase detection circuit 1522, the phase detection circuit 1524 may include all of the internal circuits 15241 to 15243 and counting circuits 1561 and 1562, similar to the phase detection circuit 324 shown in Figure 3a. Alternatively, the phase detection circuit 1524 may omit the internal circuit 15242 and counting circuit 1562, similar to the phase detection circuit 924 shown in Figure 9a. Alternatively, the phase detection circuit 1524 may omit the internal circuit 15241 and the counting circuit 1561, similar to the phase detection circuit 1024 shown in Figure 10a.

[0190] In short, the wireline receiver of the present disclosure may use one or more first edge clocks (e.g., clock cke1 in Figure 2a, or clocks cke1e and cke1o in Figure 15a) and one or more second edge clocks (e.g., clock cke2 in Figure 2a, or clocks cke2e and cke2o in Figure 15a) to track (reflect) the edge between two symbols of one or more receiver signals (e.g., signals sr1e and sr1o resulting from signal sr1 in Figure 2a, or signal sr0 in Figure 15a), and may use one or more reconstructed data clocks (e.g., clock ck0 in Figure 2a, or clocks ck0e and ck0o in Figure 15a) to distinguish the symbols of one or more receiver signals, thereby forming a data signal (e.g., signal sd1). The operation of the present disclosure may include: when triggered by a first edge clock, sampling and comparing the associated receiver signal to determine whether the associated receiver signal exceeds a low-frequency pattern threshold level (e.g., threshold level L1 or L3); and in response to the result of the sampling and comparison (e.g., one of the signal values ​​x1[i] or x3[i] in Figure 2b, or one of the signal values ​​x1e[i], x3e[i], x1o[i] and x3o[i] in Figure 15d), a plurality of associated signal values ​​of the data signal (e.g., signal values ​​sd1[i-1] to sd1[i+1] in Figure 2b, signal values ​​sd1[2i-1] to sd1[2i] in Figure 15d) If the signal values ​​sd1[2i-2] to sd1[2i] in Figure 15d (+1) match any of the constituent values ​​of a low-frequency pattern (e.g., pattern p1 or p3), the Disclosure may determine whether the effective edge of the first edge clock is earlier or later than the time corresponding to when the associated receiver signal crosses the low-frequency pattern threshold level, and accordingly provide a first set of phase detection results (for example, the first set of phase detection results may include at least one of the signals ud1 and ud3 in Figure 2a, or at least one of the signals ud1e, ud3e, ud1o, and ud3o in Figure 15b).A first set of phase detection results may include speed-up messages and / or speed-down messages, wherein the speed-up message indicates that the effective edge of the first edge clock is slower than the time corresponding to when the associated receiver signal crosses the low-frequency pattern threshold level, and the speed-down message indicates that the effective edge of the first edge clock is earlier than the time corresponding to when the associated receiver signal crosses the low-frequency pattern threshold level.

[0191] Furthermore, the operation of the present disclosure may comprise: when triggered by a second edge clock, sampling and comparing the relevant receiver signal to determine whether the relevant receiver signal exceeds a high-frequency pattern threshold level (e.g., threshold level L2); and in response to the result of the sampling and comparison (e.g., one of the signal values ​​x2[i] in Figure 2b, or one of the signal values ​​x2e[i] or x2o[i] in Figure 15d), a plurality of associated signal values ​​of the data signal (e.g., signal values ​​sd1[i-1]~sd1[i+1] in Figure 2b, signal values ​​sd1[2i-1]~sd1[2i+1] in Figure 15d, or Figure 15 If the signal values ​​sd1[2i-2] to sd1[2i]] in d match any of the constituent values ​​of a high-frequency pattern (e.g., pattern p2 or p4), the Disclosure may determine whether the effective edge of the second edge clock is earlier or later than the time at which the associated receiver signal crosses the high-frequency pattern threshold level, and accordingly provide a second set of phase detection results (for example, the second set of phase detection results may include at least one of the signals ud2 and ud4 in Figure 2a, or at least one of the signals ud2e, ud4e, ud2o, and ud4o in Figure 15d). A second set of phase detection results may include speed-up messages and / or speed-down messages, wherein the speed-up message indicates that the effective edge of the second edge clock is later than the time corresponding to when the associated receiver signal crosses the high-frequency pattern threshold level; and the speed-down message indicates that the effective edge of the second edge clock is earlier than the time corresponding to when the associated receiver signal crosses the high-frequency pattern threshold level.

[0192] Based on the pattern phase detection described above, the Disclosure may adjust the timing (frequency and / or phase) of one or more first edge clocks so that the effective edges of one or more first edge clocks correctly track the edges of symbols in a low-frequency pattern; the Disclosure may also provide one or more reconstructed data clocks in accordance with one or more first edge clocks, for example, by making the phase difference between each of the data clocks and its corresponding first edge clock equal to a predetermined base offset value (e.g., offset value d_p0); and based on the pattern phase detection described above, the Disclosure may also dynamically adjust an additional offset value (e.g., offset value d_phi) to provide a second edge clock by phase shift, so that the phase difference between each of the second edge clocks and its corresponding first edge clock is equal to the additional offset value.

[0193] When adjusting the timing of one or more first edge clocks, the principle of timing adjustment may be: balancing the total number of times speed-up messages occur in both the first set of phase detection results and the second set of phase detection results with the total number of times speed-down messages occur in both the first set of phase detection results and the second set of phase detection results; for example, if the total number of times speed-up messages occur in both the first set of phase detection results and the second set of phase detection results is greater than the total number of times speed-down messages occur by a difference exceeding a first tolerance, the disclosure may speed up the timing of the first edge clock (e.g., increase the frequency) and thus reduce the occurrence of subsequent speed-up messages; if the total number of times speed-down messages occur in both the first set of phase detection results and the second set of phase detection results is greater than the total number of times speed-up messages occur by a difference exceeding a second tolerance, the disclosure may slow down the timing of the first edge clock (e.g., decrease the frequency) and thus reduce the occurrence of subsequent speed-down messages.

[0194] When dynamically adjusting the additional offset value of the second edge clock, the Disclosure may increase the additional offset value if the number of speed-up messages in the first set of phase detection results is greater than the number of speed-down messages in the first set of phase detection results by a difference exceeding a first preset positive value and / or the number of speed-down messages in the second set of phase detection results is greater than the number of speed-up messages in the second set of phase detection results by a difference exceeding a fourth preset positive value; and the Disclosure may decrease the additional offset value if the number of speed-down messages in the first set of phase detection results is greater than the number of speed-up messages in the first set of phase detection results by a difference exceeding a third preset positive value and / or the total number of speed-up messages in the second set of phase detection results is greater than the number of speed-down messages in the second set of phase detection results by a difference exceeding a second preset positive value; and in all other cases, the Disclosure may leave the additional offset value unchanged.

[0195] Compared to prior art, the disclosure may utilize two types of edge clocks to reconstruct the data clock and perform sampling and phase detection to obtain two sets of phase detection results, and may apply two types of timing adjustments to enable the two types of edge clocks to track the edges of symbols of different data patterns, thereby effectively approximating the reconstructed data clock to the time axis center of the eye diagram (e.g., time point ts1 in Figure 1b), reducing jitter, and expanding the timing-related margin and the signal value-related margin (margin along the vertical axis of the eye diagram).

[0196] While this disclosure describes what is considered to be the most practical and preferred embodiment at present, it should be understood that this disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to encompass the various modifications and similar configurations included in the spirit and scope of the attached claims, and these claims should be consistent with the broadest interpretation to include all such modifications and similar configurations.

Claims

1. A data sampler configured to sample and compare a receiver signal when triggered by a data clock, to determine whether the receiver signal exceeds a data threshold level, and to contribute to forming a data signal accordingly; A first edge sampler, when triggered by a first edge clock, is configured to sample and compare the receiver signal to determine whether the receiver signal exceeds a first threshold level, and to provide a first edge signal accordingly; A second edge sampler, when triggered by a second edge clock, is configured to sample and compare the receiver signal to determine whether the receiver signal exceeds a second threshold level and to provide a second edge signal accordingly; A base phase detection circuit coupled to the data sampler, the first edge sampler, and the second edge sampler, the base phase detection circuit being configured to provide a base timing control signal in response to the data signal, the first edge signal, and the second edge signal; An additional phase detection circuit configured to provide an additional timing control signal in response to the data signal and at least one of the first edge signal and the second edge signal; A clock circuit coupled to the base phase detection circuit, the clock circuit providing the first edge clock and the data clock in response to the base timing control signal, and configured to make the phase difference between the data clock and the first edge clock equal to a predetermined base offset value; and A phase shift circuit coupled to the additional phase detection circuit, the phase shift circuit providing the second edge clock by phase shifting and configured to make the phase difference between the second edge clock and the first edge clock equal to an additional offset value. Equipped with; The first threshold level and the second threshold level are different; The additional offset value is controlled by the additional timing control signal. A wireline receiver with improved timing and associated margins.

2. The base phase detection circuit has a first pattern phase detection unit; If the data signal matches a first pattern, the first pattern phase detection unit is configured to assert a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the first edge signal; if the data signal does not match a first pattern, the first pattern phase detection unit does not assert the speed-up message or the speed-down message in the base timing control signal. The wireline receiver according to claim 1.

3. If the three consecutive signal values ​​of the data signal are equal to the first defined value, the first defined value, and the second defined value, respectively, then the data signal matches the first pattern; When the data signal matches the first pattern, if the current signal value of the first edge signal is equal to the second defined value, the first pattern phase detection unit is configured to assert the speed-up message in the base timing control signal; otherwise, the first pattern phase detection unit is configured to assert the speed-down message in the base timing control signal. The wireline receiver according to claim 2.

4. If the receiver signal is determined to exceed the data threshold level, the data sampler is configured to make the current signal value of the data signal equal to the first defined value; otherwise, the data sampler is configured to make the current signal value of the data signal equal to the second defined value. The wireline receiver according to claim 3.

5. The wireline receiver further comprises a third edge sampler; The third edge sampler is configured to, when triggered by the first edge clock, sample and compare the receiver signal to determine whether the receiver signal exceeds a third threshold level, and to provide a third edge signal accordingly; The third threshold level differs from the first threshold level and from the second threshold level; When the base phase detection circuit provides the base timing control signal in response to the data signal, the first edge signal, and the second edge signal, the base phase detection circuit is configured to provide the base timing control signal in response to the data signal, the first edge signal, the second edge signal, and the third edge signal; When the additional phase detection circuit provides the additional timing control signal in response to the data signal and at least one of the first edge signal and the second edge signal, the additional phase detection circuit is configured to provide the additional timing control signal in response to the data signal and at least one of the first edge signal, the second edge signal and the third edge signal. The wireline receiver according to claim 1.

6. The wireline receiver according to claim 5, wherein the second threshold level is substantially equal to the average of the first threshold level and the third threshold level.

7. The base phase detection circuit has a third pattern phase detection unit; If the data signal matches a third pattern, the third pattern phase detection unit is configured to assert a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the third edge signal; if the data signal does not match a third pattern, the third pattern phase detection unit does not assert the speed-up message or the speed-down message in the base timing control signal. The wireline receiver according to claim 5.

8. If the three consecutive signal values ​​of the data signal are equal to the second defined value, the second defined value, and the first defined value, respectively, then the data signal matches the third pattern; When the data signal matches the third pattern, if the current signal value of the third edge signal is equal to the first defined value, the third pattern phase detection unit is configured to assert the speed-up message in the base timing control signal; otherwise, the third pattern phase detection unit is configured to assert the speed-down message in the base timing control signal. The wireline receiver according to claim 7.

9. The base phase detection circuit has a second pattern phase detection unit; If the data signal matches a second pattern, the second pattern phase detection unit is configured to assert a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the second edge signal; if the data signal does not match a second pattern, the second pattern phase detection unit does not assert the speed-up message or the speed-down message in the base timing control signal. The wireline receiver according to claim 1.

10. If the three consecutive signal values ​​of the data signal are equal to the first defined value, the second defined value, and the first defined value, respectively, then the data signal matches the second pattern; When the data signal matches the second pattern, if the current signal value of the second edge signal is equal to the first defined value, the second pattern phase detection unit is configured to assert the speed-up message in the base timing control signal; otherwise, the second pattern phase detection unit is configured to assert the speed-down message in the base timing control signal. The wireline receiver according to claim 9.

11. The base phase detection circuit has a fourth pattern phase detection unit; If the data signal matches the fourth pattern, the fourth pattern phase detection unit is configured to assert a speed-up message or a speed-down message in the base timing control signal according to the current signal value of the second edge signal; if the data signal does not match the fourth pattern, the fourth pattern phase detection unit does not assert the speed-up message or the speed-down message in the base timing control signal. The wireline receiver according to claim 1.

12. If the three consecutive signal values ​​of the data signal are equal to the second defined value, the first defined value, and the second defined value, respectively, then the data signal matches the fourth pattern; When the data signal matches the fourth pattern, if the current signal value of the second edge signal is equal to the second defined value, the fourth pattern phase detection unit is configured to assert the speed-up message in the base timing control signal; otherwise, the fourth pattern phase detection unit is configured to assert the speed-down message in the base timing control signal. The wireline receiver according to claim 11.

13. The wireline receiver according to any one of claims 1 to 12, wherein the data threshold level and the first threshold level are substantially equal.

14. The wireline receiver according to any one of claims 1 to 12, wherein the base offset value orthogonals the data clock and the first edge clock.

15. The additional phase detection circuit has a first counting circuit; If, in response to the current signal value of the first edge signal, the three associated signal values ​​of the data signal are equal to the first defined value, the first defined value, and the second defined value, respectively, then the data signal matches the first pattern; When the data signal matches the first pattern and the current signal value of the first edge signal is equal to the second defined value, the first counting circuit is configured to increment the first speed-up cumulative count; when the data signal matches the first pattern and the current signal value of the first edge signal is equal to the first defined value, the first counting circuit is configured to increment the first speed-down cumulative count; when the data signal does not match the first pattern, the first counting circuit is configured to leave the first speed-up cumulative count and the first speed-down cumulative count unchanged; When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, the additional phase detection circuit is configured to increase the additional offset value; When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, the additional phase detection circuit is configured to reduce the additional offset value; When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed the first preset positive value, and the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed the third preset positive value, the additional phase detection circuit is configured to keep the additional offset value unchanged. A wireline receiver according to any one of claims 1 to 12.

16. The wireline receiver further comprises a third edge sampler; The third edge sampler is configured to, when triggered by the first edge clock, sample and compare the receiver signal to determine whether the receiver signal exceeds a third threshold level, and to provide a third edge signal accordingly; The third threshold level differs from the first threshold level and from the second threshold level; The additional phase detection circuit has a first counting circuit; If, in response to the current signal value of the first edge signal, the three associated signal values ​​of the data signal are equal to a first defined value, a first defined value, and a second defined value, the data signal conforms to a first pattern; if the three associated signal values ​​of the data signal are equal to a second defined value, a second defined value, and a first defined value, the data signal conforms to a third pattern; The first counting circuit is configured to increment a first speed-up cumulative count when the data signal matches the first pattern and the current signal value of the first edge signal is equal to the second defined value; the first counting circuit is configured to increment a first speed-down cumulative count when the data signal matches the first pattern and the current signal value of the first edge signal is equal to the first defined value; When the data signal matches the third pattern and the current value of the third edge signal is equal to the first defined value, the first counting circuit is configured to increment the first speed-up cumulative count; when the data signal matches the third pattern and the current signal value of the third edge signal is equal to the second defined value, the first counting circuit is configured to increment the first speed-down cumulative count; When the data signal does not match the first pattern and does not match the third pattern, the first counting circuit is configured to keep the first speed-up cumulative count and the first speed-down cumulative count unchanged; When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, the additional phase detection circuit is configured to increase the additional offset value; When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, the additional phase detection circuit is configured to reduce the additional offset value; When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed the first preset positive value, and the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed the third preset positive value, the additional phase detection circuit is configured to keep the additional offset value unchanged. A wireline receiver according to any one of claims 1 to 12.

17. The additional phase detection circuit has a second counting circuit; If, in response to the current signal value of the second edge signal, the three associated signal values ​​of the data signal are equal to the first defined value, the second defined value, and the first defined value, respectively, then the data signal matches the second pattern; When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit is configured to increment the second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit is configured to increment the second speed-down cumulative count; when the data signal does not match the second pattern, the second counting circuit is configured to leave the second speed-up cumulative count and the second speed-down cumulative count unchanged; When the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit is configured to reduce the additional offset value; When the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit is configured to increase the additional offset value; When the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed the second preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed the fourth preset positive value, the additional phase detection circuit is configured to keep the additional offset value unchanged. A wireline receiver according to any one of claims 1 to 12.

18. The additional phase detection circuit has a second counting circuit; If, in response to the current signal value of the second edge signal, the three associated signal values ​​of the data signal are equal to the first defined value, the second defined value, and the first defined value, respectively, then the data signal conforms to the second pattern; if the three associated signal values ​​of the data signal are equal to the second defined value, the first defined value, and the second defined value, respectively, then the data signal conforms to the fourth pattern; When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit is configured to increment a second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit is configured to increment a second speed-down cumulative count; When the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit is configured to increment the second speed-up cumulative count; when the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit is configured to increment the second speed-down cumulative count; When the data signal does not match the second pattern and does not match the fourth pattern, the second counting circuit is configured to keep the second speed-up cumulative count and the second speed-down cumulative count unchanged; When the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit is configured to reduce the additional offset value; When the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit is configured to increase the additional offset value; When the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed the second preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed the fourth preset positive value, the additional phase detection circuit is configured to keep the additional offset value unchanged. A wireline receiver according to any one of claims 1 to 12.

19. The additional phase detection circuit comprises a first counting circuit and a second counting circuit; If, in response to the current signal value of the first edge signal, the three associated signal values ​​of the data signal are equal to the first defined value, the first defined value, and the second defined value, respectively, then the data signal matches the first pattern; When the data signal matches the first pattern and the current signal value of the first edge signal is equal to the second defined value, the first counting circuit is configured to increment the first speed-up cumulative count; when the data signal matches the first pattern and the current signal value of the first edge signal is equal to the first defined value, the first counting circuit is configured to increment the first speed-down cumulative count; when the data signal does not match the first pattern, the first counting circuit is configured to leave the first speed-up cumulative count and the first speed-down cumulative count unchanged; If the three associated signal values ​​of the data signal are equal to the third defined value, the fourth defined value, and the third defined value, respectively, then the data signal matches the second pattern; When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the third defined value, the second counting circuit is configured to increment the second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the fourth defined value, the second counting circuit is configured to increment the second speed-down cumulative count; when the data signal does not match the second pattern, the second counting circuit is configured to leave the second speed-up cumulative count and the second speed-down cumulative count unchanged; When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit is configured to increase the additional offset value; When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, and the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit is configured to reduce the additional offset value; If the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed the third preset positive value, or the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed the first preset positive value, or the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed the second preset positive value, or the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed the fourth preset positive value, then the additional phase detection circuit is configured to keep the additional offset value unchanged. A wireline receiver according to any one of claims 1 to 12.

20. The wireline receiver further comprises a third edge sampler; The additional phase detection circuit comprises a first counting circuit and a second counting circuit; The third edge sampler is configured to, when triggered by the first edge clock, sample and compare the receiver signal to determine whether the receiver signal exceeds a third threshold level, and to provide a third edge signal accordingly; The third threshold level differs from the first threshold level and from the second threshold level; If, in response to the current signal value of the first edge signal, the three associated signal values ​​of the data signal are equal to a first defined value, a first defined value, and a second defined value, the data signal matches a first pattern; if the three associated signal values ​​of the data signal are equal to a second defined value, a second defined value, and a first defined value, the data signal matches a third pattern; When the data signal matches the first pattern and the current signal value of the first edge signal is equal to the second defined value, the first counting circuit is configured to increment a first speed-up cumulative count; when the data signal matches the first pattern and the current signal value of the first edge signal is equal to the first defined value, the first counting circuit is configured to increment a first speed-down cumulative count; when the data signal matches the third pattern and the current signal value of the third edge signal is equal to the first defined value, the first counting circuit is configured to increment a first speed-up cumulative count; when the data signal matches the third pattern and the current signal value of the third edge signal is equal to the second defined value, the first counting circuit is configured to increment a first speed-down cumulative count; When the data signal does not match the first pattern and does not match the third pattern, the first counting circuit is configured to keep the first speed-up cumulative count and the first speed-down cumulative count unchanged; If the three associated signal values ​​of the data signal are equal to the first defined value, the second defined value, and the first defined value, respectively, the data signal conforms to the second pattern; if the three associated signal values ​​of the data signal are equal to the second defined value, the first defined value, and the second defined value, respectively, the data signal conforms to the fourth pattern; When the data signal matches the second pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit is configured to increment a second speed-up cumulative count; when the data signal matches the second pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit is configured to increment a second speed-down cumulative count; when the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the second defined value, the second counting circuit is configured to increment a second speed-up cumulative count; when the data signal matches the fourth pattern and the current signal value of the second edge signal is equal to the first defined value, the second counting circuit is configured to increment a second speed-down cumulative count; When the data signal does not match the second pattern and does not match the fourth pattern, the second counting circuit is configured to keep the second speed-up cumulative count and the second speed-down cumulative count unchanged; When the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count exceeds a first preset positive value, and the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count exceeds a fourth preset positive value, the additional phase detection circuit is configured to increase the additional offset value; When the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count exceeds a third preset positive value, and the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count exceeds a second preset positive value, the additional phase detection circuit is configured to reduce the additional offset value; If the value obtained by subtracting the first speed-up cumulative count from the first speed-down cumulative count does not exceed the third preset positive value, or the value obtained by subtracting the first speed-down cumulative count from the first speed-up cumulative count does not exceed the first preset positive value, or the value obtained by subtracting the second speed-down cumulative count from the second speed-up cumulative count does not exceed the second preset positive value, or the value obtained by subtracting the second speed-up cumulative count from the second speed-down cumulative count does not exceed the fourth preset positive value, then the additional phase detection circuit is configured to keep the additional offset value unchanged. A wireline receiver according to any one of claims 1 to 12.

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