A signal detection circuit and a signal detection method

Abstract

This application discloses a signal detection circuit and a signal detection method. The signal detection circuit includes a latch comparator, an SR latch, a signal loss detection module, and a reset signal generator. After receiving the input signal to be detected, the latch comparator transmits the level state of its output terminal to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch. After receiving a clock signal, the reset signal generator generates a reset pulse signal based on the level state and transmits it to the reset terminal of the latch comparator. The signal loss detection module adjusts the level state of its output terminal according to the level state and transmits it to the reset terminal of the SR latch. The SR latch outputs the detection result based on the level state of its set terminal and the level state of its reset terminal. This method differs significantly from existing technologies that detect signals by triggering the latch comparator with a clock signal.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a signal detection circuit and a signal detection method. Background Technology

[0002] In signal transmission systems, the receiving end often needs to respond based on the presence or absence of an input signal. When an input signal is present, the receiving end is in an active state, performing signal processing; when no input signal is present, the receiving end is in a sleep state, not performing signal processing. Therefore, the receiving end needs to quickly detect the input signal. If the receiving end cannot quickly detect the input signal, it will be unable to process the signal in a timely manner, affecting the accuracy of the signal transmission system.

[0003] In existing technologies, a latch comparator is mainly used to detect signals by triggering a clock signal. However, because it is necessary to wait for the clock signal to trigger, there will be a time difference between the signal input and the output of the latch comparator, which makes it impossible to detect the input signal quickly.

[0004] Therefore, how to detect signals quickly and accurately is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a signal detection circuit and a signal detection method, with the aim of detecting signals quickly and accurately.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] The first aspect of this application provides a signal detection circuit, which includes: a latch comparator, an SR latch, a signal loss detection module, and a reset signal generator.

[0008] The input terminal of the latch comparator is used to receive the input signal to be detected. The output terminal of the latch comparator is connected to the set terminal of the SR latch, the input terminal of the signal loss detection module and the input terminal of the reset signal generator. The reset terminal of the latch comparator is connected to the output terminal of the reset signal generator.

[0009] The reset terminal of the SR latch is connected to the output terminal of the signal loss detection module, and the output terminal of the SR latch serves as the output terminal of the signal detection circuit.

[0010] The clock terminal of the signal loss detection module and the clock terminal of the reset signal generator are connected to the same clock signal output terminal;

[0011] The latch comparator is used to transmit the level state of the output terminal of the latch comparator to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch after receiving the input signal to be detected.

[0012] The reset signal generator is used to receive a clock signal at its own clock terminal, generate a reset pulse signal according to the level state, and transmit the reset pulse signal to the reset terminal of the latch comparator. The reset pulse signal is used to reset the output signal of the latch comparator.

[0013] The signal loss detection module is used to adjust the level state of its own output terminal according to the level state, and transmit its own level state to the reset terminal of the SR latch.

[0014] The SR latch is used to output the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch.

[0015] Optionally, if the signal detection circuit does not receive the input signal to be detected, the latch comparator is also used to output a low level;

[0016] The signal loss detection module is also used to wait for a preset time when it receives a low level output from the latch comparator at its own input terminal. If the input terminal of the signal loss detection module remains at a low level within the preset time, the output terminal of the signal loss detection module outputs a high level.

[0017] The SR latch is also used to output a low level when its reset terminal is high.

[0018] The signal loss detection module includes a sampler and a counter:

[0019] The input terminal of the sampler is connected to the output terminal of the latch comparator, and the clock terminal of the sampler serves as the clock terminal of the signal loss detection module.

[0020] The input terminal of the counter is connected to the output terminal of the sampler, and the output terminal of the counter serves as the output terminal of the signal loss detection module.

[0021] The sampler is used to sample the level state based on the clock signal to obtain a sampled signal;

[0022] The counter is used to determine whether all the sampled signals are at a low level within a preset time. If all are at a low level, a high level is output; if the sampled signals are at a high level within the preset time, a low level is output.

[0023] If the set terminal of the SR latch is high and the reset terminal of the SR latch is low, then the output terminal of the SR latch outputs a high level.

[0024] If the set terminal of the SR latch is low and the reset terminal of the SR latch is low, then the output terminal of the SR latch remains unchanged.

[0025] If the set terminal of the SR latch is low and the reset terminal of the SR latch is high, then the output terminal of the SR latch will output a low level.

[0026] A second aspect of this application provides a signal detection method applied to the signal detection circuit provided in the first aspect. The method includes:

[0027] After receiving the input signal to be detected, the latch comparator transmits the level state of its output terminal to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch.

[0028] After receiving a clock signal at its own clock terminal, the reset signal generator generates a reset pulse signal according to the level state and transmits the reset pulse signal to the reset terminal of the latch comparator. The reset pulse signal is used to reset the output signal of the latch comparator.

[0029] The signal loss detection module adjusts the level of its output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch.

[0030] The SR latch outputs the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch.

[0031] Optionally, the method further includes:

[0032] When the signal detection circuit does not receive the input signal to be detected, the latch comparator outputs a low level.

[0033] The signal loss detection module waits for a preset time after receiving a low level output from the latch comparator at its input terminal. If the input terminal of the signal loss detection module remains at a low level within the preset time, the output terminal of the signal loss detection module outputs a high level.

[0034] The SR latch outputs a low level when its reset terminal is at a high level.

[0035] The signal loss detection module includes a sampler and a counter: the input terminal of the sampler is connected to the output terminal of the latch comparator, and the clock terminal of the sampler serves as the clock terminal of the signal loss detection module; the input terminal of the counter is connected to the output terminal of the sampler, and the output terminal of the counter serves as the output terminal of the signal loss detection module.

[0036] The signal loss detection module adjusts the level of its output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch, including:

[0037] The sampler samples the level state based on the clock signal to obtain a sampled signal;

[0038] The counter determines whether all the sampled signals are at a low level within a preset time. If all are at a low level, it outputs a high level; if the sampled signals are at a high level within the preset time, it outputs a low level.

[0039] The SR latch outputs the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch, including:

[0040] If the set terminal of the SR latch is high and the reset terminal of the SR latch is low, then the output terminal of the SR latch outputs a high level.

[0041] If the set terminal of the SR latch is low and the reset terminal of the SR latch is low, then the output terminal of the SR latch remains unchanged.

[0042] If the set terminal of the SR latch is low and the reset terminal of the SR latch is high, then the output terminal of the SR latch outputs a low level.

[0043] The output of the SR latch is high, indicating that the detection result is that the signal detection circuit has detected the presence of an input signal to be detected.

[0044] When the output of the SR latch is low, it indicates that the detection result is that the signal detection circuit has not detected the presence of the input signal to be detected.

[0045] Compared with the prior art, this application has the following beneficial effects:

[0046] This application provides a signal detection circuit and a signal detection method. The signal detection circuit includes a latch comparator, an SR latch, a signal loss detection module, and a reset signal generator. The input terminal of the latch comparator is used to receive the input signal to be detected. The output terminal of the latch comparator is connected to the set terminal of the SR latch, the input terminal of the signal loss detection module, and the input terminal of the reset signal generator. The reset terminal of the latch comparator is connected to the output terminal of the reset signal generator. The reset terminal of the SR latch is connected to the output terminal of the signal loss detection module, and the output terminal of the SR latch serves as the output terminal of the signal detection circuit.

[0047] Since the latch comparator described in this application does not require a clock signal trigger, after receiving the input signal to be detected, the latch comparator transmits the level state of its output terminal to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch. When the input signal to be detected is continuously input, the reset signal generator receives a clock signal at its own clock terminal and generates a reset pulse signal according to the level state, transmitting the reset pulse signal to the reset terminal of the latch comparator to continuously reset the latch comparator, so that the latch comparator continuously responds to the input signal to be detected. When the input signal to be detected stops input, the signal loss detection module adjusts the level state of its own output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch. The SR latch outputs the detection result of the input signal to be detected based on the level state of its set terminal and the level state of its reset terminal.

[0048] In summary, the signal detection circuit and signal detection method provided in this application effectively realize the real-time detection of the input signal to be detected. They can not only respond to changes in the input signal to be detected in a timely manner, but also perform corresponding processing when the signal stops input or the signal is lost, ensuring that the signal detection is fast and accurate. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of a signal detection circuit provided in an embodiment of this application;

[0051] Figure 2This is a schematic diagram of the structure of a signal loss detection module provided in an embodiment of this application;

[0052] Figure 3 A flowchart illustrating a signal detection method provided in an embodiment of this application;

[0053] Figure 4 A flowchart illustrating yet another signal detection method provided in this application embodiment;

[0054] Figure 5 This is a schematic diagram of a signal waveform provided in an embodiment of this application. Detailed Implementation

[0055] As described above, current signal detection requires waiting for a clock signal to trigger the latch comparator. There is a time difference between the signal input and the output of the latch comparator, which makes it impossible to detect the input signal quickly.

[0056] In view of the above problems, the inventors, after research, proposed a signal detection method and a signal detection circuit. The signal detection circuit includes a latch comparator, an SR latch, a signal loss detection module, and a reset signal generator. After receiving the input signal to be detected, the latch comparator transmits the level state of its output terminal to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch. The reset signal generator, after receiving a clock signal at its own clock terminal, generates a reset pulse signal according to the level state and transmits the reset pulse signal to the reset terminal of the latch comparator. The reset pulse signal is used to reset the output signal of the latch comparator. The signal loss detection module adjusts the level state of its own output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch. The SR latch outputs the detection result of the input signal to be detected based on the level state of its set terminal and the level state of its reset terminal.

[0057] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0058] See Figure 1 This figure is a schematic diagram of a signal detection circuit provided in an embodiment of this application. Figure 1As shown, the circuit includes: a latch comparator 11, an SR latch 14, a signal loss detection module 12, and a reset signal generator 13.

[0059] The input terminal of the latch comparator 11 is used to receive the input signal to be detected. The output terminal of the latch comparator 11 is connected to the set terminal of the SR latch 14, the input terminal of the signal loss detection module 12 and the input terminal of the reset signal generator 13. The reset terminal of the latch comparator 11 is connected to the output terminal of the reset signal generator 13.

[0060] The reset terminal of the SR latch 14 is connected to the output terminal of the signal loss detection module 12, and the output terminal of the SR latch 14 serves as the output terminal of the signal detection circuit.

[0061] The clock terminals of the signal loss detection module 12 and the reset signal generator 13 are connected to the same clock signal output terminal.

[0062] The latch comparator 11 includes an input terminal, an output terminal, and a reset terminal. It is mainly used to detect changes in the input signal relative to a certain threshold and maintain the result of this change until it is reset. For example, when the input signal begins to be input, the output terminal of the latch comparator 11 outputs a high level without waiting for any clock signal to trigger.

[0063] The SR latch 14 includes a set terminal (S), a reset terminal (R), and an output terminal. If the set terminal of the SR latch 14 is high and the reset terminal is low, the output terminal of the SR latch 14 outputs a high level. If the set terminal of the SR latch 14 is low and the reset terminal is low, the output terminal of the SR latch 14 remains unchanged. If the set terminal of the SR latch 14 is low and the reset terminal is high, the output terminal of the SR latch 14 outputs a low level.

[0064] Figure 2 This is a schematic diagram of the structure of a signal loss detection module 12 provided in an embodiment of this application. The signal loss detection module 12 includes a sampler 31 and a counter 32, as shown below. Figure 2As shown, the input terminal of the sampler 31 is connected to the output terminal of the latch comparator 11, and the clock terminal of the sampler 31 serves as the clock terminal of the signal loss detection module 12; the input terminal of the counter 32 is connected to the output terminal of the sampler 31, and the output terminal of the counter 32 serves as the output terminal of the signal loss detection module 12. The sampler 31 is used to sample the level state based on the clock signal to obtain a sampled signal; the counter 32 is used to determine whether the sampled signal is low within a preset time. If it is low, it outputs a high level; if the sampled signal is high within the preset time, it outputs a low level.

[0065] The reset signal generator 13 includes an input terminal, a clock terminal, and an output terminal, and is used to generate a reset pulse signal to reset the level state of the output terminal of the latch comparator 11.

[0066] When the input signal begins to be input, the output of the latch comparator 11 is high, the set terminal of the SR latch 14 is high, the input of the signal loss detection module 12 is high, the output of the signal loss detection module 12 is low, the reset terminal of the SR latch 14 is low, and the output of the SR latch 14 is high. When the input signal continues to be input, the reset signal generator 13 generates a reset pulse signal to continuously reset the latch comparator 11, so that the latch comparator 11 can continuously detect the input signal and update the level state of its output terminal. The SR latch 14 outputs the signal detection result according to the level state of its set terminal and the level state of its reset terminal.

[0067] In summary, this signal detection circuit enables the latch comparator 11 to respond quickly when an input signal is present. When the input signal is continuously input, the reset signal generator 13 generates a reset pulse signal based on a clock signal to continuously reset the latch comparator 11, allowing it to continuously detect the input signal. When the input signal stops or is lost, the signal loss detection module 12 waits for a preset time, samples and judges the level state of the output of the latch comparator 11, and updates the level state of each part in a timely manner. The SR latch 14 outputs the detection result, making the detection result of the entire signal detection circuit accurate and fast.

[0068] Based on the signal detection circuit in the above embodiments, this application also provides an embodiment of a signal detection method, which will be described in detail below.

[0069] See Figure 3 This figure is a flowchart of a signal detection method provided in an embodiment of this application. Figure 3As shown, the method includes the following steps:

[0070] S301. After receiving the input signal to be detected, the latch comparator transmits the level state of its output terminal to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch.

[0071] Upon receiving the input signal to be detected, the latch comparator changes the level of its output terminal based on the relationship between the characteristics of the input signal and a preset threshold. This changed level is simultaneously transmitted to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch. The latch comparator not only responds quickly to changes in the input signal to be detected but also effectively transmits this information to other parts, thereby ensuring that the entire circuit can respond quickly and accurately to the input signal to be detected.

[0072] S302. After receiving a clock signal at its own clock terminal, the reset signal generator generates a reset pulse signal according to the level state and transmits the reset pulse signal to the reset terminal of the latch comparator. The reset pulse signal is used to reset the output signal of the latch comparator.

[0073] The input of the reset signal generator detects a change in the output level of the latch comparator and generates a reset pulse signal. Upon receiving the reset pulse signal, the reset terminal of the latch comparator resets the output level to its initial state. In this way, the reset signal generator ensures that the latch comparator can respond quickly and accurately to input signals and correctly resets the latch comparator after each detection.

[0074] S303. The signal loss detection module adjusts the level of its output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch.

[0075] The sampler samples the level state based on the clock signal to obtain a sampled signal; the counter determines whether the sampled signal is low within a preset time. If it is low, it outputs a high level; if the sampled signal is high within the preset time, it outputs a low level.

[0076] S304. The SR latch outputs the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch.

[0077] The output of the SR latch is high, indicating that the detection result is that the signal detection circuit has detected the presence of an input signal to be detected.

[0078] When the output of the SR latch is low, it indicates that the detection result is that the signal detection circuit has not detected the presence of the input signal to be detected.

[0079] This signal detection method enables the latch comparator to respond quickly when an input signal is present. During continuous input signals, the reset signal generator continuously resets the latch comparator by generating reset pulses based on a clock signal, allowing for continuous input signal detection. When the input signal stops or is lost, the signal loss detection module waits for a preset time, samples and judges the level state of the latch comparator's output, and updates the level states of each component in a timely manner. The SR latch outputs the detection result, ensuring accurate and rapid detection results from the entire signal detection circuit. This signal detection method features rapid response from each component, working together to quickly and accurately detect the presence of an input signal and reflect changes within it.

[0080] See Figure 4 The figure is a flowchart of another signal detection method provided in an embodiment of this application. The method fully presents the response process of the latch comparator, signal loss detection module, reset signal generator, and SR latch when the input signal starts to be input, continues to be input, and disappears. Figure 5 This is a schematic diagram of a signal waveform. This method is applicable to, for example... Figure 5 The input signal V shown in Signal detection is performed, the output level of the latch comparator is V1, the output level of the signal loss detection module is V2, and the reset pulse signal generated by the reset signal generator is V. rst The voltage level at the output of the SR latch is V. out The signal loss detection module and the reset signal generator receive the same clock signal Clk. The method includes the following steps:

[0081] S401, Received the input signal V to be detected in The output terminal V1 of the latch comparator outputs a high level and transmits its level state to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch.

[0082] At this time, the set terminal of the SR latch is at a high level, and the input terminal of the signal loss detection module is at a high level, causing its own output terminal V2 to output a low level, which in turn causes the reset terminal of the SR latch to be at a low level. Therefore, the output terminal V of the SR latch... out A high-level output indicates that the signal detection circuit has detected the presence of the input signal to be detected.

[0083] S402, when the input signal V in During continuous input, the reset signal generator receives the clock signal Clk at its own clock terminal and generates a reset pulse signal V according to the level state. rst The reset pulse signal V rst The signal is transmitted to the reset terminal of the latch comparator to reset the latch comparator, causing the output terminal V1 of the latch comparator to output a low level.

[0084] Wherein, the frequency of the clock signal Clk is related to the input signal V in The frequencies are similar. At this time, the output terminal V1 of the latch comparator after reset outputs a low level. When the latch comparator continuously detects the input signal V... in Afterwards, it immediately jumps to a high level, updating the level state of its output terminal V1. This reset process corresponds to... Figure 5 The brief fluctuation process of the V1 waveform.

[0085] S403, the latch comparator transmits the level state of its output terminal V1 to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch.

[0086] When the set terminal of the SR latch is low, the output level depends on the reset terminal of the SR latch.

[0087] After a preset time, a high level appears at the input of the signal loss detection module, and a low level is output at the output of the signal loss detection module, causing the reset terminal of the SR latch to be low. At this time, the output terminal V of the SR latch... out Maintain the same level as when there is an input signal, i.e., a high level. In summary, when the input signal V... in When input begins and continues, the output terminal V of the SR latch... out Output high level.

[0088] S404, when the input signal V in When input stops, the output terminal V1 of the latch comparator outputs a low level and transmits its level state to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch.

[0089] At this time, the set terminal of the SR latch is at a low level, and the level state of the output terminal depends on the reset terminal of the SR latch.

[0090] Waiting for a preset time, during which the input of the signal loss detection module remains at a low level and the output of the signal loss detection module V2 outputs a high level, so that the reset terminal of the SR latch is at a high level.

[0091] For example, the sampler in the signal loss detection module samples the level state of the output terminal V1 of the latch comparator. Assuming the preset time T = 5ms and the frequency f of the clock signal Clk = 10kHz, the number of samplings n is n = T / (1 / f) = 50. When the counter in the signal loss detection module detects that the sampled signal is low for 50 consecutive times within the preset time, it means that the level state of the output terminal V1 of the latch comparator is always low. Then the output terminal V2 of the signal loss detection module outputs a high level, making the reset terminal of the SR latch high.

[0092] S405, the SR latch outputs a signal to be detected V based on the level state of the set terminal and the level state of the reset terminal of the SR latch. in The test results.

[0093] At this time, the set terminal of the SR latch is at a low level, the reset terminal of the SR latch is at a high level, and the output terminal V of the SR latch is... out A low output level indicates that no input signal V was detected. in .

[0094] This method enables rapid and continuous detection of input signals when they are present, until the signals disappear, ensuring fast and accurate signal detection.

[0095] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0096] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A signal detection circuit, characterized by, The circuit includes: a latch comparator, an SR latch, a signal loss detection module, and a reset signal generator. The input terminal of the latch comparator is used to receive the input signal to be detected. The output terminal of the latch comparator is connected to the set terminal of the SR latch, the input terminal of the signal loss detection module and the input terminal of the reset signal generator. The reset terminal of the latch comparator is connected to the output terminal of the reset signal generator. The reset terminal of the SR latch is connected to the output terminal of the signal loss detection module, and the output terminal of the SR latch serves as the output terminal of the signal detection circuit. The clock terminal of the signal loss detection module and the clock terminal of the reset signal generator are connected to the same clock signal output terminal; The latch comparator is used to transmit the level state of the output terminal of the latch comparator to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch after receiving the input signal to be detected. The reset signal generator is used to receive a clock signal at its own clock terminal, generate a reset pulse signal according to the level state, and transmit the reset pulse signal to the reset terminal of the latch comparator. The reset pulse signal is used to reset the output signal of the latch comparator. The signal loss detection module is used to adjust the level state of its own output terminal according to the level state, and transmit its own level state to the reset terminal of the SR latch. The SR latch is used to output the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch.

2. The circuit according to claim 1, characterized in that, When the signal detection circuit does not receive the input signal to be detected, the latch comparator is also used to output a low level. The signal loss detection module is also used to wait for a preset time when it receives a low level output from the latch comparator at its own input terminal. If the input terminal of the signal loss detection module remains at a low level within the preset time, the output terminal of the signal loss detection module outputs a high level. The SR latch is also used to output a low level when its reset terminal is high.

3. The circuit of claim 1, wherein, The signal loss detection module includes a sampler and a counter: The input terminal of the sampler is connected to the output terminal of the latch comparator, and the clock terminal of the sampler serves as the clock terminal of the signal loss detection module. The input terminal of the counter is connected to the output terminal of the sampler, and the output terminal of the counter serves as the output terminal of the signal loss detection module. The sampler is used to sample the level state based on the clock signal to obtain a sampled signal; The counter is used to determine whether all the sampled signals are at a low level within a preset time. If all are at a low level, a high level is output; if the sampled signals are at a high level within the preset time, a low level is output.

4. The circuit according to claim 1, characterized in that, If the set terminal of the SR latch is high and the reset terminal of the SR latch is low, then the output terminal of the SR latch outputs a high level. If the set terminal of the SR latch is low and the reset terminal of the SR latch is low, then the output terminal of the SR latch remains unchanged. If the set terminal of the SR latch is low and the reset terminal of the SR latch is high, then the output terminal of the SR latch will output a low level.

5. A signal detection method characterized by, The method is applied to the signal detection circuit according to claim 1; The method includes: After receiving the input signal to be detected, the latch comparator transmits the level state of its output terminal to the input terminal of the reset signal generator, the input terminal of the signal loss detection module, and the set terminal of the SR latch. After receiving a clock signal at its own clock terminal, the reset signal generator generates a reset pulse signal according to the level state and transmits the reset pulse signal to the reset terminal of the latch comparator. The reset pulse signal is used to reset the output signal of the latch comparator. The signal loss detection module adjusts the level of its output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch. The SR latch outputs the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch.

6. The method of claim 5, wherein, The method further includes: When the signal detection circuit does not receive the input signal to be detected, the latch comparator outputs a low level. The signal loss detection module waits for a preset time after receiving a low level output from the latch comparator at its input terminal. If the input terminal of the signal loss detection module remains at a low level within the preset time, the output terminal of the signal loss detection module outputs a high level. The SR latch outputs a low level when its reset terminal is at a high level.

7. The method of claim 5, wherein, The signal loss detection module includes a sampler and a counter: the input terminal of the sampler is connected to the output terminal of the latch comparator, and the clock terminal of the sampler serves as the clock terminal of the signal loss detection module; The input terminal of the counter is connected to the output terminal of the sampler, and the output terminal of the counter serves as the output terminal of the signal loss detection module. The signal loss detection module adjusts the level of its output terminal according to the level state and transmits its own level state to the reset terminal of the SR latch, including: The sampler samples the level state based on the clock signal to obtain a sampled signal; The counter determines whether all the sampled signals are at a low level within a preset time. If all are at a low level, it outputs a high level; if the sampled signals are at a high level within the preset time, it outputs a low level.

8. The method of claim 6, wherein, The SR latch outputs the detection result of the input signal to be detected based on the level state of the set terminal and the level state of the reset terminal of the SR latch, including: If the set terminal of the SR latch is high and the reset terminal of the SR latch is low, then the output terminal of the SR latch outputs a high level. If the set terminal of the SR latch is low and the reset terminal of the SR latch is low, then the output terminal of the SR latch remains unchanged. If the set terminal of the SR latch is low and the reset terminal of the SR latch is high, then the output terminal of the SR latch outputs a low level. The output of the SR latch is high, indicating that the detection result is that the signal detection circuit has detected the presence of an input signal to be detected. When the output of the SR latch is low, it indicates that the detection result is that the signal detection circuit has not detected the presence of the input signal to be detected.

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