A comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit. The comparator comprises a first-stage circuit, a second-stage circuit, a first switch circuit and a second switch circuit. The first-stage circuit comprises a first input circuit and a second input circuit. The first switch circuit and the second switch circuit are respectively used for controlling the conduction of the first input circuit and the second input circuit according to a first feedback signal, a second feedback signal and a clock signal. The first input circuit is used for generating a first differential signal according to an input signal and a first reference signal in a sampling stage when conducting. The second input circuit is used for generating a second differential signal according to the input signal and a second reference signal in the sampling stage when conducting. The second-stage circuit is used for amplifying and latching the first differential signal or the second differential signal in a regeneration stage to output a comparison signal. The application can eliminate the influence of inter-symbol interference and reduce the working voltage of the comparator.

Description

Technical Field

[0001] This application relates to integrated circuit design, and more particularly to a comparator and a decision feedback equalization (DFE) circuit. Background Technology

[0002] With the continuous development of computer technology, more and more products are becoming intelligent through computer control. However, as application scenarios continue to expand, people are also placing increasingly higher demands on computer performance, including faster operating speeds and lower power consumption.

[0003] Storage devices are an indispensable part of computer hardware systems, storing instructions and data during computer operation to ensure normal functioning. Among these, comparators are a crucial component, and improving comparator performance contributes to overall computer performance. Summary of the Invention

[0004] This application aims to provide a comparator and decision feedback equalization circuit that can eliminate the effects of inter-symbol interference and reduce the operating voltage of the comparator.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application provides a comparator, which includes: a first-stage circuit, a second-stage circuit, a first-switching circuit, and a second-switching circuit; the first-stage circuit includes: a first-input circuit and a second-input circuit.

[0007] The first input circuit is connected to the first switching circuit; the second input circuit is connected to the second switching circuit.

[0008] The first switching circuit and the second switching circuit are also respectively connected to a ground terminal or a power supply terminal; the first input circuit and the second input circuit are also respectively connected to the ground terminal or the power supply terminal; the first input circuit and the second input circuit are also both connected to the second stage circuit;

[0009] The second-stage circuit is connected to either the power supply terminal or the ground terminal; wherein,

[0010] The first switching circuit is used to control the conduction of the first input circuit according to the first feedback signal, the second feedback signal and the clock signal;

[0011] The second switching circuit is used to control the conduction of the second input circuit according to the first feedback signal, the second feedback signal and the clock signal;

[0012] The first input circuit is used to generate a first differential signal based on the input signal and the first reference signal during the sampling phase when it is turned on;

[0013] The second input circuit is used to generate a second differential signal based on the input signal and the second reference signal during the sampling phase when the circuit is turned on.

[0014] The second-stage circuit is used to amplify and latch the first differential signal or the second differential signal during the regeneration stage to output a comparison signal.

[0015] In the above scheme, the first-stage circuit further includes: a first reset circuit;

[0016] The first input circuit and the second input circuit are connected through the first reset circuit; the first reset circuit is also connected to the power supply terminal or the ground terminal; wherein...

[0017] The first reset circuit is used to reset the first input circuit and the second input circuit during the reset phase.

[0018] In the above scheme, the first switching circuit includes: a first turning-on circuit and a first turning-off circuit;

[0019] Both the first power-on circuit and the first power-off circuit are connected to the control terminal of the first input circuit; the first power-off circuit is also connected to the ground terminal or the power supply terminal; wherein...

[0020] The first enabling circuit is used to turn on the clock signal to the control terminal of the first input circuit under the control of the first feedback signal;

[0021] The first shutdown circuit is used to connect the control terminal of the first input circuit to the ground terminal or the power supply terminal under the control of the second feedback signal, so as to turn off the first input circuit; the first feedback signal and the second feedback signal are inverse signals to each other.

[0022] In the above scheme, the second switching circuit includes: a second turning-on circuit and a second turning-off circuit;

[0023] Both the second power-on circuit and the second power-off circuit are connected to the control terminal of the second input circuit; the second power-off circuit is also connected to the ground terminal or the power supply terminal; wherein...

[0024] The second turn-on circuit is used to turn on the clock signal to the control terminal of the second input circuit under the control of the second feedback signal;

[0025] The second shutdown circuit is used to connect the control terminal of the second input circuit to the ground terminal or the power supply terminal under the control of the first feedback signal, so as to turn off the second input circuit.

[0026] In the above scheme, the first turn-on circuit includes a first switching transistor; the first turn-off circuit includes a second switching transistor.

[0027] The second terminal of the first switching transistor and the first terminal of the second switching transistor are both connected to the control terminal of the first input circuit; the second terminal of the second switching transistor is also connected to the ground terminal or the power supply terminal; the first switching transistor and the second switching transistor are NMOS or PMOS; wherein...

[0028] The control terminal of the first switching transistor receives the first feedback signal; the first terminal of the first switching transistor receives the clock signal; and the control terminal of the second switching transistor receives the second feedback signal.

[0029] In the above scheme, the second turn-on circuit includes a third switching transistor; the second turn-off circuit includes a fourth switching transistor.

[0030] The second terminal of the third switching transistor and the first terminal of the fourth switching transistor are both connected to the control terminal of the second input circuit; the second terminal of the fourth switching transistor is also connected to the ground terminal or the power supply terminal; the third and fourth switching transistors are NMOS or PMOS; wherein...

[0031] The control terminal of the third switching transistor receives the second feedback signal; the first terminal of the third switching transistor receives the clock signal; and the control terminal of the fourth switching transistor receives the first feedback signal.

[0032] In the above scheme, when the first feedback signal triggers the first switching transistor and the fourth switching transistor to be in the on state, the second feedback signal triggers the second switching transistor and the third switching transistor to be in the off state, so that the clock signal is input to the control terminal of the first input circuit through the first switching transistor, and the control terminal of the second input circuit is connected to the ground terminal or the power supply terminal through the fourth switching transistor.

[0033] When the first feedback signal triggers the first switching transistor and the fourth switching transistor to the off state, the second feedback signal triggers the second switching transistor and the third switching transistor to the on state, so that the control terminal of the first input circuit is connected to the ground terminal or the power supply terminal through the second switching transistor, and the clock signal is input to the control terminal of the second input circuit through the third switching transistor.

[0034] In the above scheme, the first input circuit includes: a first input transistor, a second input transistor, and a third input transistor;

[0035] The first terminal of the first input transistor and the first terminal of the second input transistor are respectively connected to the second stage circuit;

[0036] The control terminal of the third input transistor serves as the control terminal of the first input circuit; the second terminal of the third input transistor is connected to the ground terminal or the power supply terminal.

[0037] The second terminals of the first input transistor and the second input transistor are both connected to the first terminal of the third input transistor;

[0038] The first to third input transistors are NMOS or PMOS; wherein,

[0039] The control terminal of the first input transistor receives the input signal; the control terminal of the second input transistor receives the first reference signal.

[0040] When the third input transistor is triggered to conduct by the clock signal, the first input transistor and the second input transistor generate the first differential signal according to the input signal and the first reference signal, and input the first differential signal to the second stage circuit.

[0041] In the above scheme, the second input circuit includes: a fourth input transistor, a fifth input transistor, and a sixth input transistor;

[0042] The first terminal of the fourth input transistor and the first terminal of the fifth input transistor are respectively connected to the second stage circuit;

[0043] The control terminal of the sixth input transistor serves as the control terminal of the second input circuit; the second terminal of the sixth input transistor is connected to the ground terminal or the power supply terminal.

[0044] The second terminal of the fourth input transistor and the second terminal of the fifth input transistor are both connected to the first terminal of the sixth input transistor;

[0045] The fourth to sixth input transistors are NMOS or PMOS; wherein...

[0046] The control terminal of the fourth input transistor receives the input signal; the control terminal of the fifth input transistor receives the second reference signal.

[0047] When the sixth input transistor is triggered to conduct by the clock signal, the fourth input transistor and the fifth input transistor generate the second differential signal according to the input signal and the second reference signal, and input the second differential signal to the second stage circuit.

[0048] In the above scheme, the first reset circuit includes: a first reset transistor and a second reset transistor;

[0049] Both the first terminal of the first reset transistor and the first terminal of the second reset transistor are connected to the power supply terminal or the ground terminal; the second terminal of the first reset transistor is connected to the first input circuit; the second terminal of the second reset transistor is connected to the second input circuit; the first reset transistor and the second reset transistor are PMOS or NMOS; wherein...

[0050] The control terminals of both the first reset transistor and the second reset transistor receive the clock signal;

[0051] When the clock signal triggers the first reset transistor and the second reset transistor to be in the conducting state, the first input circuit is connected to the power supply terminal or the ground terminal through the first reset transistor to be reset, and the second input circuit is connected to the power supply terminal or the ground terminal through the second reset transistor to be reset.

[0052] In the above scheme, the second-stage circuit includes: an output circuit and a second reset circuit;

[0053] The second reset circuit is connected to the output circuit; the output circuit is also connected to the power supply terminal or the ground terminal; the second reset circuit is also connected to the power supply terminal or the ground terminal; wherein...

[0054] The output circuit is used to amplify and latch the first differential signal or the second differential signal during the regeneration stage to output a comparison signal.

[0055] The second reset circuit is used to reset the output circuit during the reset phase.

[0056] In the above scheme, the second reset circuit includes: a third reset transistor and a fourth reset transistor;

[0057] The first terminals of the third reset transistor and the fourth reset transistor are both connected to the power supply terminal or the ground terminal; the second terminals of the third reset transistor and the fourth reset transistor are respectively connected to the output circuit; the third reset transistor and the fourth reset transistor are PMOS or NMOS; wherein...

[0058] The control terminals of both the third and fourth reset transistors receive the clock signal;

[0059] When the clock signal triggers the third reset transistor and the fourth reset transistor to be in the conducting state, the output circuit is connected to the power supply terminal or the ground terminal through the third reset transistor and the fourth reset transistor to reset.

[0060] In the above scheme, the output circuit includes: a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, and a sixth output transistor;

[0061] The control terminal of the first output transistor, the first terminal of the second output transistor, the control terminal of the third output transistor, the second terminal of the fourth output transistor, and the second terminal of the sixth output transistor are all connected to the first output terminal of the output circuit;

[0062] The first terminal of the first output transistor, the control terminal of the second output transistor, the second terminal of the third output transistor, the control terminal of the fourth output transistor, and the second terminal of the fifth output transistor are all connected to the second output terminal of the output circuit;

[0063] The second terminal of the first output transistor and the second terminal of the second output transistor are respectively connected to the first input circuit, the second input circuit and the second reset circuit;

[0064] The first terminals of the third output transistor, the fourth output transistor, the fifth output transistor, and the sixth output transistor are all connected to the power supply terminal or the ground terminal.

[0065] The first and second output transistors are NMOS or PMOS; the third to sixth output transistors are PMOS or NMOS; wherein,

[0066] The control terminals of the fifth output transistor and the sixth output transistor both receive the clock signal.

[0067] In the above scheme, the voltage of the first reference signal is greater than or less than the voltage of the second reference signal.

[0068] This application embodiment also provides a decision feedback equalization circuit, the circuit including: N levels of comparators as described in the above scheme; wherein, N is a positive integer greater than 1;

[0069] The first input terminal of each comparator receives an input signal; the second input terminal of each comparator receives a first reference signal; and the third input terminal of each comparator receives a second reference signal.

[0070] The fourth input terminal of the first-stage comparator is connected to the output terminal of the Nth-stage comparator, and receives the Nth-stage comparison signal output by the Nth-stage comparator; the fifth input terminal of the first-stage comparator receives the first clock signal;

[0071] The fourth input terminal of the i-th stage comparator is connected to the output terminal of the (i-1)-th stage comparator, and receives the (i-1)-th stage comparison signal output by the (i-1)-th stage comparator; the fifth input terminal of the i-th stage comparator receives the i-th clock signal; where i is greater than 1 and less than or equal to N; where,

[0072] Each comparator, triggered by a clock signal, compares the input signal with the first reference signal or with the second reference signal according to the comparison signal corresponding to the fourth input terminal of each comparator, so as to output a comparison signal for each stage.

[0073] In the above scheme, the phase of the i-th clock signal is 360° / N later than the phase of the (i-1)-th clock signal.

[0074] In the above scheme, when N=4, the fourth input terminal of the first-stage comparator is connected to the output terminal of the fourth-stage comparator to receive the fourth-stage comparison signal output by the fourth-stage comparator; the fifth input terminal of the first-stage comparator receives the first clock signal.

[0075] In the above scheme, the decision feedback equalization circuit further includes: N latches;

[0076] The input of each latch is connected to the output of each comparator stage to receive the comparison signal from each stage.

[0077] in,

[0078] Each latch is used to store the comparison signal for each stage in order to output the latch signal for each stage.

[0079] Therefore, this application provides a comparator and a decision feedback equalization circuit. The comparator includes a first-stage circuit, a second-stage circuit, a first switching circuit, and a second switching circuit. The first-stage circuit includes a first input circuit and a second input circuit. The first input circuit and the second input circuit are respectively connected to the first switching circuit and the second switching circuit. The first switching circuit, the second switching circuit, the first input circuit, and the second input circuit are also respectively connected to a ground terminal or a power supply terminal. The first input circuit and the second input circuit are also connected to the second-stage circuit. The second-stage circuit is connected to a power supply terminal or a ground terminal. Specifically, the first switching circuit controls the conduction of the first input circuit based on a first feedback signal, a second feedback signal, and a clock signal; the second switching circuit controls the conduction of the second input circuit based on the first feedback signal, the second feedback signal, and the clock signal; the first input circuit generates a first differential signal based on the input signal and a first reference signal during the sampling phase when the circuit is on; the second input circuit generates a second differential signal based on the input signal and the second reference signal during the sampling phase when the circuit is on; the second-stage circuit amplifies and latches the first differential signal or the second differential signal during the regeneration phase to output a comparison signal. In this way, by controlling the conduction of the first and second input circuits, a more suitable one of the first and second reference signals is selected to compare with the input signal, thereby eliminating the influence of inter-symbol interference. At the same time, the first and second switching circuits are connected to the first and second input circuits from other ports respectively, without affecting the direct connection of the first and second input circuits to the ground terminal or power supply terminal respectively. Therefore, a smaller number of transistors can be used in the main circuit path of the comparator, thereby reducing the total operating voltage while keeping the voltage division of each transistor constant. Attached Figure Description

[0080] Figure 1 This is a schematic diagram of a comparator provided in a related technical solution;

[0081] Figure 2 This is a schematic diagram illustrating the working process of the comparator in the relevant technical solution;

[0082] Figure 3 This is a schematic diagram of inter-symbol interference in the relevant technical solutions;

[0083] Figure 4 A schematic diagram of the structure of a comparator provided in an embodiment of this application. Figure 1 ;

[0084] Figure 5 A schematic diagram of the structure of a comparator provided in an embodiment of this application. Figure 2 ;

[0085] Figure 6 A schematic diagram of the structure of a comparator provided in an embodiment of this application. Figure 3 ;

[0086] Figure 7 A schematic diagram of the structure of a comparator provided in an embodiment of this application. Figure 4 ;

[0087] Figure 8 A schematic diagram of the structure of a comparator provided in an embodiment of this application. Figure 5 ;

[0088] Figure 9 A schematic diagram of a decision feedback equalization circuit provided in this application embodiment. Figure 1 ;

[0089] Figure 10 A schematic diagram of a decision feedback equalization circuit provided in this application embodiment. Figure 2 ;

[0090] Figure 11 A schematic diagram of the effect of a decision feedback equalization circuit provided in an embodiment of this application. Figure 1 ;

[0091] Figure 12 A schematic diagram of the effect of a decision feedback equalization circuit provided in an embodiment of this application. Figure 2 ;

[0092] Figure 13 A schematic diagram of the effect of a decision feedback equalization circuit provided in an embodiment of this application. Figure 3 ;

[0093] Figure 14 A schematic diagram of the effect of a decision feedback equalization circuit provided in an embodiment of this application. Figure 4 . Detailed Implementation

[0094] Figure 1 This is a schematic diagram of the comparator structure in related technologies, such as... Figure 1 As shown, comparator 10 includes an input circuit 101, an output circuit 102, and a reset circuit 103. The input circuit 101 is connected to the input terminal of the output circuit 102; the reset circuit 103 is also connected to the output circuit 102.

[0095] The input circuit 101 includes NMOS (N-Metal-Oxide-Semiconductor) transistors N1, NMOS transistor N2, and NMOS transistor N3. The sources of N1 and N2 are both connected to the drain of N3; the source of N3 is connected to ground. The gate of N1 serves as the first input terminal INP of comparator 10 to receive the input signal; the gate of N2 serves as the second input terminal INN of comparator 10 to receive the reference signal; and the gate of N3 receives the clock signal CLK. N1 and N2 are an input pair that generates differential currents corresponding to the differential input levels (i.e., the input signal and the reference signal).

[0096] The output circuit 102 includes PMOS (P-Metal-Oxide-Semiconductor) transistors P1, PMOS transistor P2, NMOS transistor N4, and NMOS transistor N5. The gate of P1, the drain of P2, the gate of N4, and the drain of N5 are all connected to the first output terminal OUTP of comparator 10; the drain of P1, the gate of P2, the drain of N4, and the gate of N5 are all connected to the second output terminal OUTN of comparator 10; the source of P1 and the source of P2 are both connected to the power supply terminal; the source of N4 is connected to the drain of N1; and the source of N5 is connected to the drain of N2.

[0097] The reset circuit 103 includes PMOS transistors P3 and PMOS transistor P4. The drain of P3 is connected to the second output terminal OUTN of comparator 10; the drain of P4 is connected to the first output terminal OUTP of comparator 10; the sources of both P3 and P4 are connected to the power supply. The gates of P3 and P4 receive the clock signal CLK.

[0098] The operation of comparator 10 is divided into four stages: reset stage, sampling stage, regeneration stage, and decision stage. Figure 2 This is a timing diagram of comparator 10. The following is a combination of... Figure 2 Describe the operation of comparator 10:

[0099] During the reset phase, which is before time t1, the clock signal CLK is low, and N3 is triggered by the clock signal CLK to be in the off state, so the input circuit 101 and the output circuit 102 stop working. At the same time, P3 and P4 are triggered by the clock signal CLK to be in the on state, and the reset circuit 103 works, keeping the voltage of the first output terminal OUTP and the second output terminal OUTN at a high level.

[0100] The sampling phase, from time t1 to t2, begins at the start of sampling (time t1). At this time, the clock signal CLK goes high, triggering P3 and P4 to the cutoff state, and the reset circuit stops working. Simultaneously, N3 is triggered to the conduction state by the clock signal CLK, activating input circuit 101 and output circuit 102. The first input terminal INP acquires the input signal, and the second input terminal INN acquires the reference signal. Subsequently, the voltages of the first output terminal OUTP and the second output terminal OUTN gradually decrease to low levels due to the influence of the input and reference signals. At the end of the sampling phase (time t2), P1 is triggered to the conduction state by the low level of the first output terminal OUTP, and P2 is triggered to the conduction state by the low level of the second output terminal OUTN.

[0101] It should be noted that during the sampling phase, due to the difference in voltage between the input signal and the reference signal, the voltages at the first output terminal OUTP and the second output terminal OUTN decrease at different rates, resulting in a voltage difference between them. Figure 2 In this circuit, because the input signal is higher than the reference signal, the voltage at the second output terminal OUTN decreases faster than the voltage at the first output terminal OUTP, resulting in a lower voltage at OUTN than at OUTP. It can be understood that when the input signal is lower than the reference signal (i.e., the signal voltage acquired by the first input terminal INP is lower than the second input terminal INN), the voltage at the first output terminal OUTP will decrease faster than the voltage at OUTN, resulting in a lower voltage at OUTP than OUTN. Conversely, when the input signal is higher than the reference signal (i.e., the signal voltage acquired by the first input terminal INP is higher than the second input terminal INN), the voltage at the first output terminal OUTP will be higher than the voltage at OUTN.

[0102] The regeneration phase, from time t2 to t3, begins at the start of the regeneration phase (time t2). P1 and P2 are triggered into the conducting state, and the cross-coupled inverter composed of P1 and P2 amplifies the voltage difference formed between the first output terminal OUTP and the second output terminal OUTN during the sampling phase through positive feedback. Simultaneously, N1 and N2 sense the differential input level (i.e., the input signal and the reference signal) and generate differential drain current, affecting V... MIDP and V MIDN Charging is performed to give it a large signal swing relative to the input polarity. At the end of the regeneration phase (i.e., time t3), the voltage difference between the first output terminal OUTP and the second output terminal OUTN is amplified sufficiently, so that the first output terminal OUTP and the second output terminal OUTN are regenerated to form high and low levels, respectively. If the input signal is higher than the reference signal, i.e. Figure 2As shown, the first output terminal OUTP is regenerated to form a high level, and the second output terminal OUTN is regenerated to form a low level; if the input signal is lower than the reference signal, the first output terminal OUTP is regenerated to form a low level, and the second output terminal OUTN is regenerated to form a high level.

[0103] During the decision-making phase, from time t3 to t4, the output circuit 102 latches the levels of the first output terminal OUTP and the second output terminal OUTN to maintain the levels and outputs the latched levels as comparison signals.

[0104] When the next working cycle arrives (i.e., at time t4), the clock signal is switched to a low level, N3 is triggered to the cutoff state by the clock signal CLK, and the input circuit 101 and the output circuit 102 stop working; at the same time, P3 and P4 are triggered to the conduction state by the clock signal CLK, the reset circuit 103 works, and pulls the voltage of the first output terminal OUTP and the second output terminal OUTN back to a high level.

[0105] Therefore, the comparator works by comparing the input signal with the reference signal. If the input signal is greater than the reference signal, it outputs comparison signal one; if the input signal is less than the reference signal, it outputs comparison signal two, which is the inverse of comparison signal one. In this way, the high or low level of the input signal is determined.

[0106] It should be noted that inter-symbol interference (ISI) exists during the operation of the comparator. ISI occurs because the overall transmission characteristics of the system are not ideal, causing waveform distortion and broadening of signals at consecutive time points, and resulting in a long tail in the preceding waveform that extends to the sampling time of the current time point, thus interfering with the decision of the current time point signal. Figure 3 This is a diagram illustrating inter-symbol interference (ISI), such as... Figure 3 As shown, signals 1, 2, and 3 all exhibit long tails after their peak values, slowly decreasing to 0 only after several time points. Therefore, the determination of signals at time points after the peak value is affected, and symbols that were originally determined to be low level may be determined to be high level.

[0107] In digital integrated circuits, binary digital signals "1" and "0" are typically used to implement their functions. Comparators are used to determine whether an input signal is a digital signal "1" or "0". When the level of the input signal is greater than the reference signal, the input signal is determined to be a digital signal "1" (i.e., a high-level signal); when the level of the input signal is less than the reference signal, the input signal is determined to be a digital signal "0" (i.e., a low-level signal). Therefore, if the input signal at the previous time point is a digital signal "1", its high level will raise the actual input signal level at the next time point above the expected level. If the input signal at the next time point is a digital signal "0", meaning the expected level is low, the actual level may be raised above the reference signal, thus being determined to be a digital signal "1", causing signal distortion. Similarly, when the input signal at the previous time node is a digital signal "0", because it is at a low level, it will reduce the level of the actual input signal at the next time node to be lower than the expected level. If the input signal at the next time node is a digital signal "1", that is, the expected level is a high level, the actual level may be reduced to less than the reference signal, thus being judged as a digital signal "0", causing signal distortion.

[0108] Figure 4 This is a schematic diagram of the structure of a comparator provided in an embodiment of this application, as shown below. Figure 4 As shown, comparator 40 includes: a first-stage circuit 401, a second-stage circuit 402, a first-switching circuit 403, and a second-switching circuit 404; the first-stage circuit 401 includes: a first-input circuit 405 and a second-input circuit 406.

[0109] The first input circuit 405 is connected to the first switch circuit 403; the second input circuit 406 is connected to the second switch circuit 404; both the first input circuit 405 and the second input circuit 406 are also connected to the second-stage circuit 402. The first switch circuit 403 and the second switch circuit 404 are also respectively connected to the ground terminal GND or the power supply terminal V. DD The first input circuit 405 and the second input circuit 406 are also respectively connected to the ground terminal GND or the power supply terminal V. DD The second-stage circuit 402 is connected to the power supply terminal V. DD Or grounding terminal GND.

[0110] It should be noted that the connection between the ground or power supply terminals of the first switching circuit 403, the second switching circuit 404, the first input circuit 405, the second input circuit 406, and the second stage circuit 402 will vary depending on the electronic components used in the comparator 40. When the comparator 40 uses one type of electronic component scheme, the first switching circuit 403, the second switching circuit 404, the first input circuit 405, and the second input circuit 406 are connected to the ground terminal, and the second stage circuit 402 is connected to the power supply terminal. When the comparator 40 uses another type of electronic component scheme, the first switching circuit 403, the second switching circuit 404, the first input circuit 405, and the second input circuit 406 are connected to the power supply terminal, and the second stage circuit 402 is connected to the ground terminal. No restrictions are imposed here.

[0111] In this embodiment of the application, the first switching circuit 403 receives the first feedback signal F. i-1 Second feedback signal F i-1 B and clock signal WCK, used according to the first feedback signal F i-1 Second feedback signal F i-1 B and the clock signal WCK control the conduction of the first input circuit 405; wherein, the first feedback signal F i-1 Second feedback signal F i-1 B are opposite signals.

[0112] The second switching circuit 404 receives the first feedback signal F. i-1 Second feedback signal F i-1 B and clock signal WCK, used according to the first feedback signal F i-1 Second feedback signal F i-1 B and the clock signal WCK control the conduction of the second input circuit 406;

[0113] The first input circuit 405 receives the input signal DQ and the first reference signal V. REF _1 is used during the sampling phase when the signal is turned on, based on the input signal DQ and the first reference signal V. REF _1 Generates the first differential signal and transmits it to the second-stage circuit 402 through connection points A and B;

[0114] The second input circuit 406 receives the input signal DQ and the second reference signal V. REF _2, used during the sampling phase when the circuit is on, based on the input signal DQ and the second reference signal V. REF _2 Generates a second differential signal and transmits it to the second-stage circuit 402 through connection points A and B;

[0115] The second-stage circuit 402 receives the first differential signal or the second differential signal through connection points A and B, and amplifies and latches the first differential signal or the second differential signal during the regeneration stage to output a comparison signal; wherein, the comparison signal includes the first comparison sub-signal F. i Second comparator signal F i B, F i and F i B are opposite signals.

[0116] In this embodiment, the comparator 40 uses two different reference signals, namely the first reference signal VREF_1 and the second reference signal VREF_2. Wherein, V REF _1 is greater than or less than V REF _2, correspondingly, the comparator 40 provided in this application embodiment can adopt two circuit schemes. Meanwhile, V REF Both VREF_1 and VREF_2 are less than the high level of the input signal DQ and greater than the low level of the input signal DQ. The specific voltages of the two reference signals VREF_1 and VREF_2 can be set according to actual needs and are not limited here.

[0117] The comparator 40 uses V REF _1 is greater than V REF Taking the circuit scheme corresponding to _2 as an example, when DQ is high at the previous time node, during the DQ sampling phase of the current time node, the first switch circuit 403 controls the first input circuit 405 to conduct, and the second switch circuit 404 controls the second input circuit 406 to turn off, using V REF _1 is compared with DQ; furthermore, if DQ is low at the current time point, since V REF _1 is relatively high; even after the DQ is boosted at the current time point, it will still not exceed V. REF _1 can still be determined as a digital signal "0", and the signal is not distorted; if DQ is high at the current time point, because V REF _1 is less than the high level of DQ, and DQ at the current time point is still greater than V after being pulled up. REF _1 can still be identified as the digital signal "1", and the signal is not distorted. Similarly, when DQ is low at the previous time node, during the DQ sampling phase of the current time node, the second switch circuit 404 controls the second input circuit 406 to conduct, and the first switch circuit 403 controls the first input circuit 405 to turn off, using V REF _2 is compared with the DQ at the current time point; furthermore, if the DQ at the current time point is high, since V REF _2 is relatively low, and the DQ at the current time point will still not be less than V even after being reduced. REF_2, at the current time point, DQ is still determined to be a digital signal "1", and the signal is not distorted; if DQ at the current time point is low, because V REF _2 is greater than the low level of DQ, and DQ at the current time point is still less than V after being lowered. REF _2 is still judged as the digital signal "0", and the signal is not distorted.

[0118] Correspondingly, if comparator 40 uses V REF _1 is less than V REF In the circuit scheme of _2, when the DQ of the previous time node is high, during the DQ sampling phase of the current time node, the second switch circuit 404 controls the second input circuit 406 to conduct, and the first switch circuit 403 controls the first input circuit 405 to turn off. VREF_2 is used for comparison with the DQ of the current time node. When the DQ of the previous time node is low, during the DQ sampling phase of the current time node, the first switch circuit 403 controls the first input circuit 405 to conduct, and the second switch circuit 404 controls the second input circuit 406 to turn off. The first reference signal VREF_1 is used for comparison with the DQ of the current time node. This ensures that the DQ of the current time node is not distorted.

[0119] It is understood that the comparator 40 used in this embodiment can use a more suitable reference signal to compare with the input signal at the current time point based on the input signal at the previous time point, thereby eliminating the problem caused by inter-symbol interference and ensuring that the comparison result is not affected by inter-symbol interference, thus guaranteeing that the input signal is not distorted. At the same time, the first switching circuit 403 and the second switching circuit 404 are respectively connected to the control terminals of the first input circuit 405 and the second input circuit 406, which does not affect the direct connection of the first input circuit 405 and the second input circuit 406 to the ground terminal or the power supply terminal, respectively. Therefore, a smaller number of transistors can be used in the main circuit path of the comparator 40, thereby reducing the total operating voltage while keeping the voltage division of each transistor unchanged.

[0120] In some embodiments of this application, such as Figure 5 As shown, the first-stage circuit 401 also includes a first reset circuit 407.

[0121] The first input circuit 405 and the second input circuit 406 are connected through a first reset circuit 407; the first reset circuit 407 is also connected to the power supply terminal V. DD Or ground terminal GND. Among them, the first reset circuit 407 receives the clock signal WCK and is used to reset the first input circuit 405 and the second input circuit 406 during the reset phase according to the clock signal WCK.

[0122] In this embodiment of the application, triggered by the clock signal WCK, the first reset circuit 407 can connect the connection point C of the first input circuit 405 and the connection point D of the second input circuit 406 to the power supply terminal V respectively. DD The circuit is turned on, thereby pulling the voltage at connection points C and D to a high level to reset the first input circuit 405 and the second input circuit 406. Alternatively, triggered by the clock signal WCK, the first reset circuit 407 can connect connection points C of the first input circuit 405 and D of the second input circuit 406 to the ground terminal GND, thereby lowering the voltage at connection points C and D to a low level to reset the first input circuit 405 and the second input circuit 406.

[0123] It should be noted that the power supply terminal or ground terminal connected to the first reset circuit 407 may vary depending on the electronic components used in the comparator 40. When the comparator 40 uses one type of electronic component scheme, the first reset circuit 407 is connected to the power supply terminal; when the comparator 40 uses another type of electronic component scheme, the first reset circuit 407 is connected to the ground terminal. There is no restriction on this.

[0124] It is understandable that using the first reset circuit 407 to reset the local circuit of the comparator 40 can enable the comparator 40 to complete the reset stage more quickly and improve the operating speed of the comparator 40.

[0125] In some embodiments of this application, such as Figure 5 As shown, the second-stage circuit 402 includes: an output circuit 408 and a second reset circuit 409.

[0126] The second reset circuit 409 is connected to the output circuit 408; the output circuit 408 is also connected to the power supply terminal V. DD Or ground terminal GND; the second reset circuit 409 is also connected to the power supply terminal V. DD Or ground terminal GND. The output circuit 408 is used to amplify and latch the first differential signal or the second differential signal during the regeneration stage to output a comparison signal F. i and F i B. The second reset circuit 409 receives the clock signal WCK and is used to reset the output circuit 408 during the reset phase according to the clock signal WCK.

[0127] It should be noted that the connection between the output circuit 408 and the second reset circuit 409 to the power supply or ground terminal may vary depending on the electronic components used in the comparator 40. When the comparator 40 uses one type of electronic component, both the output circuit 408 and the second reset circuit 409 are connected to the power supply terminal; when the comparator 40 uses another type of electronic component, both the output circuit 408 and the second reset circuit 409 are connected to the ground terminal, and no restriction is imposed here.

[0128] In this embodiment, triggered by the clock signal WCK, the second reset circuit 409 can connect connection points A and B of the output circuit 408 to the power supply terminal V respectively. DD The circuit is turned on, thereby pulling the voltage at connection points A and B to a high level to reset the output circuit 408. Alternatively, triggered by the clock signal WCK, the second reset circuit 409 can connect connection points A and B of the output circuit 408 to the ground terminal GND, thereby lowering the voltage at connection points A and B to a low level to reset the output circuit 408.

[0129] It is understandable that using the second reset circuit 409 to reset the partial circuit of the comparator 40 can enable the comparator 40 to complete the reset stage more quickly and improve the operating speed of the comparator 40.

[0130] In some embodiments of this application, such as Figure 6 As shown, the first switch circuit 403 includes a first turn-on circuit 4031 and a first turn-off circuit 4032.

[0131] Both the first turn-on circuit 4031 and the first turn-off circuit 4032 are connected to the control terminal E of the first input circuit 405; the first turn-off circuit 4032 is also connected to the ground terminal GND or the power supply terminal V. DD The first activation circuit 4031 receives the first feedback signal F. i-1 and clock signal WCK, used in the first feedback signal F i-1 Under the control of [the circuit], the clock signal WCK is turned on to the control terminal E of the first input circuit 405. The first shutdown circuit 4032 receives the second feedback signal F. i-1 B, used in the second feedback signal F i-1 Under the control of B, the control terminal E of the first input circuit 405 is turned on to the ground terminal GND or the power supply terminal V. DD This causes the first input circuit 405 to turn off. The first feedback signal F i-1 Second feedback signal F i-1 B are opposite signals.

[0132] It should be noted that the connection between the ground terminal and the power supply terminal of the first shutdown circuit 4032 may vary depending on the electronic components used in the comparator 40. When the comparator 40 uses one type of electronic component scheme, the first shutdown circuit 4032 is connected to the ground terminal; when the comparator 40 uses another type of electronic component scheme, the first shutdown circuit 4032 is connected to the power supply terminal. No restriction is imposed here.

[0133] In this embodiment of the application, the first feedback signal F i-1 Second feedback signal F i-1 B are inverse signals. When the first feedback signal F... i-1 When the first activation circuit 4031 is triggered, the second feedback signal F i-1 B triggers the first shutdown circuit 4032 to stop working; at this time, the clock signal WCK is turned on by the first enable circuit 4031 to the control terminal E of the first input circuit 405, which is used to control the first input circuit 405 to work during the sampling phase of the comparator 40. When the first feedback signal F i-1 When the first activation circuit 4031 is not working, the second feedback signal F i-1 B triggers the first shutdown circuit 4032 to operate; at this time, the control terminal E of the first input circuit 405 is turned on to the ground terminal GND or the power supply terminal V. DD If the first input circuit 405 is turned off, it will not work during the sampling phase of comparator 40.

[0134] In some embodiments of this application, such as Figure 6 As shown, the second switch circuit 404 includes: a second turn-on circuit 4041 and a second turn-off circuit 4042.

[0135] Both the second opening circuit 4041 and the second closing circuit 4042 are connected to the control terminal F of the second input circuit 406; the second closing circuit 4042 is also connected to the ground terminal GND or the power supply terminal V. DD The second activation circuit 4041 receives the second feedback signal F. i-1 B and clock signal WCK are used in the second feedback signal F i-1 Under the control of B, the clock signal WCK is turned on to the control terminal F of the second input circuit 406. The second shutdown circuit 4042 receives the first feedback signal F. i-1 Used in the first feedback signal F i-1 Under the control of [the circuit], the control terminal F of the second input circuit 406 is turned on to the ground terminal GND or the power supply terminal V. DD This causes the second input circuit 406 to turn off. First feedback signal F i-1 Second feedback signal F i-1 B are opposite signals.

[0136] It should be noted that the connection between the ground terminal and the power supply terminal of the second shutdown circuit 4042 may vary depending on the electronic components used in the comparator 40. When the comparator 40 uses one type of electronic component, the second shutdown circuit 4042 is connected to the ground terminal; when the comparator 40 uses another type of electronic component, the second shutdown circuit 4042 is connected to the power supply terminal. There is no restriction on this.

[0137] In this embodiment of the application, the first feedback signal F i-1 Second feedback signal F i-1 B are inverse signals. When the second feedback signal F... i-1 When B triggers the second activation circuit 4041 to operate, the first feedback signal F i-1 The second shutdown circuit 4042 is deactivated; at this time, the clock signal WCK is turned on by the second startup circuit 4041 to the control terminal F of the second input circuit 406, which is used to control the second input circuit 406 to operate during the sampling phase of the comparator 40. When the second feedback signal F... i-1 When B triggers the second activation circuit 4041 to malfunction, the first feedback signal F i-1 This triggers the second shutdown circuit 4042 to operate; at this time, the control terminal F of the second input circuit 406 is turned on to the ground terminal GND or the power supply terminal V. DD If the second input circuit 406 is turned off, it will not operate during the sampling phase of comparator 40.

[0138] In some embodiments of this application, the first turn-on circuit includes a first switching transistor; the first turn-off circuit includes a second switching transistor.

[0139] The second terminal of the first switching transistor and the first terminal of the second switching transistor are both connected to the control terminal of the first input circuit; the second terminal of the second switching transistor is also connected to a ground terminal or a power supply terminal. The first and second switching transistors are NMOS or PMOS. The control terminal of the first switching transistor receives a first feedback signal; the first terminal of the first switching transistor receives a clock signal; and the control terminal of the second switching transistor receives a second feedback signal.

[0140] In this embodiment, whether the first switching transistor and the second switching transistor are NMOS or PMOS is determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0141] like Figure 7As shown, comparator 70 includes a first enable circuit 7031 and a first disable circuit 7032; the first enable circuit 7031 includes a first switching transistor MN0, and the first disable circuit 7032 includes a second switching transistor MN1. MN0 and MN1 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The source of MN0 and the drain of MN1 are both connected to the control terminal E of the first input circuit 705; the source of MN1 is also connected to ground. The gate of MN0 receives the first feedback signal F. i-1 The drain of MN0 receives the clock signal WCK_i; the gate of MN1 receives the second feedback signal F. i-1 B; F i-1 and F i-1 B are inverse signals. During operation, when F... i-1 When the signal is high, MN0 is turned on, and at this time, F i-1 When B is low, MN1 is turned off, and WCK_i is turned on through MN0 to the control terminal E of the first input circuit 705. The first input circuit 705 is controlled by the clock signal WCK_i; when F i-1 When the signal is low, MN0 is in the off state, at which time F i-1 When B is high, MN1 is turned on, and thus, the control terminal E of the first input circuit 705 is connected to the ground terminal through MN1, and the first input circuit 705 is turned off.

[0142] like Figure 8 As shown, comparator 80 includes a first enable circuit 8031 ​​and a first disable circuit 8032; the first enable circuit 8031 ​​includes a first switching transistor MP0, and the first disable circuit 8032 includes a second switching transistor MP1. MP0 and MP1 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The source of MP0 and the drain of MP1 are both connected to the control terminal E of the first input circuit 805; the source of MP1 is also connected to the ground terminal. The gate of MP0 receives the first feedback signal F. i-1 The drain of MP0 receives the clock signal WCK_iB; the gate of MP1 receives the second feedback signal F. i-1 B; F i-1 and F i-1 B are inverse signals. During operation, when F... i-1 When the signal is low, MP0 is in the ON state, and at this time, F i-1 When B is high, MP1 is in the off state, thus WCK_iB is turned on through MP0 to the control terminal E of the first input circuit 805, and the first input circuit 805 is controlled by WCK_iB; when F i-1When the signal is high, MP0 is in the off state, and at this time, F i-1 When B is low, MP1 is turned on, and thus, the control terminal E of the first input circuit 805 is connected to the power supply terminal through MP1, and the first input circuit 805 is turned off.

[0143] In some embodiments of this application, the second turn-on circuit includes a third switching transistor; the second turn-off circuit includes a fourth switching transistor.

[0144] The second terminal of the third switching transistor and the first terminal of the fourth switching transistor are both connected to the control terminal of the second input circuit; the second terminal of the fourth switching transistor is also connected to the ground terminal or the power supply terminal. The third and fourth switching transistors are NMOS or PMOS. The control terminal of the third switching transistor receives the second feedback signal; the first terminal of the third switching transistor receives the clock signal; and the control terminal of the fourth switching transistor receives the first feedback signal.

[0145] In this embodiment, whether the third and fourth switching transistors are NMOS or PMOS is determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0146] like Figure 7 As shown, comparator 70 includes a second enable circuit 7041 and a second disable circuit 7042. The second enable circuit 7041 includes a third switching transistor MN2, and the second disable circuit 7042 includes a fourth switching transistor MN3. MN2 and MN3 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The source of MN2 and the drain of MN3 are both connected to the control terminal F of the second input circuit 706; the source of MN3 is also connected to ground. The gate of MN2 receives the second feedback signal F. i-1 B; The drain of MN2 receives the clock signal WCK_i; The gate of MN3 receives the first feedback signal F. i-1 ;F i-1 and F i-1 B are inverse signals. During operation, when F... i-1 When the signal is high, MN3 is turned on, and at this time, F i-1 When B is low, MN2 is in the off state, thus the control terminal F of the second input circuit 706 is connected to the ground terminal through MN3, and the second input circuit 706 is turned off; when F i-1 When the signal is low, MN3 is in the off state, at which time F i-1When B is high, MN2 is turned on, and WCK_i is turned on through MN2 to the control terminal F of the second input circuit 706. The second input circuit 706 is then controlled by WCK_i.

[0147] like Figure 8 As shown, comparator 80 includes a second enable circuit 8041 and a second disable circuit 8042; the second enable circuit 8041 includes a third switching transistor MP2, and the second disable circuit 8042 includes a fourth switching transistor MP3. MP2 and MP3 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The source of MP2 and the drain of MP3 are both connected to the control terminal F of the second input circuit 806; the source of MP3 is also connected to the ground terminal. The gate of MP2 receives the second feedback signal F. i-1 B; MP2's drain receives the clock signal WCK_iB; MP3's gate receives the first feedback signal F. i-1 ;F i-1 and F i-1 B are inverse signals. During operation, when the first feedback signal F... i-1 When the signal is low, the fourth switching transistor MP3 is turned on. At this time, F i-1 When B is high, MP2 is in the off state, thus the control terminal F of the second input circuit 806 is connected to the power supply terminal through MP3, and the second input circuit 806 is turned off; when F... i-1 When the signal is high, MP3 is in the off state. At this time, F i-1 When B is low, MP2 is turned on, and WCK_iB is turned on through MP2 to the control terminal F of the second input circuit 806. The second input circuit 806 is then controlled by WCK_iB.

[0148] In some embodiments of this application, the first input circuit includes: a first input transistor, a second input transistor, and a third input transistor;

[0149] The first terminals of the first and second input transistors are respectively connected to the second-stage circuit; the control terminal of the third input transistor serves as the control terminal of the first input circuit; the second terminal of the third input transistor is connected to the ground terminal or the power supply terminal; the second terminals of both the first and second input transistors are connected to the first terminal of the third input transistor. The first to third input transistors are NMOS or PMOS transistors. The control terminal of the first input transistor receives the input signal; the control terminal of the second input transistor receives the first reference signal; when the third input transistor is triggered by a clock signal and enters the conducting state, the first and second input transistors generate a first differential signal based on the input signal and the first reference signal, and input the first differential signal to the second-stage circuit.

[0150] In this embodiment, whether the first input transistor, the second input transistor, and the third input transistor are NMOS or PMOS is determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0151] like Figure 7 As shown, comparator 70 includes a first input circuit 705; the first input circuit 705 includes a first input transistor MN4, a second input transistor MN5, and a third input transistor MN6. MN4, MN5, and MN6 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The drain of MN4 is connected to the second-stage circuit 702 at connection point A, and the drain of MN5 is connected to the second-stage circuit 702 at connection point B; the gate of MN6 serves as the control terminal of the first input circuit 705; the source of MN6 is connected to ground; the sources of MN4 and MN5 are both connected to the drain of MN6. The gate of MN4 receives the input signal DQ; the gate of MN5 receives the first reference signal V. REF _P. In the running state, when the first feedback signal F i-1 When the clock signal WCK_i is high, the clock signal WCK_i is turned on to the gate of MN6. In this case, when the clock signal WCK_i changes to high, i.e., when comparator 70 enters the sampling phase, MN6 is triggered to conduct by WCK_i, the first input circuit 705 is turned on, and then MN4 and MN5, based on the received DQ and V... REF _P generates the first differential signal, and inputs the first differential signal into the second stage circuit 702 through connection points A and B.

[0152] like Figure 8 As shown, comparator 80 includes a first input circuit 805; the first input circuit 805 includes a first input transistor MP4, a second input transistor MP5, and a third input transistor MP6. MP4, MP5, and MP6 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The drain of MP4 is connected to the second-stage circuit 802 at connection point A, and the drain of MP5 is connected to the second-stage circuit 802 at connection point B; the gate of MP6 serves as the control terminal of the first input circuit 805; the source of MP6 is connected to the power supply terminal; the sources of MP4 and MP5 are both connected to the drain of MP6. The gate of MP4 receives the input signal DQ; the gate of MP5 receives the first reference signal V. REF _N. In the running state, when the first feedback signal F i-1When the clock signal WCK_iB is low, the clock signal WCK_iB is turned on to the gate of MP6. In this case, when the clock signal WCK_iB changes to low, i.e., when comparator 80 enters the sampling phase, MP6 is triggered into the conducting state by WCK_iB, the first input circuit 805 is turned on, and then MP4 and MP5, based on the received DQ and V... REF _N generates the first differential signal, and inputs the first differential signal into the second stage circuit 802 through connection points A and B.

[0153] It should be noted that V REF _P and V REF _N is used to represent the magnitude relationship between two reference signals: V REF _P greater than V REF _N. In Figure 7 In the comparator 70 shown, since the first reference signal is greater than the second reference signal, the first reference signal uses V. REF _P, the second reference signal uses V REF _N. In Figure 8 In the comparator 80 shown, since the first reference signal is less than the second reference signal, the first reference signal uses V. REF _N, the second reference signal uses V REF _P.

[0154] In some embodiments of this application, the second input circuit includes: a fourth input transistor, a fifth input transistor, and a sixth input transistor;

[0155] The first terminals of the fourth and fifth input transistors are respectively connected to the second-stage circuit; the control terminal of the sixth input transistor serves as the control terminal of the second input circuit; the second terminal of the sixth input transistor is connected to ground or power supply; the second terminals of the fourth and fifth input transistors are both connected to the first terminal of the sixth input transistor. The fourth to sixth input transistors are either NMOS or PMOS. The control terminal of the fourth input transistor receives the input signal; the control terminal of the fifth input transistor receives the second reference signal. When the sixth input transistor is triggered by a clock signal and enters the conducting state, the fourth and fifth input transistors generate a second differential signal based on the input signal and the second reference signal, and input this second differential signal to the second-stage circuit.

[0156] In this embodiment, whether the fourth, fifth, and sixth input transistors are NMOS or PMOS is determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0157] like Figure 7 As shown, comparator 70 includes a second input circuit 706; the second input circuit 706 includes a fourth input transistor MN7, a fifth input transistor MN8, and a sixth input transistor MN9. MN7, MN8, and MN9 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The drain of MN7 is connected to the second-stage circuit 702 at connection point A, and the drain of MN8 is connected to the second-stage circuit 702 at connection point B; the gate of MN9 serves as the control terminal of the second input circuit 706; the source of MN9 is connected to ground; the sources of MN7 and MN8 are both connected to the drain of MN9. The gate of MN7 receives the input signal DQ; the gate of MN8 receives the second reference signal V. REF _N. In the running state, when the first feedback signal F i-1 When the clock signal WCK_i is low, the clock signal WCK_i is turned on to the gate of MN9. In this case, when the clock signal WCK_i changes to high, i.e., when comparator 70 enters the sampling phase, MN9 is triggered to conduct by WCK_i, the second input circuit 706 is turned on, and then MN7 and MN8, based on the received DQ and V... REF _N generates a second differential signal, which is then input to the second-stage circuit 702 via connection points A and B.

[0158] like Figure 8 As shown, comparator 80 includes a second input circuit 806; the second input circuit 806 includes a fourth input transistor MP7, a fifth input transistor MP8, and a sixth input transistor MP9. MP7, MP8, and MP9 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The drain of MP7 is connected to the second-stage circuit 802 at connection point A, and the drain of MP8 is connected to the second-stage circuit 802 at connection point B; the gate of MP9 serves as the control terminal of the second input circuit 806; the source of MP9 is connected to the power supply terminal; the sources of MP7 and MP8 are both connected to the drain of MP9. The gate of MP7 receives the input signal DQ; the gate of MP8 receives the second reference signal V. REF In operation, when the first feedback signal Fi-1 is high, the clock signal WCK_iB is turned on to the gate of MP9. In this case, when the clock signal WCK_iB changes to low, i.e., when comparator 80 enters the sampling phase, MP9 is triggered to conduct by WCK_iB, the second input circuit 806 is turned on, and then MP7 and MP8, based on the received DQ and V... REF_P generates a second differential signal, which is then input to the second-stage circuit 802 via connection points A and B.

[0159] It should be noted that V REF _P and V REF _N is used to represent the magnitude relationship between two reference signals: V REF _P greater than V REF _N. In Figure 7 In the comparator 70 shown, since the first reference signal is greater than the second reference signal, the first reference signal uses V. REF _P, the second reference signal uses V REF _N. In Figure 8 In the comparator 80 shown, since the first reference signal is less than the second reference signal, the first reference signal uses V. REF _N, the second reference signal uses V REF _P.

[0160] In some embodiments of this application, the first reset circuit includes: a first reset transistor and a second reset transistor.

[0161] The first terminal of both the first and second reset transistors are connected to either a power supply terminal or a ground terminal. The second terminal of the first reset transistor is connected to the first input circuit, and the second terminal of the second reset transistor is connected to the second input circuit. Both the first and second reset transistors are PMOS or NMOS transistors. The control terminals of both transistors receive a clock signal. When the clock signal triggers both transistors to conduct, the first input circuit is reset by connecting to either the power supply terminal or a ground terminal through the first reset transistor, and the second input circuit is also reset by connecting to either the power supply terminal or a ground terminal through the second reset transistor.

[0162] In this embodiment, whether the first reset transistor and the second reset transistor are PMOS or NMOS is determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0163] like Figure 7As shown, comparator 70 includes a first reset circuit 707; the first reset circuit 707 includes a first reset transistor MP5 and a second reset transistor MP6. MP5 and MP6 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its source is the first terminal, and its drain is the second terminal. The sources of MP5 and MP6 are both connected to the power supply terminal; the drain of MP5 is connected to the first input circuit 705; the drain of MP6 is connected to the second input circuit 706. The gates of MP5 and MP6 both receive the clock signal WCK_i. In the operating state, when the clock signal WCK_i changes to a low level, that is, when comparator 70 enters the reset stage, MP5 and MP6 are triggered to conduct by WCK_i; the first input circuit 705 and the second input circuit 706 are connected to the power supply terminal through MP5 and MP6 respectively, and the voltage at their respective connection points is pulled up to a high level because they are connected to the power supply terminal, thereby completing the reset of the first input circuit 705 and the second input circuit 706.

[0164] like Figure 8 As shown, comparator 80 includes a first reset circuit 807; the first reset circuit 807 includes a first reset transistor MN5 and a second reset transistor MN6. MN5 and MN6 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. The drains of MN5 and MN6 are both connected to ground; the source of MN5 is connected to the first input circuit 805; the source of MN6 is connected to the second input circuit 806. The gates of MN5 and MN6 both receive the clock signal WCK_iB. In operation, when the clock signal WCK_iB goes high, i.e., when comparator 80 enters the reset phase, MN5 and MN6 are triggered to conduct by WCK_iB; the first input circuit 805 and the second input circuit 806 are connected to ground through MN5 and MN6 respectively, and the voltage at their respective connection points is reduced to a low level due to being connected to ground, thereby completing the reset of the first input circuit 805 and the second input circuit 806.

[0165] In some embodiments of this application, the second reset circuit includes a third reset transistor and a fourth reset transistor.

[0166] The first terminals of both the third and fourth reset transistors are connected to either the power supply or ground. The second terminals of both transistors are connected to the output circuit. Both the third and fourth reset transistors are PMOS or NMOS transistors. The control terminals of both transistors receive a clock signal. When the clock signal triggers both transistors to conduct, the output circuit is reset by connecting them to either the power supply or ground.

[0167] In this embodiment, whether the third and fourth reset transistors are PMOS or NMOS is determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0168] like Figure 7 As shown, comparator 70 includes a second reset circuit 709; the second reset circuit 709 includes a third reset transistor MP7 and a fourth reset transistor MP8. MP7 and MP8 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its source is the first terminal, and its drain is the second terminal. The sources of MP7 and MP8 are both connected to the power supply terminal; the drain of MP7 is connected to the output circuit through connection point A, and the drain of MP8 is connected to the output circuit through connection point B. The gates of MP7 and MP8 both receive the clock signal WCK_i. In the operating state, when the clock signal WCK_i changes to a low level, that is, when comparator 70 enters the reset stage, MP7 and MP8 are triggered to conduct by WCK_i; the output circuit 708 is connected to the power supply terminal through connection points A and B respectively. The voltages at connection points A and B are pulled up to a high level because they are connected to the power supply terminal, thereby completing the reset of the output circuit 708.

[0169] like Figure 8 As shown, comparator 80 includes a second reset circuit 809; the second reset circuit 809 includes a third reset transistor MN7 and a fourth reset transistor MN8. MN7 and MN8 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its source is the first terminal, and its drain is the second terminal. The sources of MN7 and MN8 are both connected to ground; the drain of MN7 is connected to the output circuit through connection point A, and the drain of MN8 is connected to the output circuit through connection point B. The gates of MN7 and MN8 both receive the clock signal WCK_iB. In operation, when the clock signal WCK_iB changes to a high level, that is, when comparator 80 enters the reset phase, MN7 and MN8 are triggered to conduct by WCK_iB; the output circuit 808 is connected to ground through connection points A and B respectively, and the voltages at connection points A and B are reduced to a low level due to being connected to ground, thereby completing the reset of the output circuit 808.

[0170] In some embodiments of this application, the output circuit includes: a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, and a sixth output transistor.

[0171] The control terminals of the first, second, third, fourth, and sixth output transistors are all connected to the first output terminal of the output circuit. The control terminals of the first, second, third, and fourth output transistors, and the second terminal of the fifth output transistor are all connected to the second output terminal of the output circuit. The second terminals of the first and second output transistors are respectively connected to the first input circuit, the second input circuit, and the second reset circuit. The first terminals of the third, fourth, fifth, and sixth output transistors are all connected to the power supply terminal or the ground terminal. The first and second output transistors are NMOS or PMOS; the third to sixth output transistors are PMOS or NMOS. The control terminals of the fifth and sixth output transistors both receive clock signals.

[0172] In this embodiment, whether the first and second output transistors are NMOS or PMOS, and whether the third to sixth output transistors are PMOS or NMOS, are all determined by the circuit structure of the comparator. Figure 7 and Figure 8 Two different circuit structures of the comparator provided in the embodiments of this application are shown below. Figure 7 and Figure 8 Explain each separately.

[0173] like Figure 7 As shown, comparator 70 includes an output circuit 708; the output circuit 708 includes: a first output transistor MN10, a second output transistor MN11, a third output transistor MP1, a fourth output transistor MP2, a fifth output transistor MP3, and a sixth output transistor MP4. MN10 and MN11 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. MP1, MP2, MP3, and MP4 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its source is the first terminal, and its drain is the second terminal. The gate of MN10, the drain of MN11, the gate of MP1, the drain of MP2, and the drain of MP4 are all connected to the first output terminal of the output circuit 708, and the first output terminal of the output circuit 708 outputs the F signal in the comparison signal. i The drain of MN10, the gate of MN11, the drain of MP1, the gate of MP2, and the drain of MP3 are all connected to the second output terminal of the output circuit 708. The second output terminal of the output circuit 708 outputs the F signal in the comparison signal. i B signal, F i B is F iThe inverted signal. The source of MN10 is connected to the first input circuit 705, the second input circuit 706, and the second reset circuit 709 via connection point A; the source of MN11 is connected to the first input circuit 705, the second input circuit 706, and the second reset circuit 709 via connection point B. The sources of MP1, MP2, MP3, and MP4 are all connected to the power supply. The gates of MP3 and MP4 both receive the clock signal WCK_i.

[0174] When the clock signal WCK_i is low, i.e., during the reset phase of comparator 70, MP3 and MP4 are triggered by WCK_i and kept in the on state. At this time, the voltages of the first and second output terminals remain at a high level. When the clock signal WCK_i changes to a high level, i.e., when the sampling phase of comparator 70 begins, MP3 and MP4 are triggered by WCK_i and changed to the off state. At this time, the voltages of the first and second output terminals, which are affected by the first or second differential signal received by the output circuit 708, gradually decrease to a low level until MP1 and MP2 are triggered to change to the on state. Then, the sampling phase of comparator 70 ends and the regeneration phase begins. At the start of the regeneration phase of comparator 70, the cross-coupled inverter composed of MP1 and MP2 amplifies the voltage difference formed between the first and second output terminals during the sampling phase through positive feedback. When the voltage difference is amplified sufficiently, the output circuit 708 latches the voltages of the first and second output terminals and outputs the latched level as a comparison signal, i.e., output F. i and F i B.

[0175] like Figure 8 As shown, comparator 80 includes an output circuit 808; the output circuit 808 includes: a first output transistor MP10, a second output transistor MP11, a third output transistor MN1, a fourth output transistor MN2, a fifth output transistor MN3, and a sixth output transistor MN4. MP10 and MP11 are PMOS transistors; the gate of the PMOS transistor is the control terminal, its drain is the first terminal, and its source is the second terminal. MN1, MN2, MN3, and MN4 are NMOS transistors; the gate of the NMOS transistor is the control terminal, its source is the first terminal, and its drain is the second terminal. The gate of MP10, the drain of MP11, the gate of MN1, the drain of MN2, and the drain of MN4 are all connected to the first output terminal of the output circuit 808, and the first output terminal of the output circuit 808 outputs the F signal in the comparison signal. i The drain of MP10, the gate of MP11, the drain of MN1, the gate of MN2, and the drain of MN3 are all connected to the second output terminal of the output circuit 808. The second output terminal of the output circuit 808 outputs the F signal in the comparison signal.i B signal, F i B is F i The inverted signal is given. The source of MP10 is connected to the first input circuit 805, the second input circuit 806, and the second reset circuit 809 via connection point A; the source of MP11 is connected to the first input circuit 805, the second input circuit 806, and the second reset circuit 809 via connection point B. The sources of MN1, MN2, MN3, and MN4 are all connected to ground. The gates of MN3 and MN4 both receive the clock signal WCK_iB.

[0176] When the clock signal WCK_iB is high, i.e., during the reset phase of comparator 80, MN3 and MN4 are triggered by WCK_iB and remain in the on state. At this time, the voltages at the first and second output terminals remain at a low level. When the clock signal WCK_iB changes to a low level, i.e., when the sampling phase of comparator 80 begins, MN3 and MN4 are triggered by WCK_iB and change to the off state. At this time, the voltages at the first and second output terminals, influenced by the first or second differential signal received by the output circuit 808, gradually rise to a high level until MN1 and MN2 are triggered to change to the on state. Then, the sampling phase of comparator 80 ends and the regeneration phase begins. At the start of the regeneration phase of comparator 80, the cross-coupled inverter composed of MN1 and MN2 amplifies the voltage difference formed between the first output terminal and the second output terminal during the sampling phase through positive feedback; until the voltage difference is amplified to a sufficient degree, the output circuit 808 latches the voltage of the first output terminal and the second output terminal, and outputs the latched level as a comparison signal, i.e., outputs Fi and FiB.

[0177] Figure 9 This is a schematic diagram of a decision feedback equalization circuit provided in an embodiment of this application, as shown below. Figure 9 As shown, the decision feedback equalization circuit 90 includes N levels of comparators as described in the above embodiment; where N is a positive integer greater than 1.

[0178] The first input terminal of each comparator receives the input signal DQ; the second input terminal of each comparator receives the first reference signal V. REF _1; The third input of each comparator receives the second reference signal V. REF _2.

[0179] The fourth input terminal of the first-stage comparator 901 is connected to the output terminal of the Nth-stage comparator 904, and receives the Nth-stage comparison signal F output by the Nth-stage comparator 904. N / F N B; The fifth input of the first-stage comparator 901 receives the first clock signal WCK_1.

[0180] The fourth input terminal of the i-th stage comparator 903 is connected to the output terminal of the (i-1)-th stage comparator 902, and receives the (i-1)-th stage comparison signal F output by the (i-1)-th stage comparator 902. i-1 / F i-1 B; The fifth input of the i-th stage comparator 903 receives the i-th clock signal WCK_i; where i is greater than 1 and less than or equal to N.

[0181] Each comparator, triggered by its own clock signal, compares the input signal DQ with the first reference signal V according to the comparison signal corresponding to the fourth input terminal of each comparator. REF Compare _1, or compare the input signal DQ with the second reference signal V. REF _2 is compared to output the comparison signal for each stage.

[0182] In this embodiment, each comparator in the decision feedback equalization circuit 90 has five input terminals and one output terminal; the five input terminals of each comparator sequentially receive the input signal DQ and the first reference signal V, respectively. REF 1. Second reference signal V REF _2. The previous stage comparison signal (the first stage comparator receives the Nth stage comparison signal) and the clock signal corresponding to each stage comparator; the output of each stage comparator outputs the comparison signal of each stage.

[0183] In this embodiment, each comparison signal includes two inverted signals. These two inverted signals serve as the first feedback signal and the second feedback signal in the above embodiment, respectively, and are input into the next stage comparator (the first stage comparator receives the Nth stage comparison signal). For example, F i-1 and F i-1 B are inverse signals, F i-1 As the first feedback signal input to the i-th stage comparator, F i-1 B is used as the second feedback signal input to the i-th stage comparator. In this way, based on the output of each stage comparator, the next stage comparator can be controlled to select the first reference signal V during the sampling phase. REF _1 or the second reference signal V REF _2.

[0184] In this embodiment, the phase of the i-th clock signal WCK_i is 360° / N later than the phase of the (i-1)-th clock signal WCK_i-1. That is, the phase of the clock signal corresponding to each comparator stage is later than the previous comparator stage by one-Nth clock cycle. Thus, the phase of the first clock signal WCK_1 is also later than the phase of the Nth clock signal WCK_N by one-Nth clock cycle. Because the comparator's entry into the sampling phase is controlled by the clock signal, the phase delay between the clock signals causes each comparator stage to enter the sampling phase sequentially at each time node. That is, each comparator stage sequentially samples the level of the input signal DQ at each time node within one clock cycle and outputs the comparison signal for each stage. The time nodes are sequentially spaced one-Nth clock cycle apart. In other words, each comparator stage in the decision feedback equalization circuit 90 sequentially samples the symbols of the input signal DQ.

[0185] For example, the (i-1)th stage comparator 902, controlled by the (i-1)th clock signal WCK_i-1, enters the sampling stage at the (i-1)th time node, samples the level of the input signal DQ at the (i-1)th time node, and outputs the (i-1)th stage comparison signal F. i-1 / F i-1 B; then at the i-th time node, which is one N-th clock cycle after the (i-1)-th time node, the i-th stage comparator 903, controlled by the i-th clock signal WCK_i, enters the sampling stage, samples the level of the input signal DQ at the i-th time node, and outputs the i-th stage comparison signal F. i / F i B; and so on. At the Nth time node, the Nth stage comparator 904 is controlled by the Nth clock signal WCK_N to enter the sampling stage, sample the level of the input signal DQ at the Nth time node, and output the Nth stage comparison signal; after the Nth time node, the next clock cycle begins. At the N+1th time node, which is one-Nth clock cycle after the Nth time node, the first stage comparator re-enters the sampling stage to sample the level of the input signal.

[0186] Thus, the comparison signal received by each comparator from the previous stage reflects the level of the input signal DQ at the previous time point. Taking the i-th stage comparator as an example, the i-th stage comparator samples DQ at the i-th time point, and the signal it receives from F... i-1 / F i-1 The B signal reflects the level of DQ at time node i-1. Due to intersymbol interference, the level of DQ at time node i-1 will interfere with the level of DQ at time node i, while the i-th stage comparator can convert the received F signal into a signal that is not directly related to the signal. i-1 / F i-1 Signal B serves as both the first and second feedback signals, according to F i-1 / Fi-1 Signal B selects a suitable reference signal from the two reference signals and compares it with the level of DQ at the i-th time node. Specifically, when the level of DQ at the (i-1)-th time node is high, the reference signal with the higher level is selected for comparison, and when the level of DQ at the (i-1)-th time node is low, the reference signal with the lower level is selected for comparison, thereby eliminating the influence of intersymbol interference.

[0187] It should be noted that when the decision feedback equalization circuit 90 uses the comparator in the above embodiment, it needs to be adjusted accordingly based on the circuit structure of the comparator used. When the decision feedback equalization circuit 90 uses... Figure 7 When the comparator 70 shown is used as the i-th stage comparator, it can convert the first reference signal V. REF _1 is set as a relatively high level reference signal V REF _P, the second reference signal V REF _2 is set as a relatively low level reference signal V REF _N, input clock signal WCK_i; and when the decision feedback equalization circuit 90 adopts Figure 8 When the comparator 80 shown is used as the i-th stage comparator, to achieve the same effect as comparator 70, the first reference signal V needs to be... REF _1 is set as a relatively low level reference signal V REF _N, the second reference signal V REF _2 is set as a relatively high level reference signal V REF _P, and input a clock signal WCK_iB that is inverted by WCK_i. That is to say, Figure 7 The comparator 70 shown is Figure 8 The comparators 80 shown can be equivalently replaced in the decision feedback equalization circuit 90.

[0188] Understandable, Figure 9 The decision feedback equalization circuit 90 shown can use multiple comparators to sample the input signal DQ at various time nodes. When each comparator samples DQ at a time node, it can select a suitable reference signal according to the level of DQ at the previous time node, thereby eliminating the influence of inter-symbol interference and improving the accuracy of the output result.

[0189] In some embodiments of this application, such as Figure 9 As shown, the decision feedback equalization circuit 90 also includes N latches.

[0190] The input of each latch is connected to the output of each comparator stage to receive the comparison signal of each stage; wherein, each latch is used to store the comparison signal of each stage to output the latch signal of each stage.

[0191] In this embodiment, each latch included in the decision feedback equalization circuit 90, upon being triggered, receives a comparison signal for each stage, saves the comparison signal for each stage, and outputs it. For example, the i-th latch 907, upon being triggered, receives the i-th comparison signal F. i / F i B, and F i / F i B saves the data and outputs a latch signal D. i .

[0192] In some embodiments of this application, such as Figure 10 As shown, when N=4, the decision feedback equalization circuit 100 includes four levels of comparators as described in the above embodiment: a first-level comparator 1001, a second-level comparator 1002, a third-level comparator 1003, and a fourth-level comparator 1004.

[0193] The first input terminal of each comparator receives the input signal DQ; the second input terminal of each comparator receives the first reference signal V. REF _1; The third input of each comparator receives the second reference signal V. REF _2.

[0194] The fourth input of the first-stage comparator 1001 is connected to the output of the fourth-stage comparator 1004, and receives the fourth-stage comparison signal F4 / F4B output by the fourth-stage comparator 1004; the fifth input of the first-stage comparator 1001 receives the first clock signal WCK_1.

[0195] The fourth input of the second-stage comparator 1002 is connected to the output of the first-stage comparator 1001, and receives the first-stage comparison signal F1 / F1B output by the first-stage comparator 1001; the fifth input of the second-stage comparator 1002 receives the second clock signal WCK_2.

[0196] The fourth input of the third-stage comparator 1003 is connected to the output of the second-stage comparator 1002, and receives the second-stage comparison signal F2 / F2B output by the second-stage comparator 1002; the fifth input of the third-stage comparator 1003 receives the third clock signal WCK_3.

[0197] The fourth input of the fourth-stage comparator 1004 is connected to the output of the third-stage comparator 1003, and receives the third-stage comparison signal F3 / F3B output by the third-stage comparator 1003; the fifth input of the fourth-stage comparator 1004 receives the fourth clock signal WCK_4.

[0198] Each comparator, triggered by its own clock signal, compares the input signal DQ with the first reference signal V according to the comparison signal corresponding to the fourth input terminal of each comparator.REF Compare _1, or compare the input signal DQ with the second reference signal V. REF _2 is compared to output the comparison signal for each stage.

[0199] In this embodiment, the clock signal corresponding to each comparator stage is 90° (i.e., a quarter clock cycle) later than the previous comparator stage. Therefore, each comparator stage sequentially samples the level of the input signal DQ at each time point within a clock cycle and outputs the corresponding comparison signal, with each time point spaced a quarter clock cycle apart. Each comparator stage selects a suitable reference signal from two reference signals based on the level of DQ at the previous time point and compares it with the level of DQ at the current time point, thereby eliminating the influence of intersymbol interference.

[0200] In some embodiments of this application, such as Figure 10 As shown, the decision feedback equalization circuit 100 also includes four latches: a first latch 1005, a second latch 1006, a third latch 1007, and a fourth latch 1008.

[0201] The input of each latch is connected to the output of each comparator stage to receive the comparison signal of each stage; wherein, each latch is used to store the comparison signal of each stage to output the latch signal of each stage.

[0202] In this embodiment of the application, each latch included in the decision feedback equalization circuit 100, after being triggered, receives each comparison signal, saves each comparison signal and outputs it.

[0203] Figures 11 to 14 A schematic diagram illustrating the effect of the decision feedback equalization circuit (DFE) provided in this application.

[0204] like Figure 11 As shown, without DFE, the voltage at time node 0 causes intersymbol interference to the voltages at time nodes 1 and 2, pulling the low levels of time nodes 1 and 2 high, making it impossible to sample accurate voltages. However, after using DFE at time nodes 1 and 2, the sampled voltages are compensated by DFE and reduced to their original low levels, thus eliminating the influence of intersymbol interference.

[0205] like Figure 12 As shown, after using DFE at time nodes 1-4, the signal is pulled down from the original dashed line portion to the solid line portion, eliminating the intersymbol interference caused by the high level of the previous time node.

[0206] Figure 13 and Figure 14Eye diagrams are shown for both cases with and without DFE (Distributed Front-End Function). An eye diagram is formed by superimposing the waveforms of each scanned symbol. The effects of inter-symbol interference (ISI) and noise can be observed from the eye diagram. The larger the "eye" in the eye diagram and the more upright the eye diagram, the smaller the ISI; conversely, the smaller the eye, the larger the ISI. Without DFE, as shown... Figure 13 As shown, the "eye" in the eye diagram is no longer visible, and each symbol waveform interferes with each other without clear boundaries, resulting in severe inter-symbol interference. This can easily lead to symbol decision errors. However, after using DFE, as... Figure 14 As shown, a clear "eye" is formed in the eye diagram, and the waveforms of each symbol have clear boundaries. The influence of inter-symbol interference is eliminated, thus making the symbol decision more accurate.

[0207] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0208] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0209] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A decision feedback equalization circuit, characterized in that, include: An N-stage comparator; where N is a positive integer greater than 1; Each comparator stage has five inputs and one output, including: The circuit comprises a first-stage circuit, a second-stage circuit, a first-switch circuit, and a second-switch circuit; the first-stage circuit includes a first input circuit and a second input circuit. The first input circuit is connected to the first switching circuit; the second input circuit is connected to the second switching circuit; both the first input circuit and the second input circuit are also connected to the second-stage circuit; wherein... Both the first switching circuit and the second switching circuit have three input terminals and one output terminal. One input terminal serves as the fifth input terminal of the comparator to receive a clock signal, and the other two input terminals serve as the fourth input terminals of the comparator to receive a first feedback signal and a second feedback signal. The circuit is used to control the conduction of the first input circuit or the second input circuit according to the first feedback signal, the second feedback signal and the clock signal. The first input terminal of each comparator receives an input signal; the second input terminal of each comparator receives a first reference signal; and the third input terminal of each comparator receives a second reference signal. The fourth input of the first-stage comparator is directly connected to the output of the Nth-stage comparator to receive the Nth-stage comparison signal output by the Nth-stage comparator, which serves as its first and second feedback signals; the fifth input of the first-stage comparator receives the first clock signal. The fourth input of the i-th stage comparator is directly connected to the output of the (i-1)-th stage comparator to receive the (i-1)-th stage comparison signal output by the (i-1)-th stage comparator, serving as its first and second feedback signals; the fifth input of the i-th stage comparator receives the i-th clock signal; where i is greater than 1 and less than or equal to N; where... Each comparator, triggered by a clock signal, compares the input signal with the first reference signal or with the second reference signal according to the comparison signal corresponding to the fourth input terminal of each comparator, so as to output a comparison signal for each stage.

2. The decision feedback equalization circuit according to claim 1, characterized in that, The first input circuit has three input terminals and two output terminals. One input terminal is electrically connected to the output terminal of the first switching circuit. The other two input terminals are used to receive the input signal and the first reference signal, and are also used to generate a first differential signal based on the input signal and the first reference signal during the sampling phase when the circuit is turned on. The second input circuit has three input terminals and two output terminals. One input terminal is electrically connected to the output terminal of the second switching circuit. The other two input terminals are used to receive the input signal and the second reference signal, and are also used to generate a second differential signal based on the input signal and the second reference signal during the sampling phase when the circuit is turned on. The second-stage circuit has two input terminals and two output terminals. Its input terminals are electrically connected to the output terminals of the first input circuit and the second input circuit, respectively. Its output terminal is the output terminal of the comparator. It is also used to amplify and latch the first differential signal or the second differential signal during the regeneration stage to output a comparison signal.

3. The decision feedback equalization circuit according to claim 2, characterized in that, The first stage circuit also includes: a first reset circuit; The first input circuit and the second input circuit are connected through the first reset circuit; the first reset circuit is also connected to a power supply terminal or a ground terminal; wherein... The first reset circuit is used to reset the first input circuit and the second input circuit during the reset phase.

4. The decision feedback equalization circuit according to claim 2, characterized in that, The first switching circuit includes: a first turning-on circuit and a first turning-off circuit; Both the first enabling circuit and the first disabling circuit are connected to the control terminal of the first input circuit; the first disabling circuit is also connected to a ground terminal or a power supply terminal; wherein... The first enabling circuit is used to turn on the clock signal to the control terminal of the first input circuit under the control of the first feedback signal; The first shutdown circuit is used to connect the control terminal of the first input circuit to the ground terminal or the power supply terminal under the control of the second feedback signal, so as to turn off the first input circuit; the first feedback signal and the second feedback signal are inverse signals of each other.

5. The decision feedback equalization circuit according to claim 4, characterized in that, The second switching circuit includes: a second turning-on circuit and a second turning-off circuit; Both the second power-on circuit and the second power-off circuit are connected to the control terminal of the second input circuit; the second power-off circuit is also connected to the ground terminal or the power supply terminal; wherein... The second turn-on circuit is used to turn on the clock signal to the control terminal of the second input circuit under the control of the second feedback signal; The second shutdown circuit is used to connect the control terminal of the second input circuit to the ground terminal or the power supply terminal under the control of the first feedback signal, so as to turn off the second input circuit.

6. The decision feedback equalization circuit according to claim 5, characterized in that, The first turn-on circuit includes a first switching transistor; the first turn-off circuit includes a second switching transistor. The second terminal of the first switching transistor and the first terminal of the second switching transistor are both connected to the control terminal of the first input circuit; the second terminal of the second switching transistor is also connected to the ground terminal or the power supply terminal; the first switching transistor and the second switching transistor are NMOS or PMOS; wherein... The control terminal of the first switching transistor receives the first feedback signal; the first terminal of the first switching transistor receives the clock signal; and the control terminal of the second switching transistor receives the second feedback signal.

7. The decision feedback equalization circuit according to claim 6, characterized in that, The second turn-on circuit includes a third switching transistor; the second turn-off circuit includes a fourth switching transistor. The second terminal of the third switching transistor and the first terminal of the fourth switching transistor are both connected to the control terminal of the second input circuit; the second terminal of the fourth switching transistor is also connected to the ground terminal or the power supply terminal; the third and fourth switching transistors are NMOS or PMOS; wherein... The control terminal of the third switching transistor receives the second feedback signal; the first terminal of the third switching transistor receives the clock signal; and the control terminal of the fourth switching transistor receives the first feedback signal.

8. The decision feedback equalization circuit according to claim 7, characterized in that, When the first feedback signal triggers the first switching transistor and the fourth switching transistor to be in the on state, the second feedback signal triggers the second switching transistor and the third switching transistor to be in the off state, so that the clock signal is input to the control terminal of the first input circuit through the first switching transistor, and the control terminal of the second input circuit is connected to the ground terminal or the power supply terminal through the fourth switching transistor. When the first feedback signal triggers the first switching transistor and the fourth switching transistor to the off state, the second feedback signal triggers the second switching transistor and the third switching transistor to the on state, so that the control terminal of the first input circuit is connected to the ground terminal or the power supply terminal through the second switching transistor, and the clock signal is input to the control terminal of the second input circuit through the third switching transistor.

9. The decision feedback equalization circuit according to claim 2, characterized in that, The first input circuit includes: a first input transistor, a second input transistor, and a third input transistor; The first terminal of the first input transistor and the first terminal of the second input transistor are respectively connected to the second stage circuit; The control terminal of the third input transistor serves as the control terminal of the first input circuit; the second terminal of the third input transistor is connected to the ground terminal or the power supply terminal. The second terminals of the first input transistor and the second input transistor are both connected to the first terminal of the third input transistor; The first to third input transistors are NMOS or PMOS; wherein, The control terminal of the first input transistor receives the input signal; the control terminal of the second input transistor receives the first reference signal. When the third input transistor is triggered to conduct by the clock signal, the first input transistor and the second input transistor generate the first differential signal according to the input signal and the first reference signal, and input the first differential signal to the second stage circuit.

10. The decision feedback equalization circuit according to claim 2, characterized in that, The second input circuit includes: a fourth input transistor, a fifth input transistor, and a sixth input transistor; The first terminal of the fourth input transistor and the first terminal of the fifth input transistor are respectively connected to the second stage circuit; The control terminal of the sixth input transistor serves as the control terminal of the second input circuit; the second terminal of the sixth input transistor is connected to the ground terminal or the power supply terminal. The second terminal of the fourth input transistor and the second terminal of the fifth input transistor are both connected to the first terminal of the sixth input transistor; The fourth to sixth input transistors are NMOS or PMOS; wherein... The control terminal of the fourth input transistor receives the input signal; the control terminal of the fifth input transistor receives the second reference signal. When the sixth input transistor is triggered to conduct by the clock signal, the fourth input transistor and the fifth input transistor generate the second differential signal according to the input signal and the second reference signal, and input the second differential signal to the second stage circuit.

11. The decision feedback equalization circuit according to claim 3, characterized in that, The first reset circuit includes: a first reset transistor and a second reset transistor; Both the first terminal of the first reset transistor and the first terminal of the second reset transistor are connected to the power supply terminal or the ground terminal; the second terminal of the first reset transistor is connected to the first input circuit; the second terminal of the second reset transistor is connected to the second input circuit; the first reset transistor and the second reset transistor are PMOS or NMOS; wherein... The control terminals of both the first reset transistor and the second reset transistor receive the clock signal; When the clock signal triggers the first reset transistor and the second reset transistor to be in the conducting state, the first input circuit is connected to the power supply terminal or the ground terminal through the first reset transistor to be reset, and the second input circuit is connected to the power supply terminal or the ground terminal through the second reset transistor to be reset.

12. The decision feedback equalization circuit according to claim 2, characterized in that, The second-stage circuit includes: an output circuit and a second reset circuit; The second reset circuit is connected to the output circuit; the output circuit is also connected to a power supply terminal or a ground terminal; the second reset circuit is also connected to the power supply terminal or the ground terminal; wherein... The output circuit is used to amplify and latch the first differential signal or the second differential signal during the regeneration stage to output a comparison signal. The second reset circuit is used to reset the output circuit during the reset phase.

13. The decision feedback equalization circuit according to claim 12, characterized in that, The second reset circuit includes: a third reset transistor and a fourth reset transistor; The first terminals of the third reset transistor and the fourth reset transistor are both connected to the power supply terminal or the ground terminal; the second terminals of the third reset transistor and the fourth reset transistor are respectively connected to the output circuit; the third reset transistor and the fourth reset transistor are PMOS or NMOS; wherein... The control terminals of both the third and fourth reset transistors receive the clock signal; When the clock signal triggers the third reset transistor and the fourth reset transistor to be in the conducting state, the output circuit is connected to the power supply terminal or the ground terminal through the third reset transistor and the fourth reset transistor to reset.

14. The decision feedback equalization circuit according to claim 12, characterized in that, The output circuit includes: a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, and a sixth output transistor; The control terminal of the first output transistor, the first terminal of the second output transistor, the control terminal of the third output transistor, the second terminal of the fourth output transistor, and the second terminal of the sixth output transistor are all connected to the first output terminal of the output circuit; The first terminal of the first output transistor, the control terminal of the second output transistor, the second terminal of the third output transistor, the control terminal of the fourth output transistor, and the second terminal of the fifth output transistor are all connected to the second output terminal of the output circuit; The second terminal of the first output transistor and the second terminal of the second output transistor are respectively connected to the first input circuit, the second input circuit and the second reset circuit; The first terminals of the third output transistor, the fourth output transistor, the fifth output transistor, and the sixth output transistor are all connected to the power supply terminal or the ground terminal. The first and second output transistors are NMOS or PMOS; the third to sixth output transistors are PMOS or NMOS; wherein, The control terminals of the fifth output transistor and the sixth output transistor both receive the clock signal.

15. The decision feedback equalization circuit according to claim 1, characterized in that, The voltage of the first reference signal is greater than or less than the voltage of the second reference signal.

16. The decision feedback equalization circuit according to claim 1, characterized in that, The phase of the i-th clock signal is 360° / N later than the phase of the (i-1)-th clock signal.

17. The decision feedback equalization circuit according to any one of claims 1 to 16, characterized in that, When N=4, the fourth input of the first-stage comparator is connected to the output of the fourth-stage comparator, and receives the fourth-stage comparison signal output by the fourth-stage comparator; the fifth input of the first-stage comparator receives the first clock signal.

18. The decision feedback equalization circuit according to any one of claims 1 to 16, characterized in that, The decision feedback equalization circuit also includes: N latches; The input of each latch is connected to the output of each comparator stage to receive the comparison signal of each stage; wherein, each latch is used to store the comparison signal of each stage to output the latch signal of each stage.

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