Display device and driving method thereof

Abstract

This application provides a display device and its driving method. The display device includes a display panel. The display panel includes a plurality of pixel units. Each pixel unit includes a first sub-pixel and at least one second sub-pixel. The first sub-pixel includes a first driving circuit and a first light-emitting diode. The first driving circuit includes a first pulse amplitude modulation control module, a first transistor, and a second transistor. The second sub-pixel includes a second driving circuit and a second light-emitting diode. The second driving circuit includes a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor, and a fourth transistor. The technical solution of this application reduces the number of data signal lines, lowers the complexity of the driving circuit, improves color point stability and brightness uniformity, reduces transient current peaks, and improves the reliability of the display device.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] Currently, micro light-emitting diode (Micro LED) display devices and mini light-emitting diode (Mini LED) display devices mainly use pulse amplitude modulation (PAM), pulse width modulation (PWM), or pulse hybrid modulation (PHM) driving methods to achieve grayscale adjustment.

[0003] In display devices employing the PAM (Power Amplifier) ​​driving method, the pixel unit's driving circuit adjusts the grayscale by changing the driving current flowing through the light-emitting diode (LED), while maintaining a constant emission time. Under this driving method, different grayscale levels correspond to different driving currents. Changes in the driving current cause variations in the emission wavelength of the LED, resulting in changes in the color point. Specifically, the color point coordinate variation of the green LED across different grayscale levels is greater than that of the red and blue LEDs, leading to lower color point consistency across different grayscale levels. Furthermore, the luminous efficiency of the LED fluctuates significantly under low current conditions, easily resulting in uneven brightness at low and medium grayscale levels.

[0004] In display devices employing PWM (Pulse Width Modulation) driving, the pixel unit's driving circuit adjusts the grayscale by changing the light-emitting time of the LED, while the driving current flowing through the LED remains constant. Under this driving method, the LED's emission wavelength is relatively stable. However, at low grayscale levels, the thin-film transistor exhibits a relatively long response time, resulting in a longer falling edge of the emission waveform, leading to lower color uniformity at low grayscale levels. Simultaneously, the limited data bit depth of the driving chip restricts the brightness adjustment accuracy at ultra-low grayscale levels. Furthermore, in applications requiring full-screen illumination of low-to-medium brightness images, the driving circuit experiences a large transient current during the emission phase, resulting in uneven current distribution and excessive current load on local wiring, impacting the reliability of the display device.

[0005] In display devices employing PHM (Pulse Width Modulation) driving, the pixel unit's driving circuit simultaneously modulates the LED's driving current and emission time. Existing PHM driving methods require separate data signals for pulse amplitude modulation (PAM) control and pulse width modulation (PWM) control, leading to an increase in the number of data signals and higher driving costs. Furthermore, a single-bit signal source needs to correspond to both types of data signals, further increasing the complexity of the driving circuitry.

[0006] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0007] The purpose of this application is to provide a display device and its driving method, which aims to solve the technical problems of the large number of data signals and the high complexity of the driving circuit in existing display devices using PHM driving method.

[0008] This application provides a display device, the display device including a display panel, the display panel including a plurality of pixel units, each pixel unit including: a first sub-pixel, the first sub-pixel including a first driving circuit and a first light-emitting diode, the first driving circuit including a first pulse amplitude modulation control module, a first transistor and a second transistor, the input terminal of the first pulse amplitude modulation control module being electrically connected to a first data signal line, the output terminal of the first pulse amplitude modulation control module being electrically connected to the gate of the first transistor, the source of the first transistor being electrically connected to a first power supply line, the drain of the first transistor being electrically connected to the source of the second transistor, the gate of the second transistor being electrically connected to a first light emission control signal line, the drain of the second transistor being electrically connected to the anode of the first light-emitting diode, and the cathode of the first light-emitting diode being electrically connected to a second power supply line; and at least one second sub-pixel. The second sub-pixel includes a second driving circuit and a second light-emitting diode. The second driving circuit includes a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor, and a fourth transistor. The input terminal of the second pulse amplitude modulation control module is electrically connected to the global signal line, and the output terminal of the second pulse amplitude modulation control module is electrically connected to the gate of the third transistor. The source of the third transistor is electrically connected to the first power line, and the drain of the third transistor is electrically connected to the source of the fourth transistor. The input terminal of the second pulse width modulation control module is electrically connected to the second data signal line, and the output terminal of the second pulse width modulation control module is electrically connected to the gate of the third transistor or the gate of the fourth transistor. The drain of the fourth transistor is electrically connected to the anode of the second light-emitting diode, and the cathode of the second light-emitting diode is electrically connected to the second power line.

[0009] This application also provides a driving method for a display device, the display device including a display panel, the display panel including a plurality of pixel units, each pixel unit including a first sub-pixel and at least one second sub-pixel, the first sub-pixel including a first driving circuit and a first light-emitting diode, the first driving circuit including a first pulse amplitude modulation control module, a first transistor and a second transistor, the input terminal of the first pulse amplitude modulation control module being electrically connected to a first data signal line, the output terminal of the first pulse amplitude modulation control module being electrically connected to the gate of the first transistor, the source of the first transistor being electrically connected to a first power supply line, the drain of the first transistor being electrically connected to the source of the second transistor, the gate of the second transistor being electrically connected to a first light emission control signal line, the drain of the second transistor being electrically connected to the anode of the first light-emitting diode, and the cathode of the first light-emitting diode being electrically connected to a second power supply line, the second sub-pixel including a second driving circuit and a second light-emitting diode, the second driving circuit including a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor and a fourth transistor, the input terminal of the second pulse amplitude modulation control module being electrically connected to a global signal line, the second pulse amplitude modulation control module being electrically connected to a first data signal line, the output terminal of the first pulse amplitude modulation control module being electrically connected to a first data signal line, the source of the first transistor being electrically connected to a first power supply line, the drain of the first transistor being electrically connected to a first power supply line, the drain of the first transistor being electrically connected to a first power supply line, the cathode of the first light-emitting diode being electrically connected to a second power supply line, the second sub-pixel including a second driving circuit and a second light-emitting diode, the second driving circuit including a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor and a fourth transistor, the input terminal of the second pulse amplitude modulation control module being electrically connected to a global signal line, the second pulse amplitude modulation control module being electrically connected to a first data signal line, the output terminal of the first pulse amplitude modulation control module being electrically connected to a first data signal line, the output The output terminal of the block is electrically connected to the gate of the third transistor, the source of the third transistor is electrically connected to the first power line, the drain of the third transistor is electrically connected to the source of the fourth transistor, the input terminal of the second pulse width modulation control module is electrically connected to the second data signal line, the output terminal of the second pulse width modulation control module is electrically connected to the gate of the third transistor or the gate of the fourth transistor, the drain of the fourth transistor is electrically connected to the anode of the second light-emitting diode, and the cathode of the second light-emitting diode is electrically connected to the second power line; the driving method includes: in the reset phase, under the control of the second scan signal line, resetting the gate of the first transistor and the gate of the third transistor to the initialization voltage; in the data writing phase, writing a first data voltage to the first driving circuit through the first data signal line, and writing a second data voltage to the second driving circuit through the second data signal line; in the threshold compensation phase, controlling the first driving circuit and the second driving circuit to perform threshold compensation through the first scan signal line; in the light emission phase, controlling the first sub-pixel to emit light through the first light emission control signal line, and controlling the second sub-pixel to emit light through the first light emission control signal line and the second light emission control signal line.

[0010] The display device provided in the embodiments of this application includes a display panel. The display panel includes a plurality of pixel units. Each pixel unit includes a first sub-pixel and at least one second sub-pixel. The first sub-pixel includes a first driving circuit and a first light-emitting diode. The first driving circuit includes a first pulse amplitude modulation control module, a first transistor, and a second transistor. The second sub-pixel includes a second driving circuit and a second light-emitting diode. The second driving circuit includes a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor, and a fourth transistor. The input terminal of the second pulse amplitude modulation control module is electrically connected to a global signal line. The input terminal of the second pulse width modulation control module is electrically connected to a second data signal line. The technical solution of this application enables the second pulse amplitude modulation control module to receive a fixed global reference voltage from the global signal line. The global reference voltage is shared by all sub-pixels of the same color. The technical solution of this application eliminates the need to provide a separate reference voltage signal for each sub-pixel, thereby significantly reducing the number of data signal lines. The second pulse width modulation control module receives a data voltage through the second data signal line. The technical solution of this application enables all sub-pixel driving circuits of each pixel unit to achieve pulse mixing modulation driving with only a small number of data signals. Compared to existing pulse hybrid modulation driving methods that require separate data signals for pulse amplitude modulation control and pulse width modulation control, the technical solution of this application avoids the problem of doubling the number of data signals, reduces the number of output channels required for the source driver, reduces driving costs, and reduces the complexity of the driving circuit.

[0011] The first sub-pixel uses pulse amplitude modulation (PAM) for grayscale adjustment. Brightness is adjusted by changing the driving current flowing through the first light-emitting diode (LED). The first driving circuit includes only a first pulse amplitude modulation (PAM) control module and does not include a pulse width modulation (PWM) control module. Compared to a driving circuit that includes both PAM and PWM control modules, the number of transistors in the first sub-pixel's driving circuit is reduced, increasing the usable space of the pixel. The technical solution of this application increases the size of the driving transistors, reduces their operating voltage, reduces the number of transistors in the main current branch, lowers the power consumption and resistor-capacitor voltage drop of the display panel, and improves display uniformity.

[0012] The second sub-pixel uses a pulse-width modulation (PWM) method for grayscale adjustment. The driving current of the pulse amplitude modulation section is controlled by a global reference voltage provided by the global signal line. The global reference voltage remains constant. This technical solution ensures that the driving current flowing through the second LED remains constant. Under the condition of a constant driving current, the emission wavelength of the second LED remains stable. This technical solution avoids the emission wavelength drift caused by changes in driving current in the pulse amplitude modulation method, thereby improving the color point stability of the second sub-pixel at different grayscale levels. By using differentiated driving methods for different sub-pixels, this technical solution improves the color point consistency of the display device at various grayscale levels. The second sub-pixel uses a pulse width modulation method with a fixed driving current for grayscale adjustment. Brightness is adjusted by changing the emission time. Because the driving current remains at a high level, this technical solution avoids the LED operating under low current conditions. The luminous efficiency fluctuation of the LED is reduced. This technical solution avoids the brightness unevenness caused by large fluctuations in luminous efficiency under low current in the pulse amplitude modulation method, improving the display uniformity at medium and low grayscale levels.

[0013] The first sub-pixel uses pulse amplitude modulation (PWM). The second sub-pixel uses pulse width modulation (PWM) to adjust the grayscale. Compared to a driving scheme where all sub-pixels use PWM, the technical solution of this application reduces the peak transient current of the pixel unit during the light-emitting phase. As the grayscale decreases, the driving current of the first sub-pixel decreases. The reduction in the peak transient current of the pixel unit is significant. The technical solution of this application reduces the burden on the power supply circuit, alleviates the stress impact of large transient currents on the bonding area and wiring, improves the uniformity of current distribution, reduces the risk of excessive current in local wiring, and improves the reliability of the display device. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0015] Figure 2 A schematic diagram of a pixel unit in a first embodiment of the display device provided in this application.

[0016] Figure 3 A schematic diagram of a pixel unit in a second embodiment of the display device provided in this application.

[0017] Figure 4 A schematic diagram illustrating the changes in the light emission state of the red, green, and blue sub-pixels within a display cycle in the first or second embodiment of the display device provided in this application.

[0018] Figure 5A circuit diagram of the red sub-pixel in the first embodiment of the display device provided in this application.

[0019] Figure 6 A circuit diagram of the green sub-pixel in the first embodiment of the display device provided in this application.

[0020] Figure 7 A circuit diagram of the blue sub-pixel in the first embodiment of the display device provided in this application.

[0021] Figure 8 A circuit diagram of the green sub-pixel in a second embodiment of the display device provided in this application.

[0022] Figure 9 A circuit diagram of the blue sub-pixel in a second embodiment of the display device provided in this application.

[0023] Figure 10 Waveform diagrams of relevant signals for the first or second embodiment of the display device provided in this application.

[0024] Figure 11 A schematic diagram of the bonding area of ​​the display device provided in this application.

[0025] Figure 12 A bar chart comparing the peak current of the display device provided in this application and a display device using pulse width modulation driving at different gray levels.

[0026] Figure 13 A line graph showing the percentage decrease in peak current of the display device provided in this application relative to a display device using pulse width modulation driving as a function of grayscale.

[0027] Figure 14 This is a display effect diagram showing the uneven brightness of green sub-pixels in a display device using pulse amplitude modulation driving.

[0028] Figure 15 This is a display effect diagram illustrating the uneven brightness of green sub-pixels in the display device provided in this application.

[0029] Figure 16 This is a schematic diagram illustrating the green screen display effect of the display device provided in this application.

[0030] Figure 17 This is a schematic diagram illustrating the blue screen display effect of the display device provided in this application. Detailed Implementation

[0031] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0032] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0033] The technical solutions of different embodiments of this application can be combined with each other.

[0034] The display device provided in the embodiments of this application is a mini light-emitting diode display device or a micro light-emitting diode display device. The embodiments of this application are described using a micro light-emitting diode display device as an example.

[0035] Embodiments of this application provide a display device and its driving method, such as... Figure 1 As shown, the display device includes a display panel, a demultiplexing circuit, a timing controller, and a source driver. The display panel includes at least one gate driving circuit, multiple scan signal lines, multiple light emission control signal lines, multiple data signal lines, and multiple pixel units. The timing controller receives externally input image data and control signals, converts the image data into a data format suitable for processing by the source driver, and simultaneously generates timing control signals required by the gate driving circuit and the source driver. The source driver receives the image data provided by the timing controller, converts the image data into analog voltage signals, and transmits them to the pixel units through the data signal lines. The gate driving circuit receives the timing control signals provided by the timing controller and sequentially outputs scan signals to the multiple scan signal lines to select multiple rows of pixel units line by line.

[0036] Each pixel unit includes a first sub-pixel and at least one second sub-pixel. The first sub-pixel is a red sub-pixel, and the at least one second sub-pixel includes a green sub-pixel and / or a blue sub-pixel. Specifically, each pixel unit includes a first sub-pixel and two second sub-pixels, with the two second sub-pixels being a green sub-pixel and a blue sub-pixel, respectively. That is, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The global signal line corresponding to the green sub-pixel is the first global signal line VREF_G, the second data signal line corresponding to the green sub-pixel is the green sub-pixel data signal line DATA_PWM_G, the global signal line corresponding to the blue sub-pixel is the second global signal line VREF_B, and the third data signal line corresponding to the blue sub-pixel is the blue sub-pixel data signal line DATA_PWM_B. The red, green, and blue sub-pixels each include a first driving circuit, a second driving circuit, and a third driving circuit, respectively. The first driving circuit drives the first light-emitting diode LED1 to emit light, the second driving circuit drives the second light-emitting diode LED2 to emit light, and the third driving circuit drives the third light-emitting diode LED3 to emit light. The first LED, LED1, the second LED, and the third LED, LED3, are red, green, and blue LEDs, respectively, and are all miniature LEDs.

[0037] This application addresses the color dot variation characteristics of red, green, and blue sub-pixels under different current conditions, employing different driving methods for sub-pixels of different colors. The color dot coordinate variation amplitude of red LEDs under different current conditions is smaller than that of green and blue LEDs. Based on this characteristic, this application uses a pulse amplitude modulation driving method for red sub-pixels and a pulse hybrid modulation driving method for green and blue sub-pixels.

[0038] In this application, the signal received at the input terminal of the pulse amplitude modulation control module controls the magnitude of the current flowing through the light-emitting diode (LED), and the signal received at the input terminal of the pulse width modulation control module controls the emission time of the LED. For the red sub-pixel using pulse amplitude modulation driving mode, the input terminal of the first pulse amplitude modulation control module PAM-Ctrl1 is electrically connected to the first data signal line DATA_PAM_R, and the magnitude of the current flowing through the first LED1 is adjusted by the first data signal, thereby realizing grayscale adjustment. For the green and blue sub-pixels using pulse hybrid modulation driving mode, the input terminal of the second pulse amplitude modulation control module PAM-Ctrl2 is electrically connected to the first global signal line VREF_G, the input terminal of the second pulse width modulation control module PWM-Ctrl2 is electrically connected to the green sub-pixel data signal line DATA_PWM_G, the input terminal of the third pulse amplitude modulation control module PAM-Ctrl3 is electrically connected to the second global signal line VREF_B, and the input terminal of the third pulse width modulation control module PWM-Ctrl3 is electrically connected to the blue sub-pixel data signal line DATA_PWM_B. The first global signal line is electrically connected to the input terminal of the second pulse amplitude modulation control module PAM-Ctrl2, which controls multiple green sub-pixels (one of the two second sub-pixels). The second global signal line is electrically connected to the input terminal of the third pulse amplitude modulation control module PAM-Ctrl3, which controls multiple blue sub-pixels (the other of the two second sub-pixels). The second pulse amplitude modulation control module PAM-Ctrl2 and the third pulse amplitude modulation control module PAM-Ctrl3 receive fixed reference voltages from the first and second global signal lines, respectively, ensuring that the current flowing through the second LED2 and the third LED3 remains constant. The second pulse width modulation control module PWM-Ctrl2 and the third pulse width modulation control module PWM-Ctrl3 receive the second and third data signals, respectively, and adjust the emission time of the second LED2 and the third LED3 using the second and third data signals, thereby achieving grayscale adjustment.

[0039] like Figure 2 , Figure 5 , Figure 6 and Figure 7 As shown, the first embodiment of this application provides a display device. The display panel of the display device includes a plurality of pixel units, and each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0040] The red sub-pixel includes a first driving circuit and a first light-emitting diode (LED1). The first driving circuit includes a first pulse amplitude modulation control module (PAM-Ctrl1), a first transistor T2, and a second transistor T3. Both the first transistor T2 and the second transistor T3 are P-type transistors. The input terminal of the first pulse amplitude modulation control module (PAM-Ctrl1) is electrically connected to the first data signal line DATA_PAM_R, and the output terminal of the first pulse amplitude modulation control module (PAM-Ctrl1) is electrically connected to the gate of the first transistor T2. The source of the first transistor T2 is electrically connected to the first power supply line VDD, and the drain of the first transistor T2 is electrically connected to the source of the second transistor T3. The gate of the second transistor T3 is electrically connected to the first light-emitting control signal line EMA(i), and the drain of the second transistor T3 is electrically connected to the anode of the first light-emitting diode (LED1). The cathode of the first light-emitting diode (LED1) is electrically connected to the second power supply line VSS.

[0041] The first pulse amplitude modulation control module PAM-Ctrl1 generates a first control signal based on the received first data signal. This first control signal is applied to the gate of the first transistor T2, controlling the conduction level of the first transistor T2. When both the first transistor T2 and the second transistor T3 are in the on state, the first power line VDD provides driving current to the first light-emitting diode LED1 through the first transistor T2 and the second transistor T3. The magnitude of the driving current is determined by the conduction level of the first transistor T2. By adjusting the voltage value of the first data signal, the conduction level of the first transistor T2 is adjusted, thereby adjusting the magnitude of the driving current flowing through the first light-emitting diode LED1, achieving grayscale adjustment of the red sub-pixel. The second transistor T3 is turned on or off under the control of the first light-emitting control signal provided by the first light-emitting control signal line EMA(i), controlling the light-emitting time of the first light-emitting diode LED1.

[0042] The green sub-pixel (one of the two second sub-pixels) includes a second driving circuit and a second light-emitting diode (LED2). The second driving circuit includes a second pulse amplitude modulation (PAM-Ctrl2) control module, a second pulse width modulation (PWM-Ctrl2) control module, a third transistor T8, and a fourth transistor T9. Both the third transistor T8 and the fourth transistor T9 are P-type transistors. The input terminal of the second pulse amplitude modulation (PAM-Ctrl2) control module is electrically connected to the first global signal line VREF_G, and the output terminal of the second pulse amplitude modulation (PAM-Ctrl2) control module is electrically connected to the gate of the third transistor T8. The source of the third transistor T8 is electrically connected to the first power supply line VDD, and the drain of the third transistor T8 is electrically connected to the source of the fourth transistor T9. The input terminal of the second pulse width modulation (PWM-Ctrl2) control module is electrically connected to the second data signal line DATA_PWM_G, and the output terminal of the second pulse width modulation (PWM-Ctrl2) control module is electrically connected to the gate of the fourth transistor T9. The drain of the fourth transistor T9 is electrically connected to the anode of the second light-emitting diode (LED2). The cathode of the second light-emitting diode (LED2) is electrically connected to the second power supply line VSS.

[0043] The second pulse amplitude modulation control module PAM-Ctrl2 receives a first reference voltage provided by the first global signal line VREF_G, which is a fixed voltage value. Based on the first reference voltage, PAM-Ctrl2 generates a second control signal, which is applied to the gate of the third transistor T8, controlling the conduction level of T8 to a fixed state. The second pulse width modulation control module PWM-Ctrl2 receives a second data signal provided by the second data signal line DATA_PWM_G, and generates a third control signal based on the second data signal. This third control signal is applied to the gate of the fourth transistor T9, controlling the conduction time of T9. When both the third transistor T8 and the fourth transistor T9 are in the on state, the first power line VDD provides drive current to the second light-emitting diode LED2 through both transistors T8 and T9. Because the conduction level of the third transistor T8 remains constant, the magnitude of the drive current flowing through the second light-emitting diode LED2 remains constant. By adjusting the second data signal, the conduction time of the fourth transistor T9 is adjusted, thereby adjusting the light emission time of the second light-emitting diode LED2, and thus achieving grayscale adjustment of the green sub-pixel (one of the two second sub-pixels).

[0044] The blue sub-pixel (the other of the two second sub-pixels) includes a third driving circuit and a third light-emitting diode (LED3). The third driving circuit includes a third pulse amplitude modulation (PAM) control module (PAM-Ctrl3), a third pulse width modulation (PWM) control module (PWM-Ctrl3), a fifth transistor (T20), and a sixth transistor (T21). Both the fifth transistor (T20) and the sixth transistor (T21) are P-type transistors. The input of the third PAM-Ctrl3 is electrically connected to the second global signal line VREF_B, and the output of the third PAM-Ctrl3 is electrically connected to the gate of the fifth transistor (T20). The source of the fifth transistor (T20) is electrically connected to the first power supply line VDD, and the drain of the fifth transistor (T20) is electrically connected to the source of the sixth transistor (T21). The input of the third PAM-Ctrl3 is electrically connected to the third data signal line DATA_PWM_B, and the output of the third PAM-Ctrl3 is electrically connected to the gate of the sixth transistor (T21). The drain of the sixth transistor (T21) is electrically connected to the anode of the third light-emitting diode (LED3). The cathode of the third light-emitting diode LED3 is electrically connected to the second power line VSS.

[0045] The third pulse amplitude modulation control module PAM-Ctrl3 receives a second reference voltage from the second global signal line VREF_B, which is a fixed voltage value. Based on the second reference voltage, PAM-Ctrl3 generates a fourth control signal, which is applied to the gate of the fifth transistor T20, keeping its conduction level constant. The third pulse width modulation control module PWM-Ctrl3 receives a third data signal from the third data signal line DATA_PWM_B, generates a fifth control signal, and applies it to the gate of the sixth transistor T21, controlling its conduction time. When both the fifth transistor T20 and the sixth transistor T21 are on, the first power line VDD provides drive current to the third light-emitting diode LED3 through both transistors. Because the conduction level of the fifth transistor T20 remains constant, the magnitude of the drive current flowing through the third light-emitting diode LED3 remains constant. By adjusting the third data signal, the conduction time of the sixth transistor T21 is adjusted, thereby adjusting the light emission time of the third light-emitting diode LED3, and thus achieving grayscale adjustment of the blue sub-pixel (the other of the two second sub-pixels).

[0046] In this embodiment, the first data signal line DATA_PAM_R, the second data signal line DATA_PWM_G, and the third data signal line DATA_PWM_B provide data signals to the first pulse amplitude modulation control module PAM-Ctrl1, the second pulse width modulation control module PWM-Ctrl2, and the third pulse width modulation control module PWM-Ctrl3, respectively. The source driver generates the first data signal, the second data signal, and the third data signal based on the image data provided by the timing controller, and transmits them to the corresponding sub-pixels through the first data signal line DATA_PAM_R, the second data signal line DATA_PWM_G, and the third data signal line DATA_PWM_B, respectively.

[0047] The first reference voltage provided by the first global signal line VREF_G is set according to the current-brightness characteristics of the green LED, so that the driving current flowing through the second LED LED2 is within the high-efficiency light-emitting range of the green LED. The second reference voltage provided by the second global signal line VREF_B is set according to the current-brightness characteristics of the blue LED, so that the driving current flowing through the third LED LED3 is within the high-efficiency light-emitting range of the blue LED.

[0048] like Figure 3 , Figure 8 and Figure 9 As shown, the second embodiment of this application provides a display device. The difference between the display device and the display device of the first embodiment is that, in the second embodiment, the output terminal of the second pulse width modulation control module PWM-Ctrl2 is electrically connected to the gate of the third transistor T8, the gate of the fourth transistor T9 is electrically connected to the first light emission control signal line EMA(i), the output terminal of the third pulse width modulation control module PWM-Ctrl3 is electrically connected to the gate of the fifth transistor T20, and the gate of the sixth transistor T21 is electrically connected to the first light emission control signal line EMA(i).

[0049] In the second embodiment, the second pulse amplitude modulation control module PAM-Ctrl2 receives a first reference voltage provided by the first global signal line VREF_G. Based on the first reference voltage, PAM-Ctrl2 generates a second control signal, which is applied to the gate of the third transistor T8. The second pulse width modulation control module PWM-Ctrl2 receives a second data signal provided by the second data signal line DATA_PWM_G. Based on the second data signal, it generates a third control signal, which is also applied to the gate of the third transistor T8. The gate of the third transistor T8 receives the combined effect of the second and third control signals, controlling the conduction level and conduction time of the third transistor T8. The gate of the fourth transistor T9 receives a first light emission control signal provided by the first light emission control signal line EMA(i). Under the control of the first light emission control signal, the fourth transistor T9 is turned on or off.

[0050] The third pulse amplitude modulation control module PAM-Ctrl3 receives the second reference voltage provided by the second global signal line VREF_B. Based on the second reference voltage, PAM-Ctrl3 generates a fourth control signal, which is applied to the gate of the fifth transistor T20. The third pulse width modulation control module PWM-Ctrl3 receives the third data signal provided by the third data signal line DATA_PWM_B. Based on the third data signal, it generates a fifth control signal, which is also applied to the gate of the fifth transistor T20. The gate of the fifth transistor T20 receives the combined effect of the fourth and fifth control signals, controlling the conduction level and conduction time of the fifth transistor T20. The gate of the sixth transistor T21 receives the first light emission control signal provided by the first light emission control signal line EMA(i). Under the control of the first light emission control signal, the sixth transistor T21 is turned on or off.

[0051] In the first and second embodiments, grayscale adjustment is achieved by sharing three data signals among the three sub-pixels of each pixel unit, reducing the complexity of the driving circuit. Compared to the traditional pulse hybrid modulation driving method, which requires separate data signals for pulse amplitude modulation control and pulse width modulation control, this application reduces the number of data signals and lowers the driving cost.

[0052] like Figure 4 As shown, the vertical axis I represents the magnitude of the current flowing through the LED, the horizontal axis t represents time, and the brightness of the LED is equivalent to the product of the current and the emission time.

[0053] For the red sub-pixel, the red sub-pixel adopts a pulse amplitude modulation driving method, and grayscale adjustment is achieved by adjusting the current magnitude, while the emission time remains constant. Figure 4The diagram shows the emission state of the red sub-pixel at three different gray levels, from bottom to top: low gray level, medium gray level, and high gray level. The driving current corresponding to the low gray level is relatively small, the driving current corresponding to the medium gray level is moderate, and the driving current corresponding to the high gray level is relatively large. The emission time is the same for all three gray levels.

[0054] For the green sub-pixel, the green sub-pixel adopts a pulse width modulation driving method, and grayscale adjustment is achieved by adjusting the emission time, while the driving current remains constant. Figure 4 The image shows the emission state of the green sub-pixel at three different gray levels, from left to right: low gray level, medium gray level, and high gray level. The emission time corresponding to the low gray level is shorter, the emission time corresponding to the medium gray level is moderate, and the emission time corresponding to the high gray level is longer. The driving current is the same for all three gray levels.

[0055] For the blue sub-pixel, the blue sub-pixel adopts a pulse width modulation driving method, and grayscale adjustment is achieved by adjusting the emission time, while the driving current remains constant. Figure 4 The image shows the emission state of the blue sub-pixel at three different gray levels, from left to right: low gray level, medium gray level, and high gray level. The emission time corresponding to the low gray level is shorter, the emission time corresponding to the medium gray level is moderate, and the emission time corresponding to the high gray level is longer. The driving current is the same for all three gray levels.

[0056] In this application, the driving current ratio of the red, green, and blue sub-pixels is set according to the luminous efficiency of the red, green, and blue light-emitting diodes. The driving current ratio of the red, green, and blue light-emitting diodes is 4.2:1.2:1. Based on this ratio, when displaying a white image, the light emitted by the red, green, and blue sub-pixels mixes to produce a white image.

[0057] like Figure 1 As shown, the source driver provides the data signal, which is distributed to the data signal lines within the display panel through a multiplexer circuit. The gate drive circuit includes multiple gate drive units, which sequentially output scan signals. The pixel unit includes a miniature light-emitting diode, a pixel drive circuit, and multiple signal lines. The signal lines include an initialization voltage line VI, a first global signal line VREF_G, a first data signal line DATA_PAM_R, a second data signal line DATA_PWM_G, a third data signal line DATA_PWM_B, a first power supply line VDD, a second power supply line VSS, a ramp signal line SWEEP(i), a first light emission control signal line, and a second light emission control signal line.

[0058] The demultiplexing circuit includes multiple sets of selection switches, each set comprising a first selection switch, a second selection switch, and a third selection switch. The gate of the first selection switch is electrically connected to the first control line DEMUX1, and its drain is electrically connected to the first data signal line DATA_PAM_R. The gate of the second selection switch is electrically connected to the second control line DEMUX2, and its drain is electrically connected to the green sub-pixel data signal line DATA_PWM_G. The gate of the third selection switch is electrically connected to the third control line DEMUX3, and its drain is electrically connected to the blue sub-pixel data signal line DATA_PWM_B. The sources of the first, second, and third selection switches are all connected to the same data output port of the source driver; that is, one data output port of the source driver is electrically connected to the source of one set of selection switches.

[0059] The gate driving circuit includes multiple gate driving units, which output the previous stage scan signal SCAN(i-1), the current stage scan signal SCAN(), the light emission control signal, and the ramp signal SWEEP(i). The light emission control signal includes the first light emission control signal EMA(i) and the second light emission control signal EMW(i). The gate driving unit outputs the scan signal, the light emission control signal, and the ramp signal SWEEP(i) line by line.

[0060] like Figure 5 As shown, the red sub-pixel includes a first driving circuit and a first light-emitting diode LED1. The first driving circuit includes a seventh transistor T1, a first transistor T2, a second transistor T3, an eighth transistor T4, a ninth transistor T5, a tenth transistor T6, and a first capacitor C1.

[0061] The first driving circuit includes a first pulse amplitude modulation control module PAM-Ctrl1, a first transistor T2, and a second transistor T3. The first pulse amplitude modulation control module PAM-Ctrl1 includes a seventh transistor T1, an eighth transistor T4, a ninth transistor T5, a tenth transistor T6, and a first capacitor C1. The first transistor T2 is a driving transistor, and the seventh transistor T1 and the second transistor T3 are light-emitting control transistors. The seventh transistor T1 through the tenth transistor T6, the first transistor T2, and the second transistor T3 are all P-type transistors.

[0062] The gate of the seventh transistor T1 is electrically connected to the first light-emitting control signal line EMA(i), the source of the seventh transistor T1 is electrically connected to the first power supply line VDD, and the drain of the seventh transistor T1 is electrically connected to the source of the first transistor T2. The gate of the eighth transistor T4 is electrically connected to the current stage scan signal line SCAN(i), the source of the eighth transistor T4 is electrically connected to the first data signal line DATA_PAM_R, and the drain of the eighth transistor T4 is electrically connected to the source of the first transistor T2. The gate of the first transistor T2 is electrically connected to the second plate of the first capacitor C1, and the drain of the first transistor T2 is electrically connected to the source of the second transistor T3. The gate of the ninth transistor T5 is electrically connected to the current stage scan signal line SCAN(i), the drain of the ninth transistor T5 is electrically connected to the gate of the first transistor T2, and the source of the ninth transistor T5 is electrically connected to the drain of the first transistor T2. The gate of the tenth transistor T6 is electrically connected to the previous stage scan signal line SCAN(i-1), the source of the tenth transistor T6 is electrically connected to the initialization voltage line VI, and the drain of the tenth transistor T6 is electrically connected to the gate of the first transistor T2. The first plate of the first capacitor C1 is electrically connected to the first power supply line VDD, and the second plate of the first capacitor C1 is electrically connected to the gate of the first transistor T2. The gate of the second transistor T3 is electrically connected to the first light-emitting control signal line EMA(i), the source of the second transistor T3 is electrically connected to the drain of the first transistor T2, and the drain of the second transistor T3 is electrically connected to the anode of the first light-emitting diode LED1. The cathode of the first light-emitting diode LED1 is electrically connected to the second power supply line VSS.

[0063] like Figure 6 and Figure 8 As shown, the green sub-pixel (one of the two second sub-pixels) includes a second driving circuit and a second light-emitting diode (LED2). The second driving circuit includes a second pulse amplitude modulation control module (PAM-Ctrl2), a second pulse width modulation control module (PWM-Ctrl2), a third transistor (T8), and a fourth transistor (T9). The second pulse amplitude modulation control module (PAM-Ctrl2) includes an eleventh transistor (T7), a twelfth transistor (T10), a thirteenth transistor (T11), a fourteenth transistor (T12), and a second capacitor (C2). The third transistor (T8) is the driving transistor. The second pulse width modulation control module (PWM-Ctrl2) includes a fifteenth transistor (T13), a sixteenth transistor (T14), a seventeenth transistor (T15), an eighteenth transistor (T16), a nineteenth transistor (T17), a twentieth transistor (T18), and a third capacitor (C3). The eleventh transistors (T7) to the twentieth transistor (T18), the third transistor (T8), and the fourth transistor (T9) are all P-type transistors.

[0064] In the second pulse amplitude modulation control module PAM-Ctrl2, the gate of the eleventh transistor T7 is electrically connected to the first light emission control signal line EMA(i), the source of the eleventh transistor T7 is electrically connected to the first power supply line VDD, and the drain of the eleventh transistor T7 is electrically connected to the source of the third transistor T8. The gate of the twelfth transistor T10 is electrically connected to the current stage scan signal line SCAN(i), the source of the twelfth transistor T10 is electrically connected to the first global signal line VREF_G, and the drain of the twelfth transistor T10 is electrically connected to the source of the third transistor T8. The source of the third transistor T8 is electrically connected to the drain of the eleventh transistor T7 and the drain of the twelfth transistor T10, the gate of the third transistor T8 is electrically connected to the second plate of the second capacitor C2, and the drain of the third transistor T8 is electrically connected to the source of the fourth transistor T9. The gate of the thirteenth transistor T11 is electrically connected to the current stage scan signal line SCAN(i), the drain of the thirteenth transistor T11 is electrically connected to the gate of the third transistor T8, and the source of the thirteenth transistor T11 is electrically connected to the drain of the third transistor T8. The first plate of the second capacitor C2 is electrically connected to the first power supply line VDD, and the second plate of the second capacitor C2 is electrically connected to the gate of the third transistor T8. The gate of the fourteenth transistor T12 is electrically connected to the previous stage scan signal line SCAN(i-1), the source of the fourteenth transistor T12 is electrically connected to the initialization voltage line VI, and the drain of the fourteenth transistor T12 is electrically connected to the gate of the third transistor T8. The gate of the fourth transistor T9 is electrically connected to the first light emission control signal line EMA(i) or the drain of the seventeenth transistor T15, the source of the fourth transistor T9 is electrically connected to the drain of the third transistor T8, and the drain of the fourth transistor T9 is electrically connected to the anode of the second light-emitting diode LED2. The cathode of the second light-emitting diode LED2 is electrically connected to the second power supply line VSS.

[0065] In the second pulse width modulation control module PWM-Ctrl2, the gate of the eighteenth transistor T16 is electrically connected to the current stage scan signal line SCAN(i), the source of the eighteenth transistor T16 is electrically connected to the second data signal line DATA_PWM_G, and the drain of the eighteenth transistor T16 is electrically connected to the drain of the fifteenth transistor T13. The gate of the twentieth transistor T18 is electrically connected to the previous stage scan signal line SCAN(i-1), the source of the twentieth transistor T18 is electrically connected to the initialization voltage line VI, and the drain of the twentieth transistor T18 is electrically connected to the gate of the sixteenth transistor T14. The first plate of the third capacitor C3 is electrically connected to the ramp signal line SWEEP(i), and the second plate of the third capacitor C3 is electrically connected to the gate of the sixteenth transistor T14. The source of the sixteenth transistor T14 is electrically connected to the drain of the fifteenth transistor T13, and the drain of the sixteenth transistor T14 is electrically connected to the source of the seventeenth transistor T15. The gate of the nineteenth transistor T17 is electrically connected to the current stage scan signal line SCAN(i), the drain of the nineteenth transistor T17 is electrically connected to the gate of the sixteenth transistor T14, and the source of the nineteenth transistor T17 is electrically connected to the drain of the sixteenth transistor T14. The gate of the fifteenth transistor T13 is electrically connected to the second light emission control signal line EMW(i), the source of the fifteenth transistor T13 is electrically connected to the reference voltage line VRF, and the drain of the fifteenth transistor T13 is electrically connected to the source of the sixteenth transistor T14. The gate of the seventeenth transistor T15 is electrically connected to the second light emission control signal line EMW(i), the source of the seventeenth transistor T15 is electrically connected to the drain of the sixteenth transistor T14, and the drain of the seventeenth transistor T15 is electrically connected to the gate of the fourth transistor T9.

[0066] like Figure 7 and Figure 9 As shown, the blue sub-pixel (the other of the two second sub-pixels) includes a third driving circuit and a third light-emitting diode (LED3). The third driving circuit includes a third pulse amplitude modulation control module (PAM-Ctrl3), a third pulse width modulation control module (PWM-Ctrl3), a fifth transistor (T20), and a sixth transistor (T21). The third pulse amplitude modulation control module (PAM-Ctrl3) includes a twenty-first transistor (T19), a twenty-second transistor (T22), a twenty-third transistor (T23), a twenty-fourth transistor (T24), and a fourth capacitor (C4). The fifth transistor (T20) is the driving transistor. The third pulse width modulation control module (PWM-Ctrl3) includes a twenty-fifth transistor (T25), a twenty-sixth transistor (T26), a twenty-seventh transistor (T27), a twenty-eighth transistor (T28), a twenty-ninth transistor (T29), a thirtieth transistor (T30), and a fifth capacitor (C5). T19 through T30, T20, and T21 are all P-type transistors.

[0067] In the third pulse amplitude modulation control module PAM-Ctrl3, the gate of the twenty-first transistor T19 is electrically connected to the first light emission control signal line EMA(i), the source of the twenty-first transistor T19 is electrically connected to the first power supply line VDD, and the drain of the twenty-first transistor T19 is electrically connected to the source of the fifth transistor T20. The gate of the twenty-second transistor T22 is electrically connected to the current stage scan signal line SCAN(i), the source of the twenty-second transistor T22 is electrically connected to the second global signal line VREF_B, and the drain of the twenty-second transistor T22 is electrically connected to the source of the fifth transistor T20. The source of the fifth transistor T20 is electrically connected to the drains of the twenty-first transistor T19 and the twenty-second transistor T22, the gate of the fifth transistor T20 is electrically connected to the second plate of the fourth capacitor C4, and the drain of the fifth transistor T20 is electrically connected to the source of the sixth transistor T21. The gate of the 23rd transistor T23 is electrically connected to the current stage scan signal line SCAN(i), the drain of the 23rd transistor T23 is electrically connected to the gate of the 5th transistor T20, and the source of the 23rd transistor T23 is electrically connected to the drain of the 5th transistor T20. The first plate of the fourth capacitor C4 is electrically connected to the first power supply line VDD, and the second plate of the fourth capacitor C4 is electrically connected to the gate of the 5th transistor T20. The gate of the 24th transistor T24 is electrically connected to the previous stage scan signal line SCAN(i-1), the source of the 24th transistor T24 is electrically connected to the initialization voltage line VI, and the drain of the 24th transistor T24 is electrically connected to the gate of the 5th transistor T20. The gate of the 6th transistor T21 is electrically connected to the first light emission control signal line EMA(i) or the drain of the 27th transistor T27, the source of the 6th transistor T21 is electrically connected to the drain of the 5th transistor T20, and the drain of the 6th transistor T21 is electrically connected to the anode of the third light-emitting diode LED3. The cathode of the third light-emitting diode LED3 is electrically connected to the second power supply line VSS.

[0068] In the third pulse width modulation control module PWM-Ctrl3, the gate of the twenty-eighth transistor T28 is electrically connected to the current stage scan signal line SCAN(i), the source of the twenty-eighth transistor T28 is electrically connected to the third data signal line DATA_PWM_B, and the drain of the twenty-eighth transistor T28 is electrically connected to the drain of the twenty-fifth transistor T25. The gate of the thirtieth transistor T30 is electrically connected to the previous stage scan signal line SCAN(i-1), the source of the thirtieth transistor T30 is electrically connected to the initialization voltage line VI, and the drain of the thirtieth transistor T30 is electrically connected to the gate of the twenty-sixth transistor T26. The first plate of the fifth capacitor C5 is electrically connected to the ramp signal line SWEEP(i), and the second plate of the fifth capacitor C5 is electrically connected to the gate of the twenty-sixth transistor T26. The source of the twenty-sixth transistor T26 is electrically connected to the drain of the twenty-fifth transistor T25, and the drain of the twenty-sixth transistor T26 is electrically connected to the source of the twenty-seventh transistor T27. The gate of transistor T29 is electrically connected to the current stage scan signal line SCAN(i), the drain of transistor T29 is electrically connected to the gate of transistor T26, and the source of transistor T29 is electrically connected to the drain of transistor T26. The gate of transistor T25 is electrically connected to the second light emission control signal line EMW(i), the source of transistor T25 is electrically connected to the reference voltage line VRF, and the drain of transistor T25 is electrically connected to the source of transistor T26. The gate of transistor T27 is electrically connected to the second light emission control signal line EMW(i), the source of transistor T27 is electrically connected to the drain of transistor T26, and the drain of transistor T27 is electrically connected to the gate of transistor T21.

[0069]

[0070] Table 1

[0071] Table 2 like Figure 10 As shown in Tables 1 and 2, the entire driving cycle is divided into four main stages on the time axis, namely stage S1, stage S2, stage S3 and stage S4.

[0072] In phase S1, the reset phase, the previous-level scan signal SCAN(i-1) is in a low-level pulse state, initializing and resetting the key nodes of the pixel circuit. During phase S1, under the control of the previous-level scan signal line SCAN(i-1), the gates of the first transistor T2, the third transistor T8, and the fifth transistor T20 are reset to their initial voltages. Furthermore, under the control of the previous-level scan signal line SCAN(i-1), the voltage nodes in the second pulse width modulation control module PWM-Ctrl2 and the third pulse width modulation control module PWM-Ctrl3, namely the gates of the sixteenth transistor T14 and the twenty-sixth transistor T26, are reset to their initial voltages. During phase S1, the current-level scan signal SCAN(i), multiplexing control signals DEMUX1, DEMUX2, and DEMUX3 are all kept at a high level.

[0073] In phase S2, the data writing phase, the previous-level scan signal SCAN(i-1) transitions to a high level, and the multiplexing control signals DEMUX1, DEMUX2, and DEMUX3 sequentially exhibit low-level pulses. During phase S2, the data voltage is written to the first data signal line DATA_PAM_R, the green sub-pixel data signal line DATA_PWM_G, and the blue sub-pixel data signal line DATA_PWM_B in a time-division multiplexing manner through multiple selection switches of the demultiplexing circuit. During phase S2, the source driver temporarily stores the corresponding data voltage in the parasitic capacitances on the data signal lines through the demultiplexing circuit. During phase S2, the scan signal SCAN(i) remains high.

[0074] In stage S3, the threshold compensation and data writing stage, the current-stage scan signal SCAN(i) is in a low-level pulse state, which turns on the switching transistor in the pixel circuit, writing the pre-stored voltage on the data signal line into the pixel and completing the threshold voltage compensation of the driving transistor. In stage S3, the first, second, and third driving circuits are controlled by the current-stage scan signal line SCAN(i) to perform threshold compensation. In stage S3, the previous-stage scan signal SCAN(i-1) and the multiplexing control signal are both in a high-level state.

[0075] In stage S4, the emission stage, the scan signals SCAN(i-1) and SCAN(i) return to high level. In stage S4, the red sub-pixel emits light via the first emission control signal line EMA(i), the green sub-pixel (one of the two second sub-pixels) emits light via the first emission control signal line EMA(i) and the second emission control signal line EMW(i), and the blue sub-pixel (the other of the two second sub-pixels) emits light via the first emission control signal line EMA(i) and the second emission control signal line EMW(i). In stage S4, the red sub-pixel controls its brightness using pulse amplitude modulation (PAM), the green sub-pixel (one of the two second sub-pixels) controls its emission time using pulse width modulation (PWM), and the blue sub-pixel (the other of the two second sub-pixels) controls its emission duration using PWM. The first emission control signal EMA switches from high to low, the second emission control signal EMW jumps from high to low, and simultaneously, the voltage level of the ramp signal SWEEP(i) decreases linearly from high, forming a ramp waveform. In stage S4, the first pulse amplitude modulation control module PAM-Ctrl1 controls the driving current flowing through the first light-emitting diode LED1 based on the first data voltage; the second pulse amplitude modulation control module PAM-Ctrl2 controls the driving current flowing through the second light-emitting diode LED2 based on the global reference voltage from the first global signal line VREF_G; and the third pulse amplitude modulation control module PAM-Ctrl3 controls the driving current flowing through the third light-emitting diode LED3 based on the global reference voltage from the second global signal line VREF_B. In stage S4, a ramp signal is provided through the ramp signal line SWEEP(i). The ramp signal is compared with the second data voltage stored in the second driving circuit to control the light-emitting time of the green sub-pixel (one of the two second sub-pixels), and the ramp signal is compared with the third data voltage stored in the third driving circuit to control the light-emitting time of the blue sub-pixel (the other of the two second sub-pixels). The ramp signal is compared with the stored data voltage in the second pulse width modulation control module PWM-Ctrl2 and the third pulse width modulation control module PWM-Ctrl3 to control the light-emitting duration. Throughout the timing process, the first power line VDD, the initialization voltage line VI, the reference voltage line VRF, and the second power line VSS all maintain a constant voltage level.

[0076] During the operation of the pixel driving circuit for the red sub-pixel, in stage S1, the tenth transistor T6 is turned on, the seventh transistor T1 is in a pre-conduction state, the first transistor T2 is in a pre-conduction state, the second transistor T3 is turned off, the eighth transistor T4 is turned off, and the ninth transistor T5 is turned off. In stage S1, the gate voltage of the first transistor T2 is the initialization voltage VI. In stage S1, the gate of the first transistor T2 is reset. In stage S2, the tenth transistor T6 is turned off, the seventh transistor T1 is in a pre-conduction state, the first transistor T2 is in a pre-conduction state, the second transistor T3 is turned off, the eighth transistor T4 is turned off, and the ninth transistor T5 is turned off. In stage S2, the source driver sequentially writes the data voltage to the data signal line through the multiplexing / demultiplexing circuit, and the data voltage is pre-stored through the parasitic capacitance on the data signal line. In stage S3, the tenth transistor T6 is turned off, the seventh transistor T1 is in a pre-conduction state, the first transistor T2 is configured in a diode connection state, the second transistor T3 is turned off, the eighth transistor T4 is turned on, and the ninth transistor T5 is turned on. In stage S3, the gate voltage of the first transistor T2 is the voltage of the first data signal minus the threshold voltage of the first transistor T2. In stage S3, the pixel driving circuit completes threshold compensation, and the gate of the first transistor T2 completes threshold compensation. In stage S4, the seventh transistor T1 is turned on, the first transistor T2 is turned on, the second transistor T3 is turned on, the eighth transistor T4 is turned off, the ninth transistor T5 is turned off, and the tenth transistor T6 is turned off. In stage S4, the gate voltage of the first transistor T2 remains the voltage of the first data signal minus the threshold voltage of the first transistor T2. In stage S4, the first light-emitting diode LED1 emits light, and the driving current of the first light-emitting diode LED1 is K×W / L×(DATA_PAM_R-VDD)^2, where K is the transistor's process parameter, W is the channel width of the first transistor T2, L is the channel length of the first transistor T2, DATA_PAM_R is the voltage value of the first data signal, and VDD is the voltage value of the first power line.

[0077] During the operation of the pixel driving circuits for the green and blue sub-pixels, in stage S1, transistors T12 and T24 are turned on, transistors T8 and T20 are in a pre-conduction state, transistors T14 and T26 are in a pre-conduction state, and other transistors are turned off. In stage S1, the gate voltages of transistors T8 and T20 are reset to the initialization voltage VI, as are the gate voltages of transistors T14 and T26. In stage S2, the source driver sequentially writes the pulse width modulation (PWM) data voltage to the data signal lines via a multiplexer circuit. The PWM data voltage is pre-stored through parasitic capacitance on the data signal lines. In stage S2, the first global signal line VREF_G provides the first reference voltage, and the second global signal line VREF_B provides the second reference voltage. In phase S3, transistors T10 and T22 are turned on; transistors T8 and T20 are configured in a diode configuration; transistors T11 and T23 are turned on; transistors T16, T28, T17, and T29 are turned on. In phase S3, the gate voltage of transistor T8 is the first reference voltage minus its threshold voltage; the gate voltage of transistor T20 is the second reference voltage minus its threshold voltage. In phase S3, the gate voltage of transistor T14 is the initialization voltage plus the pulse width modulation data voltage minus its threshold voltage; the gate voltage of transistor T26 is the initialization voltage plus the pulse width modulation data voltage minus its threshold voltage. In stage S3, the pixel driving circuit completes threshold compensation, and the gates of the third transistor T8, the fifth transistor T20, the sixteenth transistor T14, and the twenty-sixth transistor T26 complete threshold compensation. In stage S4, the eleventh transistor T7, the fourth transistor T9, the fifteenth transistor T13, the seventeenth transistor T15, the twenty-first transistor T19, the sixth transistor T21, the twenty-fifth transistor T25, and the twenty-seventh transistor T27 are turned on. The third transistor T8 and the fifth transistor T20 are initially in the on state and then turned off.In the initial stage of S4, the second LED2 and the third LED3 emit light. The driving current of the second LED2 is K×W / L×(VREF_G-VDD)^2, and the driving current of the third LED3 is K×W / L×(VREF_B-VDD)^2, where K is the transistor's process parameter, W is the channel width of the third transistor T8 or the fifth transistor T20, L is the channel length of the third transistor T8 or the fifth transistor T20, VREF_G is the voltage value of the first global signal line, VREF_B is the voltage value of the second global signal line, and VDD is the voltage value of the first power supply line. In stage S4, as the voltage of the ramp signal SWEEP(i) decreases, the gate voltage of the sixteenth transistor T14 and the gate voltage of the twenty-sixth transistor T26 decrease synchronously. When the gate voltage of the sixteenth transistor T14 and the gate voltage of the twenty-sixth transistor T26 drop to the conduction threshold of the sixteenth transistor T14 and the twenty-sixth transistor T26, the sixteenth transistor T14 and the twenty-sixth transistor T26 begin to conduct. The voltage of the reference voltage line VRF is written to the gate of the third transistor T8 and the gate of the fifth transistor T20. The third transistor T8 and the fifth transistor T20 turn off, and the second light-emitting diode LED2 and the third light-emitting diode LED3 stop emitting light.

[0078] With the above technical solution, during the light-emitting stage, the light-emitting time of the red sub-pixel remains constant, and the brightness of the red sub-pixel is adjusted by changing the driving current flowing through the first light-emitting diode LED1. The driving current of the green sub-pixel and the blue sub-pixel remains constant, and the brightness of the green sub-pixel and the blue sub-pixel is adjusted by changing the light-emitting time.

[0079] like Figure 12 As shown, under the pulse width modulation driving mode, the peak current of the pixel unit during the light emission stage is relatively high. In this application, the peak current of the pixel unit during the light emission stage is relatively low. Figure 12The data includes two sets of bar charts. The first set represents the peak current of this application, and the second set represents the peak current of the pulse width modulation (PWM) driving method. At grayscale 255, the height of both the first and second bar charts is approximately 15 amps, essentially the same. At grayscale 224, the height of both bar charts is approximately 13 amps, and the height of the second bar chart is approximately 14.5 amps. At grayscale 192, the height of both bar charts is approximately 11 amps, and the height of the second bar chart is approximately 13.5 amps. At grayscale 128, the height of both bar charts is approximately 10 amps, and the height of the second bar chart is approximately 13 amps. At grayscale 96, the height of both bar charts is approximately 9.5 amps, and the height of the second bar chart is approximately 13 amps. At grayscale 64, the height of both bar charts is approximately 8 amps, and the height of the second bar chart is approximately 13 amps. Figure 12 It can be observed that the peak current of the pulse width modulation driving method remains relatively stable at a high value across all gray levels, while the peak current of this application shows a decreasing trend as the gray level decreases.

[0080] Figure 13 The line graph illustrates the reduction in peak current compared to the pulse width modulation (PWM) driving method, achieved using this application. At grayscale 255, the peak current reduction is approximately 0%. At grayscale 224, the reduction is approximately 13%. At grayscale 192, the reduction is approximately 17%. At grayscale 128, the reduction is approximately 23%. At grayscale 96, the reduction is approximately 27%. At grayscale 64, the reduction reaches approximately 38%. The line graph shows a clear upward trend, indicating that the lower the grayscale level, the greater the reduction in peak current.

[0081] Compared to pulse width modulation (PWM) driving methods, this application reduces peak current at low and medium grayscale levels. The peak current is reduced by approximately 23% at 128 grayscale and by approximately 38% at 64 grayscale. This reduction in peak current mitigates the stress impact of transient high current on the bonding area and wiring, thus lowering the probability of bonding area failure (e.g., ...). Figure 11 As shown, the risk of line burn-in in the bonding area of ​​the display device is reduced, the current distribution uniformity is improved, and the reliability of the display device is enhanced.

[0082] Since the red sub-pixel only includes the first pulse amplitude modulation control module PAM-Ctrl1, the number of transistors in the pixel driving circuit of the red sub-pixel is less than the number of transistors in the pixel driving circuit that includes both the second pulse amplitude modulation control module PAM-Ctrl2 and the second pulse width modulation control module PWM-Ctrl2. This reduces the area occupied by the pixel driving circuit of the red sub-pixel, increasing the usable space of the pixel. With increased usable space, the size of the driving transistors can be increased, the operating voltage of the driving transistors can be reduced, the number of transistors in the main current branch can be reduced, the power consumption and resistor-capacitor voltage drop of the display panel can be reduced, and display uniformity can be improved.

[0083] Under pulse amplitude modulation driving mode, due to the large fluctuation in the luminous efficiency of light-emitting diodes under low current conditions, green sub-pixels are prone to uneven brightness at medium and low gray levels. Figure 14 The uneven brightness of the green sub-pixels is shown in the pulse amplitude modulation driving mode. Figure 14 The display presents a bright green background with multiple dark spots distributed across it. These dark spots are irregular in shape, vary in size, and are randomly located throughout the display area. These dark spots represent the visual phenomenon of uneven brightness, reflecting the reduced uniformity of the display image and the resulting uneven brightness defect caused by the large fluctuations in the luminous efficiency of the LEDs under low current in pulse amplitude modulation driving mode.

[0084] Figure 15 The uneven brightness of the green sub-pixels is shown in this application. Figure 15 It presents a bright green background with high color uniformity. (And...) Figure 14 compared to, Figure 15 The green background is more uniform, the number of dark spots is significantly reduced, and the contrast of the remaining spots is lowered, thus reducing the visual impact. Figure 15 The high display uniformity indicates that, under this application, by using pulse width modulation driving method and fixing the current value for the green sub-pixels, the low current operating range is avoided, thereby effectively suppressing the brightness unevenness caused by fluctuations in luminous efficiency.

[0085] Compared to pulse amplitude modulation (PWM) driving methods, this application improves the brightness uniformity of green and blue sub-pixels. This application uses a pulse width modulation method with a fixed driving current for grayscale adjustment of the green and blue sub-pixels, ensuring that both green and blue LEDs operate under a fixed driving current. This avoids low-current operating ranges, reduces luminous efficiency fluctuations, and improves display uniformity at medium and low grayscale levels.

[0086] Compared to pulse amplitude modulation (PWM) driving, this application improves color point stability. Under PWM driving, the color point variations of red, green, and blue sub-pixels differ across different gray levels. The red sub-pixel's color point is relatively stable, while the green and blue sub-pixels exhibit larger variations across different gray levels. This application uses a pulse width modulation (PWM) method with a fixed driving current for gray level adjustment of the green and blue sub-pixels, ensuring stable emission wavelengths of the green and blue LEDs. This avoids the wavelength drift caused by driving current variations in PWM, thereby improving the color point stability of the green and blue sub-pixels across different gray levels.

[0087] like Figure 16 and Figure 17 As shown, this application improves the image ghosting phenomenon. Under pulse amplitude modulation (PWM) driving mode, after high current stress, the brightness of green and blue sub-pixels increases when lit with a small current, resulting in image ghosting of the green and blue sub-pixels. This application uses pulse width modulation with a fixed driving current for grayscale adjustment of the green and blue sub-pixels, significantly improving the image ghosting phenomenon and achieving better image ghosting performance than the PWM driving mode.

[0088] Figure 16 The image shows a comparison of two green backgrounds. The left image features a bright green background with several small dark spots observed in the center left and a few more in the center-right area. The right image also features a bright green background with a small dark spot in the upper left and another in the upper right corner. The overall brightness and color saturation of both images are roughly the same; while the locations of the dark spots differ, their numbers and contrast are similar.

[0089] Figure 17 The image shows a comparison of two deep blue images. The left image presents a uniform deep blue background with high color saturation and uniform overall brightness; no obvious brightness unevenness or color deviation was observed. The right image also presents a uniform deep blue background, and its color performance is basically consistent with the left image, with a uniform and stable overall display effect. Both images demonstrate the display performance of the blue subpixels under a specific driving method; the image uniformity is good, and no obvious ghosting, brightness unevenness, or other display defects are observed.

[0090] This application also provides a driving method for a display device. The display device includes a display panel, which includes multiple pixel units, each pixel unit including a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The red sub-pixel includes a first driving circuit and a first light-emitting diode (LED1). The first driving circuit includes a first pulse amplitude modulation control module (PAM-Ctrl1), a first transistor T2, and a second transistor T3. The input terminal of the first pulse amplitude modulation control module (PAM-Ctrl1) is electrically connected to a first data signal line DATA_PAM_R, and the output terminal of the first pulse amplitude modulation control module (PAM-Ctrl1) is electrically connected to the gate of the first transistor T2. The source of the first transistor T2 is electrically connected to a first power supply line VDD, the drain of the first transistor T2 is electrically connected to the source of the second transistor T3, the gate of the second transistor T3 is electrically connected to a first light-emitting control signal line EM, the drain of the second transistor T3 is electrically connected to the anode of the first light-emitting diode (LED1), and the cathode of the first light-emitting diode (LED1) is electrically connected to a second power supply line VSS. The green sub-pixel (one of the two second sub-pixels) includes a second driving circuit and a second light-emitting diode (LED2). The second driving circuit includes a second pulse amplitude modulation control module (PAM-Ctrl2), a second pulse width modulation control module (PWM-Ctrl2), a third transistor (T8), and a fourth transistor (T9). The input terminal of the second pulse amplitude modulation control module (PAM-Ctrl2) is electrically connected to the first global signal line VREF_G, and the output terminal of the second pulse amplitude modulation control module (PAM-Ctrl2) is electrically connected to the gate of the third transistor (T8). The source of the third transistor (T8) is electrically connected to the first power supply line VDD, and the drain of the third transistor (T8) is electrically connected to the source of the fourth transistor (T9). The input terminal of the second pulse width modulation control module (PWM-Ctrl2) is electrically connected to the second data signal line DATA_PWM_G, and the output terminal of the second pulse width modulation control module (PWM-Ctrl2) is electrically connected to the gate of the third transistor (T8) or the gate of the fourth transistor (T9). The drain of the fourth transistor (T9) is electrically connected to the anode of the second light-emitting diode (LED2), and the cathode of the second light-emitting diode (LED2) is electrically connected to the second power supply line VSS.The blue sub-pixel (the other of the two second sub-pixels) includes a third driving circuit and a third light-emitting diode (LED3). The third driving circuit includes a third pulse amplitude modulation control module (PAM-Ctrl3), a third pulse width modulation control module (PWM-Ctrl3), a fifth transistor (T20), and a sixth transistor (T21). The input terminal of the third pulse amplitude modulation control module (PAM-Ctrl3) is electrically connected to the second global signal line VREF_B. The output terminal of the third pulse amplitude modulation control module (PAM-Ctrl3) is electrically connected to the gate of the fifth transistor (T20). The source of the fifth transistor (T20) is electrically connected to the first power supply line VDD. The drain of the fifth transistor (T20) is electrically connected to the source of the sixth transistor (T21). The input terminal of the third pulse width modulation control module (PWM-Ctrl3) is electrically connected to the third data signal line DATA_PWM_B. The output terminal of the third pulse width modulation control module (PWM-Ctrl3) is electrically connected to the gate of the fifth transistor (T20) or the gate of the sixth transistor (T21). The drain of the sixth transistor (T21) is electrically connected to the anode of the third light-emitting diode (LED3). The cathode of the third light-emitting diode (LED3) is electrically connected to the second power supply line VSS.

[0091] The driving methods include: During the reset phase, under the control of the previous scan signal line SCAN(i-1), the gates of the first transistor T2, the third transistor T8, and the fifth transistor T20 are reset to the initial voltage.

[0092] During the data writing phase, a first data voltage is written to the first driving circuit through the first data signal line DATA_PAM_R, a second data voltage is written to the second driving circuit through the green sub-pixel data signal line DATA_PWM_G, and a third data voltage is written to the third driving circuit through the blue sub-pixel data signal line DATA_PWM_B.

[0093] During the threshold compensation stage, the first drive circuit, the second drive circuit, and the third drive circuit are controlled by the current stage scan signal line SCAN(i) to perform threshold compensation.

[0094] During the light emission phase, the red sub-pixel is controlled to emit light through the first light emission control signal line EMA(i), the green sub-pixel (one of the two second sub-pixels) is controlled to emit light through the first light emission control signal line EMA(i) and the second light emission control signal line EMW(i), and the blue sub-pixel (the other of the two second sub-pixels) is controlled to emit light through the first light emission control signal line EMA(i) and the second light emission control signal line EMW(i).

[0095] In the driving method, the display device receives display data, which includes red grayscale data, green grayscale data, and blue grayscale data. The timing controller receives the display data and transmits the display data to the source driver. The source driver generates a first data signal based on the red grayscale data and applies it to the first data signal line DATA_PAM_R. The source driver generates a second data signal based on the green grayscale data and applies it to the second data signal line DATA_PWM_G. The source driver generates a third data signal based on the blue grayscale data and applies it to the third data signal line DATA_PWM_B. A first reference voltage is applied to the first global signal line VREF_G, and a second reference voltage is applied to the second global signal line VREF_B.

[0096] Within one display cycle, the gate drive circuit sequentially outputs scan signals to the scan signal lines to select pixel units line by line. For red sub-pixels, the first pulse amplitude modulation control module PAM-Ctrl1 generates a first control signal based on the first data signal. The first control signal controls the conduction level of the first transistor T2. The second transistor T3 is turned on under the control of the first light emission control signal provided by the first light emission control signal line EMA(i). The first transistor T2 and the second transistor T3 provide driving current to the first light-emitting diode LED1, and the magnitude of the driving current is determined by the conduction level of the first transistor T2.

[0097] For the green sub-pixel (one of the two second sub-pixels), the second pulse amplitude modulation control module PAM-Ctrl2 generates a second control signal based on the first reference voltage. This second control signal controls the conduction level of the third transistor T8, keeping it constant. The second pulse width modulation control module PWM-Ctrl2 generates a third control signal based on the second data signal. This third control signal controls the conduction time of the fourth transistor T9. The third transistor T8 and the fourth transistor T9 provide driving current to the second light-emitting diode LED2. The magnitude of the driving current remains constant, and the light-emitting time is determined by the conduction time of the fourth transistor T9.

[0098] For the blue sub-pixel (the other of the two second sub-pixels), the third pulse amplitude modulation control module PAM-Ctrl3 generates a fourth control signal based on the second reference voltage. This fourth control signal controls the conduction level of the fifth transistor T20, keeping it constant. The third pulse width modulation control module PWM-Ctrl3 generates a fifth control signal based on the third data signal. This fifth control signal controls the conduction time of the sixth transistor T21. The fifth transistor T20 and the sixth transistor T21 provide driving current to the third light-emitting diode LED3. The magnitude of this driving current remains constant, and the light-emitting time is determined by the conduction time of the sixth transistor T21.

[0099] Using the above driving method, the red sub-pixel achieves grayscale adjustment by adjusting the magnitude of the driving current, while the green and blue sub-pixels achieve grayscale adjustment by adjusting the emission time, thereby realizing differentiated driving control for sub-pixels of different colors.

[0100] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, the display panel includes a plurality of pixel units, and the pixel units include: A first sub-pixel includes a first driving circuit and a first light-emitting diode (LED). The first driving circuit includes a first pulse amplitude modulation control module, a first transistor, and a second transistor. The input terminal of the first pulse amplitude modulation control module is electrically connected to a first data signal line, the output terminal of the first pulse amplitude modulation control module is electrically connected to the gate of the first transistor, the source of the first transistor is electrically connected to a first power supply line, the drain of the first transistor is electrically connected to the source of the second transistor, the gate of the second transistor is electrically connected to a first light emission control signal line, the drain of the second transistor is electrically connected to the anode of the first LED, and the cathode of the first LED is electrically connected to a second power supply line. At least one second sub-pixel, the second sub-pixel including a second driving circuit and a second light-emitting diode, the second driving circuit including a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor and a fourth transistor, the input terminal of the second pulse amplitude modulation control module being electrically connected to a global signal line, the output terminal of the second pulse amplitude modulation control module being electrically connected to the gate of the third transistor, the source of the third transistor being electrically connected to a first power supply line, the drain of the third transistor being electrically connected to the source of the fourth transistor, the input terminal of the second pulse width modulation control module being electrically connected to a second data signal line, the output terminal of the second pulse width modulation control module being electrically connected to the gate of the third transistor or the gate of the fourth transistor, the drain of the fourth transistor being electrically connected to the anode of the second light-emitting diode, and the cathode of the second light-emitting diode being electrically connected to the second power supply line.

2. The display device according to claim 1, characterized in that, The first pulse amplitude modulation control module includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor. The gate of the seventh transistor is electrically connected to the first light emission control signal line, the source of the seventh transistor is electrically connected to the first power supply line, and the drain of the seventh transistor is electrically connected to the source of the first transistor. The gate of the eighth transistor is electrically connected to the first scan signal line, the source of the eighth transistor is electrically connected to the first data signal line, and the drain of the eighth transistor is electrically connected to the drain of the first transistor. The gate of the ninth transistor is electrically connected to the first scan signal line, the source of the ninth transistor is electrically connected to the drain of the first transistor, and the drain of the ninth transistor is electrically connected to the gate of the first transistor. The gate of the tenth transistor is electrically connected to the second scan signal line, the source of the tenth transistor is electrically connected to the initialization voltage line, and the drain of the tenth transistor is electrically connected to the gate of the first transistor. The first plate of the first capacitor is electrically connected to the first power supply line, and the second plate of the first capacitor is electrically connected to the gate of the first transistor.

3. The display device according to claim 1, characterized in that, The second pulse amplitude modulation control module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a second capacitor. The gate of the eleventh transistor is electrically connected to the first light emission control signal line, the source of the eleventh transistor is electrically connected to the first power supply line, and the drain of the eleventh transistor is electrically connected to the source of the third transistor. The gate of the twelfth transistor is electrically connected to the first scan signal line, the source of the twelfth transistor is electrically connected to the global signal line, and the drain of the twelfth transistor is electrically connected to the source of the third transistor. The gate of the thirteenth transistor is electrically connected to the first scan signal line, the source of the thirteenth transistor is electrically connected to the drain of the third transistor, and the drain of the thirteenth transistor is electrically connected to the gate of the third transistor. The gate of the fourteenth transistor is electrically connected to the second scan signal line, the source of the fourteenth transistor is electrically connected to the initialization voltage line, and the drain of the fourteenth transistor is electrically connected to the gate of the third transistor. The first plate of the second capacitor is electrically connected to the first power supply line, and the second plate of the second capacitor is electrically connected to the gate of the third transistor.

4. The display device according to claim 3, characterized in that, The second pulse width modulation control module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a third capacitor. The gate of the eighteenth transistor is electrically connected to the first scan signal line, the source of the eighteenth transistor is electrically connected to the second data signal line, and the drain of the eighteenth transistor is electrically connected to the drain of the fifteenth transistor. The gate of the twentieth transistor is electrically connected to the second scan signal line, the source of the twentieth transistor is electrically connected to the initialization voltage line, and the drain of the twentieth transistor is electrically connected to the gate of the sixteenth transistor. The first plate of the third capacitor is electrically connected to the ramp signal line, and the second plate of the third capacitor... The electrode plate is electrically connected to the gate of the sixteenth transistor, the source of the sixteenth transistor is electrically connected to the drain of the fifteenth transistor, the drain of the sixteenth transistor is electrically connected to the source of the seventeenth transistor, the gate of the nineteenth transistor is electrically connected to the first scan signal line, the source of the nineteenth transistor is electrically connected to the drain of the sixteenth transistor, the drain of the nineteenth transistor is electrically connected to the gate of the sixteenth transistor, the gate of the fifteenth transistor is electrically connected to the second light emission control signal line, the source of the fifteenth transistor is electrically connected to the reference voltage line, the gate of the seventeenth transistor is electrically connected to the second light emission control signal line, and the drain of the seventeenth transistor is electrically connected to the gate of the fourth transistor.

5. The display device according to claim 1, characterized in that, The first sub-pixel is a red sub-pixel, and at least one second sub-pixel includes a green sub-pixel and / or a blue sub-pixel. The global signal line corresponding to the green sub-pixel is a first global signal line, and the second data signal line corresponding to the green sub-pixel is a green sub-pixel data signal line. The global signal line corresponding to the blue sub-pixel is a second global signal line, and the second data signal line corresponding to the blue sub-pixel is a blue sub-pixel data signal line.

6. The display device according to claim 5, characterized in that, The display device further includes a source driver and a multiplexing / demultiplexing circuit. The multiplexing / demultiplexing circuit includes multiple sets of selection switches. Each set of selection switches includes a first selection switch, a second selection switch, and a third selection switch. The gate of the first selection switch is electrically connected to a first control line, and the drain of the first selection switch is electrically connected to a first data signal line. The gate of the second selection switch is electrically connected to a second control line, and the drain of the second selection switch is electrically connected to the green sub-pixel data signal line. The gate of the third selection switch is electrically connected to a third control line, and the drain of the third selection switch is electrically connected to the blue sub-pixel data signal line. The sources of the first selection switch, the second selection switch, and the third selection switch are all connected to the same data output port of the source driver.

7. A driving method for a display device, characterized in that, The display device includes a display panel, which includes a plurality of pixel units. Each pixel unit includes a first sub-pixel and at least one second sub-pixel. The first sub-pixel includes a first driving circuit and a first light-emitting diode (LED). The first driving circuit includes a first pulse amplitude modulation control module, a first transistor, and a second transistor. The input terminal of the first pulse amplitude modulation control module is electrically connected to a first data signal line, and the output terminal of the first pulse amplitude modulation control module is electrically connected to the gate of the first transistor. The source of the first transistor is electrically connected to a first power supply line, and the drain of the first transistor is electrically connected to the source of the second transistor. The gate of the second transistor is electrically connected to a first light-emitting control signal line, and the drain of the second transistor is electrically connected to the anode of the first LED. The cathode of the first LED is electrically connected to a second power supply line. The pixel includes a second driving circuit and a second light-emitting diode. The second driving circuit includes a second pulse amplitude modulation control module, a second pulse width modulation control module, a third transistor, and a fourth transistor. The input terminal of the second pulse amplitude modulation control module is electrically connected to the global signal line, and the output terminal of the second pulse amplitude modulation control module is electrically connected to the gate of the third transistor. The source of the third transistor is electrically connected to the first power supply line, and the drain of the third transistor is electrically connected to the source of the fourth transistor. The input terminal of the second pulse width modulation control module is electrically connected to the second data signal line, and the output terminal of the second pulse width modulation control module is electrically connected to the gate of the third transistor or the gate of the fourth transistor. The drain of the fourth transistor is electrically connected to the anode of the second light-emitting diode, and the cathode of the second light-emitting diode is electrically connected to the second power supply line. The driving method includes: During the reset phase, under the control of the second scan signal line, the gates of the first transistor and the third transistor are reset to the initial voltage; During the data writing phase, a first data voltage is written to the first driving circuit through the first data signal line, and a second data voltage is written to the second driving circuit through the second data signal line. During the threshold compensation stage, the first driving circuit and the second driving circuit are controlled by the first scan signal line to perform threshold compensation. During the light emission stage, the first sub-pixel is controlled to emit light through the first light emission control signal line, and the second sub-pixel is controlled to emit light through the first light emission control signal line and the second light emission control signal line.

8. The driving method according to claim 7, characterized in that, The first sub-pixel is a red sub-pixel, and at least one second sub-pixel includes a green sub-pixel and / or a blue sub-pixel. The second data signal line corresponding to the green sub-pixel is a green sub-pixel data signal line, and the second data signal line corresponding to the blue sub-pixel is a blue sub-pixel data signal line.

9. The driving method according to claim 8, characterized in that, The driving method further includes: During the data writing phase, the data voltage is written to the first data signal line, the green sub-pixel data signal line, and the blue sub-pixel data signal line in a time-division manner through multiple sets of selection switches of the multiplexed circuit.

10. The driving method according to claim 7, characterized in that, During the light-emitting phase, the light-emitting time of the first sub-pixel remains constant, and the brightness of the first sub-pixel is adjusted by changing the driving current flowing through the first light-emitting diode. The driving current of the second sub-pixel remains constant, and the brightness of the second sub-pixel is adjusted by changing the light-emitting time.

11. The driving method according to claim 7, characterized in that, During the light-emitting phase, the first pulse amplitude modulation control module controls the magnitude of the driving current flowing through the first light-emitting diode according to the first data voltage, and the second pulse amplitude modulation control module controls the magnitude of the driving current flowing through the second light-emitting diode according to the global reference voltage from the global signal line.

12. The driving method according to claim 7, characterized in that, The driving method further includes: During the light emission stage, a ramp signal is provided through a ramp signal line, and the ramp signal is compared with the second data voltage stored in the second driving circuit to control the light emission time of the second sub-pixel.

Images