Comparator and decision feedback equalization circuit

Abstract

The application provides a comparator and a decision feedback equalization circuit, comprising a first input circuit, which is used for generating a first differential signal according to an input signal and a first reference signal under the control of a control signal; a first positive feedback circuit, which is used for accelerating the difference between the first differential signal; a second input circuit, which is used for generating a second differential signal according to the input signal and a second reference signal under the control of the control signal; wherein the first reference signal is greater than the second reference signal; a second positive feedback circuit, which is used for accelerating the difference between the second differential signal; and an output circuit, which is connected with the output end of the first input circuit and is used for amplifying and latching the voltage signal of the output end of the first input circuit or the voltage signal of the output end of the second input circuit in a regeneration stage to output a comparison result. The response rate of the comparator in the application is high, the power consumption is small, the working voltage is low and the inter-symbol interference can be eliminated.

Description

Technical Field

[0001] This application relates to integrated circuits, and more particularly to a comparator and a decision feedback equalization circuit. Background Technology

[0002] Today, people's demand for mobile devices such as smartphones, tablets, and various wearable accessories has increased significantly, greatly enriching our daily lives and work.

[0003] However, due to limited battery life, higher demands are placed on the power consumption of various components in mobile devices. Dynamic Random Access Memory (DRAM) is an essential component in mobile devices, therefore, DRAM also urgently needs to achieve lower operating voltage and lower power consumption. Among these, the comparator is a crucial device for realizing DRAM data read and write operations, and existing comparators cannot meet current usage requirements. Summary of the Invention

[0004] This application provides a comparator and a decision feedback equalization circuit, which aims to improve the comparator's response rate, reduce its power consumption, lower its operating voltage, and eliminate inter-symbol interference.

[0005] In a first aspect, this application provides a comparator, comprising:

[0006] The first input circuit has an output terminal, which is used to generate a first differential signal based on the input signal and the first reference signal under the control of the control signal.

[0007] The first positive feedback circuit is connected to the output of the first input circuit and is used to accelerate the difference between the first differential signals.

[0008] The second input circuit has an output terminal connected to the output terminal of the first input circuit. It is used to generate a second differential signal based on the input signal and the second reference signal under the control of the control signal. The first reference signal is greater than the second reference signal.

[0009] The second positive feedback circuit is connected to the output of the second input circuit and is used to accelerate the difference between the second differential signals.

[0010] The output circuit has an input terminal connected to the output terminal of the first input circuit. It is used to amplify and latch the voltage signal at the output terminal of the first input circuit or the voltage signal at the output terminal of the second input circuit during the regeneration phase, so as to output the comparison result.

[0011] In a second aspect, this application provides a decision feedback equalization circuit, including four comparators involved in the first aspect and optional schemes, which are sequentially labeled as a first comparator, a second comparator, a third comparator and a fourth comparator;

[0012] The first comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal connected to the output terminal of the fourth comparator for receiving a control signal.

[0013] The second comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal connected to the output terminal of the first comparator for receiving a control signal.

[0014] The third comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal connected to the output terminal of the second comparator for receiving a control signal.

[0015] The fourth comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal connected to the output terminal of the third comparator for receiving a control signal.

[0016] The comparator and decision feedback equalization circuit provided in this application embodiment includes a first input circuit, a second input circuit, and an output circuit. The first input circuit generates a first differential signal based on an input signal and a first reference signal under the control of a first control signal and a second control signal. The second input circuit generates a second differential signal based on the input signal and the second reference signal under the control of the first and second control signals. When inter-symbol interference (ISI) exists at the input of the comparator, affecting the value of the input signal and thus affecting the accurate output of the differential signal by the input circuit, the first reference signal is greater than the second reference signal. Based on the ISI, the first and second control signals are generated, and they control the operation of either the first or second input circuit, ensuring that the output circuit receives an accurate differential signal, thereby eliminating ISI interference in the comparator. The comparator also includes a first positive feedback circuit and a second positive feedback circuit. The first positive feedback circuit accelerates the difference between the first and second differential signals, and the second positive feedback circuit accelerates the difference between the second and third differential signals, shortening the time for the first and second input circuits to generate the differential signal, thereby reducing the power consumption of the comparator. Attached Figure Description

[0017] Figure 1The specific circuit diagram of the comparator provided in this application;

[0018] Figure 2 The timing diagram of the comparator provided in this application;

[0019] Figure 3 A structural block diagram of a comparator provided in this application;

[0020] Figure 4 For based on Figure 3 A specific circuit diagram of the provided comparator;

[0021] Figure 5 A specific circuit diagram of a first input circuit provided in this application;

[0022] Figure 6 A specific circuit diagram of a second input circuit provided in this application;

[0023] Figure 7 For based on Figure 3 Another specific circuit diagram of the provided comparator;

[0024] Figure 8 A specific circuit diagram of a comparator provided in this application;

[0025] Figure 9 A structural block diagram of another comparator provided in this application;

[0026] Figure 10 For based on Figure 9 A specific circuit diagram of one type of comparator is provided;

[0027] Figure 11 for Figure 10 The specific circuit diagram of the controllable feedback module in the provided comparator;

[0028] Figure 12 For based on Figure 9 A specific circuit diagram of one type of comparator is provided;

[0029] Figure 13 for Figure 12 The specific circuit diagram of the controllable feedback module in the provided comparator;

[0030] Figure 14 A block diagram of a decision feedback equalization circuit provided in this application;

[0031] Figure 15 The timing diagram of the decision feedback equalization circuit provided in this application. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] like Figure 1 As shown, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

[0034] The input circuit 101 includes transistors N1, N2, and N3. Transistors N1 and N2 form a differential transistor pair. The gates of transistors N1 and N2 form the first input terminal IN and the second input terminal IN of the input circuit. The drains of transistors N1 and N2 form the two output terminals of the input circuit.

[0035] The output circuit 102 includes transistors P1, P2, N4, and N5, which form a cross-coupled transistor pair. The drains of transistors P1 and N4 form the first output terminal ON of the output circuit 102, and the drains of transistors P2 and N5 form the second output terminal OP of the output circuit 102. The reset circuit 103 includes transistors P3 and P4.

[0036] The comparator's operation consists of four stages: reset, sampling, regeneration, and decision. The following section will discuss these stages in conjunction with... Figure 2 describe Figure 1 The working process of the comparator shown is as follows:

[0037] During the reset phase, from time t0 to time t1, the clock signal is low, transistor N3 is open, the input and output circuits stop working, transistors P3 and P4 are closed, the reset circuit works, and pulls the drain voltage of transistor N4 and the drain voltage of transistor N5 to high level.

[0038] During the sampling phase, from time t1 to t2, the clock signal is high, transistors P3 and P4 are open, and the reset circuit stops working. Transistor N3 is closed, and the input circuit acquires the input signal through the first input terminal IN and the reference signal through the second input terminal IN. The input signal pulls down the drain voltage of transistor N1, and the reference signal pulls down the drain voltage of transistor N2. The drain of transistor N1 pulls down the drain voltage of transistor N4, and the drain of transistor N2 pulls down the drain voltage of transistor N5. Because the input signal is higher than the reference signal, the rate at which the input signal pulls down the drain voltage of transistor N1 is faster, resulting in the drain voltage of transistor N4 being lower than that of transistor N5.

[0039] During the regeneration phase, from time t2 to t3, the drain voltages of transistor N4 and N5 reach the flip voltage, transistors P2 and N4 are turned on, while transistors P1 and N5 are gradually turned off. Transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

[0040] During the decision-making phase, from time t3 to t4, transistors P2 and N4 are turned on, while transistors P1 and N5 are turned off. The drain voltage of transistor N5 continues to be pulled up, and the drain voltage of transistor N4 continues to be pulled down. After pulling the drain of transistor N5 to a low level and the drain voltage of transistor N4 to a high level, the drain voltages of transistors N4 and N5 are maintained.

[0041] When the next working cycle arrives, the clock signal goes low, and the drain voltages of transistors N4 and N5 are reset to high by transistors P1 and P2.

[0042] like Figure 3 As shown, one embodiment of this application provides a comparator with four input terminals and two output terminals. The four input terminals of the comparator are sequentially labeled as the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal. The two output terminals of the comparator are sequentially labeled as the first output terminal and the second output terminal. The comparator includes a first input circuit 201, a second input circuit 202, a first positive feedback circuit 203, a second positive feedback circuit 204, and an output circuit 205.

[0043] The first input circuit 201 has three input terminals and two output terminals, and the second input circuit 202 also has three input terminals and two output terminals. The first input terminals of the first input circuit 201 and the second input circuit 202 serve as the first input terminals of a comparator, used to receive input signals. The second input terminal of the first input circuit 201 serves as the second input terminal of the comparator, used to receive a first reference signal. The second input terminal of the second input circuit 202 serves as the third input terminal of the comparator, used to receive a second reference signal. The third input terminals of the first input circuit 201 and the second input circuit 202 serve as the fourth input terminals of the comparator, used to receive control signals.

[0044] The output circuit 205 also has two input terminals and two output terminals. The first output terminal of the first input circuit 201 and the first output terminal of the second input circuit 202 are connected to the first input terminal of the output circuit 205. The second output terminal of the first input circuit 201 and the second output terminal of the second input circuit 202 are connected to the second input terminal of the output circuit 205. The two output terminals of the output circuit 205 serve as the two output terminals of the comparator.

[0045] After receiving the input signal, the first reference signal, and the control signal, the three input terminals of the first input circuit 201 generate a first differential signal based on the input signal and the first reference signal during the sampling phase under the control signal. After receiving the input signal, the second reference signal, and the control signal, the two input terminals of the second input circuit 202 generate a second differential signal based on the input signal and the second reference signal during the sampling phase under the control signal. The first reference signal is greater than the second reference signal.

[0046] The first differential signal and the second differential signal are a pair of voltage signals. The first positive feedback circuit 203 is used to accelerate the difference between the first differential signal and the second positive feedback circuit 204 is used to accelerate the difference between the second differential signal. The first input circuit 201 is also used to output the accelerated first differential signal, and the second input circuit 202 is also used to output the accelerated second differential signal. The output circuit 205 is used to amplify and latch the voltage signal at the output of the first input circuit 201 or the voltage signal at the output of the second input circuit 202 during the regeneration phase, so as to output the comparison result through the two output terminals.

[0047] If the comparator's output was "0" in the previous moment, and the current input signal is relatively large, inter-symbol interference (ISI) will cause the input signal value to decrease, and the amplitude of this change will be significant. In this case, the control signal will activate the second input circuit. This means that the second input circuit will output a differential signal at its two outputs based on the smaller second reference signal and the similarly decreased input signal. This ensures that the polarity of the output differential signal is the same as the polarity of the generated differential signal, assuming no ISI. If the current input signal is relatively small, and ISI has a smaller impact on the input signal, then the second input circuit will still operate, maintaining the polarity of the differential signal.

[0048] If the comparator's output was "1" in the previous time step, and the current input signal is relatively small, inter-symbol interference (ISI) will cause the input signal value to increase significantly, with a large amplitude effect. In this case, the control signal will activate the first input circuit. This means that based on the larger first reference signal and the similarly increased input signal, the first input circuit will output differential signals at its two output terminals. This ensures that the polarity of the output differential signals is the same as the polarity of the generated differential signals, assuming no ISI. If the current input signal is relatively large, and ISI has a significant impact on the input signal, then the first input circuit will still operate, maintaining the polarity of the differential signals.

[0049] If a differential signal is output from the second input circuit, the polarity of the differential signal refers to the magnitude of the signals at the first and second output terminals of the second input circuit. By ensuring that the polarity of the differential signal with inter-symbol interference is the same as that of the differential signal without inter-symbol interference, the output circuit can accurately output the comparison result after amplifying and latching the differential signal.

[0050] When the first reference signal is not properly selected, the response time of the first input circuit 201 becomes longer, meaning that the first input circuit 201 needs a longer time to present a first differential signal with a relatively large difference at the output. The first positive feedback circuit 203 accelerates the difference between the first differential signals through a positive feedback mechanism, thereby reducing the time it takes for the first input circuit 201 to present a first differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thus improving the comparator's response rate and reducing its power consumption.

[0051] Similarly, when the second reference signal is not properly selected, the response time of the second input circuit 202 becomes longer, meaning that the second input circuit 202 needs a longer time to present a second differential signal with a relatively large difference at the output. The second positive feedback circuit 204 accelerates the difference between the second differential signals through a positive feedback mechanism, thereby reducing the time that the second input circuit 202 presents a second differential signal with a relatively large difference at the output, which shortens the time the comparator is in the sampling phase, thereby improving the comparator's response rate and reducing its power consumption.

[0052] In one embodiment, the first positive feedback circuit 203 includes a first feedback unit 2031 and a second feedback unit 2032, both of which are provided with a control terminal and a first terminal.

[0053] The control terminal of the first feedback unit 2031 is connected to the first output terminal of the first input circuit 201, and the first end of the first feedback unit 2031 is connected to the second output terminal of the first input circuit 201. The control terminal of the second feedback unit 2032 is connected to the second output terminal of the first input circuit 201, and the first end of the second feedback unit 2032 is connected to the first output terminal of the first input circuit 201.

[0054] The first feedback unit 2031 is used to pull the voltage of the second output terminal of the first input circuit 201 according to the voltage of the first output terminal of the first input circuit 201 during the sampling phase, and the second feedback unit 2032 is used to pull the voltage of the first output terminal of the first input circuit 201 according to the voltage of the second output terminal of the first input circuit 201 during the sampling phase.

[0055] The direction in which the first feedback unit 2031 pulls the voltage at the second output terminal of the first input circuit 201 is the same as the direction in which the second feedback unit 2032 pulls the voltage at the first output terminal of the first input circuit 201. When the first feedback unit 2031 pulls the voltage at the second output terminal of the first input circuit 201 upwards, the second feedback unit 2032 also pulls the voltage at the first output terminal of the first input circuit 201 upwards. When the first feedback unit 2031 pulls the voltage at the second output terminal of the first input circuit 201 downwards, the second feedback unit 2032 also pulls the voltage at the first output terminal of the first input circuit 201 downwards.

[0056] In one embodiment, the second positive feedback circuit 204 includes a third feedback unit 2041 and a fourth feedback unit 2042, both of which have a control terminal and a first terminal.

[0057] The control terminal of the third feedback unit 2041 is connected to the first output terminal of the second input circuit 202, and the first terminal of the third feedback unit 2041 is connected to the second output terminal of the second input circuit 202. The control terminal of the fourth feedback unit 2042 is connected to the second output terminal of the second input circuit 202, and the first terminal of the fourth feedback unit 2042 is connected to the first output terminal of the second input circuit 202.

[0058] The third feedback unit 2041 is used to pull the voltage of the second output terminal of the second input circuit 202 according to the voltage of the first output terminal of the second input circuit 202 during the sampling phase, and the fourth feedback unit 2042 is used to pull the voltage of the first output terminal of the second input circuit 202 according to the voltage of the second output terminal of the second input circuit 202 during the sampling phase.

[0059] The third feedback unit 2041 pulls the voltage at the second output terminal of the second input circuit 202 in the same direction as the fourth feedback unit 2042 pulls the voltage at the first output terminal of the second input circuit 202. When the third feedback unit 2041 pulls the voltage at the second output terminal of the second input circuit 202 upwards, the fourth feedback unit 2042 also pulls the voltage at the first output terminal of the second input circuit 202 upwards. When the third feedback unit 2041 pulls the voltage at the second output terminal of the second input circuit 202 downwards, the fourth feedback unit 2042 also pulls the voltage at the first output terminal of the second input circuit 202 downwards.

[0060] The following example illustrates the effect of pulling down the voltage of the two output terminals of the first input circuit 201: When the voltage of the first output terminal of the first input circuit 201 is higher than the voltage of the second output terminal of the first input circuit 201, the first feedback unit 2031 has a stronger ability to pull down the voltage of the second output terminal of the first input circuit 201, while the second feedback unit 2032 has a weaker ability to pull down the voltage of the first output terminal of the first input circuit 201. In other words, the voltage drop rate of the first output terminal is lower than that of the second output terminal, thereby making the voltage difference between the first output terminal and the second output terminal increasingly larger, thus achieving positive feedback.

[0061] The following example illustrates the effect of pulling up the voltage of the two output terminals of the first input circuit 201: When the voltage of the first output terminal of the first input circuit 201 is higher than the voltage of the second output terminal of the first input circuit 201, the first feedback unit 2031 has a weaker ability to pull up the voltage of the second output terminal of the first input circuit 201, while the second feedback unit 2032 has a stronger ability to pull up the voltage of the first output terminal of the first input circuit 201. In other words, the voltage rise rate of the first output terminal is higher than that of the second output terminal, which in turn makes the voltage difference between the first output terminal and the second output terminal larger and larger, thus achieving positive feedback.

[0062] In the above technical solution, when any one or both of the first reference signal and the second reference signal are not properly selected, it takes a relatively long time to generate a differential signal with a large difference in the corresponding input circuit. The positive feedback circuit in the corresponding input circuit accelerates the difference through the positive feedback mechanism after there is a slight difference between the two output terminals of the input circuit, shortens the sampling stage time, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

[0063] In one embodiment, the first input circuit includes a first sampling unit and a first control unit. The first control unit is connected to the first sampling unit. The first sampling unit is used to receive an input signal and a first reference signal. The first sampling unit is also used to generate a first differential signal based on the input signal and the first reference signal. The first control unit is used to receive a control signal and is also used to control whether the first sampling unit operates based on the control signal. That is, to control whether the first sampling unit outputs the first differential signal.

[0064] In one embodiment, the second input circuit includes a second sampling unit and a second control unit. The second control unit is connected to the second sampling unit. The second sampling unit receives an input signal and a second reference signal, and generates a second differential signal based on the input signal and the second reference signal. The second control unit receives a control signal and controls whether the second sampling unit operates based on the control signal, that is, whether the second sampling unit outputs the second differential signal.

[0065] When the first control unit controls the first sampling unit to operate, the second control unit controls the second sampling unit to operate. That is, the first input circuit outputs a first differential signal, and the output circuit amplifies and latches the first differential signal to output the comparison result. When the first control unit controls the first sampling unit to operate, the second control unit controls the second sampling unit to operate. That is, when the second input circuit outputs a second differential signal, the output circuit amplifies and latches the second differential signal to output the comparison result.

[0066] If the comparator outputs a digit "1", the first sampling unit can be controlled to work while the second sampling unit is not working. That is, the first differential signal is generated based on the input signal with a larger value and the first reference signal with a larger value, or the input signal with a relatively large value and a relatively large first reference signal. This ensures that the polarity of the generated differential signal is the same as the polarity of the differential signal output when there is no inter-symbol interference, thereby eliminating the influence of inter-symbol interference on the comparator's output result.

[0067] If the comparator outputs a digit "0", the first sampling unit can be deactivated while the second sampling unit is activated. This means that the second differential signal is generated based on the input signal with a smaller value and the second reference signal with a smaller value, or the input signal with a smaller value and a smaller value and the second reference signal with a smaller value. This ensures that the polarity of the generated differential signal is the same as that of the differential signal output when there is no inter-symbol interference, thereby eliminating the influence of inter-symbol interference on the comparator's output.

[0068] In the above technical solution, the operation of the first sampling unit or the second sampling unit is controlled according to the influence of inter-symbol interference on the input signal, so as to ensure that the polarity of the differential signal generated by the presence of inter-symbol interference is the same as that of the differential signal generated without inter-symbol interference. Then, the output circuit amplifies and latches the differential signal and outputs the comparison result so that the comparator can accurately output the comparison result.

[0069] Figure 4 A circuit diagram of a comparator provided in another embodiment of this application is shown below. Figure 4 As shown, the comparator provided in this application includes a first input circuit, a second input circuit 202, a first positive feedback circuit 203, a second positive feedback circuit 204, and an output circuit 205.

[0070] The first input circuit includes a first acquisition circuit 2011 and a first control unit 2012. The first acquisition circuit 2011 includes a first input transistor N1, a second input transistor N2, and a third input transistor N3. The control terminal of the first input transistor N1 serves as the first input terminal of the first input circuit, receiving an input signal, and its first terminal serves as the first output terminal. The control terminal of the second input transistor N2 serves as the second input terminal of the first input circuit, receiving a first reference signal, and its first terminal serves as the second output terminal. The first terminal of the third input transistor N3 is connected to the second terminals of both the first and second input transistors N1 and N2, and its second terminal is connected to ground. The control terminal of the third input transistor N3 is connected to the first control unit 2012.

[0071] The control terminal of the first input transistor N1 receives the input signal, and the control terminal of the second input transistor N2 receives the first reference signal. After the input signal and the first reference signal are amplified by the first input transistor N1 and the second input transistor N2, a first differential signal is generated at the first terminal of the first input transistor N1 and the first terminal of the second input transistor N2.

[0072] In one embodiment, reference continues Figure 4 The first control unit 2012 includes a first control transistor N13. Control signals include a first control signal CO and a second control signal COB. The second terminal of the first control transistor N13 is connected to the control terminal of the third input transistor N3. The first terminal of the first control transistor N13 receives a clock signal CLK, and the control terminal receives the first control signal CO. The first control transistor N13 generates a signal based on the clock signal CLK and the first control signal CO to control the third input transistor N3 to be turned on or off, thereby enabling the first control unit to control whether the first sampling unit operates, that is, to control whether the first sampling unit outputs a first differential signal based on the input signal and the first reference signal.

[0073] In one embodiment, such as Figure 5 As shown, the first terminal is used to receive the clock signal, and the second terminal is connected to the control terminal of the third input transistor, which is used to turn on or off under the control of the first control signal CO. When the first transmission G1 is turned on, the clock signal CLK can control the conduction or cutoff of the third input transistor N3, thereby realizing the control of the first control unit to control whether the first sampling unit works.

[0074] The second input circuit includes a second acquisition circuit 2021 and a second control unit 2022. The first acquisition circuit 2021 includes a fourth input transistor N4, a fifth input transistor N5, and a sixth input transistor N6. The control terminal of the fourth input transistor N4 serves as the first input terminal of the second input circuit 202, and is used to receive an input signal. The first terminal of the fourth input transistor N4 serves as the first output terminal of the second input circuit 202. The control terminal of the fifth input transistor N5 serves as the second input terminal of the second input circuit 202, and is used to receive a second reference signal. The first terminal of the fifth input transistor N5 serves as the second output terminal of the second input circuit 202. The first terminal of the sixth input transistor N6 is connected to the second terminals of the fourth input transistor N4 and the fifth input transistor N5, and the second terminal of the sixth input transistor N6 is connected to ground. The control terminal of the sixth input transistor N6 is connected to the second control unit 2022.

[0075] The control terminal of the fourth input transistor N4 receives the input signal, and the control terminal of the fifth input transistor N5 receives the second reference signal. After the second reference signal and the input signal are amplified by the fourth input transistor N4 and the fifth input transistor N5, a second differential signal is generated at the first terminal of the fourth input transistor N4 and the first terminal of the fifth input transistor N5.

[0076] In one embodiment, reference continues Figure 4The second control unit 2022 includes a second control transistor N14. The second terminal of the second control transistor N14 is connected to the control terminal of the sixth input transistor N6. The first terminal of the second control transistor N14 receives a clock signal CLK, and the control terminal receives a second control signal COB. The second control transistor N14 generates a signal based on the clock signal CLK and the second control signal COB to control the sixth input transistor N6 to be turned on or off, thereby enabling the second control unit to control whether the second input circuit operates, that is, to control whether the second sampling unit outputs a second differential signal based on the input signal and the second reference signal.

[0077] In one embodiment, such as Figure 6 As shown, the first terminal is used to receive the clock signal, and the second terminal is connected to the control terminal of the sixth input transistor N6. It is used to turn on or off under the control of the second control signal COB. When the second transmission gate G2 is open, the clock signal CLK can control the conduction or cutoff of the sixth input transistor N6, thereby realizing the control of the second control unit to control whether the second sampling unit works.

[0078] The first control signal CO and the second control signal COB are a pair of inverted signals. That is, when the first control signal CO is high, the second control signal COB is low. By setting it up in this way, one of the first acquisition unit and the second acquisition unit can be controlled to work. The first control signal CO and the second control signal COB can be generated according to the inter-symbol interference. This allows the second input circuit with a smaller reference signal to generate a differential signal when the value of the input signal decreases due to inter-symbol interference, and the first input circuit with a larger reference signal to generate a differential signal when the value of the input signal increases due to inter-symbol interference, thereby eliminating inter-symbol interference.

[0079] The first control unit 2012 also includes a third control transistor N15. The first terminal of the third control transistor N15 is connected to the control terminal of the third input transistor N3, and the second terminal of the third control transistor N15 is connected to ground. The control terminal of the third control transistor N15 is used to receive the second control signal COB. When the first transmission gate G1 is closed or the first control transistor N13 is turned off, that is, when the third input transistor N3 is turned off under the control of the first transmission gate G1 or the first control transistor N13, the control terminal of the third input transistor N3 is pulled down to a low level to prevent interference from being introduced due to the control terminal of the third input transistor N3 being left floating.

[0080] The second control unit 2022 also includes a fourth control transistor N16. The first terminal of the fourth control transistor N16 is connected to the control terminal of the sixth input transistor N6, and the second terminal of the fourth control transistor N16 is connected to ground. The control terminal of the fourth control transistor N16 is used to receive the first control signal CO. When the second transmission gate G2 is closed or the second control transistor N14 is turned off, that is, when the sixth input transistor N6 is turned off under the control of the second transmission gate G2 or the second control transistor N14, the control terminal of the sixth input transistor N6 is pulled down to a low level to prevent interference from being introduced due to the control terminal of the sixth input transistor N6 being left floating.

[0081] The output circuit 205 includes a first output transistor N7, a second output transistor N8, a third output transistor P1, and a fourth output transistor P2 forming a cross-coupled circuit. The first terminal of the first output transistor N7 is connected to the second terminal of the third output transistor P1, and the first terminal of the second output transistor N8 is connected to the second terminal of the fourth output transistor P2. The control terminal of the first output transistor N7 is connected to the control terminal of the third output transistor P1, and then to the second terminal of the fourth output transistor P2. Similarly, the control terminal of the second output transistor N8 is connected to the control terminal of the fourth output transistor P2, and then to the second terminal of the third output transistor P1.

[0082] The second terminal of the first output transistor N7 is the first input terminal of the output circuit 205, and the second terminal of the second output transistor N8 is the second input terminal of the output circuit 205. The second terminal of the first output transistor N7 is connected to the first terminal of the first input transistor N1, and the second terminal of the second output transistor N8 is connected to the first terminal of the second input transistor N2. The second terminal of the third output transistor P1 serves as the first output terminal of the output circuit 205, and the second terminal of the fourth output transistor P2 serves as the second output terminal of the output circuit 205.

[0083] When the first control unit controls the first sampling unit to operate, the first input transistor N1 and the second input transistor N2 are turned on under the control of the input signal and the first reference signal, which also pulls down the voltage of the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8. When the second control unit controls the second sampling unit to operate, the fourth input transistor N4 and the fifth input transistor N5 are turned on under the control of the input signal and the second reference signal, which also pulls down the voltage of the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8.

[0084] When the voltage is pulled down to the switching voltage, the transistors conduct. That is, the first output transistor N7 and the fourth output transistor P2 conduct, or the second output transistor N8 and the third output transistor P1 conduct. If the first output transistor N7 and the fourth output transistor P2 conduct, the voltage at the second terminal of the fourth output transistor P2 is pulled up, and the voltage at the second terminal of the third output transistor P1 is pulled down. If the second output transistor N8 and the third output transistor P1 conduct, the voltage at the second terminal of the fourth output transistor P2 is pulled down, and the voltage at the second terminal of the third output transistor P1 is pulled up, thus amplifying and latching the voltage signal output from the input circuit.

[0085] In one embodiment, the first feedback unit 2031 includes a first feedback transistor N9. The control terminal of the first feedback transistor N9 is the control terminal of the first feedback unit 2031, and the first terminal of the first feedback transistor N9 is the first terminal of the first feedback unit 2031. The control terminal of the first feedback transistor N9 is connected to the first terminal of the first input transistor N1, and the first terminal of the first feedback transistor N9 is connected to the first terminal of the second input transistor N2. The second terminal of the first feedback transistor N9 is also connected to the first terminal of the third input transistor N3.

[0086] The control terminal of the second feedback transistor N10 is the control terminal of the second feedback unit 2032, and the first terminal of the second feedback transistor N10 is the first terminal of the second feedback unit 2032. The control terminal of the second feedback transistor N10 is connected to the first terminal of the second input transistor N2, and the first terminal of the second feedback transistor N1 is connected to the first terminal of the first input transistor N1. The second terminal of the second feedback transistor N10 is connected to the second terminal of the first input transistor N1, and the second terminal of the second feedback transistor N10 is also connected to the first terminal of the third input transistor N3.

[0087] In one embodiment, the first feedback transistor N9, the second feedback transistor N10, the first input transistor N1, and the second input transistor N2 are of the same type. This ensures that the direction in which the first feedback transistor N9 pulls the voltage at the second output terminal of the first input circuit is the same as the direction in which the second feedback transistor N10 pulls the voltage at the first output terminal of the first input circuit. It also ensures that the direction in which the feedback transistor pulls the voltage at the output terminal of the first input circuit is the same as the direction in which the input transistor pulls the voltage at the output terminal of the first input circuit, thereby achieving positive feedback.

[0088] The greater the voltage at the first terminal of the first input transistor N1, the greater the ability of the first feedback transistor N9 to pull down the voltage at the first terminal of the second input transistor N2, and the faster the voltage at the first terminal of the second input transistor N2 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the first input transistor N1 and the second input transistor N2.

[0089] In one embodiment, the third feedback unit 2041 includes a third feedback transistor N11. The control terminal of the third feedback transistor N11 is the control terminal of the third feedback unit 2041, and the first terminal of the third feedback transistor N11 is the first terminal of the third feedback unit 2041. The control terminal of the third feedback transistor N11 is connected to the first terminal of the fourth input transistor N4, and the first terminal of the third feedback transistor N11 is connected to the first terminal of the fifth input transistor N5. The second terminal of the third feedback transistor N11 is connected to the second terminal of the fourth input transistor N4. The second terminal of the third feedback transistor N11 is also connected to the first terminal of the sixth input transistor N6.

[0090] The fourth feedback unit 2042 includes a fourth feedback transistor N12. The control terminal of the fourth feedback transistor N12 is the control terminal of the fourth feedback unit 2042, and the first terminal of the fourth feedback transistor N12 is the first terminal of the fourth feedback unit 2042. The control terminal of the fourth feedback transistor N12 is connected to the first terminal of the fifth input transistor N5, and the first terminal of the fourth feedback transistor N12 is also connected to the first terminal of the fourth input transistor N4. The second terminal of the fourth feedback transistor N12 is connected to the second terminal of the fifth input transistor N5, and the second terminal of the fourth feedback transistor N12 is also connected to the first terminal of the sixth input transistor N6.

[0091] In one embodiment, the third feedback transistor N11, the fourth feedback transistor N12, the fourth input transistor N4, and the fifth input transistor N5 are of the same type, ensuring that the direction of the voltage at the second output terminal of the second input circuit 202 pulled by the third feedback transistor N11 is the same as the direction of the voltage at the first output terminal of the second input circuit 202 pulled by the fourth feedback transistor N12. It is also ensured that the direction of the voltage at the output terminal of the second input circuit 202 pulled by the feedback transistor is the same as the direction of the voltage at the output terminal of the second input circuit 202 pulled by the input transistor, thereby achieving positive feedback.

[0092] The greater the voltage at the first terminal of the fourth input transistor N4, the greater the ability of the third feedback transistor N11 to pull down the voltage at the first terminal of the fifth input transistor N5, and the faster the voltage at the first terminal of the fifth input transistor N5 drops, thus realizing a positive feedback mechanism and accelerating the difference in differential voltage between the fourth input transistor N4 and the fifth input transistor N5.

[0093] In one embodiment, the comparator further includes a first reset circuit and a second reset circuit. The first reset circuit is connected to the first input circuit and the second input circuit, and is used to reset the voltages of the first input circuit and the second input circuit. The second reset circuit is connected to the output circuit, and is used to reset the voltage of the output circuit.

[0094] The first reset circuit includes a first clocked transistor P3, a second clocked transistor P4, a third clocked transistor P5, and a fourth clocked transistor P6.

[0095] The control terminal of the first clock transistor P3 receives the clock signal CLK. The first terminal of the first clock transistor P3 is connected to the power supply terminal. The second terminal of the first clock transistor P3 is connected to the first terminal of the third input transistor N3, which is used to pull the first terminal of the third input transistor N3 to a high level during the reset phase.

[0096] The control terminal of the second clock transistor P4 receives the clock signal CLK. The first terminal of the second clock transistor P4 is connected to the power supply terminal, and the second terminal of the second clock transistor P4 is connected to the first terminal of the sixth input transistor N6, which is used to pull the first terminal of the sixth input transistor N6 to a high level during the reset phase.

[0097] The control terminal of the third clock transistor P5 receives the clock signal CLK. The first terminal of the third clock transistor P5 is connected to the power supply terminal. The second terminal of the third clock transistor P5 is connected to the first terminal of the first input transistor N1 and the first terminal of the fourth input transistor N4, which is used to pull the first terminal of the first input transistor N1 and the first terminal of the fourth input transistor N4 to a high level during the reset phase.

[0098] The control terminal of the fourth clock transistor P6 receives the clock signal CLK. The first terminal of the fourth clock transistor P6 is connected to the power supply terminal. The second terminal of the fourth clock transistor P6 is connected to the first terminal of the second input transistor N2 and the first terminal of the fifth input transistor N5, which is used to pull the first terminal of the second input transistor N2 and the first terminal of the fifth input transistor N5 to a high level during the reset phase.

[0099] The second reset circuit includes a fifth clock transistor P7 and a sixth clock transistor P8. The control terminal of the fifth clock transistor P7 receives the clock signal CLK. The first terminal of the fifth clock transistor P7 is connected to the power supply terminal, and the second terminal of the fifth clock transistor P7 is connected to the second terminal of the third output transistor P1, which is used to pull the second terminal of the third output transistor P1 to a high level during the reset phase.

[0100] The control terminal of the sixth clock transistor P8 receives the clock signal CLK. The first terminal of the sixth clock transistor P8 is connected to the power supply terminal, and the second terminal of the sixth clock transistor P8 is connected to the second terminal of the fourth output transistor P2, which is used to pull the second terminal of the fourth output transistor P2 to a high level during the reset phase.

[0101] In the above technical solution, a corresponding clocked transistor is set at the corresponding terminal of each transistor that needs to be reset. The clocked transistor directly pulls the voltage at the corresponding terminal of the transistor that needs to be reset, resulting in a shorter reset time and thus improving the response rate of the comparator.

[0102] In one embodiment, the first clocked transistor P3 to the sixth clocked transistor P8 are of the same type, so as to pull the two output terminals of the input circuit and the two output terminals of the output circuit 205 to the same level.

[0103] In one embodiment, when the first feedback transistor N9 to the fourth feedback transistor N12 are all N-type transistors, the first control transistor N13 to the fourth control transistor N16 are all N-type transistors, and the first input transistor N1 to the sixth input transistor N6 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0104] In one embodiment, when both the first output transistor N7 and the second output transistor N8 are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

[0105] When the third output transistor P1 and the fourth output transistor P2 are both P-type transistors, and when the first clocked transistor P3 to the sixth clocked transistor P8 are all P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0106] In one embodiment, the first feedback transistor N9 and the second feedback transistor N10 are of the same size, and the first input transistor N1 and the second input transistor N2 are of the same size. The size of the first feedback transistor N9 is less than half the size of the first input transistor N1. This avoids the first feedback transistor N9 and the second feedback transistor N10 from affecting the sensing of the input signal and the first reference signal by the first input transistor N1 and the second input transistor N2, thereby improving the accuracy of the comparator output.

[0107] In one embodiment, the third feedback transistor N11 and the fourth feedback transistor N12 are of the same size, and the fourth input transistor N4 and the fifth input transistor N5 are of the same size. The size of the third feedback transistor N11 is less than half the size of the fourth input transistor N4. This avoids the third feedback transistor N11 and the fourth feedback transistor N12 from affecting the sensing of the input signal and the second reference signal by the fourth input transistor N4 and the fifth input transistor N5, thereby improving the accuracy of the comparator output.

[0108] In one embodiment, the ratio of the size of the fourth input transistor N4 to the size of the first input transistor N1 is α, where α < 0.5, so that the size of the fourth input transistor N4 is less than half the size of the first input transistor N1. The ratio of the size of the third feedback transistor N11 to the size of the first feedback transistor N9 is α < 0.5, so that the size of the first feedback transistor N9 is less than half the size of the third feedback transistor N11. The ratio of the size of the sixth input transistor N6 to the size of the third input transistor N3 is α, where α < 0.5, so that the size of the sixth input transistor N6 is less than half the size of the third input transistor N3. With the above settings, the influence of the second input circuit 202 on the first input circuit can be avoided from being too great, causing the first differential signal to invert. For example, if the input signal and the first reference signal cause the first terminal voltage of the first input transistor N1 to be greater than the first terminal voltage of the second input transistor N2, the intervention of the second differential signal will cause the first differential signal to invert, that is, make the first terminal voltage of the first input transistor N1 less than the first terminal voltage of the second input transistor N2.

[0109] In one embodiment, the first control signal CO is the signal output by the first output terminal of the comparator at the previous time t0, and the second control signal COB is the signal output by the second output terminal of the comparator at the previous time t0. The first reference signal Vr1 and the second reference signal Vr2 are set according to the standard reference voltage Vr0. The principle of this comparator in eliminating inter-symbol interference is described below with reference to Table 1.

[0110] Table 1. Inter-symbol interference situation

[0111]

[0112] As shown in Table 1, in the first case, without intersymbol interference, the input signal is 0.9V and the standard reference signal is 0.8V. Therefore, V O1 <V O2Intersymbol interference (ISI) causes the input signal to be 0.8V. At the previous moment, the comparator outputs the digital "0", which activates the second sampling unit. The second sampling unit senses the magnitudes of the second reference signal (0.75V) and the input signal (0.8V) after ISI, causing the voltage at the first output terminal O1 of the second input circuit to be less than the voltage at the second output terminal O2. This is the same result as when there is no ISI, and the ISI is eliminated.

[0113] In the second case, assuming no inter-symbol interference, the input signal is 0.6V and the standard reference signal is 0.8V, then V O1 >V O2 Intersymbol interference (ISI) causes the input signal to be 0.65V. ISI increases the input signal, but the change in the input signal is relatively small. The comparator outputs a "0" at the previous moment, still allowing the second sampling unit to operate. This means the second sampling unit senses the magnitudes of the second reference signal (0.75V) and the ISI-interfered input signal (0.65V), resulting in the voltage at the first output terminal O1 of the second input circuit being greater than the voltage at the second output terminal O2. This is the same result as without ISI, and the ISI is eliminated. The remaining two cases are similar and will not be elaborated upon here.

[0114] In one embodiment, such as Figure 7 As shown, when the first feedback transistor P9 to the fourth feedback transistor P12 are all N-type transistors, the first control transistor P13 to the fourth control transistor P16 are all P-type transistors, and the first input transistor P1 to the sixth input transistor P6 are all P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. The second terminals of the third input transistor P3, the sixth input transistor P6, the third control transistor P15, and the fourth control transistor P16 are connected to the power supply terminal.

[0115] In one embodiment, when both the first output transistor P7 and the second output transistor P8 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

[0116] When the third output transistor N1 and the fourth output transistor N2 are both N-type transistors, and when the first clocked transistor N3 to the sixth clocked transistor N8 are all N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. The first terminals of the third output transistor N1 and the fourth output transistor N2 are connected to the ground terminal. The first terminals of the first clocked transistor N3 to the sixth clocked transistor N8 are also connected to the ground terminal.

[0117] In the above technical solution, two input circuits with different reference voltages are set up. The control signal of the comparator is determined based on the output result of the comparator at the previous moment. This allows for the selection of a suitable sampling unit to output a differential signal according to the inter-symbol interference (ISI) situation, so that the output circuit can output an accurate comparison result based on the differential signal, thereby eliminating ISI. The positive feedback circuit is used to accelerate the difference of the differential signal at the output of the input circuit, thereby shortening the time the comparator is in the sampling phase and reducing the power consumption of the comparator.

[0118] Figure 8 A structural block diagram of a comparator provided in this application, such as... Figure 8 As shown, the comparator includes a first input transistor N1, a second input transistor N2, a third input transistor N3, a fourth input transistor N4, a fifth input transistor N5, a sixth input transistor N6, and a control transistor N9.

[0119] The control terminal of the first input transistor N1 receives the input signal, the control terminal of the second input transistor N2 receives the first reference signal, and the second terminals of the first input transistor N1 and the second input transistor N2 are both connected to the first terminal of the third input transistor N3.

[0120] The control terminal of the fourth input transistor N4 receives the input signal, the control terminal of the fifth input transistor N5 receives the second reference signal, and the second terminals of the fourth input transistor N4 and the fifth input transistor N5 are both connected to the first terminal of the sixth input transistor N6.

[0121] The control terminal of the third input transistor N3 is used to receive the first control signal, the control terminal of the sixth input transistor N6 is used to receive the second control signal, the first terminal of the third input transistor N3 and the first terminal of the sixth input transistor N6 are connected to the first terminal of the control transistor N9, the second terminal of the control transistor N9 is connected to the ground terminal, and the control terminal of the control transistor N9 is used to receive the clock signal.

[0122] The comparator also includes a first output transistor N7, a second output transistor N8, a third output transistor P1, and a fourth output transistor P2. The connection relationship and function of each output transistor are the same. Figure 4 The comparators shown are the same, so they will not be described again here.

[0123] The comparator also includes a first clocked transistor P3, a second clocked transistor P4, a third clocked transistor P5, a fourth clocked transistor P6, a fifth clocked transistor P7, and a sixth clocked transistor P8. The connection relationship and function of the clocked transistors are the same as those in the previous circuit. Figure 4 The comparators shown are the same, so they will not be described again here.

[0124] and Figure 4The comparator shown differs in that the control terminal of the third input transistor N3 directly receives the first control signal, and the control terminal of the sixth input transistor N6 directly receives the second control signal. The first and second control signals are an inverted pair. During the sampling phase, the clock signal turns on the control transistor N9. If the first control signal turns on the third input transistor N3, the second control signal turns off the sixth input transistor N6. The first input transistor N1 and the second input transistor N2 output a first differential signal based on the input signal and the first reference signal. Similarly, during the sampling phase, the clock signal turns on the control transistor N9. If the second control signal turns on the sixth input transistor N6, the first control signal turns off the third input transistor N3. The fourth input transistor N4 and the fifth input transistor N5 output a second differential signal based on the input signal and the second reference signal.

[0125] In the comparator described above, a first control signal and a second control signal can be generated based on the effect of inter-symbol interference (ISI) on the input signal. If the comparator outputs data "1", the first input transistor N1 and the second input transistor N2 can be controlled to generate a first differential signal based on the input signal after ISI and a first reference signal with a larger value. This ensures that the polarity of the generated differential signal is the same as the polarity of the differential signal output when there is no ISI, thereby eliminating the influence of ISI on the comparator's output result.

[0126] If the comparator outputs data "0", then the fourth input transistor N4 and the fifth input transistor N5 can be controlled to generate a second differential signal based on the input signal after inter-symbol interference and the second reference signal with a smaller value. This ensures that the polarity of the generated differential signal is the same as the polarity of the differential signal output when there is no inter-symbol interference, thereby eliminating the influence of inter-symbol interference on the comparator's output result.

[0127] Figure 9 A structural block diagram of a comparator provided in this application, such as... Figure 9 As shown, the comparator includes a first input circuit 201, a second input circuit 202, a first positive feedback circuit 203, a second positive feedback circuit 204, and an output circuit 205.

[0128] The second positive feedback circuit 204 includes at least one controllable positive feedback module 2040, wherein each controllable positive feedback module includes a third feedback unit 2041, a fourth feedback unit 2042, a first switch 2043, and a second switch 2044. The third feedback unit 2041 and the fourth feedback unit 2042 are each provided with a control terminal and a first terminal.

[0129] The control terminal of the third feedback unit 2041 is connected to the first output terminal of the second input circuit 202 via the first switch 2043, and the first terminal of the third feedback unit 2041 is connected to the second output terminal of the second input circuit 202. The control terminal of the fourth feedback unit 2042 is connected to the second output terminal of the second input circuit 202 via the second switch 2044, and the first terminal of the fourth feedback unit 2042 is connected to the first output terminal of the second input circuit 202.

[0130] The first switch 2043 controls whether the third feedback unit 2041 generates positive feedback, and the second switch 2044 controls whether the fourth feedback unit 2042 generates positive feedback. By controlling the closing and opening of the first switch 2043 and the second switch 2044, the controllable positive feedback module 2040 can be controlled to generate positive feedback. When both the first switch 2043 and the second switch 2044 are closed, the controllable positive feedback module 2040 can accelerate the difference between the second differential signals at the output of the second input circuit through the positive feedback mechanism. When both the first switch 2043 and the second switch 2044 are open, the controllable positive feedback module 2040 is disconnected from the second input circuit and cannot generate positive feedback at the output of the second input circuit.

[0131] When the comparator is operating, the number of controllable positive feedback modules that generate positive feedback can be controlled, thereby controlling the ability of the second positive feedback circuit to pull the difference between the second differential signals. This controls the time the comparator spends in the sampling phase, ensuring the comparator's response rate.

[0132] Figure 10 and Figure 11 For based on Figure 9 The circuit diagram shown represents one specific example of a comparator, wherein the structures of the first input circuit 201, the second input circuit 202, and the output circuit 205 are identical. Figure 4 The comparators shown are the same, so they will not be described again here.

[0133] The following is combined Figure 10 and Figure 11 Describe the specific circuit structure of each controllable positive feedback module in the positive feedback circuit. The third feedback unit 2041 includes a third feedback transistor N11, the control terminal of the third feedback transistor N11 serves as the control terminal of the third feedback unit 2041, and the first terminal of the third feedback transistor N11 serves as the second terminal of the third feedback unit 2041.

[0134] The control terminal of the third feedback transistor N11 is connected to the first terminal of the third feedback transistor N11 through the first switch 2045. The first switch 2043 includes a third transmission gate G3, which is controlled by a first enable signal EN1. The first enable signal EN1 is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal.

[0135] The fourth feedback unit 2042 includes a fourth feedback transistor N12. The control terminal of the fourth feedback transistor N12 is the control terminal of the fourth feedback unit 2042, and the first terminal of the fourth feedback transistor N12 is the second terminal of the fourth feedback unit 2042.

[0136] The control terminal of the fourth feedback transistor N12 is connected to the first terminal of the fourth feedback transistor N12 through the second switch 2044. The second switch 2044 includes a fourth transmission gate G4, which is controlled by a second enable signal EN2. The second enable signal EN2 is generated based on the comparator's operating frequency, the comparator's input common-mode range, and the test mode signal.

[0137] By controlling the switching states of the third transmission gate G3 and the fourth transmission gate G4 with the enable signal, the third feedback transistor N11 and the fourth feedback transistor N12 can be controlled to provide a positive feedback mechanism, thereby adjusting the number of controllable positive feedback modules participating in the positive feedback.

[0138] In one embodiment, the second positive feedback circuit 204 further includes a first zero switch K10 and a second zero-zero switch K00. The control terminal of the third feedback unit 2041 is also connected to the ground terminal through the first zero switch K10. The first zero switch K10 is used to conduct when the third transmission gate G3 is closed, so that the transistor in the third feedback unit 2041 is not floating, reducing external interference to the comparator. The control terminal of the fourth feedback unit 2042 is also connected to the ground terminal through the second zero-zero switch K00. The second zero-zero switch K00 is used to conduct when the fourth transmission gate G4 is closed, so that the transistor in the fourth feedback unit 2042 is not floating, reducing external interference to the comparator.

[0139] In one embodiment, if the third feedback transistor N11, the fourth feedback transistor N12, the first zero switch K10, and the zero-zero switch K00 are N-type transistors, the drain of the N-type transistor is the first terminal, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal. The first terminal of the first zero switch K10 is connected to the control terminal of the third feedback transistor N11, the first terminal of the zero-zero switch K00 is connected to the control terminal of the fourth feedback transistor N12, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are grounded, so as to pull down the third feedback transistor N11 to a low level when the third transmission gate G3 is closed, and pull down the fourth feedback transistor N12 to a low level when the fourth transmission gate G4 is closed.

[0140] Figure 12 and Figure 13 For based on Figure 9 The circuit diagram shown represents one specific example of a comparator, wherein the structures of the first input circuit 201, the second input circuit 202, and the output circuit 205 are identical. Figure 7The comparators shown are the same and will not be described again here. The connection relationships between the third feedback unit 2041, the fourth feedback unit 2042, the first switch 2043, and the second switch 2044 of each controllable positive feedback module 2040 in the second positive feedback circuit 204 have been described. Figure 11 The structure is described in detail here, and will not be repeated.

[0141] It should be noted here that if the third feedback transistor P11, the fourth feedback transistor P12, the first zero switch K10, and the zero-zero switch K00 are P-type transistors, the drain of the P-type transistor is the first terminal, the source of the P-type transistor is the second terminal, the gate of the P-type transistor is the control terminal, and the second terminals of the first zero switch K10 and the zero-zero switch K00 are connected to the power supply terminal.

[0142] In the above embodiments, the second positive feedback circuit includes multiple controllable positive feedback modules. By controlling the number of controllable positive feedback modules that provide the positive feedback mechanism, the ability of the second positive feedback circuit to pull the voltage of the two output terminals of the second input circuit can be adjusted, thereby controlling the time when the comparator is in the sampling stage. It can also balance the pulling ability of the positive feedback circuit and the input signal and reference signal on the output terminal of the second input circuit, thereby improving the response rate and accuracy of the comparator.

[0143] like Figure 14 As shown, an embodiment of this application provides a decision feedback equalization circuit, including the four comparators described in the above embodiment, which are sequentially labeled as first comparator 100, second comparator 200, third comparator 300 and fourth comparator 400.

[0144] Specifically, the fourth input terminals CO and COB of the first comparator 100 are connected to the output terminals P270 and P270B of the fourth comparator 400. The fourth input terminals CO and COB of the second comparator 200 are connected to the output terminals P0 and P0B of the first comparator 100. The fourth input terminal CO and COB of the third comparator 300 are connected to the output terminals P90 and P90B of the second comparator 200. The fourth input terminal CO and COB of the fourth comparator 400 are connected to the output terminals P180 and P180B of the third comparator 300.

[0145] The first input terminal I of the first comparator 100 to the fourth comparator 400 all receive the input signal In, the second input terminal of the first comparator 100 to the fourth comparator 400 all receive the first reference signal Vr1, and the third input terminal of the first comparator 100 to the fourth comparator 400 all receive the second reference signal Vr2.

[0146] Assuming that the fourth comparator 400 output the number "1" at the previous moment, at the current moment, the first control signal CO at the fourth input terminal CO / COB of the first comparator 100 is at a high level, and the second control signal COB is at a low level. If the value of the input signal at the current moment is relatively small, the inter-symbol interference (ISI) is small, and the value of the input signal will increase. The comparator generates a differential signal based on the larger first reference signal and the larger input signal, ensuring that the polarity of the differential signal generated after ISI is the same as the polarity of the differential signal generated without ISI. Conversely, if the value of the input signal is relatively large, the ISI has a smaller impact on the input signal. The comparator generates a differential signal based on the larger first reference signal and the larger input signal, again ensuring that the polarity of the differential signal generated after ISI is the same as the polarity of the differential signal generated without ISI, thus guaranteeing the accuracy of the comparator output.

[0147] Assuming that the fourth comparator 400 output "0" at the previous moment, at the current moment, the first control signal CO at the fourth input terminal CO / COB of the first comparator 100 is low, and the second control signal COB is high. If the current input signal value is relatively large, the inter-symbol interference (ISI) will be small, causing the input signal value to decrease. The comparator generates a differential signal based on the smaller second reference signal and the smaller input signal value, ensuring that the polarity of the differential signal generated after ISI is the same as that generated without ISI. Conversely, if the input signal value is relatively small, the ISI has a smaller impact on the input signal. The comparator generates a differential signal based on the smaller second reference signal and the smaller input signal value, again ensuring that the polarity of the differential signal generated after ISI is the same as that generated without ISI, thus guaranteeing the accuracy of the comparator output.

[0148] The working principle of the second register 200 to the fourth register 400 is the same as that of the first register 100, and will not be repeated here.

[0149] In one embodiment, the phase of the first clock signal of the first comparator 100 is 90° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180° earlier than the phase of the second clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270° earlier than the phase of the second clock signal of the fourth comparator 400.

[0150] In one embodiment, the voltage switching time T at the output terminals of the first comparator 100 to the fourth comparator 400 is... FB_p Both are less than the time interval 1U1 between the first clock signal and the second clock signal, such as Figure 15As shown, when the switching time of the output voltage of the fourth comparator 400 is less than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal. This ensures that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has already stably output the comparison result, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate inter-symbol interference based on the comparison result of the fourth comparator 400.

[0151] In one embodiment, the decision feedback equalization circuit further includes four registers, labeled sequentially as a first register, a second register, a third register, and a fourth register. The input of the first register is connected to the two outputs of the first comparator 100, the input of the second register is connected to the two outputs of the second comparator 200, the input of the third register is connected to the two outputs of the third comparator 300, and the input of the fourth register is connected to the two outputs of the fourth comparator 400. The four registers are used to store the comparison results of the four corresponding comparator outputs.

[0152] In the above technical solution, the two output terminals of the fourth register are connected to the two input terminals of the first register, and the two output terminals of the first register are connected to the two input terminals of the second register, and so on, to form a decision feedback equalization circuit. The other two input terminals of the four registers receive the input signal and the first reference signal. Under the control of the output terminal signals of the four registers, the inter-symbol interference caused by continuous input signals in the registers can be effectively eliminated.

[0153] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0154] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A decision feedback equalization circuit, characterized in that, It includes four comparators, labeled as the first comparator, the second comparator, the third comparator, and the fourth comparator, respectively. Each of the comparators has four inputs and two outputs, including: The first input circuit has three input terminals and two output terminals. Its three input terminals serve as the first input terminal, the second input terminal, and the fourth input terminal of the comparator, and are used to generate a first differential signal based on the input signal and the first reference signal under the control of the control signal during the sampling stage. A first positive feedback circuit is connected to the two output terminals of the first input circuit to accelerate the difference between the first differential signals. The second input circuit has three input terminals and two output terminals. Its three input terminals serve as the first, third, and fourth input terminals of the comparator, and its output terminal is connected to the output terminal of the first input circuit. It is used to generate a second differential signal based on the input signal and the second reference signal under the control of the control signal during the sampling stage. The first reference signal is greater than the second reference signal. The second positive feedback circuit is connected to the output of the second input circuit and is used to accelerate the difference between the second differential signals. The output circuit has two input terminals and two output terminals. The two output terminals are the output terminals of the comparator, and the two input terminals are connected to the two output terminals of the first input circuit. During the regeneration phase, it amplifies and latches the voltage signal from the output terminal of the first input circuit or the voltage signal from the output terminal of the second input circuit to output a comparison result. The first comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal directly connected to the output terminal of the fourth comparator for receiving control signals. The second comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal directly connected to the output terminal of the first comparator for receiving a control signal. The third comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal directly connected to the output terminal of the second comparator for receiving a control signal. The fourth comparator has a first input terminal for receiving an input signal, a second input terminal for receiving a first reference signal, a third input terminal for receiving a second reference signal, and a fourth input terminal directly connected to the output terminal of the third comparator for receiving a control signal.

2. The decision feedback equalization circuit according to claim 1, characterized in that, The first positive feedback circuit includes: The first feedback unit has its control terminal connected to the first output terminal of the first input circuit, and its first terminal connected to the second output terminal of the first input circuit. The second feedback unit has its control terminal connected to the second output terminal of the first input circuit, and its first terminal connected to the first output terminal of the first input circuit. The second positive feedback circuit includes: The third feedback unit has its control terminal connected to the first output terminal of the second input circuit, and its first terminal connected to the second output terminal of the second input circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the second input circuit, and its first terminal connected to the first output terminal of the second input circuit.

3. The decision feedback equalization circuit according to claim 2, characterized in that, The first feedback unit includes: a first feedback transistor, whose control terminal is the control terminal of the first feedback unit, and whose first terminal is the first terminal of the first feedback unit; The second feedback unit includes: a second feedback transistor, whose control terminal is the control terminal of the second feedback unit, and whose first terminal is the first terminal of the second feedback unit; The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

4. The decision feedback equalization circuit according to claim 3, characterized in that, The first input circuit includes: The first sampling unit is configured to receive the input signal and the first reference signal, and generate the first differential signal based on the input signal and the first reference signal; A first control unit, which is connected to the first sampling unit, is used to receive control signals and control whether the first sampling unit works according to the control signals; The second input circuit includes: The second sampling unit is used to receive the input signal and the second reference signal, and generate the second differential signal based on the input signal and the second reference signal; The second control unit is connected to the second sampling unit and is used to receive control signals and control whether the second sampling unit works according to the control signals.

5. The decision feedback equalization circuit according to claim 4, characterized in that, The first sampling unit includes: The first input transistor has a control terminal for receiving the input signal, a first terminal for serving as the first output terminal of the first input circuit, and a first terminal for being connected to the control terminal of the first feedback transistor. The second input transistor has a control terminal for receiving the first reference signal, a first terminal for serving as the second output terminal of the first input circuit, and a first terminal connected to the control terminal of the second feedback transistor. The third input transistor has its first terminal connected to the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor, and the second terminal of the second feedback transistor, and its second terminal connected to the ground terminal or the power supply terminal. The second sampling unit includes: The fourth input transistor has a control terminal for receiving the second reference signal, a first terminal for serving as the first output terminal of the second input circuit, and a first terminal for connecting to the control terminal of the third feedback transistor. The fifth input transistor has a control terminal for receiving the input signal, a first terminal for serving as the second output terminal of the second input circuit, and a first terminal for connecting to the control terminal of the fourth feedback transistor. The sixth input transistor has its first terminal connected to the second terminal of the fourth input transistor, the second terminal of the fifth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor, and its second terminal connected to the ground terminal or the power supply terminal.

6. The decision feedback equalization circuit according to claim 5, characterized in that, The control signal and the first control signal and the second control signal; The first control unit includes: a first control transistor, whose control terminal is used to receive the first control signal, whose second terminal is connected to the control terminal of the third input transistor, and whose first terminal is used to receive a clock signal; The second control unit includes: a second control transistor, the control terminal of which is used to receive the second control signal, the second terminal of which is connected to the control terminal of the sixth input transistor, and the first terminal of which is used to receive a clock signal; or Its first end is used to receive a clock signal, and its second end is connected to the control terminal of the third input transistor, which is used to turn it on or off under the control of the first control signal; The second control unit includes: a second transmission gate, the first end of which is used to receive a clock signal, and the second end of which is connected to the control terminal of the sixth input transistor, for turning on or off under the control of a second control signal.

7. The decision feedback equalization circuit according to claim 6, characterized in that, The first control unit further includes: a third control transistor, whose control terminal is used to receive the second control signal, whose second terminal is connected to a ground terminal or a power supply terminal, and whose first terminal is connected to the control terminal of the third input transistor; The second control unit further includes: a fourth control transistor, whose control terminal is used to receive the first control signal, whose second terminal is connected to a ground terminal or a power supply terminal, and whose first terminal is connected to the control terminal of the sixth input transistor.

8. The decision feedback equalization circuit according to claim 7, characterized in that, The first feedback transistor to the fourth feedback transistor, the first control transistor to the fourth control transistor, and the first input transistor to the sixth input transistor are all of the same type.

9. The decision feedback equalization circuit according to claim 8, characterized in that, The first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is less than half the size of the first input transistor. The third feedback transistor and the fourth feedback transistor are the same size, the fourth input transistor and the fifth input transistor are the same size, and the size of the third feedback transistor is less than half the size of the fourth input transistor.

10. The decision feedback equalization circuit according to claim 9, characterized in that, When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all N-type transistors, the drain of the N-type transistor is the first terminal and the gate of the N-type transistor is the control terminal; When the first feedback transistor to the fourth feedback transistor and the first input transistor to the sixth input transistor are all P-type transistors, the drain of the P-type transistor is the first terminal and the gate of the P-type transistor is the control terminal.

11. The decision feedback equalization circuit according to claim 1, characterized in that, The output circuit includes: The first output transistor has its second terminal being the first input terminal of the output circuit. The second output transistor has its second terminal being the second input terminal of the output circuit. The third output transistor has its control terminal connected to the control terminal of the first output transistor. Its control terminal is also connected to the second terminal of the fourth output transistor. Its second terminal is connected to the first terminal of the first output transistor. Its second terminal serves as the first output terminal of the output circuit. The fourth output transistor has its control terminal connected to the control terminal of the second output transistor, and its control terminal is also connected to the second terminal of the third output transistor. Its second terminal is connected to the first terminal of the second output transistor, and its second terminal serves as the second output terminal of the output circuit.

12. The decision feedback equalization circuit according to claim 11, characterized in that, The comparator further includes: A first reset circuit is connected to the first input circuit and the second input circuit, and is used to reset the voltage of the first input circuit and the second input circuit; The second reset circuit is connected to the output circuit and is used to reset the voltage of the output circuit.

13. The decision feedback equalization circuit according to claim 12, characterized in that, The first reset circuit includes: The first clock-controlled transistor has a control terminal that receives a clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the first terminal of the third input transistor. The second clock transistor has a control terminal that receives the clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the first terminal of the sixth input transistor. The third clock transistor has a control terminal that receives the clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the first terminal of the first input transistor and the first terminal of the fourth input transistor. The fourth clock transistor has a control terminal that receives the clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the first terminal of the second input transistor and the first terminal of the fifth input transistor. The second reset circuit includes: The fifth clock transistor has a control terminal that receives the clock signal, a first terminal that is connected to a power supply terminal or a ground terminal, and a second terminal that is connected to the second terminal of the third output transistor. The sixth clock transistor receives the clock signal at its control terminal, its first terminal is connected to the power supply terminal or the ground terminal, and its second terminal is connected to the second terminal of the fourth output transistor.

14. The decision feedback equalization circuit according to claim 13, characterized in that, The first, second, third, and fourth clocked transistors are of the same type.

15. The decision feedback equalization circuit according to claim 14, characterized in that, Both the first output transistor and the second output transistor are N-type transistors, with the drain of the N-type transistor being the first terminal and the gate of the N-type transistor being the control terminal. The third output transistor and the fourth output transistor are both P-type transistors, and the first to sixth clocked transistors are all P-type transistors. The source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. or Both the first output transistor and the second output transistor are P-type transistors, with the drain of the P-type transistor being the first terminal and the gate of the P-type transistor being the control terminal. The third and fourth output transistors are both N-type transistors, and the first to sixth clocked transistors are all N-type transistors. The source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

16. The decision feedback equalization circuit according to claim 1, characterized in that, The second positive feedback circuit includes at least one controllable positive feedback module; wherein each controllable positive feedback module includes: The third feedback unit has its control terminal connected to the first output terminal of the second input circuit via a first switch, and its first terminal connected to the second output terminal of the second input circuit. The fourth feedback unit has its control terminal connected to the second output terminal of the second input circuit via a second switch, and its first terminal connected to the first output terminal of the second input circuit.

17. The decision feedback equalization circuit according to claim 16, characterized in that, The third feedback unit includes: a third feedback transistor, whose control terminal is the control terminal of the third feedback unit, and whose first terminal is the first terminal of the third feedback unit; The fourth feedback unit includes: a fourth feedback transistor, whose control terminal is the control terminal of the fourth feedback unit, and whose first terminal is the first terminal of the fourth feedback unit.

18. The decision feedback equalization circuit according to claim 16, characterized in that, The first switch includes a third transmission gate, which is controlled by a first enable signal, which is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and the test mode signal. The second switch includes a fourth transmission gate, which is controlled by a second enable signal, which is generated based on the operating frequency of the comparator, the input common-mode range of the comparator, and a test mode signal.

19. The decision feedback equalization circuit according to claim 16, characterized in that, The control terminal of the third feedback unit is also connected to the ground terminal or the power supply terminal through the first zero switch; the control terminal of the fourth feedback unit is also connected to the ground terminal or the power supply terminal through the zero zero switch.

20. The decision feedback equalization circuit according to claim 1, characterized in that, The phase of the first clock signal of the first comparator is 90° earlier than the phase of the second clock signal of the second comparator; The phase of the first clock signal of the first comparator is 180° earlier than the phase of the third clock signal of the third comparator; The phase of the first clock signal of the first comparator is 270° earlier than the phase of the fourth clock signal of the fourth comparator.

21. The decision feedback equalization circuit according to claim 20, characterized in that, The voltage switching time at the output terminals of the first comparator to the fourth comparator is less than the time interval between the first clock signal and the second clock signal.

22. The decision feedback equalization circuit according to any one of claims 1 to 21, characterized in that, Also includes: The four registers are labeled as Register 1, Register 2, Register 3, and Register 4, respectively. The input terminal of the first register is connected to the two output terminals of the first comparator; The input of the second register is connected to the two outputs of the second comparator; The input of the third register is connected to the two outputs of the third comparator; The input of the fourth register is connected to the two outputs of the fourth comparator.

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