In-plane inductors in IC packages

Abstract

To provide an integrated circuit (IC) package substrate.SOLUTION: An integrated circuit (IC) package substrate comprises a magnetic material embedded in a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded in the magnetic material. A second metal feature is at an interface between the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material, and a second sidewall in contact with the magnetic material.SELECTED DRAWING: Figure 2L

Description

[Technical Field]

[0001] This application relates to in-plane inductors within IC packages. [Background technology]

[0002] The integration of inductive structures within integrated circuit (IC) package substrate materials is important for increasing power delivery in high-performance IC devices. Inductive structures containing magnetic materials can be placed on any layer within the package, thus enabling multiple types of structures. For example, in-plane inductors formed by patterning conductive layers within the package substrate can be embedded within magnetic core material integrated within a cavity formed in the package substrate.

[0003] However, integrating magnetic materials within a package substrate presents process and structural challenges. One area where integrating embedded inductive structures presents challenges is in coreless packages, where traces with improved power delivery are fully encapsulated by magnetic material. Full encapsulation of traces with magnetic material can require multiple de-paneling operations to access the backside of the package buildup, for example, where supplemental magnetic material is placed across traces that are only partially buried between the front-side buildup. In some situations, this supplemental magnetic material may need to be of a different magnetic composition, introducing another layer of complexity related to the variability of magnetic materials. Summary of the Invention [Problem to be solved by the invention]

[0004] Methods and structures that allow for complete sealing without de-panelization and / or the use of a single magnetic material reduce process risk and add process flexibility. [Means for solving the problem]

[0005] Embodiments of the present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure, which should not be construed as limiting the disclosure to the specific embodiments, which are for illustration and understanding only.

[0006] Views referred to as "sections," "profiles," "plans," and "isometrics" correspond to orthogonal planes within a Cartesian coordinate system. Thus, section and profile views are taken in the xz plane, plan views are taken in the xy plane, and isometric views are taken in a three-dimensional Cartesian coordinate system (xyz). Drawings are labeled, where appropriate, with axes indicating the orientation of the view. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 illustrates a process flow diagram of an exemplary method for fabricating a package-integrated in-plane inductor (shown in FIGS. 2A-2M) according to an embodiment of the present disclosure. [Figure 2A] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2B] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2C] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2D] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2E]1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2F] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2G] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2H] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2I] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2J] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2K] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2L] 1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 2M]1A-1C illustrate cross-sectional and plan views of representative structures formed at different stages of an example process flow for forming a package substrate with an embedded inductor according to an embodiment of the present disclosure. [Figure 3A] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 3B] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 3C] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 3D] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 3E] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 3F] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 3G] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4A]1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4B] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4C] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4D] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4E] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4F] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 4G] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5A] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5B]1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5C] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5D] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5E] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5F] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 5G] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6A] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6B] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6C]1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6D] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6E] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6F] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6G] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6H] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6I] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6J] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6K]1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6L] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6M] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6N] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6O] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6P] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6Q] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 6R] 1A-1C illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate having a package-embedded inductor according to certain embodiments of the present disclosure. [Figure 7] FIG. 2 illustrates a cross-sectional view in the xz plane of an example package assembly having an IC chip and a package substrate bonded to a host member, according to an embodiment of the present disclosure. [Figure 8] FIG. 1 illustrates a block diagram of a computing device incorporating certain embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the specification, references to "an embodiment," "one embodiment," "an embodiment," or "an other embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments, but this does not necessarily mean that it is included in all embodiments. Various appearances of "an embodiment," "an embodiment," or "an embodiment" do not necessarily all refer to the same embodiment. When the specification states that an element "may include," "may include," or "could include," that particular element, feature, structure, or characteristic does not necessarily need to be included. When the specification or claims refer to "a" or "an" element, this does not mean that only one of the element is present. When the specification or claims refer to "additional" elements, it does not exclude the inclusion of more than one of the additional elements.

[0009] Herein, the term "circuit" or "module" may refer to one or more passive and / or active components arranged in cooperation with each other to provide a desired function, and the term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

[0010] The term "microprocessor" generally refers to an integrated circuit (IC) package that includes a central processing unit (CPU), a graphical processing unit (GPU, field-programmed gate array (FPGA)), or a microcontroller. The microprocessor package is referred to as the "microprocessor" in this disclosure. The microprocessor socket receives the microprocessor and electrically couples it to a printed circuit board (PCB).

[0011] The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on." Vertical orientation is the z direction, and the terms "top," "bottom," "top," "above," and "below" are understood to represent relative positions in the z dimension with their usual meanings. Typically, "top," "top," and "above" represent positions above in the z dimension, while "bottom," "below," and "below" represent positions below in the z dimension. As used in this disclosure, the term "on" is used to indicate that one feature or object is above and in direct contact with the feature or object below. However, it is understood that embodiments are not necessarily limited to the orientations or configurations depicted in the drawings.

[0012] The terms "substantially," "close," "approximately," "near," and "about" generally mean within ±10% of a target value (unless otherwise specified). The use of general adjectives such as "first," "second," and "third," unless otherwise specified, merely indicates that different instances of similar objects are being referenced to describe a common object, and does not imply that the objects so described must be in a given order, temporally, spatially, in ranking, or in any other way.

[0013] For purposes of this disclosure, the terms "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the terms "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0014] Described herein are embodiments of package-integrated inductive structures and methods for fabricating package-integrated inductive structures. As described herein, lithography steps and magnetic material settings may be minimized. Also, the described embodiments may completely encapsulate the inductor metallization in a single magnetic material without de-paneling the package substrate during processing.

[0015] 1 illustrates a process flow diagram of a method 100 for fabricating a package-integrated in-plane inductor in accordance with an embodiment of the present disclosure. Method 100 may be implemented as part of a panelized IC package substrate manufacturing process that is compatible with coreless package substrate structures. Such a process may also be implemented as part of an IC package substrate manufacturing process that is compatible with core substrate technology.

[0016] Operation 101 includes forming one or more metallization layers on a build-up material. The metallization layers may be formed between dielectric layers in a package substrate build-up stack. The stack may be formed by laminating sheets of dielectric material, for example, in a hot roller or vacuum lamination process. The newly laminated sheets are combined with the underlying dielectric to form a monolithic dielectric substrate. In one operation, the laminated sheets have a copper film (e.g., 2 μm) that provides a plating seed surface. After the dielectric lamination cycle, a metal such as copper may be plated over the exposed surface of the dielectric to form the metallization layer. The plated metallization layer may be unstructured, or "blanket," and then etched through a lithographically defined photomask to form pre-metal features. Alternatively, the metallization layer may be selectively plated through a lithographically defined photomask to form pre-metal features. One or more additional layers of dielectric may be formed to embed the pre-metal features.

[0017] In operation 102, a subtractive process may form one or more openings through the dielectric to expose portions of the preliminary metal features. In one embodiment, these openings are formed by a laser drilling operation, where the preliminary metal features prevent the laser from penetrating to lower levels of the package substrate. The openings may also be formed by other methods, such as dry and / or wet etching of the dielectric with a lithographically defined etch mask. In etching methods, the preliminary metal features may be used as etch stops.

[0018] In operation 103, a layer of photoresist is deposited over the sidewalls and bottom of the opening, covering the exposed portions of the preliminary metal features. The dielectric surrounding the opening may also be covered with photoresist. In one embodiment, a dry film resist (DFR) is laminated, for example, by a vacuum hot roller / press or vacuum lamination process, to conformally cover the preliminary metal features and the sidewalls of the opening.

[0019] In operation 104, portions of the DFR above at least the exposed portions of the preliminary metal features are patterned to define at least a portion of an inductor routing structure. The pattern features may include, for example, straight or serpentine planar inductor traces, or vertical interconnect paths to the planar inductor traces. The etch mask is then removed, leaving the inductor routing structure at the bottom of the opening in the package material stack.

[0020] In operation 105, a magnetic material is deposited over the inductor routing structure, at least partially filling the opening. A formable paste or viscous matrix having magnetic particles may be inkjet printed or screen printed into the opening, for example. The magnetic material may be selected to have a suitable magnetic permeability. The opening may be completely filled, covering the inductor trace features and the sidewalls of the opening. After deposition, curing may harden the matrix into a solid magnetic material that partially encapsulates the inductor structure. The resulting inductive device may have a specific inductance determined by the structure of the inductor trace and the size and permeability of the core containing the magnetic material.

[0021] Using the techniques described above, the inductor structure may be fully encapsulated by first forming a magnetic material underneath the preliminary metal features. As further shown below, for example, through preliminary repetitions of operations 101, 102, and 105, an underlying magnetic material may be formed such that the inductive device includes an inductor routing structure embedded between two magnetic material-filled openings stacked above each other. In another example, the underlying magnetic material may be formed as part of a composite foil that may be applied as part of operation 101, such that the inductive device has an inductor routing structure and a single magnetic material-filled opening.

[0022] In operation 106, the magnetic material is capped with one or more layers of dielectric material, completely burying the inductive structure within the package substrate dielectric. Any number of additional build-up dielectric and / or metallization layers may be formed by any known technique to arrive at a final package substrate structure suitable for a given IC chip and / or application.

[0023] 2A-2M show cross-sectional and plan views of representative structures formed at different stages of an exemplary method for forming a package substrate 200 having an embedded inductor according to one embodiment of method 100. FIG.

[0024] In FIG. 2A, an in-process IC package substrate stack 201 is received. The package substrate stack 201 includes a dielectric 202. In one embodiment, the dielectric 202 includes a material such as, but not limited to, an epoxy phenolic resin or an epoxy cyanate ester resin, as a dielectric build-up film laminated onto a package core or carrier panel in a coreless package substrate implementation. The epoxy resin laminate may have a thickness ranging, for example, between 10 and 100 μm. The package substrate stack 201 may be formed by a build-up of multiple layers of epoxy resin-based dielectric thin film layers sequentially laminated onto a growth stack. The package substrate stack structure may accommodate, for example, a flip-chip package structure or a bumpless build-up level (BBUL) package structure.

[0025] The layers of metallization between the dielectric layers may comprise copper, other suitable metals, or other conductive materials electroplated or formed directly on the dielectric material after any given iteration of the lamination process. The conductive layers may be numbered as levels of metallization within the package substrate stack 201. The highest level of metallization may be the Nth or N+mth level on or nearest the first (e.g., top) side of the package substrate, formed above multiple metallization layers N-1, N-2, etc., buried successively deeper within the package dielectric material within the package substrate stack 201. Typically, the bottom level metallization (e.g., including die interconnects) is the level of metallization nearest the second side (e.g., bottom) of the package substrate stack 201. As an example, a copper layer may be sputtered, plated, or copper foil may be laminated as metallization layer N-1 of the in-process package substrate stack 201. The copper layer may have a thickness of, for example, 5 to 50 μm and may be patterned to include metal features, such as interconnects, that attach package substrate stack 201 to an IC die or host component (not shown). Metallization level N-1 is patterned to include metallization features 203. In embodiments in which metallization level N-1 is plated, metallization features 203 may be formed by a semi-additive process (SAP). For example, a plating mask may be used to form metallization features 203. In embodiments in which metallization level N-1 is applied as a foil or plated without the use of a mask, metallization features 203 may be formed by a subtractive process. For example, a masked etching process (e.g., wet chemistry) may be used to form metallization features 203.

[0026] Dielectric layer 202 may be disposed across metallization level N-1 at a distance h1 below upper surface 204 to metallization feature 203 embedded within dielectric 202. Metallization feature 203 may have any shape in the plane of metallization level N-1. Metallization feature 203 may have, for example, lateral dimensions (x and y planes) of approximately 500 μm to 20 mm and a thickness (e.g., z-axis) in the range of 15 to 200 μm. Although not shown, a coplanar metallization feature within conductive level N-1 may be adjacent to metallization feature 203.

[0027] In FIG. 2B , an opening 205 is formed in the upper dielectric 202. In one embodiment, the opening 205 is formed by laser drilling to a depth h1, exposing at least a portion of the metallization feature 203. One or more openings 205 may be formed by laser ablation of the dielectric material, e.g., by intense heat generated by laser energy. For example, a CO or Nd:YAG laser may be used as the laser source. The metallization feature 203 may block the laser beam (e.g., as a laser stop layer) and prevent the laser beam from penetrating into the dielectric material below the package substrate stack 201. Laser ablation of the dielectric 202 may result in tapered sidewalls 206, as shown. The slope angle θ1 of the sidewalls 206 may range from 45° to 85° with respect to the plane of the metallization level N−1. As a result of the sloped sidewalls, the opening 205 may have a larger span at the opening (e.g., at the intersection of the sidewalls 206 and the surface 204). For example, distance d2 may be greater than d1 × h1 tan(π / 2 − θ1). The laser may cause slight ablation of some of the metal from the surface of the metallization feature 203 itself, resulting in scalloping or other damage artifacts indicative of the laser drilling process. For example, ablation of the metallization feature 203 may excavate the metal to a depth ranging from 100 nm to 2-3 μm. Additionally, unablated remnants of the upper dielectric may be deposited on the surface of the laser stop layer in the form of small particles of inorganic fill material.

[0028] In another embodiment, the opening 205 may be formed by a wet or dry masked etching process. In some dry etching processes, the sidewalls 206 are substantially straight. In such embodiments, the metallization feature 203 may act as an etch stop layer because the etch rate of metals such as copper is much slower than the etch rate of organic materials by etchants. Thus, the metallization feature 203 may protect the underlying dielectric material from the etching process.

[0029] The opening 205 may be formed to a depth h1 (e.g., z-height) of, for example, 15 to 200 μm. The opening 205 may have a length d1, measured at the bottom of the opening 205, in the range of 500 μm to 15 mm. The metallization features 203 may be separated by a distance d2 at the bottom of the opening 205 and extend laterally a distance d3 from the bottom of the sidewall 206, for example. In the example shown, the metallization features 203 may have a length (e.g., x-dimension) of d1 + 2d3, where d3 is sufficient to ensure a safe overlap margin between the opening 205 and the metallization features 203. The perimeter of the opening 205 may have any shape within the confines of the metallization features 203. The opening 205 can have lateral dimensions many times larger than the laser drill beam width, so that the laser beam can be rastered over any area to drill an opening between the length and width limits defined by the edges of the metallized feature 203.

[0030] In FIG. 2C , magnetic material 207 is deposited within opening 205, covering metallized feature 203 and sidewall 206. Suitable magnetic materials may include non-conductive magnetic filler particles, such as ferrite or iron oxide powder, dispersed in any matrix material. In some embodiments, the organic matrix may include a crosslinker and polymer precursor that is heat and / or light activated, and once deposited within opening 205, the matrix may harden into a solid and contact sidewall 206 and metallized feature 203. Magnetic material 207 may be deposited within opening 205 as a formable paste or ink and then cured, for example, by heat and / or light treatment. The deposition process may include screen printing or inkjet printing the material into opening 205. During deposition, magnetic material 207 may fill the holes, overflow laterally and vertically (z-direction), and extend above surface 204. A polishing or grinding operation may be performed to planarize the magnetic material 207 to have a surface 204 substantially as shown in Figure 2C.

[0031] In FIG. 2D , another metallization level N is formed on dielectric 202 and magnetic material 207. Metallization level N may comprise a copper foil, and the thickness between surface 204 and surface 208 may range from 5 to 50 μm. In another embodiment, metallization level N may be formed by electroplating or sputtering copper or another suitable metal over surface 204 and the planarized surface of magnetic material 207. In electroplating, a thin conductive seed layer containing copper, gold, silver, or another suitable metal may be deposited in a preliminary operation as a cathode. The seed layer may also be deposited to promote nucleation of a metal precursor in a CVD atmosphere. An adhesion layer containing chromium may be deposited prior to the seed layer.

[0032] In FIG. 2E , a pre-metallization feature 209 is formed on top of magnetic material 207 at metallization level N, extending laterally a distance d3 from an upper boundary of magnetic material 207 defined by the intersection of edge 210 of the magnetic material and surface 204. Pre-metallization feature 209 is one of multiple features formed at metallization level N and is coplanar with adjacent features, such as interconnect traces, pads, and other structures not shown. In this example, pre-metallization feature 209 is patterned subtractively, for example, using an etching process with an etch mask. In another embodiment, pre-metallization feature 209 is selectively formed by SAP, for example, pre-metallization feature 209 may be plated through a patterned plating mask (not shown).

[0033] The pre-metallization feature 209 has any suitable shape and extends laterally (e.g., a distance d3) beyond the upper boundary of the magnetic material 207 at the surface 204, making the pre-metallization feature 209 suitable as a laser or etch stop layer in the formation of an opening above the subsequent metallization level N. The pre-metallization feature 209 may have a lateral dimension of, for example, 500 μm to 20 mm, or greater than the distance d2. The pre-metallization feature 209 may have a thickness (e.g., z-height) between 2 and 15 μm. Depending on whether a subtractive or additive process is performed, the sidewall 211 may be substantially vertical and / or have a rounded top edge, or may have an indicative curvature indicative of an isotropic etching process.

[0034] 2F, dielectric 212 is formed on top of pre-metallization features 209 and on top of dielectric surface 204. In one embodiment, dielectric 212 is laminated as a dielectric sheet on top of package substrate stack 201, for example, in a hot roller or vacuum lamination process. Dielectric 212 may be substantially the same as dielectric 202. In one embodiment, dielectric 212 has a thickness h2 of 10 to 50 μm between pre-metallization features 209 and surface 213.

[0035] In FIG. 2G , openings 214 are formed through dielectric 212 to a depth h2. In one embodiment, openings 214 are formed by a laser drilling process (e.g., similar to the method used to form openings 205) or any suitable etching process. Openings 214 expose pre-metallization features 209 over a length d4. Sidewalls 215 may be sloped at an angle θ2 (e.g., in the range between 45° and 85°) relative to the plane of pre-metallization features 209, for example, as a result of the laser drilling process. Pre-metallization features 209 not exposed by the formation of openings 214 extend laterally outward from each opening sidewall 215 through dielectric 212 a distance d5, where d5 is approximately h2·tan(π / 2−θ2).

[0036] 2H, photoresist 216 is applied over dielectric 212 and opening 214, conformally coating pre-metallization feature 209 on the bottom and sidewalls 215 of opening 214. Photoresist 216 may be, for example, a dry film resist (DFR) having a thickness ranging between 10 μm and 100 μm. The DFR may be applied by vacuum lamination or high temperature lamination, allowing the DFR to soften and / or mold and conform to opening 214.

[0037] In FIG. 2I , a photolithography process patterns photoresist 216 (shown in dashed outline at the top) to include strips 217 and openings 218, which extend vertically in the y-dimension. In one example, strips 217 and openings 218 of pre-metallization features 209 are etched according to the pattern of photoresist 216 to form an in-plane inductor routing structure 219 (shown in dashed silhouette at the bottom) having traces 220 (shown in cross section). In the illustrated embodiment, each trace 220 has a linewidth of 5 to 50 μm, with a minimum spacing s1 between traces 220 of 10 to 100 μm. Because openings 214 overlap the ends of pre-metallization features 209 below, a peripheral “ring” structure 221 including the masked portions of pre-metallization features 209 is adjacent to inductor traces 220 (and is visible in the plan view of FIG. 2M ). Ring structure 221 is electrically isolated from inductor traces 220, which is shown in the implementation of method 100. In the illustrated embodiment, traces 220 are shown with substantially uniform line widths and spacing, but in other embodiments, some traces 220 may have different line widths and spacings. For example, spacing s2 between ring structure 221 and termination traces 220 may be different from minimum inter-trace spacing s1.

[0038] As shown in FIG. 2J, once the photoresist 216 is removed, the etched inductor trace 220 is exposed, and the exposed portion of the ring structure 221 extends into the opening 214. The inductor trace 220 and the ring structure 221 may have a thickness ranging from 5 to 50 μm. The sidewalls 222 of the inductor trace 220 have a sloped and / or curved profile 223 representative of a wet (e.g., isotropic) chemical etching patterning process. The sloped sidewalls 222 provide the inductor trace 220 with a substantially trapezoidal cross-sectional profile, as further shown in the inset, for example. The trapezoidal profile of the inductor trace 220 may result from a subtractive isotropic wet etching process. In this method, lateral chemical etching occurs simultaneously with vertical chemical etching within the exposed metal area. As a result, the sidewalls 222 have a curved, negative taper, resulting in a minimum spacing s1 between the inductor traces 220.

[0039] In one embodiment, the outer wall 224 of the ring structure 221 has a substantially vertical, linear profile, e.g., indicative of the semi-additive pattern of the pre-metallization features 209. The metallization features are electroplated against a patterned plating mask. The plating mask openings may have linear sidewalls that are substantially vertical or slope less than 10° from vertical. The sidewalls 224 may also have rounded top edges 225, which also indicative of the semi-additive pattern of the pre-metallization features 209. As shown in the inset of FIG. 2J of the ring structure 221, the outer wall 224 is not subjected to subtractive etching, while the inner wall 226 of the ring structure 221 is exposed within the opening 214 and is therefore subjected to the subtractive etching process used to pattern the inductor trace 220. Thus, in addition to the presence of the ring structure 221 indicative of method 100, the difference in the profiles of the inner and outer sidewalls 224, 226 is also indicative of the manufacturing technique used.

[0040] As shown in FIG. 2K, a magnetic material 227 is deposited in the opening 214 (e.g., as shown in FIG. 2J) to cover the exposed adjacent portions of the inductor trace 220 and the ring structure 221. The magnetic material may have, for example, similar lateral dimensions to the opening 214 (e.g., 500 μm to 15 mm) and a thickness (z-height) between 5 μm and 100 μm. In the illustrated embodiment, the ring structure 221 extends across an interface 228 at the boundary between the magnetic material 227 and the dielectric 212. An inner wall 226 is within the magnetic material 227, and an outer wall 224 is embedded within the dielectric 212.

[0041] In some embodiments, magnetic material 227 is substantially the same material as magnetic material 207 described above. In other embodiments, magnetic material 227 is a different material than magnetic material 207. Magnetic material 227 may have a relative magnetic permeability of, for example, 5 to 10. Magnetic material 227 may be deposited by printing the material into opening 214. In some embodiments, magnetic material 227 has a relatively low initial viscosity, which may be printed directly into opening 214 by inkjet printing. In some embodiments, magnetic material 227 is part of a paste otherwise disposed across surface 228 of dielectric 212, filling opening 214. Magnetic material 227 may contact underlying magnetic material 207 through openings 218 between inductor traces 220, forming continuous mass-encapsulated inductor traces 220. Excess material may be removed from surface 229, leaving magnetic material 227 within opening 214 at surface 228.

[0042] A thermal or photochemical curing process may then be performed to harden the magnetic material 227. The inductor trace 220 is fully embedded in the magnetic materials (e.g., the lower magnetic material 207 and the upper magnetic material 227). The combined magnetic materials may form a magnetic core that encapsulates the inductor trace 220. The in-plane inductor structure 219 is fully embedded in the dielectric of the package substrate 200. The magnetic core, with the inductor trace 220 fully embedded, is formed from the combined magnetic materials 207, 227, and has a total thickness in the range of 10 to 200 μm and a relative magnetic permeability between 5 and 10. The ring structure 221 extends across the interface between the magnetic material 227 and the adjacent dielectric 212, and the outer wall 224 is embedded in the dielectric 212. The magnetic material 227 may be planarized to have a surface 229 by a polishing and / or grinding process (e.g., chemical mechanical polishing, CMP).

[0043] 2L, fabrication of in-plane inductor structure 219 is substantially complete. Magnetic material 227 is capped with a dielectric material, for example, by depositing dielectric 230 over surface 229 to complete package substrate 200 or for subsequent metallization level adjustment.

[0044] FIG. 2M shows a plan view in the xy plane of metallization level N. Line A-A′ across the plan view indicates the location of the cross section shown in FIG. 2L. As shown in FIG. 2M, inductor trace 220 is a continuous serpentine trace structure 231 including multiple interconnected parallel segments. Inductor structure 219 crosses the A-A′ plane and terminates with interconnect pad 232. Interconnect pad 232 may be a via cap or may vertically interconnect to higher (e.g., N+1) and / or lower (e.g., N−1) levels of metallization within package substrate 200. Inductor trace 220 is interconnected to package land pads at the bottom of package substrate 200 (not shown) through a lower metallization level and bonded to external circuitry (e.g., mounted in a socket or surface mounted directly to a printed circuit board).

[0045] Ring structure 221 is shown as a rectangular perimeter feature surrounding inductor trace 220. In the illustrated embodiment, inductor structure 219 is bounded by outer wall 224 of ring structure 221 within dielectric 212. In some implementations, ring structure 221 is interconnected to other metallized features. For example, ring structure 221 may be electrically grounded via a vertical or lateral trace path (not shown) coupled to a ground plane within the package substrate or in a printed circuit board electrically coupled to the package substrate. In some embodiments, ring structure 221 may be electrically floating or connected to any reference voltage source.

[0046] 3A-3G illustrate cross-sectional views of representative structures formed at different stages of an exemplary process flow for forming a package substrate 300 having a package-embedded inductor according to another embodiment of method 100. FIG.

[0047] The process shown in Figure 3A may be preceded by process operations similar to those shown in Figures 2A-2D. Package substrate stack 301 may be obtained, for example, as an in-process structure as shown in Figure 2C. Accordingly, the descriptions regarding the metal and dielectric structures obtained and shown in Figures 2A-2C are also applicable to package substrate stack 301.

[0048] In FIG. 3A , pre-metallization structure 302 and adjacent trace path 303 are formed by a semi-additive process (SAP) on level N. An example SAP may include deposition of a suitable metal (e.g., copper) into openings patterned in a lithographically defined plating mask formed across surface 204 of dielectric 202 and magnetic material 207 in a previous operation. Pre-metallization structure 302 and adjacent trace path 303 may also be plated into lithographically defined openings in a photoresist deposition mask formed across surface 204 in a previous operation (not shown). The electroplated structure may have a thickness h3 in the range of 2 to 50 μm. Pre-metallization feature 302 has a lateral dimension in the x-y plane in the range of 500 μm to 20 mm, which covers and may extend beyond the top edge of magnetic material 207.

[0049] The inset of Figure 3A shows a close-up view of the pre-metallization structure 302 and trace path 303. The sidewalls 304 may have a substantially vertical profile, indicative of a semi-additive process (e.g., a metal electroplating process), as previously described. The top edge 305 may have a rounded profile, as shown in the inset. The spacing between the sidewalls 304 is measured by a minimum spacing s3, which may scale with technology node but is typically smaller than the minimum spacing achievable via a subtractive process.

[0050] 3B, a dielectric 306 is formed over the metallization structures and open dielectric surface 204. The dielectric 306 may be formed as described above. The dielectric 306 may be conformally laminated over the surface 204, for example, by a hot roller or a high-temperature vacuum lamination process, filling the spaces between the metallization structures. The dielectric 306 may have a thickness ranging, for example, between 5 and 100 μm.

[0051] In FIG. 3C , an opening 307 and a via opening 308 are formed in the dielectric 306 above the pre-metallization feature 302 and the pad 309, respectively. The opening 307 may be formed by a laser drilling operation, as previously described, to a depth determined by the distance h4 between the surface 310 and the pre-metallization feature 302. As previously described, the pre-metallization feature 302 may block the laser from penetrating the magnetic material 207. In another embodiment, the opening 307 may be formed by a chemical etching method. The sidewall 311 may have a slope of between 45° and 85° from the plane of the pre-metallization feature 302, which may again suggest a laser drilling process. The opening 307 may have at least one lateral dimension d6 (measured from the bottom of the opening) in the range of 500 μm to 15 mm.

[0052] Alternatively, the via opening 308 may be formed by a laser drilling operation to a depth of h3 (e.g., 100 μm), exposing a portion of the pad 309. In another embodiment, the via opening 308 may instead be formed by a suitable etching process. The via opening 308 may have a circular cross-section in the xy plane, although other suitable cross-sectional profiles are possible. In one embodiment, the sidewalls 312 of the via opening 308 may be sloped at between 45° and 85°.

[0053] 3D , metallization layer 313 is conformally deposited over opening 307, via opening 308, exposed portions of pre-metallization features 302, and surface 310 of dielectric 306. For example, copper or another suitable metal may be deposited by electrolytic or electroless plating to fill via opening 308 and form via 314 above pad 309. Metallization layer 313 has a thickness h5 (e.g., up to 50 μm thick) over surface 310 and pre-metallization features 302. The deposited metallization layer 313 may increase the metal thickness over the exposed portions of pre-metallization features 302 by approximately h5. The increased metal thickness at the bottom of opening 307 can be significant in lowering the resistance of the inductor trace.

[0054] 3E, photoresist 315 is deposited over metallization layer 313. In one embodiment, photoresist 315 is a dry film resist (DFR) and is deposited over metallization layer 313, for example, substantially as described above.

[0055] In FIG. 3F, metallization layer 302 is patterned using a subtractive process (e.g., isotropic wet chemical etching) to simultaneously define features on metallization levels N and N+1. Metallization layer 313 is patterned into trace paths 317, including multiple inductor traces on level N and via pads 318 on level N+1, across surface 310 of dielectric 306. Inductor traces 316 are multiple interconnected parallel traces, and may form one or more in-plane serpentine inductor lines. Sidewalls 319 have a trapezoidal profile in the xz plane, which may represent an isotropic etch, as previously described. Inductor traces 316 may have a thickness (e.g., z-height) of h6, a width of w4 (e.g., 20 to 50 μm), and be separated by a minimum spacing s4 (e.g., 20 to 50 μm). The z-height h6 may be approximately the sum of h3 and h5. The minimum spacing s4 of the inductor traces 316 formed by the subtractive isotropic etching process may be significantly larger than the minimum spacing s3 of the SAP structures 303 within the same N-1 metallization level.

[0056] Metallization structures on level N+1, such as trace path 317, may have a thickness (z-height) h5, as shown in the example. Trace path 317 has a minimum pitch that is expected to be significantly larger than feature 303 and larger than that of inductor trace 316 as a result of the difference between thicknesses h5 and h6. The larger thickness of inductor trace 316 compared to other metallization structures may reduce the resistance of the inductor window.

[0057] At level N, a ring structure 320 is formed simultaneously with the inductor trace 316. As shown in FIG. 3F, the ring structure 320 extends horizontally below the dielectric 306 at a distance d7 from the sidewall 311 and is protected from chemical attack. The ring structure 320 is etched back to the sidewall 311 of the opening 307. The inner sidewall 319 of the ring structure 320 may have a concave profile indicating isotropic etching. The ring structure 320 may be completely etched to the opening sidewall 311, or a part of the ring structure 320 may remain within the opening 307. The width w3 of the ring structure 320 may depend on the etching rate and time. The ring structure 320 has a thickness h3 < h6. The ring structure 320 surrounds the inductor trace 316 but may be electrically insulated from the inductor trace 316. In some embodiments, the ring structure 320 may be interconnected with a ground plane or ground metallization, for example, a ground protection ring may be provided around the inductor trace 316.

[0058] In FIG. 3G, a magnetic material 321 is deposited within the opening 307 to encapsulate the inductor trace 316. The magnetic material 321 may be planarized to have a surface 310 as shown in the figure. In some embodiments, the magnetic material 321 has substantially the same composition as the magnetic material 207. Other suitable compositions are also possible. The magnetic material 307 may contact the magnetic material 207 below the inductor trace 316 to form a continuous magnetic core that encapsulates the inductor trace 316. In some embodiments, the inductor traces 316 are interconnected to form a serpentine structure similar to the inductor structure 231 as shown in FIG. 2M. The ring structure 320 may extend substantially across the interface between the dielectric 306 adjacent to the magnetic material 321 as shown in FIG. 2M.

[0059] Dielectric 322 is formed over surface 310, encapsulating metallization structures 317, 318 and capping magnetic material 321 and dielectric 306 to complete package substrate 300. Dielectric 322 may be the same as or similar to the package dielectric materials discussed above and may be laminated as discussed above. In one embodiment, the formation of dielectric 322 substantially completes the fabrication of buried inductor structure 323 (encircled by dashed outline).

[0060] 4A-4G illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate 400 having a package-embedded inductor according to another embodiment of method 100. FIG.

[0061] The process shown in Figure 4A may be preceded by operations similar to those shown in Figures 3A-3B. Package substrate stack 401 may be obtained, for example, during the fabrication of the structure shown in Figure 3B. Accordingly, the descriptions relating to the resulting metal and dielectric structures shown in Figures 2A-2C are also applicable to package substrate stack 401.

[0062] In FIG. 4A , package substrate stack 401 has substantially the same structure as package substrate stack 301 in FIG. 3C , including dielectric 202 and magnetic material 207 embedded within dielectric 202. Metallization feature 203 is in metallization level N−1 and is directly below magnetic material 207. Trace path 303 is coplanar with pre-metallization feature 302 in metallization level N, where pre-metallization feature 302 covers magnetic material 207. For example, a laser drilling process may be used to form opening 307 and expose a portion of pre-metallization feature 302, forming sloped sidewall 319 as described above. Level N metallization feature 302 and adjacent coplanar trace path 303 may be formed by the semi-additive plating process described above. In the example shown, pre-metallization feature 302 and trace path 303 have substantially vertical sidewalls. The features on level N (eg, pre-metallization feature 302 and adjacent trace path 303) may have a thickness h3 (eg, z-height of 5 to 50 μm).

[0063] 4B, photoresist 402 is conformally deposited over surface 310, covering sidewalls 319 and pre-metallization features 302. In one embodiment, photoresist 402 is a laminated DFR, as described above, having a thickness of, for example, between 10 and 100 μm.

[0064] In Figure 4C, photoresist 402 is patterned into an etch mask having openings 403. Isotropic etching through openings 403 may form inductor traces 404 and ring structures 405. Inductor traces 404 and surrounding ring structures 405 have concave sidewalls 406, 407, respectively. Inductor traces 404 are separated by a minimum spacing s6, as shown. Spacing s6 may be significantly larger than the minimum spacing s5 between adjacent trace path structures 303.

[0065] 4D , magnetic material 408 is deposited in opening 307 to encapsulate traces 404. Magnetic material 408 is shown overflowing sidewall 319, forming overhangs 409 that extend across adjacent regions of dielectric 306. Magnetic material 408 may, for example, have substantially the same material as magnetic material 207. Magnetic material 408 extends between inductor traces 404 and contacts magnetic material 207 below inductor traces 404, forming a continuous magnetic core that completely encapsulates inductor traces 404.

[0066] 4E, a via opening 410 is formed in the dielectric 306 adjacent the sidewall 315. The via opening 410 may be formed by a laser drilling process, as previously described. Prior to the formation of the via opening 410, the magnetic material 408 may be planarized with an overhang 409.

[0067] 4F , trace path 411 on level N+1 may be formed by a semi-additive plating process across surface 310 adjacent sidewall 311 and adjacent via pad 412 over via 413. Prior to the formation of structures 411 and 412, via opening 410 may be filled and via 413 formed by an electrolytic or electroless plating process. As a result of feature resolution differences between subtractive and SAP fabrication techniques, trace path 411 on level N+1 may have a minimum spacing s6 that is the same as or similar to spacing s5 of trace path 303 on level N.

[0068] 4G, dielectric 414 is deposited over metallization level N+1, magnetic material 408, and surface 310, substantially completing the fabrication of buried inductor structure 415 (outlined in dashed outline). Inductor structure 415 has magnetic materials 207, 408 encapsulating inductor trace 404.

[0069] 5A-5G illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate 500 having a package-embedded inductor according to another embodiment of method 100. FIG.

[0070] In FIG. 5A , package substrate stack 501 has metallization features 502 embedded in dielectric 503 on level N+1. Magnetic material is incorporated into package substrate stack 501 as a layer in a multilayer sheet of thin film laminated on dielectric 503. Multilayer thin film 4 includes a sheet of high magnetic permeability material 504, such as a nickel-iron (NiFe) or nickel-cobalt (NiCo) alloy, having a relative magnetic permeability in the range of, for example, 10,000 to 30,000. Magnetic material 504 has a thickness in the range of 5 to 500 μm and may be joined with non-magnetic material 505, for example, having a thickness in the range of 5 to 500 μm. Non-magnetic material 505 may be copper or another conductive material suitable for metallization level N of package substrate stack 501.

[0071] In FIG. 5B, photoresist 506 is applied and patterned on top of the multilayer thin film. Photoresist 506 may be a DFR or liquid resist. A suitable etching process etches at least through the non-magnetic material 505 and may also etch through the magnetic material 504, where the material has a high electrical conductivity (e.g., NiFe, NiCo, etc.). As shown, patterned structure 507 has pre-metallization features 508 etched from non-magnetic material 505 above magnetic material features 509 etched from magnetic material 504. Pre-metallization features 508 and magnetic thin film features 509 may have lateral dimensions ranging, for example, between 500 μm and 20 mm. A suitable etching process, such as a wet etching bath of acid and / or oxidant, may be used to attack the metal in both materials. The etch rate may be similar for both thin films. In the example shown, an isotropic wet etch is used to form undercut, recessed sidewalls 510, 511, respectively, of pre-metallization feature 508 and magnetic thin film feature 509. Due to varying etch rates for different materials, the amount of recession of the illustrated sidewalls varies slightly for each film, as indicated by the lateral offset of sidewalls 510 and 511.

[0072] 5C , dielectric 512 is formed on top of dielectric 503 and pre-metallization feature 508 by a lamination process or another suitable method, as described above. Opening 513 is formed over pre-metallization feature 508 by a laser drilling or etching process, as described above. Formation of opening 513 may expose a portion of pre-metallization feature 508 at a bottom of opening 513. The exposed portion of pre-metallization feature 508 may have a lateral dimension (e.g., length) d8, for example, in the range of 500 μm to 15 mm. Opening 513 has sidewalls 514. In one embodiment, sidewalls 514 are inclined at an angle θ3 (e.g., 45° to 85°) with respect to the plane of pre-metallization feature 508.

[0073] 5D, photoresist 515 is conformally deposited over package substrate stack 501, covering dielectric 512, sidewalls 514 of opening 513, and pre-metallization features 508. Photoresist 515 may be, for example, a DFR stack. Photoresist 515 may be patterned to form an etch mask over pre-metallization features 508 and magnetic thin film features 509.

[0074] In FIG. 5E, lithographically formed stripes and openings in photoresist 515 (not shown) are transferred to pre-metallization features 508 and magnetic thin film features 509. Both structures are simultaneously patterned, for example, by isotropic wet etching, to form concave sidewalls 516 and 517, respectively, of multiple etched copper inductor traces 518 and magnetic strips 519 below the inductor traces 518. Sidewalls 516 and 517 may have substantially the same profile as sidewalls 510 and 511, respectively, obtained in the lithography process shown in FIG. 5B. Inductor traces 518 may have a spacing represented by a minimum spacing s7 (e.g., 5 to 50 μm). Openings 520 are etched in magnetic thin film features 509 to form multiple magnetic strips 519 below the inductor traces 518 and expose portions of dielectric 503 between the magnetic strips 519. Openings 520 (depicted in dashed outline) coincide with spaces 521 between inductor traces 518 (also depicted as such).

[0075] A ring structure 522 is formed around the copper film and is separated from the inductor trace 518 by a patterning process. The ring structure 522 and a portion of the underlying magnetic material 509 extend from the sidewall 514 through the dielectric 512. The ring structure 522 has an outer sidewall 510 formed in the etching process shown in FIG. 5B (e.g., before the formation of the dielectric 512) and an inner sidewall 516 obtained during the formation of the inductor trace 518. In an embodiment, the ring structure 522 may be interconnected with the inductor trace 518. In an embodiment, the ring 522 is electrically isolated from the inductor trace 518. In the illustrated embodiment, the ring structure 522 extends asymmetrically from the opening sidewall 514, for example, to provide a vertical interconnect land pad, as described below.

[0076] In FIG. 5F, magnetic material 523 is deposited within opening 513. In some embodiments, magnetic material 523 may have a similar or substantially the same composition as the magnetic materials previously described (e.g., magnetic material 207). Magnetic material 523 has a different composition than magnetic strip 519. Magnetic material 523 may be deposited, for example, by inkjet or screen printing, as previously described. In the embodiment shown, magnetic material 523 has surface 524 that is flat and surrounds dielectric 512. After deposition and curing of magnetic material 523, polishing and grinding operations (not shown) may be performed to achieve planarization with the surrounding dielectric 512.

[0077] Magnetic material 523 extends through opening 520 and space 521 to the floor of (former) opening 513 and contacts the top surface of dielectric 503, encapsulating inductor trace 518 within the magnetic material and electrically insulating high permeability magnetic strip 519. Inductor trace 518 is completely encapsulated within the magnetic material by both magnetic strip 519 (below) and magnetic material 523 (above and adjacent to the sidewalls).

[0078] In a subsequent operation, metallization features 525 are formed at level N+1 on surface 524. Metallization features 525 may be formed by a semi-additive process, for example, by plating copper or other suitable metal through a plating mask, as described above. Sidewalls 526 of metallization features 525 may be substantially vertical (slope of 10° or less) and have rounded top edges, representing semi-additive formation of metal structures by deposition onto a plating mask. Metallization features 525 may have a minimum spacing s8 that is smaller than the minimum spacing s7 between inductor traces 518 on level N.

[0079] In FIG. 5G, a dielectric 527 is formed on top of package substrate stack 501, covering dielectric 512 and metallization feature 525. Magnetic material 523 is capped by dielectric 527 and completely embedded within package substrate stack 501. In a subsequent operation, a level N+2 metallization feature 528 is formed on top of dielectric 527. Metallization feature 528 may be formed by a semi-additive plating process (or a subtractive metal etching process) to form, for example, an upper-level interconnect pad that may receive a solder bump or other interconnect. Via 529 may be formed by plating into openings formed in both dielectrics 527 and 512 that expose a portion of ring structure 522. Via 529 interconnects ring structure 522 (on level N) with the metallization on level N+2. Via cap 530 may be formed simultaneously with metallization feature 528. In one embodiment, the formation of metallization features on level N+2 substantially completes the fabrication of package substrate 500. In the example shown, via 529 interconnects ring structure 522 with an upper metallization level N+2. Ring structure 522 may also be interconnected with external ground circuitry (e.g., on a printed circuit board) through via 529.

[0080] As shown in the illustrated embodiment, magnetic strip 519 has a significantly smaller z-height than magnetic material 523 and may occupy a relatively small portion of the magnetic core, including both magnetic material 523 and magnetic strip 519. In the illustrated embodiment, the high magnetic permeability of magnetic strip 519, as shown as the structure enclosed within the dashed outline, dominates the overall magnetic permeability of the magnetic core (e.g., including magnetic material 523 and magnetic strip 519) of inductor structure 531. The magnetic permeability of the combined core may be thousands of times greater than the permeability of magnetic material 523 alone. The significant increase in permeability reduces the z-height requirements of the combined core structure, allowing for a reduced overall z-height of package substrate 500.

[0081] 6A-6R illustrate cross-sectional views of representative structures formed at different stages of an example process flow for forming a package substrate 600 having a package-embedded inductor according to another embodiment of method 100. FIG.

[0082] 6A, package substrate stack 601 has dielectric 602 and buried metallization feature 603 (level N-1). Pre-metallization feature 604 and adjacent metal features (e.g., via pad 605) are formed on level N above dielectric 602 in a previous metallization operation, including semi-additive or subtractive metallization processes, as described above. Vias 606 and 607 interconnect the metallization structure on level N, including pre-metallization feature 604, to metallization structure 603 on level N-1.

[0083] In Figure 6B, dielectric 608 is formed on top of dielectric 602, covering pre-metallization feature 604 and adjacent metallization (e.g., pad 605). As shown in Figure 6C, opening 609 is formed in dielectric 608 by the laser drilling process or etching operation described above. Opening 609 is formed to a depth h7, for example, in the range of 5 to 100 μm, exposing a portion of pre-metallization feature 604. In the illustrated embodiment, sidewall 610 has a slope angle θ4, for example, in the range of between 45° and 85°, for example, as a result of the laser drilling process.

[0084] 6D, a conformal metal layer 611 of seed metal is deposited over the dielectric 608, sidewalls 610, and pre-metallization features 604. The metal layer 611 may be formed by sputtering or electroless deposition of a suitable metal, such as copper, on the dielectric 608 to a thickness h9 in the range of 5 to 50 μm. The metal layer 611 is deposited on the pre-metallization features 604, so that the total thickness of the structure is approximately the sum of h7 and h9. 10 increases to.

[0085] 6E, photoresist 612 is applied across package substrate stack 601. Photoresist 612 may be, for example, a DFR laminate. Photoresist 612 has a thickness h that is greater than the depth h8 of opening 609. 11 (in the range of 15 to 150 μm). Photoresist 612 may be patterned in a lithography operation to form openings 613 in the act shown in FIG. 6F.

[0086] In FIG. 6G, pillars 615 are deposited in openings 613. Pillars 615 may be formed by electrolytic (or electroless) deposition of copper or other suitable metal into openings 613. As shown, pillars 615 fill openings 613 and may extend above photoresist 612. For example, photoresist 612 may have a thickness of 15 μm, and pillars 615 may be grown to a z-height of 20 μm and extend, for example, 5 μm above via 606. Seed metal layer 611 and pre-metallization features 604 are etched to expose the underlying dielectric (e.g., dielectrics 602, 608). Ring structures 616 may remain from the previous etch.

[0087] 6I, magnetic material 617 is deposited in opening 609, embedding pillar 615. Magnetic material 617 may be any magnetic material paste or ink described above in this disclosure (e.g., the same as magnetic material 207). Magnetic material 617 may overfill opening 609 and extend over dielectric 608, forming overhang 618.

[0088] In FIG. 6J, the magnetic material 617 and pillars 615 are planarized along with the dielectric 608. In FIG. 6K, metallization level N+1 is formed on the package substrate stack 601 above the dielectric 608 and magnetic material 617. The pre-metallization feature 619 and adjacent metallization (e.g., via pad 620) may be formed as a SAP metal structure, where the structure has substantially vertical, straight sidewalls as shown, or may be formed by a subtractive etching process that forms concave sidewalls. The via 621, the interconnection between metallization level N and metallization level N+1, may be formed in the electrodeposition process described above. The pillars 615 interconnect the pre-metallization feature 619 (which is later patterned into inductor traces) with the underlying metallization (e.g., metallization structure 603). The pre-metallization feature 619 may have at least the same lateral dimensions (e.g., up to 20 mm) as the magnetic material 617.

[0089] In Figure 6L, a dielectric 622 is formed over the N+1 metallization with pre-metallization features 619. In Figure 6M, an opening 623 is formed in the dielectric 622 (e.g., by a laser drilling process or the etching methods described above). The opening 623 may be the same size (e.g., width, depth) as the opening 609 formed in the operation shown in Figure 6C, or it may be smaller. In the process shown in Figure 6N, a photoresist 624 is conformally applied (e.g., deposited or spin-coated) over the package substrate stack 601, covering the sidewalls 611 at the opening 623 and the pre-metallization features 619. The photoresist 624 provides a lithographically patterned etch mask from which an inductor structure may be formed from the pre-metallization features 619.

[0090] In Figure 6O, a subtractive etching process (described above) forms multiple inductor traces 625 on level N+1, transferring the lithographic pattern formed in the previous operation to pre-metallization features 619. The inductor traces 625 may have concave sidewalls and a trapezoidal profile, indicative of an isotropic etching process, as described above. The etching process simultaneously forms pads 626 on top of the pillars 615, and the inductor traces 625 may be coupled to the pillars 615 for vertical interconnect paths. A ring structure 627 extends from inside the opening 623 through the sidewalls 628 and into the dielectric 622.

[0091] 6P, magnetic material 629 is deposited in opening 623 to cover inductor trace 625. The magnetic material may have the same or similar composition and magnetic properties (e.g., a relative permeability of 5 to 10) as magnetic material 617 and may extend between and contact inductor trace 625 with magnetic material 617. Thus, a continuous magnetic inductor core may sufficiently encapsulate the inductor trace in the magnetic material, and inductor structure 630 (depicted in dashed outline) may be formed.

[0092] 6Q, dielectric 631 is formed over package substrate stack 601, with inductor structure 630 (shown in dashed outline) fully embedded in the package dielectric. Metallization N+2 is formed over dielectric 631 to complete package 600. Via 632 is formed and extends from via pad 633 on an upper level (e.g., level N+2) to via pad 620 on level N+1. Via 632 may be part of a power path within package 500.

[0093] FIG. 6R shows a plan view in the xy plane of metallization level N+1. Line A-A' across the plan view represents the location of the cross section shown in FIG. 6Q. As shown in FIG. 6R, inductor traces 625 are arranged in a continuous serpentine structure configured to form a single inductor trace 634 (dashed outline). Pad 626 terminates inductor trace 634 and, in some embodiments, may be interconnected to a higher level of metallization by forming a via on pad 626. As shown in FIG. 6Q, via pad 620 is interconnected with metallization pad 633 on the upper level. Ring structure 627 is shown electrically isolated from inductor trace 634.

[0094] FIG. 7 illustrates a cross-sectional view in the xz plane of an example component mounting assembly 700 having a package substrate 600 mounted on an IC package 701, according to an embodiment of the present disclosure.

[0095] Top-level package metallization features 633 are interfaced with host component 702 by second-level interconnects 703 (e.g., solder) and interfaced with host component pads 704. IC die 705 is interfaced on the opposite side of package substrate 600. First-level interconnects 706 (e.g., solder) couple bottom-level package metallization features 707 to interconnect pads 708 on IC die 705. In the example shown, power may be transmitted from power source 709 through PCB 702 and through inductor structure 628 to die 705.

[0096] The inductor structure 630 is used as part of a fully integrated voltage regulation (FIVR) circuit, and by embedding the entire inductor structure 630 within the package substrate, larger inductors and / or larger magnetic cores can be obtained than those that can be fabricated on the die. As a result, the on-die buck conversion circuitry can operate at lower switching frequencies, relaxing power path design rules on both the die and the package substrate. In another example, the inductor structure may be part of an RF oscillating tank circuit or an RF filter circuit.

[0097] FIG. 8 illustrates a block diagram of a computing device 800 as part of a system-on-chip (SoC) package in a package-integrated inductor implementation, according to an embodiment of the present disclosure.

[0098] In one embodiment, computing device 800 represents a server, a desktop workstation, or a mobile workstation such as, but not limited to, a laptop computer, a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or other wireless mobile device.

[0099] In some embodiments, computing device 800 has wireless connectivity (e.g., Bluetooth, WiFi, and 5G networks). It is understood that, typically, certain components are shown, and not all components of such a device are shown in computing device 800.

[0100] Various embodiments of the present disclosure also include a network interface 870, such as a wireless interface, and system embodiments may be incorporated into wireless devices, such as mobile phones or personal digital assistants. The wireless interface includes a millimeter-wave generator and an antenna array. The millimeter-wave generator may be part of a monolithic microwave integrated circuit.

[0101] In one embodiment, processor 810 represents a CPU or GPU and may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. As disclosed, processor 810 may include any one of package substrates (e.g., any one of package substrates 200, 300, 400, 500, or 600) having embedded inductor structures. Processing operations performed by processor 810 include execution of an operating platform or operating system on which applications and / or device functions are executed. Processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, and / or operations related to connecting computing device 800 to other devices. Processing operations may also include operations related to audio I / O and / or display I / O.

[0102] In one embodiment, computing device 800 includes an audio subsystem 820, which represents the hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components involved in providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone output, and microphone input. Such functional devices may be integrated into computing device 800 or connected to computing device 800. In one embodiment, a user can interact with computing device 800 by providing audio commands that are received and processed by processor 810.

[0103] Display subsystem 830 represents the hardware (e.g., display device) and software (e.g., drivers) components that provide a user with a visual and / or tactile display for interacting with computing device 800. Display subsystem 830 has a display interface 832, which includes a specific screen or hardware device used to provide a display to the user. In some embodiments, display interface 832 includes logic separate from processor 810, where at least some processing related to the display is performed. In some embodiments, display subsystem 830 includes a touchscreen (or touchpad) device that provides both output and input to the user.

[0104] The I / O controller 840 represents hardware devices and software components related to user interaction. The I / O controller 840 is operated to manage hardware that is part of the audio subsystem 820 and / or the display subsystem 830. The I / O controller 840 also represents a connection point for additional devices that connect to the computing device 800, through which a user can interact with the system. For example, devices that can be attached to the computing device 800 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices used for specific applications, such as a card reader or other device.

[0105] As previously mentioned, I / O controller 840 can interact with audio subsystem 820 and / or display subsystem 830. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of computing device 800. Audio output can also be provided instead of or in addition to display output. In another example, if display subsystem 830 has a touchscreen, the display device can also function as an input device and be managed, at least in part, by I / O controller 840. Additional buttons or switches can also be present on computing device 800 to provide I / O functionality managed by I / O controller 840.

[0106] In one embodiment, I / O controller 840 manages devices such as accelerometers, cameras, light or other environmental sensors, or other hardware that may be included in computing device 800. The inputs may be part of direct user interaction as well as provide environmental input to the system to affect system operation (e.g., filtering noise, adjusting the display for brightness detection, applying a flash for a camera, or other features).

[0107] In one embodiment, computing device 800 includes power management 850, which manages battery power usage, battery charging, and power-saving operation features. Memory subsystem 860 includes memory devices for storing information in computing device 800. Memory may include non-volatile (state does not change when power to the memory device is interrupted) and / or volatile (state is indeterminate when power to the memory device is interrupted) memory devices. Memory subsystem 860 may store (long-term or temporary) application data, user data, music, photos, documents, or other data, as well as system data related to the execution of applications and functions of computing device 800.

[0108] Elements of the embodiments may also be provided as a machine-readable medium (e.g., memory 860) carrying computer-executable instructions. The machine-readable medium (e.g., memory 860) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD-ROMs, RAM, EPROMs, EEPROMs, magnetic or optical cards, phase-change memory (PCM), or other types of machine-readable media suitable for carrying electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS) that is transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by data signals over a communications link (e.g., a modem or network connection).

[0109] Connectivity via network interface 870 includes hardware components (e.g., wireless and / or wired connectors and communications hardware) and software components (e.g., drivers, protocol stacks) that allow computing device 800 to communicate with external devices. Computing device 800 may be a separate device, such as another computing device, a wireless access point, or a base station, or a peripheral device, such as a headset, printer, or other device.

[0110] Network interface 870 may have several different types of connectivity. For generalization, computing device 800 is shown with cellular connectivity 872 and wireless connectivity 874. Cellular connectivity 872 typically represents cellular network connectivity provided by a wireless carrier, such as provided via GSM (Global System for Mobile Communications) or variations or derivatives, CDMA (Code Division Multiple Access) or variations or derivatives, TDM (Time Division Multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or air interface) 874 represents non-cellular wireless connectivity, which may include personal area networks (e.g., Bluetooth, near field, etc.), local area networks (e.g., Wi-Fi), and / or wide area networks (e.g., WiMax), or other wireless communications.

[0111] The peripheral connections 880 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) for forming the peripheral connections. It is understood that the computing device 800 may be a peripheral device (“to”) 882 to other computing devices or may have peripheral devices (“from”) 884 connected to it. Typically, the computing device 800 has a “docking” connector for connecting to other computing devices, such as for managing (e.g., downloading and / or uploading, modifying, synchronizing) content on the computing device 800. The docking connector also allows the computing device 800 to connect to certain peripheral devices, thereby enabling the computing device 800 to control, for example, content output, audiovisual, or other systems.

[0112] In addition to proprietary docking connectors or other proprietary connection hardware, computing device 800 can make peripheral connections 880 through common or standards-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of many different hardware interfaces), DisplayPort, including Multi-DisplayPort (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0113] Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, provided that particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0114] While the present disclosure has been described in conjunction with specific embodiments, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. It is intended that the embodiments of the present disclosure embrace all such alternatives, modifications, and variations as fall within the broad scope of the appended claims.

[0115] Also, for simplicity of illustration and explanation, and to avoid obscuring the disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings. Furthermore, layouts may be shown in block diagram form to avoid obscuring the disclosure, taking into account the fact that descriptions of the implementation of such block diagram layouts are highly dependent on the platform on which the disclosure is implemented (i.e., such descriptions are well within the purview of those skilled in the art). Where specific details (e.g., circuits) are described to explain exemplary embodiments of the disclosure, it will be apparent to those skilled in the art that the disclosure can be practiced without these specific details or with variations. Therefore, the description is to be considered illustrative, not limiting.

[0116] The following examples relate to other embodiments. The descriptions in the examples can be used in any one or more embodiments. Also, any optional feature of the device described herein may be implemented in the context of a method or process.

[0117] Example 1 is an integrated circuit (IC) package substrate comprising: a magnetic material embedded in a dielectric material, wherein a first surface of the dielectric material is below the magnetic material and a second surface of the dielectric material opposite the first surface is above the magnetic material; and a metallization level having a first metal feature embedded in the magnetic material and a second metal feature at an interface between the magnetic material and the dielectric material, the second metal feature having a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

[0118] Example 2 includes all of the features of example 1, wherein the second metallic feature completely surrounds the first metallic feature and extends along the periphery of the magnetic material.

[0119] Example 3 includes all of the features of examples 1 or 2, wherein the metallization level has a multi-layer material stack including a first metal on a second metal, the second metal having a higher magnetic permeability than the first metal.

[0120] Example 4 includes all of the features of any one of Examples 1 to 3, wherein the metallization level further includes a third metal feature embedded within a portion of the dielectric material laterally adjacent a sidewall of the magnetic material, the sidewall of the third metal feature being less laterally undercut than the second metal feature.

[0121] Example 5 includes all the features of Example 4, wherein the second metallic feature is one of a plurality of second metallic features embedded in the magnetic material, the third metallic feature is one of a plurality of third metallic features embedded in a portion of the dielectric material, the second metallic feature has a first pitch, and the third metallic feature has a second pitch, the second pitch being smaller than the first pitch.

[0122] Example 6 includes all of the features of examples 4 or 5, wherein the first sidewall is less laterally undercut than the second sidewall.

[0123] Example 7 includes all of the features of any one of examples 4-6, wherein the second metal feature has a greater thickness than the third metal feature.

[0124] Example 8 includes all of the features of any one of examples 1-7, wherein the sidewalls of the magnetic material are sloped at least 45 degrees from the plane of the metallization layer.

[0125] Example 9 includes all the features of any one of Examples 1 to 8, wherein the metallization level is an upper metallization level, and the substrate further includes a lower metallization level, the lower metallization level including a lower metal feature between a bottom of the magnetic material and the first surface of the dielectric material, the lower metal feature having a lateral dimension greater than a portion of the magnetic material in contact with the lower metal feature.

[0126] Example 10 is an integrated circuit (IC) package assembly comprising: a power supply attached to a host circuit board; and an IC die electrically coupled to the host circuit board via an inductor embedded in an IC package substrate, the IC package substrate further comprising: a magnetic material embedded in a dielectric material, wherein a first surface of the dielectric material is below the magnetic material and a second surface of the dielectric material opposite the first surface is above the magnetic material; and a metallization level having elements of the inductor embedded in the magnetic material and metal features at the interface between the magnetic material and the dielectric material, the metal features having a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

[0127] An eleventh example includes all the features of the tenth example, wherein the inductor has a planar structure with a serpentine structure embedded in the magnetic material.

[0128] Example 12 includes all of the features of examples 10 or 11, wherein the metallic feature completely surrounds the element of the inductor and extends along the periphery of the magnetic material.

[0129] Example 13 includes all of the features of any one of examples 10-12, wherein the metallization level comprises a multi-layer stack including a first metal on a second metal, the second metal having a higher magnetic permeability than the first metal.

[0130] Example 14 is a method for manufacturing an integrated circuit (IC) package substrate, comprising: forming one or more metallization layers embedded within a dielectric material, at least one of the metallization layers being patterned into preliminary metal features; forming an opening through the dielectric material, the opening exposing a portion of a preliminary metal feature; applying a dry film resist over a portion of the preliminary metal feature; patterning the preliminary metal feature into a first metal feature based on a pattern in the dry film resist; depositing a magnetic material in the opening and over the first metallic feature; forming a dielectric material over the magnetic material; The method has the following features:

[0131] Example 15 includes all the features of example 14, wherein forming the opening through the dielectric material comprises laser drilling an opening in the dielectric over the preliminary metal feature.

[0132] Example 16 includes all the features of examples 14 or 15, wherein forming one or more metallization layers embedded in the dielectric material includes forming the preliminary metal features by a subtractive-additive process, wherein one or more sidewalls of the preliminary metal features have a slope of 10° or less from a plane of the preliminary metal feature.

[0133] Example 17 includes all the features of any one of examples 14 to 16, wherein patterning the preliminary metal feature into a first metal feature comprises subtractively removing metal from the preliminary metal feature; One or more sidewalls of the first metal feature have an inclination between 45° and 85° from the plane of the preliminary metal feature.

[0134] Example 18 includes all of the features of any one of Examples 14 to 17, wherein the first metal feature includes a serpentine trace having a plurality of parallel traces and a ring structure surrounding the serpentine trace, and sidewalls of the serpentine trace and the ring structure adjacent to the serpentine trace are formed by subtractive removal of metal of a preliminary metal feature in a wet metal etching bath according to a pattern of the dry film resist.

[0135] Example 19 includes all of the features of any one of Examples 14-18, wherein a sidewall of the parallel traces of the serpentine trace and a sidewall of the ring structure adjacent to the serpentine trace are sloped at an angle between 45° and 85° from the plane of the preliminary metal feature.

[0136] Example 20 includes all of the features of any one of Examples 14 to 19, wherein the preliminary metal feature is a first preliminary metal feature in a first conductive level flush with a bottom of the opening, and a second preliminary metal feature is in a second conductive level on the dielectric material above the first conductive level, and a plurality of second metal features are formed simultaneously with the first metal feature by subtractive removal of metal from the second preliminary metal feature.

[0137] Example 21 includes all of the features of any one of Examples 14 to 20, wherein the first metal feature has a plurality of parallel traces, one of the plurality of parallel traces separated by a minimum pitch, and the plurality of second metal features are separated by a second minimum pitch, and the first minimum pitch is substantially equal to the second minimum pitch.

[0138] Example 22 includes all of the features of any one of Examples 14 to 18, and further includes forming a plurality of second metal features on top of the dielectric material adjacent to the magnetic material by a subtractive-additive process, the plurality of second metal features being formed by patterned openings in photoresist or by depositing metal on the dielectric material.

[0139] Example 23 includes all of the features of any one of Examples 14 to 22, further comprising: the sidewalls of the plurality of parallel traces are separated by a first minimum pitch; and the sidewalls of the plurality of second metal features are separated by a second minimum pitch, and the first minimum pitch is greater than the second minimum pitch.

[0140] Example 24 includes all of the features of any one of Examples 14 to 23, and the step of depositing a magnetic material in the opening includes the steps of laminating a magnetic foil on a first dielectric, forming a second dielectric on the magnetic foil, and forming the opening in the second dielectric across the magnetic foil to expose a portion of the magnetic foil.

[0141] Example 25 includes all of the features of any one of Examples 14 to 23, wherein a copper foil is on the magnetic foil and bonded to the magnetic foil, the magnetic foil having a first magnetic material; the copper foil and the magnetic foil are patterned simultaneously to form a serpentine having a plurality of parallel traces, the serpentine having a first layer having the first magnetic material and a second layer on the first layer having copper; a second magnetic material is deposited on the plurality of parallel traces; and the copper in the second layer is encapsulated by the first magnetic material in the first layer and the second magnetic material on the copper.

[0142] An Abstract has been submitted, with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. [Explanation of symbols]

[0143] 201 board stack 202 Dielectric 203 Metallized Features 204 Upper surface 205 Aperture 206 Side wall 207 Magnetic materials 209 Pre-metallized Features 212 Dielectrics 214 Aperture 218 Opening 220 inductor trace 221 Ring Structure 227 Magnetic materials 230 Dielectric 231 Serpentine Trace Structure

Claims

1. 1. An integrated circuit (IC) package substrate, comprising: a magnetic material embedded in a dielectric material, a first layer of the dielectric material underlying the magnetic material; a metallization level having a first metal feature embedded within the magnetic material and a second metal feature at an interface of the magnetic material and the dielectric material, the second metal feature having a first sidewall in contact with the second layer of dielectric material and a second sidewall in contact with the magnetic material; and the metallization level further includes a third metal feature embedded within the second layer of dielectric material laterally adjacent a sidewall of the magnetic material; An integrated circuit (IC) package substrate, wherein the sidewalls of the third metal feature are less laterally undercut than the second metal feature.

2. 10. The IC package substrate of claim 1, wherein the second metallic feature completely surrounds the first metallic feature and extends along a perimeter of the magnetic material.

3. the metallization level has a multi-layer material stack including a first metal on a second metal; 3. The IC package substrate of claim 1, wherein the second metal has a higher magnetic permeability than the first metal.

4. the second metallic feature is one of a plurality of second metallic features embedded within the magnetic material; the third metal feature is one of a plurality of third metal features embedded within the second layer of dielectric material; the second metallic feature has a first pitch; the third metallic feature has a second pitch; 3. The IC package substrate of claim 1, wherein the second pitch is smaller than the first pitch.

5. 3. The IC package substrate of claim 1, wherein the second metal feature has a thickness greater than the third metal feature.

6. 3. The IC package substrate of claim 1, wherein the first sidewall has less lateral undercut than the second sidewall.

7. 3. The IC package substrate of claim 1, wherein the sidewalls of the magnetic material have a slope of at least 45 degrees from the plane of the metallization level.

8. the metallization level is an upper metallization level; The IC package substrate further includes a lower metallization level; the lower metallization level having lower metal features between a bottom of the magnetic material and the first layer of the dielectric material; 3. The IC package substrate of claim 1, wherein the lower metallic feature has an area that is greater than an area of the magnetic material that contacts the lower metallic feature.

9. 1. An integrated circuit (IC) package assembly comprising: a power supply mounted on the host circuit board; an IC die electrically coupled to the host circuit board through an inductor embedded in an IC package substrate; and The IC package substrate further comprises: a magnetic material embedded in a dielectric material, a first layer of the dielectric material underlying the magnetic material; a metallization level having an element of the inductor embedded within the magnetic material and a metal feature at the interface of the magnetic material and the dielectric material, the metal feature having a first sidewall in contact with the second layer of dielectric material and a second sidewall in contact with the magnetic material; and the metallization level further includes a second metal feature embedded within the second layer of dielectric material laterally adjacent a sidewall of the magnetic material; An integrated circuit (IC) package assembly, wherein a sidewall of the second metal feature has less lateral undercut than the metal feature.

10. 10. The integrated circuit (IC) package assembly of claim 9, wherein the inductor has a planar structure with a serpentine structure embedded in the magnetic material.

11. 11. The integrated circuit (IC) package assembly of claim 9 or 10, wherein the metallic feature completely surrounds the element of the inductor and extends along the periphery of the magnetic material.

12. the metallization level has a multi-layer material stack including a first metal on a second metal; 11. The integrated circuit (IC) package assembly of claim 9 or 10, wherein the second metal has a higher magnetic permeability than the first metal.

13. 1. A method for manufacturing an integrated circuit (IC) package substrate, comprising: forming one or more metallization layers over the first layer of dielectric material; patterning at least one of the metallization layers into preliminary metal features; forming a second layer of dielectric material over the preliminary metal features; forming an opening through the second layer of dielectric material, the opening exposing a portion of a preliminary metal feature; applying a dry film resist over the portion of the preliminary metal feature; patterning the preliminary metal feature into a first metal feature based on a pattern in the dry film resist; depositing a magnetic material in the opening and over the first metallic feature; forming an additional dielectric material over the magnetic material; A method comprising:

14. 14. The method of claim 13, wherein forming an opening through the second layer of dielectric material comprises laser drilling an opening in the second layer of dielectric on top of the preliminary metal feature.

15. forming one or more metallization layers embedded within the dielectric material comprises forming the pre-metal features by a semi-additive process (SAP); 14. The method of claim 13, wherein one or more sidewalls of the preliminary metal feature have an inclination of 10 degrees or less from the plane of the preliminary metal feature.

16. patterning the preliminary metal feature into a first metal feature comprises subtractively removing metal from the preliminary metal feature; 16. The method of claim 13, wherein one or more sidewalls of the first metal feature have an inclination between 45° and 85° from the plane of the preliminary metal feature.

17. the first metallic feature includes a serpentine trace having a plurality of parallel traces and a ring structure surrounding the serpentine trace; 16. The method of claim 13, wherein the serpentine traces and sidewalls of the ring structure adjacent to the serpentine traces are formed by subtractive removal of metal of preliminary metal features in a wet metal etching bath according to a pattern in the dry film resist.

18. 18. The method of claim 17, wherein sidewalls of the plurality of parallel traces of the serpentine trace and sidewalls of the ring structure adjacent the serpentine trace have an inclination of between 45° and 85° from the plane of the preliminary metal feature.

19. the preliminary metal feature is a first preliminary metal feature at a first conductive level flush with a bottom of the opening; second preliminary metal features are in a second conductive level on the second dielectric material layer above the first conductive level; 20. The method of claim 18, wherein subtractive removal of metal from the second preliminary metal feature forms a plurality of second metal features simultaneously with the first metal feature.

20. the first metallic feature has a plurality of parallel traces; one of the plurality of parallel traces separated by a first minimum pitch; the plurality of second metallic features are separated by a second minimum pitch; 20. The method of claim 19, wherein the first minimum pitch is substantially equal to the second minimum pitch.

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