AD conversion circuit driving method, AD conversion circuit, photoelectric conversion device, and equipment

Abstract

To improve AD conversion accuracy in performing AD conversion of a plurality of analog signals.SOLUTION: There is provided a method for driving an AD conversion circuit comprising a plurality of comparator circuits each having a first terminal that receives input of a plurality of analog signals including a first analog signal and a second analog signal and a second terminal that is connected with wiring through which a lamp signal is transmitted, and the method includes: a first operation of adjusting the potential of the wiring from a predetermined potential to a first potential to cause some comparator circuits of the plurality of comparator circuits to hold first offset; a second operation of converting the first analog signals to digital signals after the first operation; a third operation of adjusting the potential of the wiring to a potential included in a range from the predetermined potential to the first potential after the second operation; and a fourth operation of converting the second analog signals to digital signals after the third operation.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to a driving method for an AD conversion circuit, an AD conversion circuit, a photoelectric conversion device, and equipment. [Background technology]

[0002] Patent Document 1 describes a configuration in which multiple AD conversion circuits, each having a comparator, are provided, and describes providing different offsets to the comparators in this configuration so that the timing at which the output of the comparator in some AD conversion circuits changes differs from the timing at which the output of the comparator in other AD conversion circuits changes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-096670 Summary of the Invention [Problem to be solved by the invention]

[0004] In the operation described in Patent Document 1, after an offset is applied, the potential of the ramp signal is reset to the start level of AD conversion of the noise signal. Meanwhile, in AD conversion of the optical signal, the potential is reset from the level at which AD conversion of the noise signal is completed to the start level. In other words, the potential before resetting to the start potential of AD conversion of the noise signal differs from the potential before resetting to the start potential of AD conversion of the optical signal. As a result, the ramp start potential of AD conversion of the noise signal may differ from the ramp start potential of AD conversion of the optical signal. This may result in a decrease in AD conversion accuracy.

[0005] The present disclosure provides a technique for suppressing a decrease in AD conversion accuracy when AD conversion is performed on each of a plurality of analog signals. [Means for solving the problem]

[0006] One aspect of the present disclosure is a method for driving an AD conversion circuit including a plurality of comparison circuits, each having a first terminal to which a plurality of analog signals including a first analog signal and a second analog signal are input, and a second terminal connected to a wiring through which a ramp signal is transmitted, the method comprising: a first operation of causing some comparison circuits of the plurality of comparison circuits to hold a first offset by changing the potential of the wiring from a predetermined potential to a first potential; a second operation of converting the first analog signal into a digital signal after the first operation; a third operation of changing the potential of the wiring to a potential included in the range from the predetermined potential to the first potential after the second operation; and a fourth operation of converting the second analog signal into a digital signal after the third operation.

[0007] Another aspect is an AD conversion circuit including: a plurality of comparison circuits each having a first terminal to which a plurality of analog signals including a first analog signal and a second analog signal are input; and a control circuit, wherein the control circuit controls the following: a first operation of causing some comparison circuits of the plurality of comparison circuits to hold a first offset by changing the potential of the wiring from a predetermined potential to a first potential; a second operation of converting the first analog signal into a digital signal after the first operation; a third operation of changing the potential of the wiring to a potential included in the range from the predetermined potential to the first potential after the second operation; and a fourth operation of converting the second analog signal into a digital signal after the third operation. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to improve the AD conversion accuracy when performing AD conversion on a plurality of analog signals. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 2] Diagram showing the configuration of a comparison circuit [Figure 3A] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 3B] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 4] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 5] Diagram showing the pixel configuration [Figure 6] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 7A] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 7B] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 8] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 9] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 10] 1 is a diagram showing the operation of a photoelectric conversion device; [Figure 11] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 12] Equipment configuration diagram DETAILED DESCRIPTION OF THE INVENTION

[0010] Each embodiment will be described below with reference to the drawings.

[0011] In each of the embodiments described below, the explanation will be focused on an AD conversion circuit installed in a photoelectric conversion device, but the present disclosure is not limited to this form and can be applied to an AD conversion circuit that converts an analog signal into a digital signal.

[0012] In addition, the following description will be focused on an imaging device as an example of a photoelectric conversion device. However, each embodiment is not limited to an imaging device and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device that measures the amount of incident light) can be used.

[0013] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the examples. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors can be changed as appropriate.

[0014] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type. The conductivity types of the semiconductor regions described in the following examples are merely examples and are not limited to the conductivity types described in the examples. The conductivity types described in the examples can be changed as appropriate, and the potential of the semiconductor regions is accordingly changed accordingly.

[0015] In the following examples, connections between circuit elements may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest will be treated as being connected unless otherwise specified. For example, assume that element A is connected to one node of a capacitance element C having multiple nodes, and element B is connected to the other node. Even in such a case, elements A and B will be treated as being connected unless otherwise specified.

[0016] (Embodiment 1) The schematic configuration of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment.

[0017] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel array 101, a vertical scanning circuit 20, AD conversion circuit units 30A and 30B, horizontal scanning circuits 50A and 50B, and a timing generation circuit 60. The photoelectric conversion device 100 according to this embodiment also includes reference signal output circuits (output circuits) 36A and 36B and counters 44A and 44B. The AD conversion circuit unit 30A, the reference signal output circuit 36A, the counter 44A, and the horizontal scanning circuit 50A constitute one set of readout circuit units. The AD conversion circuit unit 30B, the reference signal output circuit 36B, the counter 44B, and the horizontal scanning circuit 50B constitute another set of readout circuit units. The pixel array 101 is disposed between these two readout circuit units.

[0018] The pixel array 101 has a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit formed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array 101 is not particularly limited. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel array 101 may also include optical black pixels whose photoelectric conversion units are shielded from light, dummy pixels that do not output signals, and the like.

[0019] Each pixel 12 arranged in the pixel array 101 is provided with a color filter having a predetermined spectral sensitivity characteristic.

[0020] In the Bayer array, rows in which R pixels and G pixels are alternately arranged and rows in which G pixels and B pixels are alternately arranged are alternately arranged.

[0021] Control lines are arranged in each row of the pixel array 101, extending in a first direction (the horizontal direction in FIG. 1). Each control line is connected to the pixels 12 aligned in the first direction, and serves as a signal line common to these pixels 12. The first direction in which the control lines extend is sometimes referred to as the row direction or horizontal direction. The control lines are connected to a vertical scanning circuit 20.

[0022] In each column of the pixel array 101, an output line 16A and an output line 16B are arranged, extending in a second direction (the vertical direction in FIG. 1) intersecting the first direction. The pixels 12 constituting the pixel array 101 are divided into pixels 12 connected to the output line 16A and pixels 12 connected to the output line 16B. In the configuration example shown in FIG. 1, in each row and column of the pixel array 101, the pixels 12 connected to the output line 16A and the pixels 12 connected to the output line 16B are arranged alternately.

[0023] Specifically, each of the output lines 16A is connected to an R pixel or a Gb pixel among the pixels 12 aligned in the second direction, and serves as a common signal line for these pixels 12. Each of the output lines 16B is connected to a Gr pixel or a B pixel among the pixels 12 aligned in the second direction, and serves as a common signal line for these pixels 12. The second direction in which the output lines 16A and 16B extend may be referred to as the column direction or the vertical direction. The output line 16A is connected to an AD conversion circuit unit 30A. The output line 16B is connected to an AD conversion circuit unit 30B.

[0024] The vertical scanning circuit 20 is a control circuit that supplies control signals to the pixels 12 via control lines provided in each row of the pixel array to drive readout circuits in the pixels 12 when reading out signals from the pixels 12. The vertical scanning circuit 20 may be configured using a shift register and an address decoder. The vertical scanning circuit 20 drives the pixels 12 of the pixel array 101 row by row using the control signals supplied via the control lines. The pixel signals of each column read out from the pixels 12 row by row are input to the AD conversion circuit unit 30A via output line 16A or to the AD conversion circuit unit 30B via output line 16B.

[0025] The reference signal output circuits 36A and 36B are circuits that generate reference signals used in AD conversion, such as ramp signals. A ramp signal is a signal whose level gradually changes (increases or decreases) from a predetermined value over time.

[0026] The AD conversion circuit unit 30A has a plurality of comparison circuits 32 and a plurality of memories 42 provided corresponding to each column of the pixel array 101. The comparison circuit 32 and memory 42 arranged in each column constitute a column AD conversion circuit unit. An input terminal of the comparison circuit 32 in each column is connected to an output line 16A of the corresponding column and a reference signal output circuit 36A. The reference signal output circuit 36A supplies a reference signal to the comparison circuit 32 in each column via the reference signal line. An input terminal of the memory 42 in each column is connected to an output terminal of the comparison circuit 32 in the corresponding column, a counter 44A, and a horizontal scanning circuit 50A.

[0027] The horizontal scanning circuit 50A is a control circuit unit that sequentially supplies control signals to the memories 42 of each column of the AD conversion circuit unit 30A, for outputting pixel signals stored in the memories 42 of each column. A control line of the horizontal scanning circuit 50A provided corresponding to each column of the pixel array 101 is connected to the memory 42 of the corresponding column. When the memory 42 of each column receives a control signal via the control line of the corresponding column of the horizontal scanning circuit 50A, it outputs the pixel signal it holds to an output line 46A.

[0028] Similarly, the AD conversion circuit unit 30B has a plurality of comparison circuits 32 and a plurality of memories 42 provided corresponding to each column of the pixel array 101. The comparison circuits 32 and memories 42 arranged in each column constitute a column AD conversion circuit unit. An input terminal of the comparison circuit 32 of each column is connected to an output line 16B of the corresponding column and a reference signal output circuit 36B. The reference signal output circuit 36B supplies a reference signal to the comparison circuit 32 of each column via the reference signal line. An input terminal of the memory 42 of each column is connected to an output terminal of the comparison circuit 32 of the corresponding column, a counter 44B, and a horizontal scanning circuit 50B.

[0029] The horizontal scanning circuit 50B is a control circuit unit that sequentially supplies control signals to the memories 42 of each column of the AD conversion circuit unit 30B for outputting pixel signals stored in the memories 42 of each column. A control line of the horizontal scanning circuit 50B provided corresponding to each column of the pixel array 101 is connected to the memory 42 of the corresponding column. When the memory 42 of each column receives a control signal via the control line of the corresponding column of the horizontal scanning circuit 50B, it outputs the pixel signal it holds to an output line 46B.

[0030] The timing generation circuit 60 (control circuit) is a control circuit section for supplying control signals for controlling the operations and timings of the vertical scanning circuit 20, the comparison circuit 32, the reference signal output circuits 36A and 36B, the counters 44A and 44B, and the horizontal scanning circuits 50A and 50B. At least some of these control signals may be supplied from outside the photoelectric conversion device 100.

[0031] 1 are reset signals for the comparator circuit 32, which are supplied from the timing generating circuit 60 to the comparator circuit 32. The control signals ΦCRES1, ΦCRES2, ΦCRES3, ΦCRES4 are supplied to the comparator circuit 32 of a predetermined column via separate reset signal lines. The control signals ΦCRES1, ΦCRES2, ΦCRES3, ΦCRES4 supplied to the AD conversion circuit unit 30A and the control signals ΦCRES1, ΦCRES2, ΦCRES3, ΦCRES4 supplied to the AD conversion circuit unit 30B may be separate control signals.

[0032] Next, an outline of the operation of the photoelectric conversion device according to this embodiment will be described with reference to FIG.

[0033] Each of the pixels 12 constituting the pixel array 101 includes a photoelectric conversion element such as a photodiode and outputs an analog pixel signal to an output line 16A or an output line 16B. The pixel signal output by the pixel 12 includes a signal corresponding to a signal amount according to the amount of incident light and a signal corresponding to a noise amount (hereinafter, sometimes referred to as a noise signal). The pixel signals are output from the pixels 12 row by row under the control of a timing generation circuit 60 in response to a control signal supplied from the vertical scanning circuit 20 via a control line. The pixel signal output from the pixel 12 to the output line 16A is input to an AD conversion circuit unit 30A. The pixel signal output from the pixel 12 to the output line 16B is input to an AD conversion circuit unit 30B.

[0034] The pixel signal input from the pixel 12 to the AD conversion circuit unit 30A via the output line 16A is input to the comparison circuit 32 of the corresponding column. The comparison circuit 32 performs a comparison operation to compare the signal level of the pixel signal with the signal level of a reference signal supplied from a reference signal output circuit 36A, and outputs a latch signal at the timing when the magnitude relationship between the signal level of the pixel signal and the signal level of the ramp signal is inverted. The memory 42 receives the count signal supplied from the counter 44A and the output signal of the comparison circuit 32. The memory 42 stores the count value indicated by the count signal at the timing when the latch signal is received from the comparison circuit 32 as digital data of the pixel signal.

[0035] The horizontal scanning circuit 50A outputs control signals to the memory 42 of the AD conversion circuit unit 30A sequentially for each column under the control of the timing generation circuit 60. Upon receiving the control signal from the horizontal scanning circuit 50A, the memory 42 outputs digital data obtained by AD converting the pixel signals to an output line 46A.

[0036] Similarly, a pixel signal input from a pixel 12 to the AD conversion circuit unit 30B via an output line 16B is input to the comparison circuit 32 of the corresponding column. The comparison circuit 32 performs a comparison operation to compare the signal level of the pixel signal with the signal level of a reference signal supplied from a reference signal output circuit 36B, and outputs a latch signal at the timing when the magnitude relationship between the signal level of the pixel signal and the signal level of the ramp signal is inverted. The memory 42 receives as input a count signal supplied from a counter 44B and an output signal of the comparison circuit 32. The memory 42 stores the count value indicated by the count signal at the timing when the latch signal is received from the comparison circuit 32 as digital data of the pixel signal.

[0037] Furthermore, under the control of the timing generation circuit 60, the horizontal scanning circuit 50B outputs control signals to the memory 42 of the AD conversion circuit unit 30B sequentially for each column. Upon receiving the control signal from the horizontal scanning circuit 50B, the memory 42 outputs digital data obtained by AD converting the pixel signals to an output line 46B. Note that, although a plurality of AD conversion circuit units 30A and 30B are provided in this embodiment, only one of them may be provided.

[0038] Next, a configuration example of the comparison circuit 32 in the photoelectric conversion device according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing a configuration example of the comparison circuit in the photoelectric conversion device according to this embodiment. Here, the comparison circuit 32 constituting the AD conversion circuit unit 30A will be described as an example, but the same applies to the comparison circuit 32 constituting the AD conversion circuit unit 30B. Fig. 2 shows four comparison circuits 32 provided corresponding to four consecutive columns out of the multiple columns constituting the pixel array.

[0039] As shown in FIG. 2, each of the comparison circuits 32 provided corresponding to each column of the pixel array includes a differential pair circuit (hereinafter, referred to as the differential pair circuit 34), an input capacitor (hereinafter, referred to as the input capacitor C1) to which the signal PIX is applied, and an input capacitor (hereinafter, referred to as the input capacitor C2) to which the signal VRAMP is applied. The differential pair circuit includes a negative input terminal, a positive input terminal, and two corresponding output terminals (a positive output terminal and a negative output terminal). The comparison circuit 32 includes a transistor (hereinafter, referred to as the transistor M1) connected to the negative input terminal and the output terminal, and a transistor (hereinafter, referred to as the transistor M2) connected to the positive terminal and the output terminal. The differential pair circuit 34 includes a negative input terminal, a positive input terminal, and two corresponding output terminals (a positive output terminal and a negative output terminal). The negative input terminal of the differential pair circuit 34 is connected to the output line 16A shown in FIG. 1 via the input capacitor C1. A reference signal line (hereinafter, referred to as reference signal line 38), for example, is connected to the positive input terminal of the differential pair circuit 34 via an input capacitance C2. A transistor M1 is provided between the negative input terminal and the positive output terminal of the differential pair circuit 34, controlling the connection state (conduction / non-conduction) therebetween. A transistor M2 is provided between the positive input terminal and the negative output terminal of the differential pair circuit 34, controlling the connection state (conduction / non-conduction) therebetween. The positive output terminal of the differential pair circuit 34 is connected to a memory 42 of a corresponding column.

[0040] A pixel signal PIX is input to a negative input terminal of the differential pair circuit 34 from a pixel 12 in a corresponding column via an output line 16A and an input capacitor C1. For ease of explanation, it is assumed that pixel signals PIX1, PIX2, PIX3, and PIX4 are input in this order, starting from the comparison circuit 32 on the left side in FIG. 2. For example, a reference signal VRAMP is input to a positive input terminal of the differential pair circuit 34 from a reference signal output circuit 36A via a reference signal line 38 and an input capacitor C2.

[0041] The transistors M1 and M2 of each comparator circuit 32 are controlled by a common control signal ΦCRES. Here, it is assumed that the control signals ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4 are supplied to the comparator circuits 32 in order, starting from the left one in FIG. 2. When the control signal ΦCRES goes high and the transistors M1 and M2 turn on, the threshold voltage of the comparator circuit 32 is reset to a voltage corresponding to the potential difference between the pixel signal PIX being output at that time and the reference signal VRAMP. This allows different offset levels to be set for the comparator circuits 32 of each column depending on the timing of the control signals CRES1, ΦCRES2, ΦCRES3, and ΦCRES4.

[0042] The operation of setting the threshold voltage of the comparator circuit 32 in this manner is called resetting or auto-zeroing the comparator circuit 32. Since the threshold voltage of the comparator circuit 32 is determined by the timing of the control signals ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4, it can be said that the control signals ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4 reset the threshold voltage of the comparator circuit 32.

[0043] The threshold voltage of the comparison circuit 32 is a voltage corresponding to the difference between the signal level of the pixel signal and the signal level of the reference signal when the level of the comparison signal output from the comparison circuit 32 changes. That is, the comparison circuit 32 outputs a comparison signal that indicates a different level when the difference between the signal level of the pixel signal and the signal level of the reference signal is smaller than the threshold voltage and when it is larger than the threshold voltage.

[0044] Next, the operation of the AD conversion circuit section 30A in the photoelectric conversion device according to this embodiment will be described in more detail with reference to FIG.

[0045] First, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to FIG.

[0046] 3A and 3B show the signal levels of the reference signal VRAMP and the control signals ΦRAMP_RES, ΦRAMP_EN, ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4. The control signal ΦRAMP_RES is a reset signal for the reference signal output circuit 36 that is supplied from the timing generation circuit 60 to the reference signal output circuit 36. When the control signal ΦRAMP_RES goes high, the reference signal output circuit 36 goes into a reset state, and the output of the reference signal output circuit 36 goes to the reference level. The control signal ΦRAMP_EN is an enable signal for the reference signal VRAMP, and when the control signal ΦRAMP_EN is high, the signal level of the reference signal VRAMP changes over time.

[0047] In the initial state before time t1, the control signal ΦRAMP_RES is at a high level, and the control signals ΦRAMP_EN, ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4 are at a low level. The reference signal VRAMP is at a reference potential in response to the high level of the control signal ΦRAMP_RES.

[0048] First, at time t1, the timing generation circuit 60 controls the control signal ΦRAMP_RES to change from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0049] Also, at time t1, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the potential of the reference signal VRAMP to gradually change (decrease) from the reference potential over time.

[0050] Next, at time t2, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the potential of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a first voltage level that is lower than the reference level.

[0051] Also, at time t2, the timing generation circuit 60 changes the control signals ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4 from low to high, turning on the transistors M1 and M2 of the comparison circuit 32 and shorting the input terminal and output terminal, resetting the comparison circuit 32.

[0052] Next, at time t3, the timing generation circuit 60 controls the control signal ΦCRES1 to change from High to Low. As a result, the first voltage level is clamped as an offset level in the comparison circuit 32 of the column to which the control signal ΦCRES1 is supplied. In other words, the first offset is held in the comparison circuit of the comparison circuit 32 of the column to which the control signal ΦCRES1 is supplied, which is one of the column circuits. At this time, a pixel signal PIX (noise signal) corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparison circuit 32 of the column to which the control signal ΦCRES1 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX1 and the first voltage level.

[0053] Next, at time t4, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the first voltage level over time.

[0054] Next, at time t5, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a second voltage level that is lower than the first voltage level.

[0055] Next, at time t6, the timing generation circuit 60 controls the control signal ΦCRES2 to change from High level to Low level. As a result, the second voltage level is clamped as an offset level in the comparison circuit 32 of the column to which the control signal ΦCRES2 is supplied. In other words, the second offset is held in the comparison circuit of the comparison circuit 32 of the column to which the control signal ΦCRES2 is supplied, which is another part of the column circuit. At this time, a pixel signal PIX (noise signal) corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparison circuit 32 of the column to which the control signal ΦCRES2 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX2 and the second voltage level.

[0056] Next, at time t7, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the second voltage level over time.

[0057] Next, at time t8, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a third voltage level that is lower than the second voltage level.

[0058] Next, at time t9, the timing generation circuit 60 controls the control signal ΦCRES3 to change from High level to Low level. As a result, the third voltage level is clamped as an offset level in the comparison circuit 32 of the column to which the control signal ΦCRES3 is supplied. In other words, the third offset is held in the comparison circuit of the comparison circuit 32 of the column to which the control signal ΦCRES3 is supplied, which is another part of the column circuit. At this time, a pixel signal PIX (noise signal) corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparison circuit 32 of the column to which the control signal ΦCRES3 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX3 and the third voltage level.

[0059] Next, at time t10, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the third voltage level over time.

[0060] Next, at time t11, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from a high level to a low level, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a fourth voltage level (an example of the first potential) that is lower than the third voltage level.

[0061] Next, at time t12, the timing generation circuit 60 controls the control signal ΦCRES4 to change from High level to Low level. As a result, the fourth voltage level is clamped as an offset level in the comparison circuit 32 of the column to which the control signal ΦCRES4 is supplied. In other words, the fourth offset is held in the comparison circuit of the comparison circuit 32 of the column to which the control signal ΦCRES4 is supplied, which is another part of the column circuit. At this time, a pixel signal PIX (noise signal) corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparison circuit 32 of the column to which the control signal ΦCRES4 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX4 and the fourth voltage level.

[0062] Next, at time t13, the timing generation circuit 60 changes the control signal ΦRAMP_RES from low level to high level, which resets the reference signal output circuit 36 and returns the voltage level of the reference signal to the reference level.

[0063] Next, at time t14, the timing generation circuit 60 controls the control signal ΦRAMP_RES to change from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0064] Also, at time t14, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference level over time.

[0065] The period from time t14 to time t15 is a period during which AD conversion is performed on pixel signals PIX1, PIX2, PIX3, and PIX4 corresponding to the amount of noise.

[0066] When the voltage level of the reference signal VRAMP reaches the first voltage level, the potential difference between the level of the pixel signal PIX1 and the reference signal VRAMP becomes the threshold voltage of the comparator circuit 32 for that column, and the level of the output signal of the comparator circuit 32 is inverted. The memory 42 for that column holds, as digital data of the pixel signal PIX1, a count value corresponding to the count signal received from the counter 44A at the timing when the level of the output signal of the comparator circuit 32 is inverted.

[0067] When the voltage level of the reference signal VRAMP further decreases and reaches the second voltage level, the potential difference between the level of the pixel signal PIX2 and the reference signal VRAMP becomes the threshold voltage of the comparator circuit 32 for that column, and the level of the output signal of the comparator circuit 32 is inverted. The memory 42 for that column holds, as digital data of the pixel signal PIX2, a count value corresponding to the count signal received from the counter 44A at the timing when the level of the output signal of the comparator circuit 32 is inverted.

[0068] When the voltage level of the reference signal VRAMP further decreases and reaches the third voltage level, the potential difference between the level of the pixel signal PIX3 and the reference signal VRAMP becomes the threshold voltage of the comparator circuit 32 for that column, and the level of the output signal of the comparator circuit 32 is inverted. The memory 42 for that column holds, as digital data of the pixel signal PIX3, a count value corresponding to the count signal received from the counter 44A at the timing when the level of the output signal of the comparator circuit 32 is inverted.

[0069] When the voltage level of the reference signal VRAMP further decreases and reaches the fourth voltage level, the potential difference between the level of the pixel signal PIX4 and the reference signal VRAMP becomes the threshold voltage of the comparator circuit 32 for that column, and the level of the output signal of the comparator circuit 32 is inverted. The memory 42 for that column holds, as digital data of the pixel signal PIX4, a count value corresponding to the count signal received from the counter 44A at the timing when the level of the output signal of the comparator circuit 32 is inverted.

[0070] Next, at time t15, the timing generation circuit 60 changes the control signal ΦRAMP_EN from High to Low and changes the control signal ΦRAMP_RES from Low to High, thereby resetting the reference signal output circuit 36 and returning the voltage level of the reference signal to the reference level.

[0071] Next, the operation after time t16 will be described.

[0072] Before AD conversion of the optical signal, the reference signal output circuit 36 performs the driving again as performed at times t1 to t14.

[0073] At time t16, the timing generation circuit 60 changes the control signal ΦRAMP_RES from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0074] Similarly, the timing generating circuit 60 controls the control signal ΦRAMP_EN from low level to high level, so that the voltage level of the reference signal VRAMP gradually changes (decreases) from the reference voltage level over time.

[0075] Next, at time t17, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP remains constant at a first voltage level that is lower than the reference level.

[0076] Next, at time t18, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the first voltage level over time.

[0077] Next, at time t19, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a second voltage level that is lower than the first voltage level.

[0078] Next, at time t20, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the second voltage level over time.

[0079] Next, at time t21, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a third voltage level that is lower than the second voltage level.

[0080] Next, at time t22, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the third voltage level over time.

[0081] Next, at time t23, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a fourth voltage level that is lower than the third voltage level.

[0082] Next, at time t24, the timing generation circuit 60 changes the control signal ΦRAMP_RES from low level to high level, which resets the reference signal output circuit 36 and returns the voltage level of the reference signal to the reference level.

[0083] Next, at time t25, the timing generation circuit 60 controls the control signal ΦRAMP_RES to change from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0084] Also, at time t25, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference level over time.

[0085] The period from time t25 to time t26 is a period during which AD conversion is performed on the pixel signals PIX1, PIX2, PIX3, and PIX4, whose signal amounts correspond to the amount of incident light. At this time, the reference signal VRAMP supplied from the reference signal output circuit 36A is a ramp signal corresponding to the optical signal amplitude.

[0086] Next, at time t26, the timing generation circuit 60 changes the control signal ΦRAMP_EN from High to Low and changes the control signal ΦRAMP_RES from Low to High, thereby resetting the reference signal output circuit 36 and returning the voltage level of the reference signal to the reference level.

[0087] 3A in this way, multiple offset levels can be generated and stored in the comparator circuits 32, and it is possible to prevent the outputs of all the comparator circuits 32 from being inverted simultaneously. As a result, it is possible to reduce noise caused by IR drop and current fluctuations that accompany the simultaneous inversion of the outputs of the comparator circuits 32, and ultimately improve image quality.

[0088] Furthermore, a drive sequence similar to that for driving the reference signal output circuit 36 before AD conversion of the noise signal is also performed before AD conversion of the optical signal, which makes it easier to align the potential before resetting the noise signal to the AD conversion start potential and the potential before resetting the optical signal to the AD conversion start potential.

[0089] According to this embodiment, the drive sequences of the reference signal output circuits 36 before AD conversion of the noise signal and before AD conversion of the optical signal are aligned. This makes it possible to align the ramp start potential of AD conversion of the noise signal and the ramp start potential of AD conversion of the optical signal even if there is not enough time to reset the ramp signals before each AD conversion.

[0090] As a result, deterioration in the accuracy of CDS (Correlated Double Sampling) is less likely to occur, and deterioration in the signal quality after AD conversion is less likely to occur.

[0091] In this embodiment, CDS is performed by setting four voltage levels (for four column circuits ≈ four pixels) that the comparator circuit 32 clamps as offset levels. However, the benefits of this embodiment are not limited to four levels. At least two levels should be set, and if there are no restrictions on the readout time or circuit configuration, offset levels may be set for the number of circuit columns.

[0092] In this embodiment, the order in which the offset levels are generated does not have to be set to the order of highest or lowest potential.

[0093] The order of generation and time interval of the offset levels before AD conversion of the optical signal are aligned with those before AD conversion of the noise signal. Furthermore, the offset levels and time intervals immediately before the ramp signal reset before AD conversion of the optical signal and noise signal are aligned.

[0094] Furthermore, as shown in the timing chart of FIG. 3B, the output waveform of the reference signal when determining the offset level of the comparison circuit 32 may be a slope (triangular wave) instead of a stepped waveform.

[0095] Even with this configuration, the same effects as those of the configuration shown in FIG. 3A can be obtained.

[0096] As a result, it is possible to suppress the deterioration of CDS accuracy and the deterioration of signal quality after AD conversion.

[0097] In this embodiment, the potential change of the reference signal before AD conversion of the optical signal is set to a first potential, a second potential, a third potential, and a fourth potential, respectively. However, this is not limiting. That is, the following operation may be performed during the period from AD conversion of a signal corresponding to the noise level, which is an example of a first analog signal, to AD conversion of the optical signal, which is an example of a second analog signal. The potential of the wiring transmitting the reference signal may be set to a potential within the range of potential change of the reference signal (the range from the reference potential to the fourth potential in FIG. 3A) for maintaining an offset in the comparator circuit. That is, the potential may be set to a potential within the range from the reference potential to the fourth voltage level, which is the range from the predetermined potential to the first potential. For example, the potential may simply be set to the first voltage level. Even in this case, it is easier to align the ramp start potential compared to when there is no period during which the potential is set to a potential within the range from the predetermined potential to the first potential.

[0098] Furthermore, when setting the potential to one of the potentials included in the range from the reference potential to the fourth voltage level, which is the range from the predetermined potential to the first potential, it is preferable to set it to the potential immediately before returning it to the reference potential for AD conversion of the first analog signal. In other words, in the case of the configuration of FIG. 3A, it is preferable to set it to the potential from time t11 to t12 before time t24. This makes it easier to align the ramp start potentials of the AD conversion of the first analog signal and the second analog signal. Note that, as shown in FIGS. 3A and 3B, changing the potential of the wiring before AD conversion of the second analog signal to coincide with the operation of maintaining the offset of the comparator circuit is the most preferable form in terms of aligning the ramp start potentials. However, because this operation takes time, as mentioned above, it is possible to omit some of the changes in the potential of the wiring from time t16 to t24.

[0099] Furthermore, it is not necessary to hold multiple offsets for each comparator circuit at times t1 to t13; instead, a single offset may be used that is common to all column circuits. In this case, it becomes difficult to achieve the effect of preventing the outputs of all comparators 32 from being inverted simultaneously, as described in this embodiment. However, in this embodiment, a potential is set within the range from a predetermined potential to a single potential at which the offset is set during the period from times t15 to t24. This has the effect of making it easier to align the ramp start potentials of the AD conversions of multiple analog signals. Therefore, this embodiment is also within the scope of the present disclosure.

[0100] The direction in which the reference signal is changed in AD conversion is not limited to that in this embodiment, and the reference signal may be changed in a direction in which the potential increases. In this case, the potential for maintaining the offset may also be changed in a direction in which the potential increases from the reference potential.

[0101] In this embodiment, all of the components shown in FIG. 1 may be provided on a single substrate. As another example, a structure in which multiple substrates are stacked may be used, as shown in FIG. 11. In this case, the first substrate 1 may be provided with pixels 12 (including pixels 12 in the third embodiment, which will be described later) included in the pixel array 10 (corresponding to the pixel array 101 shown in FIG. 1), and the second substrate 2 may be provided with the AD conversion circuit units 30A and 30B shown in FIG. 1. The second substrate 2 may further be provided with a timing generation circuit 60, a vertical scanning circuit 20, reference signal output circuits 36A and 36B, counters 44A and 44B, and horizontal scanning circuits 50A and 50B.

[0102] (Embodiment 2) The present embodiment will be described, focusing on the differences from the first embodiment.

[0103] 4 is a diagram showing the operation of this embodiment. In this embodiment, the control of the reference signal output circuit is changed, and the threshold voltage levels at the time of reset or auto-zero of the comparator circuits 32 corresponding to Pix1 to Pix4 are interchanged.

[0104] The sequence up to time t1 is the same as that shown in FIGS. 3A and 3B.

[0105] At time t2, the timing generation circuit 60 changes the control signal ΦRAMP_EN from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP remains constant at a fourth voltage level that is lower than the reference level.

[0106] Also, at time t2, the timing generation circuit 60 changes the control signals ΦCRES1, ΦCRES2, ΦCRES3, and ΦCRES4 from low to high, turning on the transistors M1 and M2 of the comparison circuit 32 and shorting the input terminal and output terminal, resetting the comparison circuit 32.

[0107] Next, at time t3, the timing generation circuit 60 controls the control signal ΦCRES1 to change from high to low. As a result, the fourth voltage level is clamped as an offset level in the comparator circuit 32 of the column to which the control signal ΦCRES1 is supplied. At this time, the pixel signal PIX corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparator circuit 32 of the column to which the control signal ΦCRES1 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX1 and the fourth voltage level.

[0108] Next, at time t4, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (increase) from the fourth voltage level over time.

[0109] Next, at time t5, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at the third voltage level, which is higher than the fourth voltage level.

[0110] Next, at time t6, the timing generation circuit 60 controls the control signal ΦCRES2 to change from high to low. As a result, the third voltage level is clamped as an offset level in the comparator circuit 32 of the column to which the control signal ΦCRES2 is supplied. At this time, the pixel signal PIX corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparator circuit 32 of the column to which the control signal ΦCRES2 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX2 and the third voltage level.

[0111] Next, at time t7, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (increase) from the third voltage level over time.

[0112] Next, at time t8, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at the second voltage level that is lower than the third voltage level.

[0113] Next, at time t9, the timing generation circuit 60 controls the control signal ΦCRES3 to change from high to low. As a result, the second voltage level is clamped as an offset level in the comparator circuit 32 of the column to which the control signal ΦCRES3 is supplied. At this time, the pixel signal PIX corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparator circuit 32 of the column to which the control signal ΦCRES3 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX3 and the third voltage level.

[0114] Next, at time t10, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (increase) from the second voltage level over time.

[0115] Next, at time t11, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP remains constant at the first voltage level, which is higher than the second voltage level.

[0116] Next, at time t12, the timing generation circuit 60 controls the control signal ΦCRES4 to change from high to low. As a result, the first voltage level is clamped as an offset level in the comparator circuit 32 of the column to which the control signal ΦCRES4 is supplied. At this time, the pixel signal PIX corresponding to the amount of noise is output to the output line 16A, and the threshold voltage of the comparator circuit 32 of the column to which the control signal ΦCRES4 is supplied is reset to a voltage corresponding to the potential difference between the level of the pixel signal PIX4 and the first voltage level.

[0117] Next, at time t13, the timing generation circuit 60 changes the control signal ΦRAMP_RES from low level to high level, which resets the reference signal output circuit 36 and returns the voltage level of the reference signal to the reference level.

[0118] The timing and driving purpose from time t14 to time t16 are the same as those in FIG. 3A.

[0119] Next, the drive sequence from t1 to t14 is repeated only in the reference signal output circuit.

[0120] Although this is an insertion of a drive sequence that has no functional meaning, this is one embodiment of the present invention.

[0121] At time t16, the timing generation circuit 60 changes the control signal ΦRAMP_RES from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0122] Similarly, the timing generating circuit 60 controls the control signal ΦRAMP_EN from low level to high level, so that the voltage level of the reference signal VRAMP gradually changes (decreases) from the reference voltage level over time.

[0123] Next, at time t17, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a fourth voltage level that is lower than the reference level.

[0124] Next, at time t18, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (increase) from the fourth voltage level over time.

[0125] Next, at time t19, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at the third voltage level, which is higher than the fourth voltage level.

[0126] Next, at time t20, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (increase) from the third voltage level over time.

[0127] Next, at time t21, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at the second voltage level that is higher than the third voltage level.

[0128] Next, at time t22, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (increase) from the second voltage level over time.

[0129] Next, at time t23, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP remains constant at the first voltage level, which is higher than the second voltage level.

[0130] Next, at time t24, the timing generation circuit 60 changes the control signal ΦRAMP_RES from low level to high level, which resets the reference signal output circuit 36 and returns the voltage level of the reference signal to the reference level.

[0131] The subsequent timing drive is the same as in FIG. 3A.

[0132] In this way, by performing driving in accordance with the timing chart of FIG. 4, it is possible to obtain the same effects as in the first embodiment.

[0133] Furthermore, the potential levels before resetting to the ramp start potential of AD conversion of each of the first analog signal and the second analog signal are set to potentials closer to the ramp start potential than in the first embodiment, which makes it easier to align the ramp start potentials of AD conversion of the signal corresponding to the noise amount (noise signal) and the optical signal than in the first embodiment.

[0134] According to this embodiment, the drive sequences of the reference signal output circuits 36 before AD conversion of the noise signal and before AD conversion of the optical signal are aligned. This makes it possible to align the ramp start potential of AD conversion of the noise signal and the ramp start potential of AD conversion of the optical signal, even if there is not enough time to reset the ramp signals before each AD conversion.

[0135] As a result, it is possible to suppress the deterioration of CDS accuracy and the deterioration of signal quality after AD conversion.

[0136] (Embodiment 3) The present embodiment will be described, focusing on the differences from the first embodiment.

[0137] This embodiment differs in that the pixel 12 included in the pixel array 101 includes a plurality of photoelectric conversion units corresponding to one microlens.

[0138] Fig. 5 shows an equivalent circuit of a pixel 12 for explaining the photoelectric conversion device according to this embodiment. Of the multiple pixels 12 arranged two-dimensionally in the row and column directions, Fig. 5 shows nine pixels 12 arranged in three rows and three columns.

[0139] Each of the plurality of pixels 12 includes two photoelectric conversion units (hereinafter also referred to as PDs) 201A and 201B, two transfer transistors 202A and 202B, and a floating diffusion (hereinafter also referred to as FD) 203. By detecting the phase difference between the signals output from the two PDs, the pixel 12 has an image plane phase difference AF function. The pixel 12 also includes a reset transistor 204, an amplification transistor 205, and a selection transistor 206. The pixel 12 further includes an output unit 207 connected to a vertical output line Vout, a ground 208 connected to a ground potential, and a power supply 209.

[0140] The PD 201 photoelectrically converts incident light and accumulates the photoelectrically converted charges.

[0141] When the transfer transistor 202 is turned on, it transfers the charge of the PD to the FD.

[0142] The amplification transistor 205 forms a source follower circuit, and outputs a signal based on the voltage of the FD to the vertical output line Vout via the selection transistor 206. In addition, by turning on the reset transistor 204, the voltage of the FD can be reset by the voltage of the power supply 209.

[0143] A common control signal is supplied to the pixels 12 in the same row from the vertical scanning circuit 20. That is, control signals Φ202A(n), Φ202B(n), Φ204(n), and Φ206(n) are supplied to the gates of the transfer transistors 202, reset transistors 204, and selection transistors 206 in the nth row, respectively. These transistors are turned on when the control signals are at a high level, and turned off when they are at a low level.

[0144] FIG. 6 is a diagram showing the operation of a photoelectric conversion device including the pixel 12 shown in FIG.

[0145] Fig. 6 shows control signals and output signals related to the nth row pixels 12 in one frame period of the photoelectric conversion device 100. More specifically, Fig. 6 shows control signals φSEL(n), φRES(n), φTXA(n), and pTXB supplied to the nth row pixels 12. The operation of the photoelectric conversion device 100 will be described with reference to Fig. 6.

[0146] At time t1, the control signal φSEL(n) goes high, turning on the row selection transistor 206. This selects the pixels 12 in the nth row. Thereafter, at time t2, the control signal φRES(n) goes low, turning off the reset transistor 204. This operation causes the reset noise signal level held in the floating diffusion region FD203 of the pixel 12 to be amplified by the amplifier transistor 205, and then output to the vertical output line Vout via the row selection transistor 206 and input to the AD conversion circuit 32.

[0147] Thereafter, the same driving as from time t1 to time t15 in FIG. 3A is performed from time t3 to time t17, and the pixel reset noise signal is AD converted.

[0148] At time t18, the control signal φTXA(n) goes high, turning on the transfer transistor 202A. Thereafter, at time t19, the control signal φTXA(n) goes low, turning off the transfer transistor 202A. This operation causes the charge accumulated in the photoelectric conversion unit PD201A of the pixel 12 to be transferred to the floating diffusion region FD203 of the pixel 12 and amplified by the amplifier transistor 205. The output of this amplifier transistor 205 is output to the vertical output line Vout via the row selection transistor 206 and input to the AD conversion circuit 32.

[0149] Thereafter, the same driving as that from time t16 to time t26 in FIG. 3A is performed from time t20 to time t30, and the optical signal accumulated in the photoelectric conversion unit PD201A of the pixel 12 is AD converted.

[0150] At time t31, the control signals pTXA(n) and pTX2B(n) go high, turning on the transfer transistors 202A and 202B. Thereafter, at time t32, the control signals pTXA(n) and pTXB(n) go low, turning off the transfer transistors 202A and 202B. This operation transfers the charge accumulated in the photoelectric conversion unit PD201A of the pixel 12 between times t19 and t32 and the charge accumulated in the photoelectric conversion unit PD201B to the floating diffusion region FD203 of the pixel 12 and amplified by the amplifier transistor 205. The output of this amplifier transistor 205 is output to the vertical output line Vout via the row selection transistor 206 and input to the AD conversion circuit 32.

[0151] At time t33, the timing generation circuit 60 changes the control signal ΦRAMP_RES from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0152] Also at time t33, the timing generation circuit 60 changes the control signal ΦRAMP_EN from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference voltage level over time.

[0153] Next, at time t34, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP remains constant at a first voltage level that is lower than the reference voltage level.

[0154] Next, at time t35, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference voltage level over time.

[0155] Next, at time t36, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a second voltage level that is lower than the first voltage level.

[0156] Next, at time t37, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference voltage level over time.

[0157] Next, at time t38, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a third voltage level that is lower than the second voltage level.

[0158] Next, at time t39, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference voltage level over time.

[0159] Next, at time t40, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from high to low, so that the voltage level of the reference signal VRAMP no longer changes and the reference signal VRAMP becomes constant at a fourth voltage level that is lower than the third voltage level.

[0160] Next, at time t41, the timing generation circuit 60 changes the control signal ΦRAMP_RES from low level to high level, which resets the reference signal output circuit 36 and returns the voltage level of the reference signal to the reference level.

[0161] At time t42, the timing generation circuit 60 changes the control signal ΦRAMP_RES from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0162] Also at time t42, the timing generation circuit 60 controls the control signal ΦRAMP_EN to change from low level to high level, causing the voltage level of the reference signal VRAMP to gradually change (decrease) from the reference level over time.

[0163] This is the period during which AD conversion of the optical signal corresponding to the signal amount equivalent to the sum of the amounts of light incident on the PD 201A and PD 201B of the pixel 12 is performed.

[0164] Incidentally, the optical signal read out here is a signal equivalent to the sum of the charges accumulated in the photoelectric conversion unit PD201A and the charges accumulated in the photoelectric conversion unit PD201B.

[0165] As a result, the A+B signal based on both the charge generated in the photoelectric conversion unit PD201A of the pixel 12 and the charge generated in the photoelectric conversion unit PD201B of the pixel 12 is acquired.

[0166] Next, at time t43, the timing generation circuit 60 changes the control signal ΦRAMP_RES from low level to high level, which causes the reference signal output circuit 36 to enter a reset state and returns the voltage level of the reference signal to the reference level.

[0167] At time t44, the control signal pRES(n) goes high, turning on the reset transistor 204. This returns the floating diffusion region FD203 to the reset state, and the readout process from the pixels 12 in the nth row ends.

[0168] The signal B is obtained by obtaining the difference between the signal A+B and the signal A using a signal processing circuit or the like external to the image capture device 100. The signals A and B are based on charges generated by light that has passed through different pupil regions of the image capture optical system (i.e., pupil-divided light), and are therefore focus detection signals that can be used for phase-difference focus detection. The signal A+B is also an image capture signal used to generate an image. In this way, the image capture device 100 of this embodiment can obtain a focus detection signal and an image capture signal in parallel within one frame period.

[0169] Furthermore, according to this embodiment, the drive sequences of the reference signal output circuit 36 before AD conversion of the noise signal and before AD conversion of each of the optical signals, signal A and signal A+B, are aligned. This makes it easier to align the ramp start potential of AD conversion of the noise signal and the ramp start potential of AD conversion of each of the optical signals, signal A and signal A+B, even if there is not enough time to reset the ramp signals before AD conversion.

[0170] Therefore, it is possible to suppress the deterioration of CDS accuracy and the deterioration of signal quality after AD conversion.

[0171] (Embodiment 4) The present embodiment will be described, focusing on the differences from the first embodiment.

[0172] In this embodiment, AD conversion is performed multiple times on one pixel signal, and the average value of the multiple signals is obtained by a downstream processing circuit or the like. This makes it possible to suppress random noise contained in the pixel signal (hereinafter also referred to as multi-sampling). The techniques of embodiments 1 to 3 can also be applied to this multi-sampling. The number of AD conversions performed on one pixel signal is not particularly limited, but two conversions will be described here as an example. Note that by increasing the number of AD conversions performed on one pixel signal, the effect of suppressing random noise can be enhanced.

[0173] FIG. 7A is a diagram showing the operation of this embodiment.

[0174] During the period up to time t2, φRES(n) goes high, turning on the reset transistor, resetting the floating diffusion region FD to a potential based on the power supply potential. After that, φRES(n) goes low, turning off the reset transistor, and releasing the reset of the floating diffusion region FD.

[0175] Next, the timing generation circuit 60 sends control signals for control in the period from time t3 to time t17, similar to the drive sequence for the period from time t1 to time t15 in Figure 3A of embodiment 1. Through the drive up to this point, the noise signals (first time) of the pixels of pixel signals PIX1 to PIX4 from time t16 to time t17 are stored and held in the respective column memories 42.

[0176] Next, the timing generation circuit 60 repeats the drive sequence from time t3 to time t17 only for φRAMP_RES and φRAMP_EN during the period from time t18 to time t28. By this drive, the noise signals (for the second time) of the pixels PIX1 to PIX4 from time t27 to time t28 are stored in the respective column memories 42.

[0177] Next, at time t29, φTX(n) transitions to a high level, turning on the transfer transistor 202. This transfers the optical signal to the floating diffusion region 203, and the amplification transistor 205 outputs an amplified signal according to the level of the floating diffusion region 203 to the vertical output line 16 via the row selection transistor 206.

[0178] Next, during the period from time t31 to time t41, the timing generation circuit 60 sends out the same control signals as in the drive sequence from time t18 to time t28, and repeats this. However, the period from time t40 to time t41 is generally longer than the period from time t27 to time t28. By this drive, the optical signals (first time) of the pixels PIX1 to PIX4 at times t40 to t41 are stored in the respective column memories 42.

[0179] Next, the timing generation circuit 60 repeats the drive sequence from time t28 to time t41 in the period from time t41 to time t52. By this drive, the optical signals (for the second time) of the pixels PIX1 to PIX4 from time t51 to time t52 are stored in the respective column memories 42.

[0180] As described above, each digital signal held in memory is transferred to a subsequent processing circuit via the horizontal transfer circuit 50. The subsequent processing circuit then calculates the average of each of the two optical signal and pixel reset noise signals converted at different AD conversion timings, and then calculates the difference between the optical signal and the pixel reset noise signal, thereby performing CDS on the multi-sampled signal.

[0181] In this way, according to this embodiment, AD multi-sampling is performed on the same pixel signal multiple times, and the average value of these multiple signals is used as the final output value in a downstream processing circuit, etc., making it possible to suppress random noise contained in the signal.

[0182] Furthermore, multiple offset levels can be generated and stored in the comparator circuit 32, making it possible to prevent the outputs of all the comparator circuits 32 from being inverted simultaneously. As a result, noise caused by IR drop and current fluctuations that accompany simultaneous inversion of the outputs of the comparator circuits 32 can be reduced, thereby improving image quality.

[0183] Furthermore, a drive sequence similar to that for driving the reference signal output circuit 36 before AD conversion of the noise signal is also inserted before AD conversion of the optical signal, which makes it easier to align the potential before resetting the noise signal to the AD conversion start potential and the potential before resetting the optical signal to the AD conversion start potential.

[0184] According to this embodiment, the drive sequences of the reference signal output circuits 36 before AD conversion of the noise signal and before AD conversion of the optical signal are aligned. This makes it easier to align the ramp start potential of AD conversion of the noise signal and the ramp start potential of AD conversion of the optical signal, even if there is not enough time to reset the ramp signals before each AD conversion.

[0185] Therefore, in this embodiment, the same effects as in the first embodiment can be obtained.

[0186] Furthermore, when a plurality of comparator circuits 32 and memories 42 are used for the signal of one pixel (one column), even if multi-sampling is performed, it is possible to suppress random noise while preventing a decrease in readout speed.

[0187] FIG. 7B is a diagram illustrating the operation of an embodiment in which two comparison circuits 32 and memories 42 can be used for one pixel (one column).

[0188] In the embodiment of FIG. 7B, unlike the previous embodiments, pixel signals PIX1 to PIX4 are not AD-converted while changing the offset level of the comparator circuit 32. The reference signal is driven to provide a first offset level and a second offset level, with φCRES1 controlling the reset timing of the first comparator circuit 32 and φCRES2 controlling the reset timing of the second comparator circuit 32 (circuit connection). Furthermore, the signal output of PIX1 (one pixel) is connected to both the first and second comparator circuits 32 via the vertical output line 16. This circuit configuration and driving method allows the reset noise signal of PIX1 to be AD-converted twice, at different times (within the period from t10 to t11) corresponding to the first and second offset levels, respectively. Similarly, the optical signal is AD-converted twice, at different times within the period from time t19 to time t20.

[0189] In this way, according to this embodiment, AD conversion is performed on the same pixel signal multiple times, and the average value of these multiple signals is obtained in a downstream processing circuit. This multi-sampling makes it possible to suppress random noise contained in the pixel signal.

[0190] Furthermore, according to the embodiment of FIG. 7B, it is possible to suppress an increase in readout time due to AD multi-sampling, and in turn a decrease in the frame rate of the photoelectric conversion element.

[0191] Furthermore, a drive sequence similar to that for driving the reference signal output circuit 36 before AD conversion of the noise signal is also inserted before AD conversion of the optical signal, thereby avoiding a difference between the potential before resetting the noise signal to the AD conversion start potential and the potential before resetting the optical signal to the AD conversion start potential.

[0192] According to this embodiment, the drive sequences of the reference signal output circuits 36 before AD conversion of the noise signal and before AD conversion of the optical signal are aligned. This makes it easier to align the ramp start potential of AD conversion of the noise signal and the ramp start potential of AD conversion of the optical signal, even if there is not enough time to reset the ramp signals before each AD conversion.

[0193] As a result, in this embodiment, the same effects as those in the first embodiment can be obtained.

[0194] In this embodiment, an example of multi-sampling has been shown in which two comparator circuits and memories 42 are assigned to one pixel. This is just one example, and the driving method is not limited to two comparator circuits and memories 42. The number of comparator circuits 32 and memories 42 assigned to one pixel may be increased within the range in which an increase in column circuitry and an increase in current consumption are allowed.

[0195] (Embodiment 5) The present embodiment will be described, focusing on the differences from the first embodiment.

[0196] This embodiment relates to a technology that achieves a high dynamic range while maintaining simultaneity by using an image generated by amplifying the signal of the same pixel 12 with different (AD conversion) gains and combining the signals of two pixels 12 through subsequent image processing.

[0197] When the slope of the reference signal is small, the amount of change in the reference signal for one clock of the counter is small, and therefore the resolution of the AD conversion is improved.

[0198] This allows for more precise detection of potential fluctuations on the output line 16, resulting in a higher amplification factor (AD conversion gain). On the other hand, when the slope of the reference signal is large, the amount of change in the reference signal per clock of the counter increases, reducing the resolution of the AD conversion. This reduces the accuracy of detecting potential fluctuations on the output line 16, resulting in a lower amplification factor (AD conversion gain).

[0199] FIG. 8 is a diagram showing the operation of this embodiment.

[0200] The period from time t2 to time t17 is the readout period for the pixel reset noise signal (first noise signal) amplified by the first amplification factor. The period from time t18 to time t30 is the readout period for the optical signal (first optical signal) amplified by the first amplification factor. The period from time t30 to time t41 is the readout period for the optical signal (second optical signal) amplified by the second amplification factor. The period from time t42 to time t54 is the readout period for the pixel reset noise signal (second noise signal) amplified by the second amplification factor. In this embodiment, the signals are read out in the order of the first noise signal, first optical signal, second optical signal, and second noise signal.

[0201] In this embodiment, the first and second noise signals and the optical signal read out in the above order are all signals from the same pixel 12.

[0202] During the period up to time t2, φRES(n) goes high, turning on the reset transistor, resetting the floating diffusion region FD to a potential based on the power supply potential. After that, φRES(n) goes low, turning off the reset transistor, and releasing the reset of the floating diffusion region FD.

[0203] Next, similar to the drive sequence from time t1 to time t26 in FIG. 3A of the first embodiment, the timing generation circuit 60 sends out control signals from time t3 to time t30.

[0204] Up to this point, the first noise signal and the first optical signal amplified by the first amplification factor have been stored in the memory 42.

[0205] Next, the slope of the reference signal from the reference signal output circuit 36 is changed and the gain is switched to the second gain.

[0206] Although the amplification factor is different, the same driving sequence as that in the period from time t17 to time t30 is repeated in the period from time t30 to time t41.

[0207] Next, at time t42, φRES(n) goes high, turning on the reset transistor, resetting the floating diffusion region FD to a potential based on the power supply potential. After that, at time t43, φRES(n) goes low, turning off the reset transistor, and releasing the reset of the floating diffusion region FD.

[0208] Thereafter, although the slope of the reference signal is different, a driving sequence similar to that of the period from time t3 to time t17 is repeated in the period from time t44 to t51.

[0209] Up to this point, the second optical signal and the second noise signal amplified at the second amplification factor have been stored in the memory 42.

[0210] Thereafter, in a subsequent processing circuit, the digital value of the first noise signal is subtracted from the digital value of the first optical signal, and the result is output as digital data of the first signal.Similarly, the digital value of the second noise signal is subtracted from the digital value of the second optical signal, and the result is output as second digital data.

[0211] In this way, in this embodiment, signals from the same pixel 12 are amplified with different (AD conversion) gains. By using an image generated by combining signals from two pixels 12 through image processing at a later stage, it is possible to achieve a high dynamic range while maintaining simultaneity.

[0212] Furthermore, multiple offset levels can be generated and stored in the comparator circuit 32, making it possible to prevent the outputs of all the comparator circuits 32 from being inverted simultaneously. As a result, noise caused by IR drop and current fluctuations that accompany simultaneous inversion of the outputs of the comparator circuits 32 can be reduced, thereby improving image quality.

[0213] Furthermore, a drive sequence similar to that for driving the reference signal output circuit 36 before AD conversion of the noise signal is also inserted before AD conversion of the optical signal, which makes it easier to align the potential before resetting the noise signal to the AD conversion start potential and the potential before resetting the optical signal to the AD conversion start potential.

[0214] According to this embodiment, the drive sequences of the reference signal output circuits 36 before AD conversion of the noise signal and before AD conversion of the optical signal are aligned. This makes it easier to align the ramp start potential of AD conversion of the noise signal and the ramp start potential of AD conversion of the optical signal, even if there is not enough time to reset the ramp signals before each AD conversion.

[0215] Therefore, in this embodiment, the same effects as in the first embodiment can be obtained.

[0216] The noise signal superimposed on the second optical signal obtained by amplifying the optical signal by the second amplification factor is different from the second noise signal. However, the signal amplified by the second amplification factor, which is lower than the first amplification factor, is mainly used on the high-luminance side after image synthesis in the subsequent stage. Therefore, even if these noise signals are different, the optical shot noise is dominant, and the impact on the image quality after image synthesis is small, making it unlikely to be a problem.

[0217] Furthermore, in this embodiment, a drive sequence similar to that of the reference signal output circuit 36 before AD conversion of the second noise signal is inserted before AD conversion of the second optical signal. However, the effects of this embodiment can be obtained if a ramp signal drive sequence similar to that before AD conversion of the first noise signal is inserted only before AD conversion of the first optical signal. The reason is the same as above: the signal amplified with the second amplification factor is used mainly on the high-luminance side after image synthesis in the subsequent stage. Therefore, even if these noise signals are different, optical shot noise is dominant, and the impact on image quality after image synthesis is small, making it unlikely to be a problem.

[0218] Furthermore, in this embodiment, an example in which signals are read out in the order of first noise signal, first optical signal, second optical signal, and second noise signal has been described. However, this order may be changed to second noise signal, first noise signal, first optical signal, and second optical signal. In this case, the reset operation of the floating diffusion region FD by ON / OFF control of φRES(n) from time t42 to time t43 is unnecessary, and the noise signal superimposed on the second optical signal amplified by the second amplification factor becomes equivalent to the second noise signal. This has the effect of improving CDS accuracy even in high-brightness images. In this embodiment, a memory for separately storing the first noise signal and the second noise signal may be provided within memory 42 or in a downstream processing circuit.

[0219] Furthermore, as described as another example of the fourth embodiment, when multiple comparison circuits are provided for one pixel, AD conversions with different AD conversion gains (i.e., different slopes of the ramp signals) can be performed in parallel for the first noise signal and the second noise signal. Also, AD conversions with different AD conversion gains (i.e., different slopes of the ramp signals) can be performed in parallel for the first optical signal and the second optical signal.

[0220] (Embodiment 6) The schematic configuration of the photoelectric conversion device according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a block diagram showing an outline of the photoelectric conversion device according to this embodiment.

[0221] In this embodiment, in the AD conversion of an optical signal, multiple slopes of a reference signal (amount of potential change per unit time) are used, and they are selected according to the amount of optical signal for each pixel. In other words, the AD conversion gain is changed based on the pixel signal. This relates to a technology that can shorten the AD conversion period while suppressing a decrease in the effective AD resolution of a photoelectric conversion device.

[0222] Note that explanations of parts that overlap with FIG. 1 will be omitted.

[0223] The photoelectric conversion device 100 according to this embodiment further includes a reference signal selection circuit 501 in addition to the components of the photoelectric conversion device in FIG. 1. Furthermore, the reference signal output circuits 36A and 36B output ramp signals of the reference signals VRAMPL and VRAMPH. The reference signals VRAMPL and VRAMPH are ramp signals with different slopes (amount of potential change per unit time). The reference signal selection circuit 501 selects one of the reference signals VRAMPL and VRAMPH and outputs the ramp signal to the corresponding comparison circuit 32. The selection of this ramp signal is made based on the result of the comparison between the pixel signal and the determination threshold by the comparison circuit 32.

[0224] 10 is a diagram illustrating the readout operation of this embodiment. The operation is shown for the pixels 12 arranged in one row among the multiple rows of pixels 12 shown in FIG. 9. The pixels 12 arranged in one row include at least a first pixel 12 and a second pixel 12.

[0225] The reference signal VRAMPI shown in FIG. 10 is the reference signal that the reference signal selection circuit 501 outputs to the comparison circuit 32.

[0226] 10, SEL indicates whether the reference signal selection circuit 501 selects the reference signal VRAMPL or the reference signal VRAMPH as the reference signal corresponding to VRMPI. Also, FIG. 10 shows two types of output CMPO from the comparison circuit 32. The output CMPO1 (Dark to VTH) indicates the case where the imaging object is dark, specifically, the case where the output signal from the pixel based on the light incident on the photodiode PD is smaller than the difference (VTH-VOFF1) between a comparison level VTH and a reference level VOFF1 (described later). The output CMPO1 (VTH-Bright) indicates the case where the imaging object is bright, specifically, the case where the output signal is greater than (VTH-VOFF1).

[0227] Between time t1 and time t2, φRES(n) goes high, turning on the reset transistor, resetting the floating diffusion region FD to a potential based on the power supply potential. φRES(n) then goes low, turning off the reset transistor, and releasing the floating diffusion region FD from reset. The amplifier transistor outputs a signal based on the potential of the floating diffusion region FD from which the reset has been released to the vertical output line 16 via the selection transistor. The signal at this time is referred to as the N signal, and the potential level of the N signal is referred to as VN.

[0228] From time t1 to time t15, the reference signal selection circuit 501 outputs the reference signal VRMPL to VRMPI.

[0229] At time t3, the timing generation circuit 60 changes the control signal ΦRAMP_RESL from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0230] Also at time t3, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL, i.e., VRAMPI, to gradually change (decrease) from the reference voltage level over time.

[0231] Next, at time t4, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low. As a result, the voltage level of the reference signal VRAMPL, i.e., VRAMPI, no longer changes, and the reference signal VRAMPI remains constant at a first voltage level lower than the reference voltage level. The potential at this time is referred to as the offset level VOFF1. At time t5, the timing generation circuit 60 controls the control signal ΦCRES1 to change from high to low. As a result, the comparator circuit 32 of the column to which the control signal ΦCRES1 is supplied performs a clamp (auto-zero) operation to capture the pixel reset noise signal based on the offset level VOFF1.

[0232] Next, at time t6, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL, i.e., VRAMPI, to gradually change (decrease) from the reference voltage level over time.

[0233] Next, at time t7, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low. As a result, the voltage level of the reference signal VRAMPL, i.e., VRAMPI, no longer changes, and the reference signal VRAMPL remains constant at a second voltage level lower than the first voltage level. The potential at this time is referred to as the offset level VOFF2. At time t8, the timing generation circuit 60 controls the control signal ΦCRES2 to change from high to low. As a result, the comparator circuit 32 of the column to which the control signal ΦCRES2 is supplied performs a clamp (auto-zero) operation to capture the pixel reset noise signal based on the offset level VOFF2.

[0234] Next, at time t9, the timing generating circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, so that the reference signal VRAMPL, i.e., the voltage level of VRAMPL, gradually changes (decreases) from the reference voltage level over time.

[0235] Next, at time t10, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low. As a result, the voltage level of the reference signal VRAMPL, i.e., VRAMPI, no longer changes, and the reference signal VRAMPI becomes constant at a third voltage level lower than the second voltage level. The potential at this time is referred to as the offset level VOFF3. At time t11, the timing generation circuit 60 controls the control signal ΦCRES3 to change from high to low. As a result, the comparator circuit 32 of the column to which the control signal ΦCRES3 is supplied performs a clamp (auto-zero) operation to capture the pixel reset noise signal based on the offset level VOFF3.

[0236] Next, at time t12, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL, i.e., VRAMPI, to gradually change (decrease) from the reference voltage level over time.

[0237] Next, at time t13, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low. As a result, the voltage level of the reference signal VRAMP no longer changes, and the reference signal VRAMPL, i.e., VRAMPI, remains constant at a fourth voltage level lower than the third voltage level. The potential at this time is referred to as the offset level VOFF4. At time t14, the timing generation circuit 60 controls the control signal ΦCRES4 to change from high to low. As a result, the comparator circuit 32 of the column to which the control signal ΦCRES4 is supplied performs a clamp (auto-zero) operation to capture the pixel reset noise signal based on the offset level VOFF4.

[0238] Next, at time t15, the timing generation circuit 60 changes the control signal ΦRAMP_RESL from low to high, which puts the reference signal output circuit 36 into a reset state and returns the voltage level of the reference signal to the reference level.

[0239] Then, the output CMPO1 goes to high level. Whether the output CMPO1 goes to high level or low level at this point depends on the configuration of the comparison circuit 32. In this example, the following explanation will be continued assuming that the output CMPO1 goes to high level.

[0240] In the period from time t16 to time t18, the first AD conversion is performed.

[0241] At time t16, the timing generating circuit 60 changes the control signal ΦRAMP_RESL from high level to low level.

[0242] At the same time, at time t16, the timing generation circuit 60 changes the control signal ΦRAMP_ENL from low to high, causing the voltage level of the reference signal VRAMPL, i.e., VRAMPI, to gradually change (decrease) from the reference level over time.

[0243] The counter 44 also starts counting. When the potential of the reference signal VRMPI reaches the offset level VOFF1 at time t17, the magnitude relationship between the two input signal levels VRMPI and VIN of the comparator circuit 32 on the PIX1 column is inverted, and the output CMPO1 changes to Lo. This change in the output CMPO1 triggers the memory 42 to capture the count value at that time as a digital signal. The digital signal at this time is designated as the N1 signal.

[0244] The same applies to subsequent times when the potential of VRAMPI reaches the offset levels VOFF2 to VOFF4. The digital signals at these times are designated as N2 to N4, respectively.

[0245] At time t18, the control signal ΦRAMP_RESL goes high and the enable signal ΦRAMP_ENL goes low, resetting the reference signal VRMPL and causing the output CMPO1 to go high.

[0246] Between time t19 and time t20, φTX(n) goes high and the pixel transfer transistor turns on, transferring the charge accumulated in the photodiode PD to the floating diffusion region FD. The amplifier transistor outputs a signal based on the potential of the floating diffusion region FD to the vertical output line 16 via the row selection transistor. The signal that this amplifier transistor outputs to the vertical signal line 16 is called an optical signal, and the potential level of the optical signal is denoted as VS. The optical signal is a signal generated by photoelectric conversion in the pixel 12.

[0247] During this period, the node VRMPI outputs a comparison potential level (comparison level) VTH for comparing the magnitude of the optical signal. The comparison level VTH can be achieved, for example, by connecting a current source for generating a comparison level (not shown) to the node VRMPL and passing a large current through it during this period. The case where the change (VS-VN) from the potential level of the reset noise signal to the potential level of the optical signal is smaller than the difference (VTH-VOFF1-4) between the comparison level VTH (decision threshold) and each of the reference levels VOFF1-4 (Dark-VTH) will be described. In this case, each of the outputs CMPO1-4 is low. On the other hand, the case where the change (VS-VN) is larger than the difference (VTH-VOFF1-4) between the comparison level VTH and each of the reference levels VOFF1-4 (VTH-VOFF1-4) (VTH-Bright) will be described. In this case, each of the outputs CMPO1-4 is high. This comparison is performed for each column, and the results of the comparison for each column are stored in the memory 42. That is, the results of the comparison operation of whether each of the outputs CMPO1 to CMPO4 is at a high level or a low level are input to the memory 42. The results of this comparison operation are also input to the reference signal selection circuit 501.

[0248] The comparison level VTH is preferably set lower than the level at which the change in the potential of the reference signal VRMPL ends.With this configuration, the signal from the pixel can be compared with either the reference signal VRMPL or VRMPH.

[0249] Between time t22 and time t23, the reference signal selection circuit 501 selects the signal VRMPI to be output depending on the result of the comparison operation. When the amplitude of the signal from the pixel is equal to or less than a predetermined value, the reference signal selection circuit 501 selects the reference signal VRMPL as VRMPI, and when the amplitude of the signal from the pixel exceeds the predetermined value, the reference signal selection circuit 501 selects the reference signal VRMPL as VRMPI. That is, when each of the outputs CMPO1 to CMPO4 is at a low level, the reference signal selection circuit 501 outputs VRMPL as VRMPI, and when each of the outputs CMPO1 to CMPO4 is at a high level, the reference signal selection circuit 501 outputs VRMPH as VRMPI. The reference signal selection circuit 501 selects and outputs ramp signals VRMPH or VRMPL with different slopes depending on the difference between the comparison level VTH and each of the reference levels VOFF1 to VOFF4.

[0250] Next, at time t23, the timing generation circuit 60 controls the control signal ΦRAMP_RESL to change from high level to low level, thereby releasing the reference signal output circuit 36 from the reset state.

[0251] Also at time t23, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL to gradually change (decrease) from the reference voltage level over time.

[0252] Next, at time t24, the timing generating circuit 60 controls the control signal ΦRAMP_ENL to change from high to low, so that the voltage level of the reference signal VRAMPL no longer changes and the reference signal VRAMPL remains constant at the first voltage level that is lower than the reference voltage level.

[0253] Next, at time t25, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL to gradually change (decrease) from the reference voltage level over time.

[0254] Next, at time t26, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low, so that the voltage level of the reference signal VRAMPL no longer changes and the reference signal VRAMPL becomes constant at a second voltage level that is lower than the first voltage level.

[0255] Next, at time t27, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL to gradually change (decrease) from the reference voltage level over time.

[0256] Next, at time t28, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low, so that the voltage level of the reference signal VRAMPL no longer changes and the reference signal VRAMPI becomes constant at a third voltage level that is lower than the second voltage level.

[0257] Next, at time t29, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from low level to high level, causing the voltage level of the reference signal VRAMPL to gradually change (decrease) from the reference voltage level over time.

[0258] Next, at time t30, the timing generation circuit 60 controls the control signal ΦRAMP_ENL to change from high to low, so that the voltage level of the reference signal VRAMPL no longer changes and the reference signal VRAMPL becomes constant at a fourth voltage level that is lower than the third voltage level.

[0259] Next, at time t31, the timing generation circuit 60 changes the control signal ΦRAMP_RESL from low to high, which puts the reference signal output circuit 36 into a reset state and returns the voltage level of the reference signal to the reference level.

[0260] Just before time t32, the enable signals ΦRAMP_ENL and ΦRAMP_ENH become high level, preparing for the second AD conversion operation described below.

[0261] Between time t32 and time t34, the second AD conversion is performed.

[0262] From here on, the cases where the result of the comparison operation is low level (Dark to VTH) and high level (VTH to Bright) will be explained separately.

[0263] When the result of the comparison operation is at a low level (Dark to VTH), for example, the comparison operation is performed on a signal from a first pixel where no light is incident on the photodiode PD or the light is below a certain level.

[0264] In the example of CMPO1 in FIG. 10, the optical signal on the vertical output line 16 connected to the corresponding pixel is at the same level as the reset noise signal. Therefore, the output CMPO1 is inverted to low at time t33 when the potential of the ramp signal VRMPL reaches VOFF1, or in other words, when the change in the potential of the reference signal VRMPL reaches (VRES-VOFF1). This case will be described where the change in the pixel signal (VS-VN) is greater than (VRES-VOFF1) and less than (VTH-VOFF1). The output CMPO1 is inverted to low at any of the times t33 to t35 when the ramp signal VRMPL reaches (VRES-(VS-VN)-VOFF1). The brighter the optical signal, the later the time at which CMPO1 is inverted to low. This change in the output CMPO1 triggers the memory 42 to capture the count value at that time as a digital signal. This digital signal is referred to as the SADL signal.

[0265] When the comparison result is high (VTH~Bright), for example, the comparison is performed on a signal from a second pixel where the amount of light incident on the photodiode PD exceeds a certain level. This example illustrates a bright row where the pixel signal change (VS-VN) for the corresponding pixel connected to the comparison result is high and has an amplitude equivalent to (VTH-VOFF1). At time t34, when the potential of the ramp signal VRMPH reaches (VRES-VTH), the output CMP01 switches to low. While exceptions may occur due to noise, when the ramp signal VRMPH is selected, the pixel signal change (VS-VN) is usually greater than (VTH-VOFF1), and the output CMP01 does not switch to low before time t34. The larger the pixel signal change (VS-VN), the later the output CMP01 switches to low after time t34. This change in the output CMP01 triggers the memory 42 to capture the count value at that time as a digital signal. This digital signal is designated the SADH signal.

[0266] At time t35, the control signals RESL and RESH go to high level and the enable signals ENL and ENH go to low level, thereby resetting the reference signals VRMPL and RMPH and causing the output CMPO1 to go to high level.

[0267] After time t34, the NAD signal, SADL signal or SADH signal, which is a digital signal, and the result of the comparison operation are output from the memory 42 to the signal processing circuit at the subsequent stage, where CDS processing is performed.

[0268] Next, we will explain the outline of the CDS processing performed in the signal processing circuit at the subsequent stage. In this example, AD conversion processing is performed using two reference signals VRMPL and VRMPH with a slope ratio of 1:4, so the AD conversion gain performed using the reference signal VRMPL is four times larger than that of the ramp signal VRMPH. Therefore, the AD conversion gain is adjusted before the following CDS processing is performed. If the comparison result is low: SADL-NAD If the comparison result is high: 4 x SADH-NAD

[0269] Correction processing is also performed in the signal processing circuit at the subsequent stage.

[0270] When combining the AD conversion results of the reference signals VRMPL and VRMPH, two correction processes are performed to maintain linearity: slope correction, which corrects the error from the ideal slope ratio (1:4 in this example) of the ramp signals VRMPL and VRMPH, and step correction, which corrects the step that occurs near the level (VTH-VOFF1 to 4) at which the ramp signal selection switches. SADH = S(RMPH) / S(RMPL) / f(counter)

[0271] S(RMPH) is the slope of the reference signal VRMPH, S(RMPL) is the slope of the reference signal VRMPL, and f(counter) is the count frequency of the counter 44.

[0272] As described above, according to this embodiment, two types of reference signal slopes are prepared and used depending on the amount of incident light for each pixel, thereby achieving high-speed AD conversion and signal readout without reducing the effective resolution of the digital signal ultimately output by the photoelectric conversion device.

[0273] Furthermore, according to this embodiment, the drive sequences of the reference signal output circuit 36 before AD conversion of the noise signal and before AD conversion of the optical signal in the dark and at low illuminance that is AD converted by the reference signal VRAMPL are aligned. This makes it easy to align the ramp start potential of AD conversion of the noise signal and the AD conversion ramp start potential of the optical signal in the dark and at low illuminance, even if there is not enough time to reset the ramp signals before each AD conversion.

[0274] Therefore, in this embodiment, the same effects as in the first embodiment can be obtained.

[0275] In this embodiment, φRAMP_RESH remains at a low level until time t32. Therefore, in the reference signal VRAMPH, the drive sequences of the reference signal output circuit 36 before AD conversion of the pixel reset noise signal and before AD conversion of the optical signal at high illuminance of VTH-VOFF or higher are not aligned.

[0276] However, this is unlikely to be a problem in terms of the image quality of an actual photoelectric conversion device. The noise generated by this drive sequence is not gain-related (the type that increases in proportion to the magnitude of the optical signal), but offset-related, and the noise becomes smaller relative to the optical signal at high illuminance. Furthermore, optical shot noise exists at high illuminance levels, and this optical shot noise is greater than the amount of noise caused by the above issue.

[0277] For the above two reasons, noise caused by CDS errors is difficult to see in the reference signal VRAMPH even under the control of this embodiment, and is unlikely to cause any problems.

[0278] Note that the reference signal VRAMPH may be controlled in the same manner as the reference signal VRAMPL. In this case, for example, VRAMPI is controlled to output VRAMPH between times t18 and t19, and φRAMP_ENH is controlled in the same manner as φRAMP_ENL between times t3 and t18 during that time. At this time, the values of N1' to N4' when VRAMPH is output to VRAMPI are also separately stored and held in the memory 42. In addition, from time t23 onward, φRAMP_ENH is similarly controlled in the same manner as φRAMP_ENL. As a result, by using N1' to N4' as NAD signals for pixels for which VRAMPH is selected on the high-illuminance side, the benefits of this embodiment can also be obtained for signals on the high-illuminance side.

[0279] (Embodiment 7) Embodiment 7 can be applied to any of Embodiments 1 to 6. FIG. 12(a) is a schematic diagram illustrating a device 9191 including a photoelectric conversion device 930 of this embodiment. The device 9191 including the photoelectric conversion device 930 will be described in detail. As described above, the photoelectric conversion device 930 can include a package 920 that houses the semiconductor device 910, in addition to the semiconductor device 910 having the semiconductor layer 10. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0280] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the photoelectric conversion device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric conversion device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0281] The processing device 960 processes the signal output from the photoelectric conversion device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0282] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the photoelectric conversion device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a storage device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the photoelectric conversion device 930. The mechanical device 990 may be controlled based on the signal output from the photoelectric conversion device 930.

[0283] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the photoelectric conversion device 930 for vibration isolation.

[0284] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the photoelectric conversion device 930 or for assisting and / or automating driving (piloting) using an imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the photoelectric conversion device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0285] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the photoelectric conversion device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0286] Therefore, if the photoelectric conversion device 930 according to this embodiment is used in equipment 9191, the value of the equipment can also be improved. For example, by installing the photoelectric conversion device 930 in transportation equipment, excellent performance can be obtained when photographing the exterior of the transportation equipment or measuring the external environment. Therefore, when manufacturing and selling transportation equipment, deciding to install the photoelectric conversion device according to this embodiment in the transportation equipment is advantageous in terms of improving the performance of the transportation equipment itself. In particular, the photoelectric conversion device 930 is suitable for transportation equipment that performs driving assistance and / or automatic driving of the transportation equipment using information obtained by the photoelectric conversion device.

[0287] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration. [Explanation of symbols]

[0288] 12 pixels 32 Comparison circuit 36 Reference signal output circuit 101 pixel array

Claims

1. A method for driving an AD conversion circuit including a plurality of comparison circuits, each having a first terminal to which a plurality of analog signals including a first analog signal and a second analog signal are input, and a second terminal connected to a wiring through which a ramp signal is transmitted, comprising: a first operation of changing a potential of the wiring from a predetermined potential to a first potential, thereby causing some of the plurality of comparison circuits to hold a first offset; a second operation, after the first operation, of converting the first analog signal into a digital signal; a third operation of setting the potential of the wiring to a potential included in a range from the predetermined potential to the first potential after the second operation; a fourth operation of converting the second analog signal into a digital signal after the third operation; A driving method for an AD conversion circuit, comprising:

2. The driving method for an AD conversion circuit according to claim 1, characterized in that, before the first operation, the potential of the wiring is set to a second potential between the predetermined potential and the first potential, thereby performing an operation to cause another part of the plurality of comparison circuits to hold a second offset different from the first offset.

3. A driving method for an AD conversion circuit as described in claim 2, characterized in that after the second operation and before the third operation, the potential of the wiring is changed from the predetermined potential to the second potential, and the third operation is an operation of changing the potential of the wiring from the second potential to the first potential.

4. 4. The method for driving an AD converter circuit according to claim 2, wherein the potential of the wiring changes in a slope pattern from the predetermined potential to the first potential via the second potential.

5. 4. The method for driving an AD converter circuit according to claim 2, wherein the potential of the wiring changes stepwise from the predetermined potential to the first potential via the second potential.

6. an output circuit that outputs the ramp signal; 6. The method for driving an AD conversion circuit according to claim 2, wherein the output circuit outputs the predetermined potential, the first potential, and the second potential to the wiring.

7. A method for driving an AD conversion circuit according to any one of claims 1 to 6, characterized in that in the second operation, the ramp signal changes in potential beyond the first potential, with the predetermined potential as a ramp start potential.

8. 8. The method for driving an AD converter circuit according to claim 7, wherein in the third operation, the ramp signal changes in potential beyond the first potential, with the predetermined potential being a ramp start potential.

9. In the second operation, the ramp signal changes in potential from a third potential that is a ramp start potential different from the predetermined potential, A driving method for an AD conversion circuit according to any one of claims 1 to 6, characterized in that the first operation changes the potential of the wiring from the third potential to the predetermined potential and then sets it to the first potential.

10. a plurality of comparison circuits each having a first terminal to which a plurality of analog signals including a first analog signal and a second analog signal are input, and a second terminal connected to a wiring through which a ramp signal is transmitted; and a control circuit, The control circuit a first operation of changing a potential of the wiring from a predetermined potential to a first potential, thereby causing some of the plurality of comparison circuits to hold a first offset; a second operation, after the first operation, of converting the first analog signal into a digital signal; a third operation of setting the potential of the wiring to a potential included in a range from the predetermined potential to the first potential after the second operation; a fourth operation of converting the second analog signal into a digital signal after the third operation; An AD conversion circuit characterized by controlling

11. an AD conversion circuit according to claim 10; A photoelectric conversion device comprising a plurality of pixels, each of which has a photoelectric conversion unit and outputs the first analog signal and the second analog signal at different times.

12. 12. The photoelectric conversion device according to claim 11, wherein the first analog signal is a noise signal, and the second analog signal is a signal based on charges generated by the photoelectric conversion unit based on incident light.

13. Each of the plurality of pixels includes a plurality of photoelectric conversion units, a plurality of microlenses are arranged such that one microlens corresponds to the plurality of photoelectric conversion units of one pixel; each of the plurality of pixels outputs the second analog signal as a signal based on charges of some of the plurality of photoelectric conversion units; each of the plurality of pixels outputs a third analog signal as a signal based on the charges of the plurality of photoelectric conversion units; The control circuit a fifth operation of setting the potential of the wiring to a potential included in a range from the predetermined potential to the first potential after the fourth operation; 13. The photoelectric conversion device according to claim 11, wherein after the fifth operation, a sixth operation of converting the third analog signal into a digital signal is performed.

14. the control circuit causes each of the plurality of comparison circuits to compare the second analog signal with a threshold value; 14. The photoelectric conversion device according to claim 11, wherein an amount of change in potential per unit time of a ramp signal used in the fourth operation is changed based on a result of the comparison.

15. a first substrate on which the plurality of pixels are provided; 15. The photoelectric conversion device according to claim 11, further comprising a structure in which the plurality of comparison circuits and a second substrate on which the control circuit is provided are stacked.

16. An apparatus comprising the photoelectric conversion device according to any one of claims 11 to 15, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

Images