Acoustic processing system, acoustic processing method, and information processing device

Abstract

To provide an acoustic processing system, an acoustic processing method, and an information processing device that make sound signal processing be distributed and processed flexibly and easily.SOLUTION: An acoustic processing system comprises: an information processor 12 that is a first device including a current memory 351 that is a first memory for holding a parameter for sound signal processing, and an operation unit for receiving operation of the parameter held by the current memory 351; and a processor 11 including a manager 503 that is a second device including a current memory 251 that is a second memory for holding a parameter in synchronization with the parameter held by the current memory 351 and a first CPU 2041 for performing system control and a player 502 that is a third device including a second CPU 2042 for performing sound signal processing. The first CPU transmits, to the player, control information for controlling the sound signal processing on the basis of the parameter held by the current memory 251. The second CPU performs the sound signal processing on the basis of the received control information.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a sound processing system, a sound processing method, and an information processing device. [Background technology]

[0002] Patent Document 1 discloses a personal computer on which a large number of remote control software programs that can be plugged into music software are installed. The personal computer synchronizes operation parameters between each remote control software program and a corresponding external device.

[0003] The control device of Patent Document 2 includes first and second control boards that can communicate with each other. The first and second control boards include parameter storage units that store parameters. The parameters of the first and second control boards are synchronized. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-072656 [Patent Document 2] Patent Publication No. 2021-018590 Summary of the Invention [Problem to be solved by the invention]

[0005] Both Patent Documents 1 and 2 simply disclose a configuration for synchronizing the memories (parameters) of two devices. Neither of the prior art documents takes into consideration the distribution of sound signal processing.

[0006] Therefore, an object of one embodiment of the present invention is to provide an audio processing system that can flexibly and easily perform distributed processing of audio signals. [Means for solving the problem]

[0007] The acoustic processing method includes a first device including a first memory that stores parameters for sound signal processing and an operation unit that accepts operations on the parameters stored in the first memory, a second device including a second memory that stores parameters synchronized with the parameters in the first memory and a first CPU that performs system control, and a third device including a second CPU that performs sound signal processing. The first CPU transmits control information to the third device for controlling the sound signal processing based on the parameters stored in the second memory, and the second CPU receives the control information and performs the sound signal processing based on the control information. [Effects of the Invention]

[0008] An embodiment of the present invention makes it possible to flexibly and easily perform distributed processing of sound signals. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of a sound processing system 1. [Figure 2] FIG. 2 is a block diagram showing the hardware configuration of the processor 11. [Figure 3] FIG. 2 is a block diagram showing the configuration of an information processing device 12. [Figure 4] FIG. 2 is a functional block diagram of a processor 11 and an information processing device 12. [Figure 5] 10 is a flowchart illustrating the operation of the sound processing system. [Figure 6] FIG. 2 is a block diagram of a sound processing system 1 further including a cloud server 20. [Figure 7] 2 is a functional block diagram of a processor 11, a cloud server 20, and an information processing device 12. FIG. [Figure 8] 2 is a functional block diagram of a processor 11, a cloud server 20, and an information processing device 12. FIG. [Figure 9] FIG. 1 is a block diagram of an audio processing system 1 further including a processor 11A. [Figure 10]2 is a functional block diagram of a processor 11, a processor 11A, and an information processing device 12. FIG. [Figure 11] 2 is a functional block diagram of a processor 11, a processor 11A, a cloud server 20, and an information processing device 12. FIG. [Figure 12] FIG. 2 is a functional block diagram of a processor 11 and an information processing device 12. [Figure 13] FIG. 10 is a functional block diagram showing an example of transmitting control information to an audio amplifier 20A. [Figure 14] FIG. 10 is a functional block diagram illustrating an example of storing signal processing components as a DLL. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1 is a block diagram showing the configuration of a sound processing system 1. The sound processing system 1 includes a processor 11, an information processing device 12, a network 13, a speaker 14, and a microphone 15.

[0011] The processor 11 and the information processing device 12 are connected via a network 13. The network 13 includes a LAN (Local Area Network) or the Internet. The processor 11 is connected to a speaker 14 and a microphone 15 via an audio cable.

[0012] However, in the present invention, the connection between devices is not limited to this example. For example, the processor 11, the speaker 14, and the microphone 15 may be connected via a network. Also, the processor 11 and the information processing device 12 may be connected by a communication line such as a USB cable.

[0013] The processor 11 is an example of a sound signal processing device. The processor 11 receives a sound signal from a microphone 15. The processor 11 also outputs the sound signal to a speaker 14. In this embodiment, the speaker 14 and the microphone 15 are shown as examples of audio devices connected to the processor 11, but a larger number of audio devices may also be connected.

[0014] 2 is a block diagram showing the configuration of the processor 11. The processor 11 includes a display 201, a user I / F 202, an audio I / O (Input / Output) 203, a CPU 204, a network I / F 205, a flash memory 206, and a RAM 207.

[0015] The display 201 is made up of an LED, an LCD, or the like, and displays various information (for example, the power ON / OFF state, etc.). The user I / F 202 is an operator such as a switch or a button. The user I / F 202 accepts user operations such as turning the power ON / OFF.

[0016] The CPU 204 functions as a control unit (first CPU) for performing system control. The CPU 204 also functions as a signal processing unit (second CPU) for performing sound signal processing. The CPU 204 performs the operations of the control unit and the signal processing unit by reading a predetermined program stored in a flash memory 206, which is a storage medium, into a RAM 207 and executing it.

[0017] The CPU 204 performs sound signal processing such as filtering on sound signals input from an audio device such as the microphone 15 via the audio I / O 203 or the network I / F 205. The CPU 204 outputs the processed sound signals to an audio device such as the speaker 14 via the audio I / O 203 or the network I / F 205.

[0018] Parameters indicating the details of the sound signal processing are held in current memory 251 in flash memory 206. CPU 204 performs sound signal processing based on the parameters held in current memory 251.

[0019] The setting contents (setting information) for system control are stored in a setting memory 252 in the flash memory 206. The CPU 204 performs system control based on the setting information stored in the setting memory 252. The system control includes, for example, patch settings (wiring management) for input ports (physical ports) that input audio signals and input channels.

[0020] The program read by CPU 204 does not need to be stored in flash memory 206 within the device itself. For example, the program may be stored in a storage medium of an external device such as a server. In this case, CPU 204 simply reads the program from the server into RAM 207 and executes it each time.

[0021] 3 is a block diagram showing the configuration of the information processing device 12. The information processing device 12 is, for example, an information processing device such as a personal computer or a dedicated embedded system.

[0022] The information processing device 12 includes a display 301 , a user I / F 302 , a CPU 303 , a RAM 304 , a network I / F 305 , and a flash memory 306 .

[0023] CPU 303 reads a program stored in flash memory 306, which is a storage medium, into RAM 304 to implement a predetermined function. Note that the program read by CPU 303 does not have to be stored in flash memory 306 within its own device. For example, the program may be stored in a storage medium of an external device such as a server. In this case, CPU 303 simply reads the program from the server into RAM 304 and executes it each time.

[0024] The flash memory 306 has a current memory 351 and a setting memory 352. The current memory 351 is synchronized with the current memory 251 of the processor 11. The setting memory 352 is synchronized with the setting memory 252 of the processor 11.

[0025] For example, when a user changes a parameter by operating user I / F 202 of processor 11, processor 11 updates the content of current memory 251 and transmits the updated content of current memory 251 to information processing device 12. CPU 303 receives the updated content of current memory 251 via network I / F 305 and synchronizes the updated content of current memory 351 with the updated content of current memory 251. Furthermore, when a user changes a parameter by operating user I / F 302 of information processing device 12, information processing device 12 updates the content of current memory 351 and transmits the updated content of current memory 351 to processor 11. CPU 204 receives the updated content of current memory 351 via network I / F 205 and synchronizes the updated content of current memory 251 with the updated content of current memory 351.

[0026] When the processor 11 and the information processing device 12 are not connected to each other, they each change the contents of their current memories independently. When the processor 11 and the information processing device 12 are connected to each other, the contents of either the current memory 251 of the processor 11 or the current memory 351 of the information processing device 12 are used to update the contents of the other. The user may select whether to use the contents of the current memory 251 of the processor 11 or the current memory 351 of the information processing device 12.

[0027] Next, Fig. 4 is a functional block diagram of the processor 11 and the information processing device 12. Fig. 5 is a flowchart showing the operation of the sound processing system. As shown in Fig. 4, the processor 11 functionally constitutes a player 502 and a manager 503. The manager 503 constitutes a control unit (first CPU 2041) for performing system control. The player 502 constitutes a signal processing unit (second CPU 2042) for performing sound signal processing. In this example, the information processing device is an example of a first device, the manager 503 is an example of a second device, and the player 502 is an example of a third device.

[0028] The player 502 and the manager 503 are configured as virtually separate devices within the same physical device. The player 502 and the manager 503 communicate using a predetermined protocol (for example, TCP / IP: Transmission Control Protocol / Internet Protocol). In this example, the first CPU 2041 and the second CPU 2042 function as virtually separate CPUs within a single physical CPU 204. However, the first CPU 2041 and the second CPU 2042 may be separate cores within a single physical CPU having multiple cores. Furthermore, the first CPU 2041 and the second CPU 2042 may be physically separate CPUs.

[0029] The CPU 303 of the information processing device 12 accepts an operation for parameters via the user I / F 302, which is an operation unit (S11). The CPU 303 updates the current memory 351, which is a first memory, with the changed parameters (S12).

[0030] The manager 503 synchronizes the current memory 251, which is the second memory, with the current memory 351, which is the first memory (S22). At this time, the manager 503 may also synchronize the setting memory 252 and the setting memory 352. The manager 503 performs system control based on the synchronized setting memory 252. In other words, the first memory may include both the current memory 351 and the setting memory 352, and the second memory may include both the current memory 251 and the setting memory 252.

[0031] Next, the first CPU 2041 transmits control information for controlling sound signal processing to the player 502 based on the parameters stored in the current memory 251 (S23). The control information includes, for example, filter coefficients for filter processing. As described above, the manager 503 and the player 502 are configured as virtually separate devices, and the manager 503 transmits control information to the player 502 using a protocol such as TCP / IP.

[0032] The second CPU 2042 of the player 502 receives control information (S31) and performs sound signal processing based on the control information (S32). Specifically, the second CPU 2042 performs sound signal processing such as filtering on a sound signal input from an audio device such as the microphone 15, and outputs the processed sound signal to an audio device such as the speaker 14.

[0033] As described above, according to the sound processing system 1 of this embodiment, the processor 11 configures the manager 503 and the player 502 as separate devices, and the manager 503 transmits control information to the player 502 using a protocol such as TCP / IP. Therefore, the manager 503 can transmit control information to control sound signal processing not only to the player 502 in the processor 11, but also to any sound signal processing device that can receive information using a protocol such as TCP / IP. For example, FIG. 6 is a block diagram of the sound processing system 1 further including a cloud server 20. FIG. 7 is a functional block diagram of the processor 11, the cloud server 20, and the information processing device 12.

[0034] The cloud server 20 is an example of a sound signal processing device. In this case, the first CPU 2041 of the manager 503 transmits control information to the cloud server 20 using a protocol such as TCP / IP. The cloud server 20 constitutes a second CPU 211. The second CPU 211 receives control information from the first CPU 2041 and performs sound signal processing based on the control information. At this time, the first CPU 2041 also transmits sound signals input from audio devices such as the microphone 15 to the second CPU 211 using a protocol such as TCP / IP. The second CPU 211 receives control information and sound signals from the first CPU 2041 and performs sound signal processing on the received sound signals based on the control information. The second CPU 211 transmits the processed sound signals to the first CPU 2041 using a protocol such as TCP / IP. The first CPU 2041 outputs the received sound signals to audio devices such as the speaker 14.

[0035] In this way, the second device that performs system control and the third device that performs sound signal processing do not need to be configured as virtually separate devices within the same physical device, but may be physically separate devices, i.e., the second device and the third device may each be an independent information processing device.

[0036] According to the sound processing system 1 of this embodiment, it is possible to have the player 502 of the manager 503 execute sound signal processing, or to have another device such as the cloud server 20 execute sound signal processing. Furthermore, as shown in FIG. 8 , the first CPU 2041 of the manager 503 can also have both the second CPU 2042 of the player 502 of the manager 503 and the second CPU 211 of the cloud server 20 execute sound signal processing. In this case, the manager 503 may determine the sound signal processing to be executed by the second CPU 2042 and the sound signal processing to be executed by the second CPU 211 based on the respective processing capabilities of the second CPU 2042 and the second CPU 211. Alternatively, the manager 503 may determine the sound signal processing to be executed by the second CPU 2042 and the sound signal processing to be executed by the second CPU 211 based on the allowable range of latency in filter processing. When sound signals are transmitted to and received from the cloud server 20, communication latency increases. Therefore, the manager 503 may cause the second CPU 211 to execute sound signal processing that has a wide tolerance range for latency, for example.

[0037] As described above, the manager 503 uses a general-purpose protocol such as TCP / IP, allowing for flexible and easy distributed processing of sound signal processing. Furthermore, the user only needs to remotely change the parameters of the processor 11 using the information processing device 12, and does not need to control the player 502 on the signal processing side, nor does he need to manage which device is to perform what kind of signal processing.

[0038] Furthermore, the information processing device 12 can change parameters not only for one sound signal processing device but also for multiple sound signal processing devices. Fig. 9 is a block diagram of the sound processing system 1 further including a processor 11A. Fig. 10 is a functional block diagram of the processor 11, the processor 11A, and the information processing device 12. The hardware and functional configuration of the processor 11A are the same as those of the processor 11.

[0039] In this example, the information processing device 12 includes a current memory 351A that stores parameters different from the current memory 351. The current memory 351A is an example of a third memory. The current memory 351A is synchronized with the current memory 251A of the processor 11A. When the processor 11A and the information processing device 12 are not connected to each other, they each change the contents of their current memories independently. When the processor 11A and the information processing device 12 are connected to each other, the contents of either the current memory 251 of the processor 11A or the current memory 351 of the information processing device 12 are updated with the contents of the other. In other words, the information processing device 12 can change the contents of the current memory 351 independently when not connected to the processor 11A, and can also change the contents of the current memory 351 independently when not connected to the processor 11A.

[0040] 10, the processor 11A functionally configures a player 502A and a manager 503A, similar to the processor 11. The manager 503A configures a control unit (third CPU 2041A) for performing system control. The player 502A configures a signal processing unit (fourth CPU 2042A) for performing sound signal processing. In this example, the manager 503A includes a current memory 251A, which is a fourth memory, and is an example of a fourth device that performs system control, and the player 502A is an example of a fifth device that performs sound signal processing.

[0041] In this example, the player 502A and the manager 503A are configured as virtually separate devices within the same physical device. The player 502A and the manager 503A communicate using a protocol such as TCP / IP. Of course, the fourth device that performs system control and the fifth device that performs sound signal processing do not necessarily have to be configured as virtually separate devices within the same physical device, but may be physically separate devices. In other words, the fourth device and the fifth device may also each be an independent information processing device.

[0042] The third CPU 2041A transmits control information for controlling sound signal processing to the player 502A based on the parameters stored in the current memory 251A. The fourth CPU 2042A of the player 502A receives the control information and performs sound signal processing based on the control information.

[0043] In this way, the information processing device 12 can also remotely control the contents of signal processing (current memory) of a plurality of sound signal processing devices.

[0044] 11 , the manager 503A of the processor 11A can also cause another device, such as the cloud server 20, to execute sound signal processing. Also, as shown in FIG. 11 , the third CPU 2041A of the manager 503A can cause both the fourth CPU 2042A of the player 502A of the own device and the second CPU 211 of the cloud server 20 to execute sound signal processing. In this case, the manager 503A may determine the sound signal processing to be executed by the fourth CPU 2042A and the sound signal processing to be executed by the second CPU 211 based on the respective processing capabilities of the fourth CPU 2042A and the second CPU 211. Alternatively, the manager 503A may determine the sound signal processing to be executed by the fourth CPU 2042A and the sound signal processing to be executed by the second CPU 211 based on the allowable range of latency in filter processing.

[0045] The description of the present embodiment is illustrative in all respects and is not restrictive. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention is intended to include all modifications that are equivalent to the claims and fall within the scope thereof.

[0046] The sound signal processing device includes not only a processor but also, for example, an amplifier, a mixer, an audio amplifier, or the like.

[0047] In the above embodiment, the sound signal processing function is implemented by a CPU. However, as shown in Fig. 12, the processor 11 may perform the signal processing function using hardware (for example, a DSP or FPGA). The processor 11 shown in Fig. 12 further includes a signal processing device 702 having an FPGA 902. The manager 503 transmits control information for controlling sound signal processing to the player 502 and the signal processing device 702 based on parameters stored in the current memory 251. The FPGA 902 of the signal processing device 702 receives the control information and performs sound signal processing based on the control information.

[0048] The manager 503 may determine the sound signal processing to be executed by the second CPU 2042 and the sound signal processing to be executed by the FPGA 902 based on the respective processing capabilities of the second CPU 2042 and the FPGA 902. Alternatively, the manager 503 may determine the sound signal processing to be executed by the second CPU 2042 and the sound signal processing to be executed by the FPGA 902 based on the allowable range of latency in the filter processing.

[0049] When transmitting control information to multiple sound signal processing devices, the manager 503 may transmit the control information to some devices using a first protocol and to other devices using a second protocol. Fig. 13 is a functional block diagram showing an example of transmitting control information to the audio amplifier 20A. The audio amplifier 20A includes a fourth CPU 211A that performs sound signal processing. The manager 503 may transmit the control information to the player 502 using TCP / IP, and to the fourth CPU 211A of the audio amplifier 20A using another protocol (for example, TMDS: Transition Minimized Differential Signaling).

[0050] FIG. 14 is a functional block diagram showing an example of saving a signal processing component as a dynamic link library (DLL). The signal processing component is a collection of specific details of signal processing as information, including parameter details and filter coefficients. The processor 11 functionally includes a software development kit (SDK) 80. The SDK 80 is an example of an application program for saving the signal processing component as a DLL. The SDK 80 generates, as a DLL 80, a signal processing component including parameters managed by a first CPU and filter coefficients managed by a second CPU. The DLL 80 is stored in, for example, the flash memory 206.

[0051] This allows the processor 11 to save the contents of the signal processing set by the user as a DLL. Any sound signal processing device that can deploy the DLL can perform sound signal processing by executing the DLL. [Explanation of symbols]

[0052] 1...Sound processing system 11,11A...Processor 12...Information processing device 13…Network 14...Speaker 15...Mike 20...Cloud server 20A...Audio amplifier 80…DLL 201...Display unit 202...User I / F 203...Audio I / O 204...CPU 205...Network I / F 206...Flash memory 207...RAM 251,251A...Current memory 252...Setting memory 301...Indicator 302...User I / F 303...CPU 304...RAM 305...Network I / F 306...Flash memory 351,351A...Current memory 352...Setting memory 502, 502A...Player 503,503A…Manager 702...Signal processing device 902...FPGA

Claims

1. a first device including a first memory that stores parameters for sound signal processing and an operation unit that accepts operations on the parameters stored in the first memory; a second device including a second memory for holding parameters synchronized with the parameters of the first memory, and a first CPU for performing system control; a third device including a second CPU for processing sound signals; Equipped with the first CPU transmits to the third device first control information for controlling the sound signal processing based on the parameters stored in the second memory; the second CPU receives the first control information and performs the sound signal processing based on the first control information; 1. An audio processing system comprising: the sound processing system includes a fourth device including a third CPU for controlling the system; a fifth device including a fourth CPU for processing sound signals; a server including a fifth CPU that processes sound signals; Furthermore, the third CPU transmits second control information to the fifth device and third control information to the server; the fourth CPU receives the second control information and performs the sound signal processing based on the second control information; the fifth CPU receives the third control information and performs the sound signal processing based on the third control information; the first CPU of the second device transmits the first control information to the third device using a general-purpose protocol; the third CPU of the fourth device transmits the second control information and the third control information to the fifth device and the server, respectively, using a general-purpose protocol; the third CPU of the fourth device determines the sound signal processing indicated by the second control information and the third control information based on the processing capabilities of the fourth CPU and the fifth CPU, and causes the fifth device and the server to execute the sound signal processing, respectively; Sound processing system.

2. the first device includes a third memory that stores parameters different from the parameters stored in the first memory; the fourth device further comprises a fourth memory synchronized with the third memory; The sound processing system of claim 1 .

3. the second device and the third device are configured as virtually separate devices within the same physical device; The sound processing system according to claim 1 or 2.

4. The third CPU transmitting the second control information to the fifth device in a first protocol; transmitting the third control information to the server in a second protocol; The sound processing system according to any one of claims 1 to 3.

5. the first memory and the second memory further hold setting information for the system control. The sound processing system according to any one of claims 1 to 4.

6. The first device is parameters for sound signal processing are stored in a first memory; accepting an operation of the parameter stored in the first memory by an operation unit; The second device is storing parameters synchronized with the parameters in the first memory in a second memory; The first CPU controls the system, The third device is The second CPU processes the sound signal; the first CPU transmits to the third device first control information for controlling the sound signal processing based on the parameters stored in the second memory; the second CPU receives the first control information and performs the sound signal processing based on the first control information; 1. A method of acoustic processing, comprising: A fourth device: The third CPU controls the system. The fifth device is The fourth CPU processes the sound signal; The server The fifth CPU processes the sound signal; the third CPU transmits second control information to the fifth device and third control information to the server; the fourth CPU receives the second control information and performs the sound signal processing based on the second control information; the fifth CPU receives the third control information and performs the sound signal processing based on the third control information; the first CPU of the second device transmits the first control information to the third device using a general-purpose protocol; the third CPU of the fourth device transmits the second control information and the third control information to the fifth device and the server, respectively, using a general-purpose protocol; the third CPU of the fourth device determines the sound signal processing indicated by the second control information and the third control information based on the processing capabilities of the fourth CPU and the fifth CPU, and causes the fifth device and the server to execute the sound signal processing, respectively; Acoustic processing methods.

7. the first device stores, in a third memory, parameters different from the parameters stored in the first memory; The fourth device, synchronizing the third memory with the fourth memory; The acoustic processing method according to claim 6.

8. the second device and the third device are configured as virtually separate devices within the same physical device; The acoustic processing method according to claim 6 or 7.

9. The third CPU transmitting the second control information to the fifth device in a first protocol; transmitting the third control information to the server in a second protocol; The acoustic processing method according to any one of claims 6 to 8.

10. the first memory and the second memory further hold setting information for the system control. The acoustic processing method according to any one of claims 6 to 9.

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