Memory management unit, memory management method, and information processing device

Abstract

To suppress a memory management unit from increasing in a material quantity.SOLUTION: A memory management unit comprises: a first storage part where one or more first entries indicative of physical addresses matching a first bit range of virtual addresses are set; a second storage part where a second entry associating the first bit range and the one or more first entries is set; and a control part which converts virtual addresses into physical addresses on the basis of the first and second storage parts. The control part sets, when a second entry matching the first bit range of a first virtual address is hit by searching the second storage part, the number of a first entry specified with a first virtual address among the one or more first entries corresponding to the second entry to the second entry, and then acquires, when the same second entry is hit by making a search with a second virtual address and the number of a first entry specified with the second virtual address is larger than the number set to the second entry, information on one or more following first entries.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a memory management unit, a memory management method, and an information processing device. [Background technology]

[0002] Processes running on a computer's OS have independent virtual address spaces and use virtual addresses to access main memory. A computer processor includes an MMU (Memory Management Unit) that converts virtual addresses into physical addresses in main memory, and a processor core that executes processes and accesses main memory using the physical addresses converted by the MMU.

[0003] In addition, IO (Input / Output) devices that access main memory, such as network interfaces, are equipped with an IOMMU that converts the virtual address that is the destination of input packets into a physical address. The configuration and operation of the IOMMU are similar to that of a processor's MMU. Hereinafter, when there is no need to distinguish between the processor's MMU and the IO device's IOMMU, they will be collectively referred to simply as "MMU."

[0004] To quickly translate virtual addresses into physical addresses, the MMU has a memory area, such as a TLB (Translation Lookaside Buffer), that stores information indicating the correspondence between virtual addresses and physical addresses. The TLB stores physical addresses corresponding to virtual addresses based on a translation table obtained from the main memory.

[0005] If the MMU finds an entry in the TLB corresponding to the virtual address obtained from the translation requester, such as a process (TLB hit), it reads the physical address from the TLB and responds to the translation requester, thereby skipping the access to main memory.

[0006] On the other hand, if there is no entry corresponding to the virtual address in the TLB (TLB miss), the MMU obtains (fetches) information indicating the correspondence from the main memory, returns the correspondence to the processor core, and stores it in the TLB.

[0007] The TLB prefetching technique is also known as a method for suppressing the increase in translation processing time due to access to main memory in the event of a TLB miss. In the TLB prefetching technique, the MMU predicts the virtual address that the process will access next, fetches information indicating the correspondence between the virtual address and the predicted address from main memory in advance, and stores it in the TLB.

[0008] A known method for predicting the virtual address that a process will access is to use a Reference Prediction Table (RPT) that contains entries corresponding to the Program Counter (PC) of a store / load instruction.

[0009] In this method, each time a store / load instruction is executed by a process, the MMU saves the virtual address of the instruction's access target, the difference (stride) between the virtual address and the virtual address of the access target the previous time the same instruction was executed, etc. in the RPT.

[0010] When a TLB miss occurs, the MMU predicts that the virtual address to be accessed next is the virtual address obtained by adding the PC of the store / load instruction at that time and the stride in the entry corresponding to the virtual address to the virtual address. [Prior art documents] [Non-patent literature]

[0011] [Non-Patent Document 1] GB Kandiraju and A. Sivasubramaniam, “Going the distance for TLB prefetching: an application-driven study,” Proceedings 29th Annual International Symposium on Computer Architecture, 2002, pp. 195-206, doi: 10.1109 / ISCA.2002.1003578 [Non-patent document 2] T. Chen and J. Baer. Effective hardware based data prefetching for high-performance processors. IEEE Transactions on Computers, 44(5):609-623, May 1995 Summary of the Invention [Problem to be solved by the invention]

[0012] The RPT has several hundred (for example, 512) entries, and each entry has a PC and address bit width of several tens to several hundred bits in total.

[0013] Furthermore, when a processor executes multiple processes, the MMU uses information such as a process ID (Identifier) to identify the PC of a load / store instruction. In this case, the RPT has entries for the number of processes, and each entry is added with bits for information such as the process ID.

[0014] In this way, in order to suppress the increase in the conversion processing time by the memory management unit, the method of prefetching conversion table information requires providing tables such as RPT separately from the TLB, which increases the circuitry (material volume) of the memory management unit, which may result in an increase in the manufacturing cost and circuit size of the memory management unit, as well as an increase in power consumption.

[0015] In one aspect, an object of the present invention is to suppress an increase in the physical size of a memory management unit. [Means for solving the problem]

[0016] In one aspect, the memory management unit may include a first storage unit, a second storage unit, and a control unit. The first storage unit may be configured with one or more first entries indicating a physical address that matches a first bit range of a virtual address. The second storage unit may be configured with second entries that associate the first bit range of the virtual address with the one or more first entries. The control unit may perform a conversion process to convert the virtual address to the physical address based on the first storage unit and the second storage unit in response to a conversion request including the virtual address. Furthermore, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit in the first conversion process in response to the first conversion request including the first virtual address, the control unit may set, to the found second entry, an identification number of one of the one or more first entries corresponding to the found second entry, the identification number being identified based on the first virtual address. Furthermore, in a second conversion process in response to a second conversion request including a second virtual address, if a search of the second memory unit finds a second entry that is the same as that found in the first conversion process, and the identification number of one first entry identified based on the second virtual address is greater than the identification number set for the second entry, the control unit may obtain from memory information on one or more first entries that follow the one or more first entries associated with the found second entry. [Effects of the Invention]

[0017] In one aspect, the present invention can suppress an increase in the physical size of a memory management unit. [Brief explanation of the drawings]

[0018] [Figure 1]FIG. 10 is a diagram illustrating an example of address translation processing in an MMU (in the case of a TLB hit). [Figure 2] FIG. 2 is a diagram for explaining a TLB. [Figure 3] FIG. 10 is a diagram illustrating an example of address translation processing in an MMU (in the case of a TLB miss). [Figure 4] 4 is a diagram illustrating an example of processing after the conversion table illustrated in FIG. 3 is acquired. [Figure 5] FIG. 10 is a diagram illustrating an example of the relationship between tag entries and TLB entries. [Figure 6] FIG. 10 is a diagram illustrating an example of the configuration of a virtual address. [Figure 7] FIG. 10 is a diagram illustrating an example of address translation processing in an MMU having an RPT. [Figure 8] FIG. 10 is a diagram illustrating an example of address information of an RPT entry. [Figure 9] FIG. 1 is a block diagram illustrating an example of a hardware (HW) configuration focusing on address translation processing in a computer according to an embodiment. [Figure 10] FIG. 2 is a diagram illustrating an example of the hardware configuration of an MMU according to an embodiment. [Figure 11] FIG. 10 is a diagram showing an example of a tag entry. [Figure 12] FIG. 10 is a diagram showing an example of a state transition in a state field of a tag entry. [Figure 13] 10A and 10B are diagrams illustrating an example of an operation of an address conversion process performed by a control unit. [Figure 14] 10A and 10B are diagrams for explaining an example of the operation of address conversion processing by a control unit; [Figure 15] 10A and 10B are diagrams for explaining an example of the operation of address conversion processing by a control unit; [Figure 16] 10 is a flowchart illustrating an example of the operation of a TLB prefetch process by an MMU according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiments described below are merely examples, and are not intended to exclude various modifications or application of techniques not explicitly described below. For example, the present embodiment can be implemented with various modifications within the scope of the spirit thereof. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0020] [1] One embodiment [1-1] Explanation of address conversion process First, the address translation process will be described. Fig. 1 is a diagram showing an example of the address translation process (in the case of a TLB hit) in the MMU 100, and Fig. 2 is a diagram for explaining the TLB 130. Fig. 3 is a diagram showing an example of the address translation process (in the case of a TLB miss) in the MMU 100, and Fig. 4 is a diagram showing an example of the process after the translation table shown in Fig. 3 is acquired.

[0021] As illustrated in FIG. 1, the MMU 100 includes a control unit 110, a tag 120, and a TLB 130.

[0022] The control unit 110 acquires a conversion request and conversion information from a conversion request source such as a process. The conversion information includes a virtual address to be converted and an address space ID assigned to each conversion request source.

[0023] The tag 120 is a storage area that stores information linking translation information with the TLB 130, and translation information is set in each entry (tag entry) 121.

[0024] The number indicating the tag entry 121 (entry number; tag number) corresponds to the number indicating the entry (TLB entry) 131 of the TLB 130 (TLB number). For example, the tag number may match the TLB number.

[0025] The TLB 130 is a storage area that stores information indicating the correspondence between a virtual address space 140 and a physical address space 150 (see FIG. 2), and a physical address is set in each TLB entry 131. One TLB entry 131 corresponds to one page.

[0026] A "page" is the size of the smallest unit (constant unit) of translation processing between virtual addresses and physical addresses. For example, if the address bit width is 64 bits and the page size is 4 KB, a correspondence between the upper 52 bits of the virtual address and the physical address is set in one TLB entry 131. The lower 12 bits of the virtual address become the lower 12 bits of the physical address as they are.

[0027] The control unit 110 searches the tag 120 and determines whether or not there is an entry 121 that matches the translation information (for example, a virtual address and an address space ID) acquired from the translation request source. If there is an entry 121 in the tag 120 that matches the translation information (TLB hit), the control unit 110 reads the contents of the TLB entry 131 corresponding to the entry 121 from the TLB 130. In this way, the control unit 110 translates the virtual address into a physical address.

[0028] If the tag 120 does not contain an entry 121 that matches the translation information (TLB miss), the control unit 110 fetches a translation table indicating the correspondence between virtual addresses and physical addresses from the main memory (not shown), as illustrated in FIG. 3.

[0029] When the control unit 110 acquires the translation table from the main memory, it translates the virtual address into a physical address based on the information in the translation table and outputs the resulting physical address to the translation request source, as shown in Fig. 4. The control unit 110 also registers the translation information in a tag entry 121 and the physical address indicated by the translation table in a TLB entry 131.

[0030] As a result, when the same virtual address is to be translated in subsequent translation requests, control unit 110 can detect tag entry 121 that matches the virtual address (TLB hit), and can perform translation processing at high speed.

[0031] However, the first translation request that causes a TLB miss requires access to the main memory as described above (see FIG. 3), which may increase the translation processing time.

[0032] Incidentally, the tag entry 121 and the TLB entry 131 may be linked not only in a one-to-one relationship but also in a one-to-many relationship.

[0033] Fig. 5 is a diagram showing an example of the relationship between tag entries 121 and TLB entries 131. Fig. 5 shows an example in which one tag entry 121 is associated with four consecutive TLB entries 131 in the virtual address space. In the example of Fig. 5, the translation information of the tag 120 stores upper bits that are common to the virtual addresses of four pages.

[0034] Fig. 6 is a diagram showing an example of the configuration of a virtual address. As shown in Fig. 6, the virtual address includes upper bits 141 for tag search, lower bits 142 indicating a tag entry number, and an area for an in-page address 143. The upper bits 141 are a range of a predetermined number of upper bits of the virtual address, and are an example of a first bit range. The lower bits 142 are a range of a predetermined number of bits following the first bit range in the virtual address, and are an example of a second bit range.

[0035] For example, if the page size is 4 KB and one (one page) tag entry 121 corresponds to four (four pages) TLB entries 131, the lower bits 142 are 2 bits wide and the intra-page address 143 is 12 bits wide.

[0036] When searching tag 120 based on the virtual address included in the translation request, the MMU searches for tag entry 121 having translation information that matches upper bits 141 of the virtual address. If a matching tag entry 121 exists, the MMU uses lower bits 142 to identify TLB entry 131 for one of the four pages associated with that tag entry 121.

[0037] FIG. 7 is a diagram showing an example of address translation processing in the MMU 200 having the RPT 240, and FIG. 8 is a diagram showing an example of address information of the RPT entry 241.

[0038] As shown in FIG. 7, the MMU 200 includes an RPT 240 in addition to a control unit 210, a tag 220, and a TLB 230, and uses the RPT 240 to predict the virtual address that the translation requester will access next, thereby executing TLB prefetch.

[0039] The RPT 240 is a storage area that stores information about the access destination of a translation request source, and address information is set in each entry (RPT entry) 241. The control unit 210 executes the update process of the RPT 240 and the address translation process in parallel.

[0040] As shown in FIG. 8, the address information of the RPT entry 241 may illustratively include the items of "PC (Program Counter)," "Target Address," "Stride," and "Status." The "PC" is an example of identification information for a store / load instruction, and may be, for example, information indicating the address in main memory where the store instruction or load instruction to be executed is stored. The "Target Address" is the virtual address of the target of access in main memory by the store / load instruction. The "Stride" is the difference between the "Target Address" and the target address that was accessed the previous time the same store / load instruction was executed. The "Status" indicates the status of the entry, such as "New Registration," "New Difference Registration," or "Difference Match."

[0041] 7, when receiving a conversion request, the control unit 210 acquires the PC of the load / store instruction that is the source of the conversion request along with the conversion information, and updates the entry 241 of the RPT 240 using the acquired PC and the virtual address included in the conversion information. For example, if a load instruction with a PC of "500" is executed three times and the virtual addresses for the first to third executions are "1000", "1004", and "1008", respectively, the control unit 210 updates the following entry 241.

[0042] (1st time) PC: 500, target address: 1000, stride: -, status: new registration (2nd time) PC: 500, target address: 1004, stride: 4, status: new difference registration (3rd time) PC: 500, target address: 1008, stride: 4, status: difference match

[0043] The first state, "New Registration," means the first registration of an entry for PC "500," and the second state, "New Difference Registration," means the first registration of stride "4" (= "1004" - "1000") for PC "500." The third state, "Difference Match," means that the stride "4" (= "1008" - "1004") for PC "500" matches the stride from the previous time (second time).

[0044] When a TLB miss occurs in the translation process for a store / load instruction that matches a PC registered in the RPT 240, the control unit 210 specifies a virtual address obtained by adding the stride of the RPT entry 241 corresponding to the PC to the virtual address related to the translation request. Then, the control unit 210 prefetches information from the TLB 230 that corresponds to the specified virtual address, i.e., the virtual address that is most likely to be accessed next.

[0045] For example, when a load instruction accesses target address “1012”, the control unit 210 prefetches the translation table corresponding to target address “1016” (=“1012”+“4”) from the main memory and registers it in the TLB 230.

[0046] Prefetching using the RPT 240 utilizes the following properties related to addresses in the main memory. When a process performs repetitive processing such as a loop, if the PC of the load / store instruction is the same, each repetition is likely to follow the same access pattern as the previous one. One type of memory access pattern is called stride access. Stride access is an access in which the virtual address increases by a constant K (K is an integer), such as "A" → "A+K" → "A+2K" ... In the above example, A=1000, K=4.

[0047] However, as described above, in the prefetch method using the RPT 240, the MMU 200 is provided with the RPT 240 in addition to the TLB 230, which may increase the amount of circuitry (materials).

[0048] Therefore, in one embodiment, a method for realizing TLB prefetching corresponding to the access pattern of stride access while suppressing an increase in the amount of hardware will be described. For example, in one embodiment, an MMU stores information on memory access patterns in a tag that associates and manages virtual addresses with TLBs, and performs TLB prefetching based on the information, thereby reducing the frequency of TLB misses and suppressing an increase in translation processing time.

[0049] [1-2] Example of a hardware configuration of a computer according to an embodiment FIG. 9 is a block diagram showing an example of a hardware (HW) configuration focusing on address translation processing in a computer 1 according to an embodiment.

[0050] As shown in FIG. 9, the computer 1 may include, for example, a processor 2, a main memory 3, and an IO device 4 as a HW configuration focused on address translation processing.

[0051] In addition to the configuration shown in FIG. 9, the computer 1 may also include various devices such as a storage device such as an HDD (Hard Disk drive) or an SSD (Solid State Drive), an input device such as a mouse and keyboard, and a display device such as a monitor.

[0052] The processor 2 is an example of a processing unit that performs various controls and calculations. The processor 2 may be connected to each block in the computer 1 via a bus 1a so that they can communicate with each other. The processor 2 may be a multiprocessor including multiple processors, a multi-core processor having multiple processor cores, or a configuration having multiple multi-core processors.

[0053] Examples of the processor 2 include integrated circuits (ICs) such as a CPU, MPU, GPU, APU, DSP, ASIC, and FPGA. Note that a combination of two or more of these integrated circuits may be used as the processor 2. CPU is an abbreviation for Central Processing Unit, MPU is an abbreviation for Micro Processing Unit, GPU is an abbreviation for Graphics Processing Unit, and APU is an abbreviation for Accelerated Processing Unit. DSP is an abbreviation for Digital Signal Processor, ASIC is an abbreviation for Application Specific IC, and FPGA is an abbreviation for Field-Programmable Gate Array.

[0054] 9, the processor 2 may include a processor core 21 and a processor MMU 22. The processor 2 may include a plurality of processor cores 21.

[0055] The processor core 21 executes an OS program expanded in the main memory 3 and executes one or more processes on the OS. A process has an independent virtual address space and uses a virtual address to specify a storage destination (address) on the main memory 3. The processor core 21 notifies the processor MMU 22 of a conversion request to convert the virtual address into a physical address on the main memory 3, and accesses the main memory 3 using the physical address that is the result of the conversion by the processor MMU 22.

[0056] The processor MMU 22 is an example of a memory management unit or a memory management device, and executes address translation processing in response to a translation request from the processor core 21, and returns the translation result to the processor core 21.

[0057] The main memory 3 is an example of HW that stores various types of data, programs, and other information. The main memory 3 may be, for example, one or both of a volatile memory such as a DRAM (Dynamic Random Access Memory) and a non-volatile memory such as a PM (Persistent Memory).

[0058] The IO device 4 is an example of a network IF (Interface) or communication IF device that communicates with the processor 2 and the main memory 3, and may be capable of accessing the main memory 3, for example, via DMA (Direct Memory Access).

[0059] For example, the IO device 4 may be a NIC (Network Interface Card) having an adapter that complies with a LAN (Local Area Network) such as Ethernet (registered trademark) or optical communication such as FC (Fibre Channel).

[0060] As shown in FIG. 9, the IO device 4 may include an IO controller 41 and an IOMMU 42.

[0061] The IO controller 41 executes various controls in the IO device 4, including access to the main memory 3. For example, the IO controller 41 may access the main memory 3 based on a packet received from a device (a device external to the computer 1) connected via an adapter and a network.

[0062] The packet may use a virtual address to specify the access destination (address) on the main memory 3. The IO controller 41 notifies the IOMMU 42 of a conversion request to convert the virtual address included in the packet into a physical address of the main memory 3, and accesses the main memory 3 using the physical address that is the conversion result by the IOMMU 42.

[0063] The IOMMU 42 is an example of a memory management unit or memory management device, and executes address translation processing in response to a translation request from the IO controller 41, and returns the translation result to the IO controller 41.

[0064] The processor MMU 22 and the IOMMU 42 have the same configuration and operation. Hereinafter, when there is no need to distinguish between the processor MMU 22 and the IOMMU 42, they will be referred to as "MMU 5."

[0065] [1-3] Description of MMU according to one embodiment Fig. 10 is a diagram illustrating an example of the hardware configuration of an MMU 5 according to an embodiment. As illustrated in Fig. 10, the MMU 5 may illustratively include a control unit 51, a tag 52, and a TLB 53. Unless otherwise specified, each component and piece of information illustrated in Fig. 10 is the same as the component or piece of information having the same name illustrated in Fig. 1, Fig. 3, Fig. 4, or Fig. 7.

[0066] In response to a translation request including a virtual address, the control unit 51 executes a translation process to translate the virtual address into a physical address based on the tag 52 and the TLB 53. For example, the control unit 51 acquires the translation request and translation information from a translation request source, and executes the translation process including a TLB prefetch process. The translation request source may be, for example, a process executed by the processor core 21 or a packet processed by the IO controller 41.

[0067] The tag 52 is a storage area that stores information linking translation information with the TLB 53, and translation information is set in each entry (tag entry) 521. The tag 52 is an example of a second storage unit in which the tag entry 521 is set. The tag entry 521 is an example of a second entry that associates a first bit range of a virtual address with one or more TLB entries 531.

[0068] The tag entries 521 of the tag 52 and the TLB entries 531 may be associated one-to-one, or one-to-many, as illustrated in FIGS.

[0069] The translation information may include a virtual address to be translated and an address space ID assigned to each translation request source (e.g., each process, etc.). The address space ID is an example of identification information of an address space assigned to the issuer of the translation request.

[0070] The TLB 53 is a storage area that stores information indicating the correspondence between a virtual address space and a physical address space (see FIG. 2), and a physical address is set in each entry (TLB entry) 531. The TLB 53 is an example of a first storage unit in which one or more TLB entries 531 are set. The TLB entry 531 is an example of a first entry that indicates a physical address that matches a first bit range of a virtual address.

[0071] Here, the MMU 5 according to one embodiment stores information used to determine whether to perform TLB prefetch in the tag 52. This allows the MMU 5 (computer 1) to omit the RPT, thereby suppressing an increase in the amount of HW circuitry.

[0072] Fig. 11 is a diagram showing an example of a tag entry 521, and Fig. 12 is a diagram showing an example of a state transition of the state field of the tag entry 521. As shown in Fig. 11, the tag entry 521 may include, for example, items such as a flag 521a indicating whether the entry is "valid" or "invalid," translation information 521b, a previously hit TLB number 521c, and a state 521d.

[0073] The flag 521a is an example of information indicating whether the tag entry 521 is valid or invalid. For example, when the flag 521a is "1," it may indicate that the tag entry 521 is valid (or invalid), and when the flag 521a is "0," it may indicate that the tag entry 521 is invalid (or valid).

[0074] The translation information 521b may include a virtual address to be translated and an address space ID assigned to each translation request source (e.g., each process, etc.). In this way, since the tag entry 521 includes the translation information 521b including the address space ID, it can be said that the control unit 51 sets the tag entry 521 of the tag 52 for each address space ID.

[0075] The TLB number 521c indicates the number of the TLB 53 that was previously hit. For example, the TLB number 521c may be the TLB number corresponding to the tag entry 521 that was hit in a search for the tag 52 using the translation information included in the translation request. The number indicating the tag entry 521 (entry number; tag number) may correspond to the number indicating the TLB entry 531 (TLB number). For example, the tag number may match the TLB number.

[0076] When one tag number corresponds to multiple TLB numbers, the tag number may indicate a range of multiple TLB entries 531. When the tag number indicates a range of multiple TLB entries 531, the TLB number may be an index of a TLB entry 531 within that range, and may be, for example, a value indicated by the lower bits 142 of the virtual address (see FIG. 6). In other words, the TLB number 521c is an example of an identification number of one TLB entry 531 identified based on the virtual address from among one or more TLB entries 531 corresponding to the hit tag entry 521.

[0077] The state 521d indicates the state of the tag entry 521. For example, the state 521d may have the states "new", "prefetch not performed", and "prefetch performed", as shown in FIG. 12. "new" is the initial state when the tag entry 521 is newly registered. "prefetch not performed" indicates a state in which a TLB prefetch based on the tag entry 521 has not been performed. "prefetch performed" indicates a state in which a TLB prefetch based on the tag entry 521 has been performed.

[0078] In the TLB prefetch process, the control unit 51 sets the hit TLB number to the previously hit TLB number 521c of the tag entry 521. Then, if the currently hit TLB number in the conversion process is increased by "1" or more from the previously hit TLB number 521c in the tag entry 521, the control unit 51 prefetches information of the next TLB 53.

[0079] As an example, when the tag entries 521 and the TLB entries 531 correspond to one another in a one-to-n relationship (n is an integer equal to or greater than 2), the control unit 51 may prefetch the number of TLB entries 531 corresponding to the value of n.

[0080] In addition, even if the TLB number hit this time is not consecutive to the TLB number 521c hit last time in the tag entry 521, the control unit 51 may prefetch information of the next TLB 53 as long as the value of the TLB number is increased from the previous one.

[0081] For example, if a stride access occurs, the next translation request is likely to request translation of a virtual address corresponding to a TLB number greater than the TLB number hit this time. Also, as mentioned above, in a stride access, there is a possibility that the addresses to be accessed are not consecutive (accesses are made at intervals of a predetermined size).

[0082] Therefore, the control unit 51 sets the condition that the currently hit TLB number is greater than the previously hit TLB number 521c as one of the conditions for detecting the occurrence of a stride access. When the control unit 51 detects the occurrence of a stride access, it prefetches, for example, the next n TLB entries 531. This allows the control unit 51 to suppress an increase in the translation processing time by the MMU 5 with a configuration simpler than that of the RPT.

[0083] Next, an example of address conversion processing by the control unit 51 will be described with reference to Fig. 13 to Fig. 15. Fig. 13 to Fig. 15 are diagrams for explaining an example of the operation of address conversion processing by the control unit 51. Note that in the description of Fig. 13 to Fig. 15, a case where tag entries 521 and TLB entries 531 correspond to each other in a one-to-four (n=4) ratio will be taken as an example.

[0084] The control unit 51 acquires a translation request including a virtual address and translation information from a translation request source, and searches the tag 52 based on the virtual address and translation information. For example, the control unit 51 determines whether or not a tag entry 521 that matches the upper bits of the virtual address and the address space ID exists in the tag 52 (whether or not there is a TLB hit).

[0085] 13, when a TLB miss occurs in the conversion process in response to the conversion request (see arrow A1), the control unit 51 fetches the conversion table from the main memory 3 (see arrow A2). The control unit 51 responds to the source of the conversion request with a physical address based on the conversion table (for example, physical address A) (see arrow A3).

[0086] Furthermore, the control unit 51 registers a tag entry 521 and a TLB entry 531 in the tag 52 and the TLB 53, respectively, based on the translation table (see arrows A4 and A5). Note that the process indicated by the arrow A3 and the processes indicated by the arrows A4 and A5 may be executed first, or at least part of them may be executed in parallel.

[0087] In the example of FIG. 13, as the tag entry 521 to be registered, the translation information 521b stores the upper bits common to the virtual addresses of the four pages. The virtual addresses of the four pages correspond to the physical addresses A to D, respectively. No value is set in the TLB number 521c because this is a new registration. The status 521d is set to "new." In this way, in the example of FIG. 13, the control unit 51 registers the tag entry 521 corresponding to the physical addresses A to D of the TLB entry 531.

[0088] Next, referring to Fig. 14, an example of translation processing when a TLB hit occurs in translation processing in response to a translation request subsequent to Fig. 13 will be described. The translation processing shown in Fig. 14 is an example of first translation processing in response to a first translation request including a first virtual address. Fig. 14 describes processing when a tag entry 521 that matches the upper bits 141 (see Fig. 6) (and the address space ID) of the first virtual address is hit by searching the tag 52 in the translation processing.

[0089] 14, when a TLB hit occurs in the translation process in response to the translation request subsequent to FIG. 13 (see arrow B1), the control unit 51 refers to the TLB entry 531 indicated by the translation information 521b (see arrow B2). The control unit 51 responds to the translation request source with the physical address of the entry content (e.g., physical address B) (see arrow B3) acquired from the TLB entry 531 (see arrow B4).

[0090] Furthermore, control unit 51 updates tag entry 521 (see arrow B5). For example, control unit 51 updates state 521d of tag entry 521 to "prefetch not performed" (indicated as "not performed" in FIG. 14), and sets TLB number "1" indicating TLB entry 531 acquired at arrow B3 to TLB number 521c. Note that either the process indicated by arrow B4 or the process indicated by arrow B5 may be executed first, or at least a part of the processes may be executed in parallel.

[0091] In this way, the control unit 51 sets the identification number of one TLB entry 531 identified based on the first virtual address from among one or more TLB entries 531 corresponding to the hit tag entry 521 to the hit tag entry 521.

[0092] Next, referring to Fig. 15, an example of translation processing when a TLB hit occurs in translation processing in response to a translation request subsequent to Fig. 14 will be described. The translation processing shown in Fig. 15 is an example of second translation processing in response to a second translation request including a second virtual address. Fig. 15 describes processing when a tag entry 521 that matches the upper bits 141 (see Fig. 6) (and address space ID) of the second virtual address and is the same as the tag entry 521 used in the translation processing of Fig. 14 is hit by searching the tag 52.

[0093] 15, when a TLB hit occurs in the translation process in response to the translation request subsequent to FIG. 14 (see arrow C1), the control unit 51 refers to the TLB entry 531 indicated by the translation information 521b (see arrow C2). The control unit 51 responds to the translation request source with the physical address of the entry content (e.g., physical address D) (see arrow C3) acquired from the TLB entry 531 (see arrow C4).

[0094] Furthermore, if the state of tag entry 521 at the time of a TLB hit satisfies a prefetching condition, control unit 51 performs a prefetch. The prefetching condition may be, for example, that both of the following (i) and (ii) are satisfied: (i) The status 521d of the tag entry 521 indicates "prefetch not performed." (ii) The TLB number indicating the TLB entry 531 obtained by arrow C3 is larger than the previously hit TLB number 521c of the tag entry 521; in other words, the TLB entry number hit by the TLB has increased.

[0095] If the state of the tag entry 521 satisfies the prefetch execution condition, the control unit 51 prefetches (see arrow C5) information of the next TLB 53. The information of the next TLB 53 may be, for example, a TLB entry 531 following the TLB entry 531 that has been hit this time, and may be one or more (for example, n) consecutive TLB entries 531 that have not yet been acquired.

[0096] For example, the control unit 51 may calculate a virtual address corresponding to the next information of the TLB 53 based on the following formula (1), and prefetch a translation table corresponding to the calculated virtual address from the main memory 3. [Virtual address to be prefetched] = [Virtual address to be translated] + [page size] x [number of TLB entries corresponding to tags] (1)

[0097] As an example, assume that the page size is 4 KB, the number of TLB entries (n) corresponding to tag 52 is 4, a TLB hit occurs in the translation process of the virtual address of 0x1_0000, and prefetching is performed. In this case, control unit 51 may prefetch a translation table indicating n TLB entries 531 corresponding to the virtual address of 0x1_0000 + 0x10000 x 4 = 0x1_4000.

[0098] In the example of FIG. 15, the control unit 51 may prefetch the TLB entries 531 corresponding to the four physical addresses E to H following the physical address D.

[0099] When performing prefetching, control unit 51 updates state 521d of tag entry 521 that has been hit in the TLB to "prefetched" (denoted as "prefetched" in FIG. 15).

[0100] In this way, the control unit 51 may perform prefetching when the TLB number of one TLB entry 531 identified based on the second virtual address is larger than the TLB number 521c set in the tag entry 521. For example, the control unit 51 may obtain, from the main memory 3, information on one or more TLB entries 531 that follow the one or more TLB entries 531 associated with the hit tag entry 521.

[0101] When the control unit 51 performs a prefetch, it updates the tag 52 and the TLB 53 based on the translation table in the same way as when a fetch is performed when a TLB miss occurs (see arrows C6 and C7).

[0102] For example, as shown in FIG. 15 , the control unit 51 registers a tag entry 521 whose translation information 521b includes upper bits that are common to the virtual addresses of four pages corresponding to physical addresses E to H. No value is set in the TLB number 521c of the tag entry 521, and "new" is set in the status 521d. The tag entry 521 is associated with four TLB entries 531 to be added to the TLB 53. The control unit 51 also registers the four TLB entries 531 corresponding to the physical addresses E to H in the TLB 53. Note that the process indicated by the arrow C4 and the processes indicated by the arrows C5 to C7 may be executed first, or at least some of them may be executed in parallel.

[0103] Note that the control unit 51 may suppress the execution of prefetching if the TLB number indicating the TLB entry 531 acquired along the arrow C3 is equal to or less than the previously hit TLB number 521c of the tag entry 521. In this case, the control unit 51 may set (update) the TLB number indicating the TLB entry 531 acquired along the arrow C3 to the previously hit TLB number 521c of the tag entry 521.

[0104] As described above, according to the MMU 5 of one embodiment, by storing information used to determine whether to perform TLB prefetch in the tag 52, it is possible to realize prefetching that supports stride access while omitting hardware such as the RPT.

[0105] Furthermore, the TLB number 521c and the state 521d added to the tag 52 according to an embodiment have a data size of about several bits. Therefore, according to the technique according to an embodiment, it is possible to suppress an increase in the amount of hardware compared to adding an RPT, which has a data size of about several tens to several hundred bits per entry.

[0106] Furthermore, the tag 52 according to an embodiment includes, as the conversion information 521b, an ID (address space ID) that identifies a process that is an example of a conversion request source. This allows the MMU 5 to perform an appropriate conversion process for each address space ID, even when the MMU 5 receives conversion requests for different address spaces from multiple conversion request sources, such as multiple processes or multiple packets transmitted from multiple sources.

[0107] [1-4] Example of operation Next, an example of the operation of the computer 1 (MMU 5) according to the embodiment will be described. Fig. 16 is a flowchart for explaining an example of the operation of the TLB prefetch process by the MMU 5 according to the embodiment.

[0108] 16 focuses on the TLB prefetch process of the address translation process in the MMU 5, and shows an example of the process of updating the tag 52 and the TLB 53 depending on whether there is a TLB hit, and the process of determining whether prefetching is possible. The MMU 5 is not limited to the TLB prefetch process exemplified in Fig. 16, and may execute various other processes in the MMU 5, such as the process of outputting the address translation result in response to a translation request (see Figs. 13 to 15).

[0109] As illustrated in FIG. 16, the control unit 51 determines whether a TLB hit occurs in a search for the tag 52 using the translation information included in the acquired translation request (step S1).

[0110] If a TLB hit does not occur, in other words, if a TLB miss occurs (NO in step S1), the control unit 51 fetches information about the TLB 53 that has been missed from the main memory 3 (step S2). The control unit 51 registers an entry in the tag 52 and the TLB 53 based on the translation table fetched (acquired) from the main memory 3 (step S3), and the TLB prefetch process ends. For example, in step S3, the control unit 51 registers the tag entry 521 whose status 521d is "new" in the tag 52 based on the translation table, and registers one or more (n) TLB entries 531 corresponding to the tag entry 521 in the TLB 53.

[0111] If a TLB hit occurs (YES in step S1), the control unit 51 determines whether the state 521d of the hit tag entry 521 is "prefetch not yet performed" (step S4).

[0112] If the state 521d is not "prefetched yet" (NO in step S4), the control unit 51 determines whether the state 521d is "new" (step S5). If the state 521d is not "new", in other words, if the prefetch is "performed" (NO in step S5), the TLB prefetch process ends.

[0113] If the status 521d is "new" (YES in step S5), the current TLB hit is the first TLB hit since the tag entry 521 was registered. In this case, the control unit 51 updates the status 521d to "prefetch not yet performed" (step S6), updates the previously hit TLB number 521c of the tag entry 521 to the currently hit TLB number (step S7), and the TLB prefetch process ends.

[0114] In step S4, if the state 521d is "not yet prefetched" (YES in step S4), the control unit 51 determines whether the currently hit TLB number is greater than the previously hit TLB number 521c of the tag entry 521 (step S8).

[0115] If the currently hit TLB number is equal to or less than the previously hit TLB number 521c of tag entry 521 (NO in step S8), the process proceeds to step S7.

[0116] If the currently hit TLB number is larger than the previously hit TLB number 521c of the tag entry 521 (YES in step S8), the control unit 51 prefetches information of the next TLB 53 from the main memory 3. The control unit 51 also updates the status 521d of the tag entry 521 to "prefetch completed" (step S9), and the TLB prefetch process ends. After acquiring the translation table by prefetching, the control unit 51 registers the tag entry 521 and the TLB entry 531 in the tag 52 and the TLB 53, respectively, based on the translation table, as in step S3.

[0117] [2] Other The technology according to the embodiment described above can be implemented with the following modifications and variations.

[0118] For example, in one embodiment, n="4" is used, and one tag entry 521 corresponds to four TLB entries 531, but this is not limited to this, and n may be a value other than "4".

[0119] [3] Supplementary Note The following additional notes are provided regarding the above-described embodiments.

[0120] (Appendix 1) a first storage unit in which one or more first entries indicating physical addresses that match a first bit range of the virtual address are set; a second storage unit in which a second entry is set that associates the first bit range of the virtual address with the one or more first entries; a control unit that executes a conversion process of converting the virtual address into the physical address based on the first storage unit and the second storage unit in response to a conversion request including the virtual address; The control unit In a first translation process in response to a first translation request including a first virtual address, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit, an identification number of one first entry identified based on the first virtual address among one or more first entries corresponding to the found second entry is set to the found second entry; In a second conversion process in response to a second conversion request including a second virtual address, if the same second entry as in the first conversion process is hit by searching the second storage unit and the identification number of one first entry specified based on the second virtual address is larger than the identification number set in the second entry, information on one or more first entries subsequent to the one or more first entries associated with the hit second entry is obtained from memory. Memory management unit.

[0121] (Appendix 2) the control unit, based on the information acquired from the memory, sets one or more first entries subsequent to one or more first entries associated with the hit second entry in the first storage unit, and sets second entries associated with the set one or more first entries in the second storage unit. 2. The memory management unit according to claim 1.

[0122] (Appendix 3) When the second conversion process finds the same second entry as in the first conversion process by searching the second storage unit, and the identification number of the one first entry identified based on the second virtual address is equal to or less than the identification number set in the second entry, the control unit sets the identification number of the one first entry identified based on the second virtual address in the second entry. 3. The memory management unit of claim 1 or 2.

[0123] (Appendix 4) the translation request includes the virtual address and identification information of an address space assigned to an issuer of the translation request; The control unit setting the second entry in the second storage unit for each of the identification information; In the conversion process, the second storage unit is searched based on the identification information included in the conversion request and the virtual address. The memory management unit according to any one of Supplementary notes 1 to 3.

[0124] (Appendix 5) the first bit range is a range of a predetermined number of upper bits of the virtual address, the identification number is a value indicated by a predetermined number of bit ranges following the first bit range in the virtual address; The memory management unit according to any one of Supplementary notes 1 to 4.

[0125] (Appendix 6) The control unit of the memory management unit In response to a conversion request including a virtual address, a conversion process is performed to convert the virtual address into the physical address based on a first storage unit in which one or more first entries indicating a physical address that matches a first bit range of the virtual address are set and a second storage unit in which second entries that associate the first bit range of the virtual address with the one or more first entries are set; In a first translation process in response to a first translation request including a first virtual address, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit, an identification number of one first entry identified based on the first virtual address among one or more first entries corresponding to the found second entry is set to the found second entry; In a second conversion process in response to a second conversion request including a second virtual address, if the same second entry as in the first conversion process is hit by searching the second storage unit and the identification number of one first entry specified based on the second virtual address is larger than the identification number set in the second entry, information on one or more first entries subsequent to the one or more first entries associated with the hit second entry is obtained from memory. A memory management method for performing processing.

[0126] (Appendix 7) the control unit, based on the information acquired from the memory, sets one or more first entries subsequent to one or more first entries associated with the hit second entry in the first storage unit, and sets second entries associated with the set one or more first entries in the second storage unit. 7. The memory management method of claim 6, wherein the memory management method performs processing.

[0127] (Appendix 8) when the control unit finds the same second entry as in the first conversion process by searching the second storage unit in the second conversion process and the identification number of the one first entry identified based on the second virtual address is equal to or less than the identification number set in the second entry, the control unit sets the identification number of the one first entry identified based on the second virtual address in the second entry. 8. The memory management method according to claim 6 or 7, wherein the memory management method executes processing.

[0128] (Appendix 9) the translation request includes the virtual address and identification information of an address space assigned to an issuer of the translation request; The control unit setting the second entry in the second storage unit for each of the identification information; In the conversion process, the second storage unit is searched based on the identification information included in the conversion request and the virtual address. The memory management method according to any one of Supplementary notes 6 to 8, wherein processing is executed.

[0129] (Appendix 10) the first bit range is a range of a predetermined number of upper bits of the virtual address, the identification number is a value indicated by a predetermined number of bit ranges following the first bit range in the virtual address; The memory management method according to any one of Supplementary notes 6 to 9.

[0130] (Appendix 11) Memory and a memory management unit that converts a virtual address into a physical address on the memory; The memory management unit a first storage unit in which one or more first entries indicating physical addresses that match a first bit range of the virtual address are set; a second storage unit in which a second entry is set that associates the first bit range of the virtual address with the one or more first entries; a control unit that executes a conversion process of converting the virtual address into the physical address based on the first storage unit and the second storage unit in response to a conversion request including the virtual address; The control unit In a first translation process in response to a first translation request including a first virtual address, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit, an identification number of one first entry identified based on the first virtual address among one or more first entries corresponding to the found second entry is set to the found second entry; In a second conversion process in response to a second conversion request including a second virtual address, if the same second entry as in the first conversion process is hit by searching the second storage unit and the identification number of one first entry specified based on the second virtual address is larger than the identification number set in the second entry, information on one or more first entries subsequent to the one or more first entries associated with the hit second entry is obtained from the memory. Information processing device.

[0131] (Appendix 12) the control unit, based on the information acquired from the memory, sets one or more first entries subsequent to one or more first entries associated with the hit second entry in the first storage unit, and sets second entries associated with the set one or more first entries in the second storage unit. 12. The information processing device according to claim 11.

[0132] (Appendix 13) When the second conversion process finds the same second entry as in the first conversion process by searching the second storage unit, and the identification number of the one first entry identified based on the second virtual address is equal to or less than the identification number set in the second entry, the control unit sets the identification number of the one first entry identified based on the second virtual address in the second entry. 13. The information processing device according to claim 11 or 12.

[0133] (Appendix 14) the translation request includes the virtual address and identification information of an address space assigned to an issuer of the translation request; The control unit setting the second entry in the second storage unit for each of the identification information; In the conversion process, the second storage unit is searched based on the identification information included in the conversion request and the virtual address. An information processing device according to any one of Supplementary notes 11 to 13.

[0134] (Appendix 15) the first bit range is a range of a predetermined number of upper bits of the virtual address, the identification number is a value indicated by a predetermined number of bit ranges following the first bit range in the virtual address; An information processing device according to any one of Supplementary Note 11 to Supplementary Note 14.

[0135] (Appendix 16) a processor that accesses the memory; The memory management unit is provided in the processor. An information processing device according to any one of Supplementary notes 11 to 15.

[0136] (Appendix 17) an IO (Input / Output) device that accesses the memory; The memory management unit is provided in the IO device. An information processing device according to any one of Supplementary notes 11 to 16. [Explanation of symbols]

[0137] 1. Computer 2 processors 21 processor cores 22 Processor MMU 3. Main memory 4 IO device 41 IO Controller 42 IOMMU 5 MMU 51 Control section 52 Tags 521 tag entries 521a Enable / Disable Flag 521b Conversion Information 521c Last hit TLB number 521d Status 53 TLB 531 TLB entries

Claims

1. a first storage unit in which one or more first entries indicating physical addresses that match a first bit range of the virtual address are set; a second storage unit in which a second entry is set that associates the first bit range of the virtual address with the one or more first entries; a control unit that executes a conversion process of converting the virtual address into the physical address based on the first storage unit and the second storage unit in response to a conversion request including the virtual address, The control unit In a first translation process in response to a first translation request including a first virtual address, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit, an identification number of one first entry identified based on the first virtual address among one or more first entries corresponding to the found second entry is set to the found second entry; In a second translation process in response to a second translation request including a second virtual address, if the same second entry as in the first translation process is hit by searching the second storage unit and the identification number of one first entry specified based on the second virtual address is larger than the identification number set in the second entry, information on one or more first entries subsequent to the one or more first entries associated with the hit second entry is obtained from memory. Memory management unit.

2. the control unit sets, in the first storage unit, one or more first entries subsequent to the one or more first entries associated with the hit second entry, based on the information acquired from the memory, and sets, in the second storage unit, second entries associated with the one or more set first entries.

2. The memory management unit of claim 1.

3. When the same second entry as that used in the first conversion process is found by searching the second storage unit in the second conversion process and the identification number of the one first entry specified based on the second virtual address is equal to or less than the identification number set in the second entry, the control unit sets the identification number of the one first entry specified based on the second virtual address in the second entry.

3. A memory management unit according to claim 1 or claim 2.

4. the translation request includes the virtual address and identification information of an address space assigned to an issuer of the translation request; The control unit setting the second entry in the second storage unit for each of the pieces of identification information; In the conversion process, the second storage unit is searched based on the identification information included in the conversion request and the virtual address. The memory management unit according to any one of claims 1 to 3.

5. the first bit range is a range of a predetermined number of upper bits of the virtual address, the identification number is a value indicated by a predetermined number of bit ranges following the first bit range in the virtual address; The memory management unit according to any one of claims 1 to 4.

6. The control unit of the memory management unit In response to a conversion request including a virtual address, a conversion process is performed to convert the virtual address into the physical address based on a first storage unit in which one or more first entries indicating a physical address that matches a first bit range of the virtual address are set, and a second storage unit in which second entries that associate the first bit range of the virtual address with the one or more first entries are set; In a first translation process in response to a first translation request including a first virtual address, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit, an identification number of one first entry identified based on the first virtual address among one or more first entries corresponding to the found second entry is set to the found second entry; In a second translation process in response to a second translation request including a second virtual address, if the same second entry as in the first translation process is hit by searching the second storage unit and the identification number of one first entry specified based on the second virtual address is larger than the identification number set in the second entry, information on one or more first entries subsequent to the one or more first entries associated with the hit second entry is obtained from memory. A memory management method for performing processing.

7. Memory and a memory management unit that converts a virtual address into a physical address on the memory; The memory management unit a first storage unit in which one or more first entries indicating physical addresses that match a first bit range of the virtual address are set; a second storage unit in which a second entry is set that associates the first bit range of the virtual address with the one or more first entries; a control unit that executes a conversion process of converting the virtual address into the physical address based on the first storage unit and the second storage unit in response to a conversion request including the virtual address, The control unit In a first translation process in response to a first translation request including a first virtual address, when a second entry that matches the first bit range of the first virtual address is found by searching the second storage unit, an identification number of one first entry identified based on the first virtual address among one or more first entries corresponding to the found second entry is set to the found second entry; In a second translation process in response to a second translation request including a second virtual address, if the same second entry as in the first translation process is hit by searching the second storage unit and the identification number of one first entry specified based on the second virtual address is larger than the identification number set in the second entry, information on one or more first entries subsequent to the one or more first entries associated with the hit second entry is obtained from the memory. Information processing device.

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