Information processing device and control method

Abstract

To efficiently manage a page table cache.SOLUTION: An information processing device includes: a conversion buffer which stores a conversion pair of a virtual address and a physical address of a page; and a page table cache 203 which stores data in page tables at levels other than the last level and physical addresses of the data in the page tables, with the data and the physical addresses being associated with each other. A hash of the virtual address of a conversion source and process management information are stored at each of entries of the page table cache 203. In executing a maintenance instruction to delete the conversion pair of the conversion buffer by specifying at least one of the hash of the virtual address and the process management information, an entry matching the at least one of the hash of the virtual address and the process management information in the page table cache 203 is deleted.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to an information processing device and a control method. [Background technology]

[0002] Modern CPUs (Central Processing Units) generally support VA (Virtual Address), which is assisted by hardware. For example, the TLB (Translation Lookaside Buffer) is known to cache VA to PA (Physical Address) translation pairs, and hardware equipped with this TLB is widely used.

[0003] Entries to be registered in the TLB are obtained by performing a page table walk, which can be performed by hardware or software. Whether the page table walk is performed by hardware or software, the page table walk can reference one or more page tables, depending on the method used.

[0004] In such a page table walk, a page table walk involving multiple page table references takes a considerable amount of time to execute because the number of times the page table is referenced from memory increases.

[0005] Therefore, for example, a method is used in which the number of entries is increased to maximize the chance of hitting the TLB, but this alone is not sufficient, and there is a demand to make the page table walk itself as fast as possible. Therefore, in order to make the page table walk itself as fast as possible, a technique is known that includes a dedicated cache for the page table.

[0006] Since the page table cache is a cache of page tables, just like the TLB, when the OS (Operating System) issues a TLBI command to erase TLB entries, the page table cache entries must also be erased.

[0007] Hereinafter, erasing a TLB entry may simply be referred to as erasing the TLB. Similarly, hereafter, erasing a page table cache entry may simply be referred to as erasing the page table cache.

[0008] The OS clears the TLB when it needs to clear a page when it evacuates a page from memory. When a page is cleared, it is stored in the page table, and an inconsistency occurs between the page table and the page table cache (TLB or page table cache), so the page table cache needs to be cleared. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2019-212167 [Patent Document 2] Japanese Patent Application Publication No. 6-139149 [Patent Document 3] Special table 2020-529656 publication Summary of the Invention [Problem to be solved by the invention]

[0010] In conventional page table management methods, when the TLBI instruction is executed, the page table cache is completely cleared. This causes page table cache entries that do not need to be cleared to be cleared, reducing cache efficiency. In one aspect, the present invention aims to efficiently manage a page table cache. [Means for solving the problem]

[0011] For this reason, this information processing device includes a translation buffer that stores translation pairs between virtual addresses and physical addresses of pages, and a page table cache that stores data in page tables of levels other than the last level in association with the physical addresses of the data in the page table, and also includes a processor that stores a hash of the virtual address that is the source of the translation and process management information in each entry of the page table cache, and that, upon execution of a maintenance instruction that specifies at least one of the hash of the virtual address or the process management information and erases the translation pairs from the translation buffer, erases entries in the page table cache where at least one of the hash of the virtual address and the process management information matches. [Effects of the Invention]

[0012] According to one embodiment, the page table cache can be managed efficiently. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram schematically illustrating a configuration of an information processing device as an example of an embodiment. [Figure 2] FIG. 1 is a diagram illustrating a configuration of an L1 cache of an information processing device as an example of an embodiment. [Figure 3] FIG. 2 is a diagram illustrating a configuration of a TLB of an information processing device according to an embodiment; [Figure 4] 1 is a diagram illustrating a configuration of a TLB maintenance command control circuit in an information processing device as an example of an embodiment; [Figure 5] 10 is a diagram illustrating a method for generating a page table cache delete signal by a TLB maintenance command control circuit in an information processing device as an example of an embodiment. FIG. [Figure 6]FIG. 2 is a diagram illustrating a TTL in an information processing device as an example of an embodiment. [Figure 7] FIG. 2 is a diagram illustrating a configuration of a table walk circuit of an information processing device as an example of an embodiment; [Figure 8] FIG. 10 illustrates a method for generating a VA hash by a hashing circuit of an information processing apparatus according to an embodiment; [Figure 9] FIG. 1 is a diagram illustrating an example of a configuration of a page table cache in an information processing device as an example of an embodiment; [Figure 10] FIG. 2 is a diagram illustrating an example of the configuration of each entry of a page table cache in an information processing device as an example of an embodiment; [Figure 11] FIG. 2 is a diagram illustrating a configuration of a comparison circuit in an information processing device as an example of an embodiment; [Figure 12] 10A and 10B are diagrams illustrating a method for setting a VA-hash-match by a delete signal generation circuit in an information processing apparatus as an example of an embodiment; [Figure 13] 10A and 10B are diagrams illustrating processing by a delete signal generation circuit in an information processing device as an example of an embodiment. [Figure 14] 10 is a flowchart illustrating a method for maintaining a page table cache in an information processing apparatus as an example of an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, an embodiment of the information processing device and control method will be described with reference to the drawings. However, the embodiment shown below is merely an example, and it is not intended to exclude various modifications and application of techniques not explicitly stated in the embodiment. In other words, the present embodiment can be implemented with various modifications within the scope of its purpose. Furthermore, each figure does not intend to include only the components shown in the figure, but can also include other functions, etc.

[0015] (A) Configuration 1 is a diagram illustrating a configuration of an information processing device 1 according to an embodiment of the present invention. The information processing device 1 illustrated in FIG.

[0016] The main memory device 105 is, for example, a semiconductor memory such as a RAM (Random Access Memory), and stores information used by the processor 10. The information stored in the main memory device 105 may be instructions included in a program executed by the processor 10, or may be data processed by the processor 10 based on instructions.

[0017] The processor 10 is, for example, a CPU, and includes an instruction control unit 101, an arithmetic unit 102, an L1 cache 103, and an L2 cache 104 in the example shown in FIG.

[0018] The L1 cache 103 and the L2 cache 104 are cache memory circuits within the processor 10, and the L2 cache 104 is a cache memory circuit lower in level than the L1 cache 103. The L1 cache 103 and the L2 cache 104 temporarily store information read from the main memory device 105.

[0019] For example, the L2 cache 104 may be provided outside the processor 10, or another cache may be provided inside the processor 10, and modifications may be made as appropriate.

[0020] When the instruction control unit 101 requests data to be accessed that is stored in the main memory device 105, the instruction control unit 101 outputs a data request (S001) to the L1 cache 103. When the L1 cache 103 stores the data to be accessed, the L1 cache 103 outputs the data to be accessed (S004) to the calculation unit 102.

[0021] On the other hand, if the L1 cache 103 does not store the data to be accessed, the L1 cache 103 outputs a data request (S002) to the L2 cache 104. If the L2 cache 104 stores the data to be accessed, the L2 cache 104 outputs the data to be accessed (S005) to the L1 cache 103. Then, the L1 cache 103 outputs the data (S005) received from the L2 cache 104 to the calculation unit 102 as data (S004).

[0022] On the other hand, if the L2 cache 104 does not store the data to be accessed, the L2 cache 104 outputs a data request (S003) to the main memory device 105. The main memory device 105 outputs the data to be accessed (S006) to the L2 cache 104. The L2 cache 104 then outputs the data (S006) received from the main memory device 105 to the L1 cache 103 as data (S005). The L1 cache 103 outputs the received data (S005) to the calculation unit 102 as data (S004). The calculation unit 102 performs calculations using the data (S004).

[0023] In addition, when the software (OS) rewrites the page table, the software (OS) issues a TLB maintenance command to resolve the mismatch between the address translation pair (combination of source VA and destination PA) of the TLB 204 (described later) and the page table on the main memory device 105.

[0024] The TLB maintenance instruction is a maintenance instruction that instructs the deletion of translation pairs in the TLB 204 (translation buffer). This TLB maintenance instruction is issued either with no VA or ASID specified, with either VA or ASID specified, or with both VA and ASID specified. The ASID is identification information used to identify processes on the OS, and corresponds to process management information.

[0025] In this case, the instruction control unit 101 notifies the L1 cache 103 of a TLB maintenance request. This TLB maintenance request includes accompanying information. The accompanying information includes, for example, the instruction type of the TLB maintenance instruction, the ASID, and the VA of the instruction to be accessed. The VA of the access target instruction corresponds to the request address. The instruction control unit 101 also functions as a request generation unit that generates an information request including the request address.

[0026] The arithmetic unit 102 performs an arithmetic operation in accordance with an instruction from the instruction control unit 101. The arithmetic unit 102 performs an arithmetic operation using data obtained from the L1 cache 103 (S004). FIG. 2 is a diagram illustrating a schematic configuration of the L1 cache 103 of the information processing device 1 according to an example of the embodiment.

[0027] As shown in FIG. 2, the L1 cache 103 includes an L1 data cache 201, a table walk circuit 202, a page table cache 203, and a TLB 204.

[0028] The L1 data cache 201 stores data and the like, and when it receives a data request (reference symbol S001) from the instruction control unit 101, it responds to the instruction control unit 101 with data (reference symbol S004) corresponding to the data request.

[0029] The TLB 204 is a translation buffer that associates the VA of a page with the PA of that page and stores the associated data. The page table cache 203 associates data in page tables at levels other than the last level among the multiple levels of page tables included in the multi-level page table with the PA of that data and stores the associated data. This is because the number of tables at the last level tends to be greater than the number of tables at other levels, and storing data at the last level increases the number of entries in the page table cache 203.

[0030] In the information processing device 1, when the page table to be accessed is a last-level table, the data in the page table to be accessed is prevented from being registered in the page table cache 203. This significantly reduces the number of entries in the page table cache 203, and reduces the hardware scale of the page table buffer 503. The data in the page table is also called a page table entry.

[0031] If TLB 204 stores the VA of the page corresponding to the requested address, the requested address may be said to hit TLB 204, and if TLB 204 does not store the VA of that page, a TLB miss may occur. The TLB 204 corresponds to a translation buffer that stores the VA of a page and the PA of the page in association with each other.

[0032] When the TLB 204 receives a VA translation request sent from the L1 data cache 201, it searches whether the VA related to the translation request is registered as an entry in the TLB 204. If the search results in a hit in the entry, the TLB 204 responds with the translation result (S013) to the L1 data cache 201. The L1 data cache 201 stores the data (S004) corresponding to the conversion result (S013) in the arithmetic unit. Output to 102.

[0033] If the VA related to the translation request is not entered and registered in the TLB 204, that is, if a TLB miss occurs, the TLB 204 issues a page table walk request to the table walk circuit 202. The page table walk request is a request to cause the table walk circuit 202 to execute a page table walk and perform address translation. The page table walk request includes a control signal (S016) and an address signal (S021). FIG. 3 is a diagram illustrating a schematic configuration of the TLB 204 of the information processing device 1 according to an embodiment. As shown in FIG. 3, the TLB 204 includes a TLB main body 701 and a TLB maintenance instruction control circuit 702 . The TLB body 701 includes a storage area for storing VA to PA translation pairs.

[0034] When the TLB maintenance command control circuit 702 is notified of a TLB maintenance command (S014 / S033) from the command control unit 101, it executes maintenance on the TLB body 701 and deletes the entry in the TLB body 701 that is the target of deletion.

[0035] When the TLB maintenance command control circuit 702 receives the TLB maintenance command (S014 / S033), it issues an instruction to the page table cache 203 and the TLB main body 701 to erase the entry.

[0036] The TLB maintenance command control circuit 702 first transmits a TLB search instruction (S034) based on the accompanying information (S033) of the TLB maintenance command to the TLB body 701. The TLB body 701 performs a search in accordance with this TLB search instruction (S034), and if a hit is found, responds to the TLB maintenance command control circuit 702 with the TLB search result (S035).

[0037] Based on the received TLB search result (S035), the TLB maintenance command control circuit 702 transmits a TLB deletion instruction (S036) to the TLB body 701. The TLB body 701 deletes the corresponding entry in accordance with the TLB deletion instruction (S036). FIG. 4 is a diagram illustrating a configuration of the TLB maintenance command control circuit 702 in the information processing device 1 as an example of an embodiment. As shown in FIG. 4, the TLB maintenance command control circuit 702 includes a TLBI control circuit 801, a register 802, and a hashing circuit 803. The register 802 stores accompanying information (S033) of the TLB maintenance instruction.

[0038] The TLB maintenance command control circuit 702 generates a page table cache delete signal (S015), a TLBI-opcode (OPCODE), a VA-Hash, and an ASID (S031) based on the associated information (S033) stored in this register 802. The VA-Hash is a hash value generated based on the VA. Hereinafter, the VA-Hash may also be referred to as a VA hash.

[0039] FIG. 5 is a diagram for explaining a method for generating a page table cache delete signal (S015) by the TLB maintenance command control circuit 702 in the information processing device 1 as one example of an embodiment.

[0040] 5 shows a rule for generating a page table cache delete signal. The TLB maintenance command control circuit 702 generates a page table cache delete signal according to the type (instruction type) of TLBI, as shown in FIG. 5. The TLB maintenance command control circuit 702 also sets a TLBI-opcode according to the type of TLBI.

[0041] 5 shows five types of TLBI: a VA instruction type, an ASID instruction type, a VA·ASID instruction type, an IPA instruction type, and other types. For example, in the VA instruction type, the page table of an entry with a matching VA (VA hash) is erased in the page table cache 203 during TLB maintenance. In the ASID instruction type, the page table of an entry with a matching ASID is erased in the page table cache 203 during TLB maintenance. In the VA·ASID VA instruction type, the page table of an entry with a matching VA (VA hash) and ASID is erased in the page table cache 203 during TLB maintenance.

[0042] The hashing circuit 803 of the TLB maintenance command control circuit 702 reads the VA stored in the register 802 and generates a VA hash by performing a hashing operation. The hashing operation can be realized using a known method, and a description thereof will be omitted.

[0043] The hashing circuit 803 generates three VA hashes for each TTL. That is, the hashing circuit 803 generates three VA hashes for TTL=0100, TTL=0101, and TTL=0110 based on the VA. In addition, the TLB maintenance instruction control circuit 702 outputs ASID0 stored in the register 802 as is (S031). FIG. 6 is a diagram illustrating a TTL in the information processing device 1 as an example of an embodiment.

[0044] Fig. 6 illustrates the meaning of each TTL value. In the example shown in Fig. 6, the TTL values (0100 to 0111) indicate flags corresponding to page tables Lv0 to Lv3. Note that the TTL is generated by the control circuit 305 (see Fig. 7) of the table walk circuit 202, which will be described later, based on states such as Stage1-Lv0-Stat.

[0045] When the table walk circuit 202 receives a page table walk request (S016, S021) from the TLB 204, it executes a page table walk in response to the table walk request and performs address translation of the requested address. The page table walk request (S016, S021) includes a control signal (S016) and an address signal (S021). Note that the table walk is well known, and its description will be omitted.

[0046] Furthermore, the table walk circuit 202 associates the converted PA with the VA and registers it in the TLB 204. The table walk circuit 202 instructs the TLB 204 to register the conversion result, thereby registering the address conversion pair of PA and VA in the TLB 204. This conversion result registration includes the control signal (S017), the address signal of the VA (S027), and the address signal of the PA (S022).

[0047] During the table walk process, the table walk circuit 202 fetches a page table. First, the table walk circuit 202 outputs a page table request to the page table cache 203 to inquire whether the page table is stored in the page table cache 203. This page table request includes a control signal (S009), an address signal (S019), and a VA context (S032). The address signal (S019) includes the PA of the data in the page table to be accessed. The VA context (S032) may include, for example, a TTL and an ASID-valid.

[0048] If the result of the inquiry by the page table request (S009 / S019 / S032) is that the target page table is in the page table cache 203, the table walk circuit 202 receives the page table data from the page table cache 203 and continues address translation. The page table data returned from the page table cache 203 includes a control signal (S010) and a data signal (S025).

[0049] Furthermore, if the result of the inquiry by the page table request (S009 / S019 / S032) shows that the target page table is not in the page table cache 203, the page table cache 203 outputs a page table cache miss signal (S026) to the table walk circuit 202. If the target page table is not in the page table cache 203, the table walk circuit 202 sends a page table request to the L1 data cache 201 to request a page table. The page table request includes a control signal (S007) and an address signal (S018).

[0050] The table walk circuit 202 queries the L2 cache 104 and the main memory device 105 via the L1 data cache 201, and receives page table data from the L1 data cache 201. The page table data includes a control signal (S008) and a data signal (S020).

[0051] When the table walk circuit 202 acquires a page table via the L1 data cache 201, it registers the data of this page table in the page table cache 203. The table walk circuit 202 registers the data of the page table in the page table cache 203 by instructing the page table cache 203 to register the page table. The page table registration includes a control signal (S011), a data signal (S019), and a VA context (S032). However, if the page table is a table at the last level, the registration of the page table data in the page table cache 203 is suppressed.

[0052] When the table walk is completed, the table walk circuit 202 instructs the TLB 204 to register the conversion result, thereby registering the conversion result in the TLB 204. The conversion result registration includes a control signal (S017) and an address signal (S018).

[0053] If the TLB 204 does not store a virtual address corresponding to the request address, the table walk circuit 202 obtains the physical address of the data in the page table to be accessed from the request address. If the page table to be accessed is a page table of a level other than the last level, the table walk circuit 202 searches the page table cache 203 for the data in the page table to be accessed.

[0054] When the page table to be accessed is the last level page table, the table walk circuit 202 functions as a control unit that acquires data in the page table to be accessed from the L1 data cache 201 and registers the VA and PA of the page indicated by the acquired data in the TLB 204. FIG. 7 is a diagram illustrating a configuration of the table walk circuit 202 of the information processing device 1 as an example of an embodiment.

[0055] The table walk circuit 202 includes a VA / IPA register 301, a TTBR register 302, a VTTBR register 303, a page table data register 304, a control circuit 305, a hashing circuit 306, an address calculation circuit 307, an output address register 308, and a selector 309. IPA is an abbreviation for Intermediate Physical Address. TTBR is an abbreviation for Translation Table Base Register, and VTTBR is an abbreviation for Virtualization Translation Table Base Register.

[0056] The VA / IPA register 301 is a register that stores the address signal (S021) of a page table walk request. The TTBR register 302 is a register that holds the physical base address of a page table at a specific operating level. The VTTBR register 303 is a register that holds the physical base address of a page table for stage 2 translation of memory access from a non-secure mode other than the Hyp mode.

[0057] The hashing circuit 306 generates a VA hash using the address read from the VA / IPA register 301. The generated VA hash is included in, for example, the VA context (S032) of the page table registration, sent to the page table cache 203, and managed in association with the page table data. FIG. 8 is a diagram illustrating a method for generating a VA hash by the hashing circuit 306 of the information processing device 1 as an example of an embodiment.

[0058] 8, the hash calculation formula is shown in association with the TTL value (0100, 0101, 0110, 0111). In the figure, the circled + indicates exclusive OR (EXOR). As shown in FIG. 8, the hashing circuit 306 calculates a VA hash according to the TTL value.

[0059] The address calculation circuit 307 calculates the address of the table according to the instruction of the control circuit 305. The address calculation circuit 307 calculates the address using the Lv0-index, which is a part of the VA, and the BADDR of the TTBR register 302, and inputs the address to the output address register 308.

[0060] For example, the address calculation circuit 307 adds the Lv1-index stored in the VA / IPA register 301 to the level 1 table address to find the PA of the data in the level 1 page table.

[0061] Furthermore, the address calculation circuit 307 adds the Lv2-index stored in the VA / IPA register 301 to the level 2 table address to find the PA of the data in the level 2 page table.

[0062] Furthermore, the address calculation circuit 307 adds the Lv3-index stored in the VA / IPA register 301 to the level 3 table address to find the PA of the data in the level 3 page table.

[0063] The address calculation circuit 307 stores the determined PA in the output address register 308, and the output address register 308 outputs an address signal (S019) indicating the stored PA to the page table cache 203.

[0064] The table fetch address calculated by the address calculation circuit 307 is input to the output address register 308. The address read from this output address register 308 is used to search the page table cache 203.

[0065] If a cache hit occurs as a result of searching the page table cache 203 with the address read from the output address register 308, page table data is input to the selector 309. The page table data includes a control signal (S010) and a data signal (S025).

[0066] The selector 309 is controlled by the page table data transfer signal (S010=1), and inputs the address of the page table data sent from the page table cache 203 to the page table data register 304. The page table data register 304 stores the address of the page table to be accessed by the table walk. The control circuit 305 controls the table walk process in the table walk circuit 202 .

[0067] For example, when a page table walk request (S016 / S021) is input from the TLB 204 to the table walk circuit 202, the requested address (S021) is stored in the VA / IPA register 301. At this time, the control circuit 305 enters a state (Stage 1-Lv0-State) in which the page table of level 0 (Lv0) is fetched. In this state, the control circuit 305 instructs the address calculation circuit 307 to calculate the PA of the data in the page table of level 0.

[0068] Furthermore, if the page table cache 203 is searched for the address read from the output address register 308 and there is no cache hit, that is, if the page table cache 203 misses, a page table cache miss signal (S026) is sent from the page table cache 203 to the control circuit 305. The control circuit 305 sends a page table data request to the L1 data cache 201. This page table data request includes a control signal (S007) and an address signal (S018).

[0069] When page table data (S008 / S020) is returned from the L1 data cache 201, the control circuit 305 controls the selector 309 to store the page table data in the page table data register 304. Only when the control circuit 305 has acquired the page table from the L1 data cache 201, does the control circuit 305 instruct the page table cache 203 to register the page table (S011 / S019 / S032).

[0070] When a page table is acquired from the page table cache 203 or the L1 data cache 201, the page table data transfer signal (S008 / S010) notifies the control circuit 305 that the page table has been acquired. Then, the control circuit 205 transitions to the next state (Stage1-Lv1-State) and begins the operation of calculating the next page table address.

[0071] The control circuit 305 performs address calculations in the same manner up to Lv3. Since Lv3 is the last level, when a page table is obtained from the L1 data cache 201, no registration operation is performed in the page table cache 203. Since the page table obtained by the table fetch of Lv3 contains the desired PA, the control circuit 305 extracts this PA via the output address register 308 and registers it in the TLB 204 (S017 / S027 / S022).

[0072] The control circuit 305 also generates TTL. The control circuit 305 generates TTL based on states such as Stage1-Lv0-Stat, etc. Note that the method for generating TTL is known, and a description thereof will be omitted.

[0073] If the page table to be accessed is a page table of a level other than the last level and the page table buffer does not store the PA of the data in the page table to be accessed, or if the page table buffer stores the PA but the hash of the VA of the conversion source (VA hash) and the ASID do not match the contents of the entry in the page table cache 203, the table walk circuit 202 obtains the data in the page table to be accessed from the L1 data cache 201 and outputs it to the page table cache 203.

[0074] The L1 data cache 201 receives a data request (S001) from the instruction control unit 101 and responds with data corresponding to the data request to the arithmetic unit 102 (S004). The data request from the instruction control unit 101 is given in VA for accessing data, so it needs to be converted into PA. Therefore, the L1 data cache 201 issues a VA conversion request (S012) to the TLB 204. When the L1 data cache 201 receives PA as the translation result of VA from the TLB 204, it returns the data of the PA to the arithmetic unit 102.

[0075] Furthermore, when the instruction control unit 101 issues a TLB maintenance request (S001) along with accompanying information to the L1 data cache 201, the L1 data cache 201 temporarily holds the TLB maintenance request.

[0076] Thereafter, the L1 data cache 201 outputs a TLB maintenance command to the TLB 204. This TLB maintenance command includes a control signal (S014) and an associated signal (S033). The associated information (S033) is set according to the type of the TLB maintenance command. The associated information (S033) may include the command type, ASID, and VA of the TLB maintenance command. The page table cache 203 stores the data of the page table.

[0077] The page table is a cache memory that stores data in a page table at a level other than the last level in association with the PA (physical address) of the data in the page table.

[0078] FIG. 9 is a diagram illustrating an example of the configuration of the page table cache 203 in the information processing device 1 as an example of an embodiment, and FIG. 10 is a diagram illustrating an example of the configuration of each entry in the page table cache 203.

[0079] 9, the page table cache 203 includes a plurality of entries. In the example shown in Fig. 9, each entry of the page table cache 203 includes a valid bit V, a VA hash, a TTL, an ASID-Valid, an ASID, a PA, and a Page-table-data.

[0080] The valid bit V is a flag that indicates whether the entry in which the valid bit is set is valid. For example, when the valid bit V is a logical "1", the entry is valid, and when the valid bit V is a logical "0", the entry is invalid.

[0081] Page-table-data is the data in the page table and corresponds to the data section. VA Hash, TTL, ASID-Valid, ASID, and PA correspond to the tag section. PA indicates the PA of the data in the page table. TTL, ASID-Valid, and ASID are all known information, and detailed explanations will be omitted. Each entry of the page table cache 203 stores the hash of the VA of the conversion source (VA hash) and ASID (process management information).

[0082] The page table cache 203 is updated, for example, by an LRU (Least Recently Used) method. For example, a control queue (not shown) stores the order of use of multiple entries in the page table cache 203, and the entry that was used least recently among the multiple entries, i.e., the entry that has been used the longest since it was last used, is targeted for deletion.

[0083] When the table walk circuit 202 searches the page table cache 203, the page table cache 203 receives an address signal (S019) indicating the PA of the data in the page table from the table walk circuit 202. Then, each entry in the page table cache 203 compares the PA indicated by the address signal (S019) with the PA included in the entry, and outputs a hit signal (S028) indicating the comparison result to the selector 402 and the NOR (negative OR) circuit 403.

[0084] If the PA indicated by the address signal (S019) matches the PA of the entry, the hit signal (S028) becomes logic "1", and if the PA indicated by the address signal (S019) does not match the PA of the entry, the hit signal (S028) becomes logic "0".

[0085] Each entry outputs a data signal (S030) indicating page table data to the selector 402. Based on the control signal (S028) output from each entry, the selector 402 selects the data signal (S030) of the entry indicated by the hit signal (S028) of logic "1", and outputs it as a data signal (S025).

[0086] The NOR circuit 403 outputs the NOR of the control signals (S028) output from each entry EN as a miss signal (S026). Therefore, if the PA indicated by the address signal (S019) matches the PA of any entry, the miss signal (S026) becomes logic "0," and if the PA indicated by the address signal (S019) does not match the PA of any entry, the miss signal (S026) becomes logic "1." If the miss signal (S026) is logic "1," the table walk circuit 202 outputs the page table request control signal (S007) and the address signal (S018) to the L1 data cache 201.

[0087] When the table walk circuit 202 registers data in the page table in the page table buffer page table cache 203, the page table cache 203 receives a page table registration control signal (S011), an address signal (S019), a data signal (S024), and a VA context (S032) from the table walk circuit 202. Then, the PA indicated by the address signal (S019) and the data in the page table indicated by the data signal (S024) are stored in the entry indicated by the signal (S029) of the oldest entry in the LRU, and the data in that entry is updated.

[0088] When searching the page table cache 203, the table walk circuit 202 notifies the page table cache 203 of the VA-Hash / TTL / ASID-valid / ASID / PA (S019 / S032) of the table address. The page table cache 203 compares the notified VA-Hash / TTL / ASID-valid / ASID / PA (S019 / S032) with the flags of the same name stored in each entry of the page table cache 203.

[0089] A hit signal as a comparison result is input to the selector 402, which selects the entry that has caused a cache hit, and the page table data of this entry is read out.

[0090] In addition, all of the hit signals (S028) are input to the NOR circuit 403, and a page table cache miss signal (S026) is output when all of these hit signals are 0. This page table cache miss signal (S026) is input to the table walk circuit 202.

[0091] When the page table cache miss signal (S026) is input, the table walk circuit 202 transmits a page table data request (S007) to the L1 data cache 201.

[0092] Replacement of the page table cache 203 is controlled by LRU. Therefore, in the page table cache 203, the entries are rearranged so that the entry corresponding to the hit signal (S028) is at the top (newest). Furthermore, when registering in the page table cache 203, a signal (S029) indicating the oldest entry is output, and registration is performed on the entry indicated by this signal.

[0093] 10 shows the configuration of an arbitrary entry (Entry N) of the page table cache 203. Each entry of the page table cache 203 includes AND (logical product) circuits 502, 508, 5042, 5043, buffers 503, 2031, comparison circuits 506, 507, an OR circuit 5041, and a delete signal (Entry N Delete signal) generation circuit 505. The buffer 2031 stores the VA-Hash, TTL, ASID-valid, ASID, PA, and Page-table-data.

[0094] The AND circuit 502 outputs the logical product of the page table registration control signal (S011) and the signal (S029) of the oldest entry in the LRU to the AND circuit 5043 and the buffer 2031. When the table walk circuit 202 registers data in the page table in the page table cache 203, the page table registration control signal (S011) becomes logical "1", and otherwise the page table registration control signal (S011) becomes logical "0".

[0095] The AND circuit 5042 outputs to the OR circuit 5041 the logical product of the negation of a delete signal (Entry N Delete) output by a delete signal generation circuit 505 (described later) and the valid bit V stored in the buffer 503 .

[0096] The AND circuit 5043 outputs the logical product of the negation of the delete signal from the delete signal generation circuit 505 and the output of the AND circuit 502 to the OR circuit 5041. The OR circuit 5041 outputs the logical sum of the output of the AND circuit 5042 and the output of the AND circuit 5043 to the buffer 503, and the buffer 503 holds the output of the OR circuit 5041 as a valid bit V.

[0097] When the table walk circuit 202 searches the page table cache 203, the comparison circuit 507 compares the PA indicated by the address signal (S019) with the PA stored in the buffer 2031, and outputs the comparison result to the AND circuit 508. If the PA indicated by the address signal (S019) matches the PA in the buffer 2031, the comparison result is logic "1", and if the PA indicated by the address signal (S019) does not match the PA in the buffer 2031, the comparison result is logic "0".

[0098] The comparator circuit 506 compares the VA-Hash / TTL / ASID-valid / ASID (S032) of the page table address sent from the table walk circuit 202 with the VA-Hash / TTL / ASID-valid / ASID of the TAG section stored in the buffer 2031, and outputs the comparison result to the AND circuit 508. If each value of the VA-Hash / TTL / ASID-valid / ASID (S032) matches the VA-Hash / TTL / ASID-valid / ASID in the buffer 2031, the comparison result is logic "1". On the other hand, if each value of the VA-Hash / TTL / ASID-valid / ASID (S032) does not match the VA-Hash / TTL / ASID-valid / ASID in the buffer 2031, the comparison result is logic "0". FIG. 11 is a diagram illustrating a configuration of the comparison circuit 506 in the information processing device 1 as an example of an embodiment.

[0099] The comparison circuit 506 includes an AND circuit 5062, an OR circuit 5063, and a plurality of comparison circuits 5061-1 to 5061-4. Hereinafter, the comparison circuits 5061-1 to 5061-4 will be referred to as comparison circuit 5061 unless they are particularly distinguished from one another.

[0100] The number of comparator circuits 5061 provided is the same as the number of elements to be compared in the TAG section. In the example shown in Fig. 11, four comparator circuits 5061-1 to 5061-4 are provided corresponding to VA-Hash, TTL, ASID-valid, and ASID, respectively.

[0101] The comparison circuit 5061 - 1 receives the VA-Hash of the entry in the page table cache 203 and the VA-Hash of the page table address sent from the table walk circuit 202 , and the comparison result is input to the AND circuit 5062 .

[0102] The comparator circuit 5061 - 2 receives the TTL of the entry in the page table cache 203 and the TTL of the page table address sent from the table walk circuit 202 , and the comparison result is input to the AND circuit 5062 .

[0103] The comparison circuit 5061 - 3 receives the ASID-valid of the entry in the page table cache 203 and the ASID-valid of the page table address sent from the table walk circuit 202 , and the comparison result is input to the AND circuit 5062 .

[0104] The comparison circuit 5061 - 4 receives the ASID of the entry in the page table cache 203 and the ASID of the page table address sent from the table walk circuit 202 , and the comparison result is input to the OR circuit 5063 .

[0105] The comparison result of the comparator circuit 5061-4 and the inverted value of ASID-valid of the page table address transmitted from the table walk circuit 202 are input to the OR circuit 5063, and the logical sum thereof is output to the AND circuit 5062. The logical product (match signal S038) by the AND circuit 5062 is output to the AND circuit 508.

[0106] The AND circuit 508 outputs the logical AND of the comparison result output by the comparison circuit 507, the comparison result output by the comparison circuit 506, and the valid bit V stored in the buffer 503 as an Entry N hit signal (S028), and the buffer 2031 outputs a data signal (S030) indicating the page table data. Therefore, if the entry is valid, the PA indicated by the address signal (S019) matches the PA in the buffer 2031, and the VA-Hash / TTL / ASID-valid / ASID (S032) of the page table address transmitted from the table walk circuit 202 matches the VA-Hash / TTL / ASID-valid / ASID stored in the buffer 2031, the Entry N hit signal (S028) becomes logic "1." The Entry N hit signal (S028) is input to, for example, the selector 402 (see FIG. 9). The comparison target in the comparison circuit 506 is determined according to the type of TLBI (see FIG. 5).

[0107] The AND circuit 502 receives the signal (S029) of the oldest entry in the LRU and the page table cache registration signal (S011).

[0108] When an entry is registered in the page table cache 203, the page table cache registration signal (S011) becomes 1, and the write signal of the entry becomes 1 due to the logical product output of the AND circuit 502 for the same entry as the oldest in the LRU.

[0109] At this time, the page table address PA (S019), VA-Hash / TTL / ASID-valid / ASID (S032), and page table data (S024) sent from the table walk circuit 202 are written to the entry. Furthermore, at this time, the valid bit V is set in the buffer 503.

[0110] The page table cache 203 receives the VA-Hash / TTL / ASID-valid / ASID / PA (S019 / S032) of the table address. Each entry N compares the VA-Hash / TTL / ASID-valid / ASID values stored in that entry N with the input VA-Hash / TTL / ASID-valid / ASID / PA (S019 / S032) values to determine whether they match. The ASID comparison result (match / mismatch) may be expressed as ASID-match.

[0111] The delete signal (Entry N Delete signal) generation circuit 505 generates a delete signal (Entry N Delete signal) for controlling the deletion of a specific entry in the page table cache 203 . The delete signal generation circuit 505 generates a delete signal in accordance with an instruction from the TLBI control circuit 801 (see FIG. 4).

[0112] The delete signal generation circuit 505 selects a VA hash corresponding to the TTL from the three types of VA hashes (S031) sent from the TLB 204, and sets a VA-hash-match.

[0113] FIG. 12 is a diagram for explaining a method for setting a VA-hash-match by the delete signal generation circuit 505 in the information processing device 1 as an example of an embodiment.

[0114] In Fig. 12, TTL is the TTL held in the buffer 2031 (Entry-N) of the page table cache 203 illustrated in Fig. 10. VA-hash-match (before selection) is the VA hash output from the hashing circuit 803 illustrated in Fig. 4. The delete signal generation circuit 505 sets the VA-hash-match based on these combinations.

[0115] FIG. 13 is a diagram for explaining the processing of the delete signal generation circuit 505 in the information processing device 1 as one example of an embodiment, and shows a generation rule of the delete signal (Entry N Delete) by the delete signal generation circuit 505. The delete signal generation circuit 505 receives TLBI-opcode, ASID-valid, VA-hash-match, and ASID-match.

[0116] As shown in FIG. 13, the delete signal generation circuit 505 generates and outputs a delete signal (Entry N Delete) corresponding to the input combination of TLBI-opcode, ASID-valid, VA-hash-match, and ASID-match.

[0117] In FIG. 13, the “0”, “1”, and “*” in VA-hash-match and ASID-match indicate the output signals of a match circuit (not shown) for the VA hash and ASID, where “0” indicates no match and “1” indicates a match. Also, “*” indicates that the result is valid whether it matches or not. In addition, in the delete signal (Entry N Delete), "1" indicates that the data is to be deleted, and "0" indicates that the data is not to be deleted.

[0118] The delete signal (Entry N Delete) output from the delete signal generation circuit 505 is inverted and input to AND circuits 5042 and 5043, respectively. The AND circuit 5042 outputs the logical product of the negation of the delete signal and the valid bit V stored in the buffer 503 to the OR circuit 5041 .

[0119] The AND circuit 5043 outputs the logical product of the negation of the delete signal and the output of the AND circuit 502 to the OR circuit 5041. The OR circuit 5041 outputs the logical sum of the output of the AND circuit 5042 and the output of the AND circuit 5043 to the buffer 503, and the buffer 503 holds the output of the OR circuit 5041 as a valid bit V.

[0120] As a result, when the delete signal generation circuit 505 outputs "1" as the delete signal (Entry N Delete), the OR circuit 5041 outputs "0", and the valid bit V of the buffer 503 is set to "0".

[0121] In this way, by setting the valid bit V of the buffer 503 to "0", the entry of the buffer 2031 corresponding to the buffer 503 in the page table cache 203 is invalidated. This prohibits the use of data in the old page table that does not match the rewritten page table.

[0122] That is, in the page table cache 203, only the entry (buffer 2031) specified by the VA or ASID included in the accompanying information (S033) of the TLB maintenance command (S014) is erased.

[0123] When the page table cache 203 is cleared by a TLB maintenance instruction, if a VA or an ASID or both are specified, it only clears entries that match the VA hash or the ASID or both. Specifically, the page table cache 203 determines the target of the match check in TLB maintenance according to the type of TLBI.

[0124] For example, in the VA instruction type, during TLB maintenance, if the VA (VA hash) matches in the page table cache 203, the page table cache 203 erases the target entry (buffer 2031). In the VA instruction type, the VA hash corresponds to the match determination target.

[0125] In the ASID instruction type, the page table cache 203 erases the target entry (buffer 2031) when the ASID matches in the page table cache 203. In the ASID instruction type, the ASID corresponds to the target for match determination.

[0126] Furthermore, in the VA·ASID instruction type, if both the VA (VA hash) and ASID match in the page table cache 203, the page table cache 203 erases the target entry (buffer 2031). In the VA·ASID instruction type, both the VA hash and the ASID correspond to the match determination targets.

[0127] That is, when a TLB maintenance instruction is executed in the page table cache 203, only entries in which at least one of the VA hash and ASID (process management information) matches are erased.

[0128] Furthermore, the page table cache 203 identifies the match determination target (VA hash, ASID) from among the VA hash and ASID (process management information) based on the instruction type related to the maintenance command, that is, the type of TLBI.

[0129] Then, the delete signal generation circuit 505 generates a delete signal (control signal) for setting a bit indicating invalidity for the entry that matches the identified match determination target. This generated delete signal is set to the valid bit V set in the buffer 503.

[0130] Furthermore, since the value of the valid bit V set in the buffer 503 is input to the AND circuit 508, when "0" is set in the valid bit V of the buffer 503, the AND circuit 508 outputs "0" as the Entry N hit signal (S028). As a result, the entry of the buffer 503 with the valid bit V set to "0" is no longer hit in the page table cache 203, which is essentially the same as if the entry had been deleted.

[0131] (B) Operation A maintenance method for the page table cache 203 in the information processing device 1 configured as above as an example of an embodiment will be described with reference to the flowchart (steps S1 to S6) shown in FIG.

[0132] When the software (OS) rewrites the page table, the software (OS) issues a TLB maintenance request to resolve the mismatch between the address translation pair (combination of source VA and destination PA) in the TLB 204 and the page table in the main memory 105.

[0133] When the instruction control unit 101 issues a TLB maintenance request (S001) accompanied by accompanying information to the L1 data cache 201, the L1 data cache 201 temporarily holds the TLB maintenance request.

[0134] Thereafter, the L1 data cache 201 transmits a TLB maintenance command (S014 / S033) to the TLB 204, and the TLB 204 receives the TLB maintenance command (S014 / S033) (step S1).

[0135] This TLB maintenance instruction (S014 / S033) includes a control signal (S014) and an accompanying signal (S033). The accompanying information (S033) is set according to the type of TLB maintenance instruction, and may include the instruction type, ASID, and VA of the TLB maintenance instruction.

[0136] When the TLB 204 receives a TLB maintenance command (S014 / S033), it sends a page table cache delete signal (S015 / S031) to the page table cache 203 (step S2). The comparator circuit 507 compares the PA indicated by the address signal (S019) with the PA stored in the buffer 2031, and outputs the comparison result to the AND circuit 508.

[0137] In addition, the comparison circuit 506 compares the VA-Hash / TTL / ASID-valid / ASID (S032) of the page table address sent from the table walk circuit 202 with the VA-Hash / TTL / ASID-valid / ASID of the TAG section stored in the buffer 2031, and the comparison result is output to the AND circuit 508.

[0138] The comparator circuit 506 compares the VA-Hash / TTL / ASID-valid / ASID (S032) values of the page table address sent from the table walk circuit 202 with the VA-Hash / TTL / ASID-valid / ASID values of the TAG section stored in the buffer 2031 (step S3). The comparator circuit 506 determines whether the VA-Hash / TTL / ASID-valid / ASID match the target of the match determination (VA hash, ASID, etc.) determined according to the instruction type specified by the type of TLBI (step S4).

[0139] If the values of VA-Hash / TTL / ASID-valid / ASID (S032) of the page table address match the values of VA-Hash / TTL / ASID-valid / ASID of buffer 2031 (see the YES route in step S4), proceed to step S5.

[0140] In step S5, the target entry (buffer 2031) in the page table cache 203 is erased, and the maintenance process for the page table cache 203 is completed.

[0141] On the other hand, if the values of VA-Hash / TTL / ASID-valid / ASID (S032) of the page table address do not match the values of VA-Hash / TTL / ASID-valid / ASID of buffer 2031 (see the NO route in step S4), proceed to step S6.

[0142] In step S6, erasure of the target entry (buffer 2031) in the page table cache 203 is prevented, and the maintenance process for the page table cache 203 is completed.

[0143] (C) Effects Thus, according to the information processing device 1 as an example of an embodiment, the hash of the VA of the conversion source and the ASID are stored in each entry that manages page table data in the page table cache 203. When a TLB maintenance instruction (an instruction to erase the TLB) that specifies a VA or an ASID, or both, is executed, only entries that match the VA hash or the ASID, or both, are erased.

[0144] That is, when a TLB maintenance request is issued, in the page table cache 203, the comparison circuit 506 determines whether there is a match for the target of match determination (VA hash, ASID, etc.) determined according to the instruction type specified by the type of TLBI, among the VA-Hash / TTL / ASID-valid / ASID stored in the entry of the page table cache 203.

[0145] Then, if the values of VA-Hash / TTL / ASID-valid / ASID (S032) of the page table address match the values of VA-Hash / TTL / ASID-valid / ASID of buffer 2031 that are the subject of match determination, the entry to be maintained is erased.

[0146] For example, when the type of TLBI is a VA instruction type, the page table of an entry with a matching VA (VA hash) is erased in the page table cache 203. When the type is an ASID instruction type, the page table of an entry with a matching ASID is erased in the page table cache 203. When the type is a VA·ASID VA instruction type, the page table of an entry with a matching VA (VA hash) and ASID is erased in the page table cache 203.

[0147] As a result, when a TLB maintenance instruction specifying VA or ASID or both is executed, only entries that match the VA or ASID or both are erased according to the type of TLBI, without erasing the entire page table cache 203. This prevents entries with different VAs from being erased by a TLB maintenance instruction specifying VA, which is expected to improve the hit rate of the page table cache 203. The same effect of improving the hit rate is also seen for TLB maintenance instructions specifying ASID, or VA and ASID. Therefore, it is possible to prevent a decrease in the hit rate in the page table cache 203 due to a TLB maintenance instruction.

[0148] (D) Other The configurations and processes of this embodiment can be selected as needed, or can be combined as appropriate. The disclosed technology is not limited to the above-described embodiment, and can be implemented in various modifications without departing from the spirit of the present embodiment.

[0149] For example, in the above-described embodiment, VA-Hash / TTL / ASID-valid / ASID are managed in each entry of the page table cache 203, but this is not limited to this. For example, other information such as regime and VMID may also be managed, and can be implemented with appropriate modifications.

[0150] Furthermore, in the above-described embodiment, an example is shown in which ASID is used as process management information, but this is not limited to this, and information other than ASID may be used as information by which the OS manages processes, and can be modified and implemented as appropriate. Furthermore, the above disclosure will enable those skilled in the art to implement and manufacture the present embodiment.

[0151] (E) Supplementary Note The following additional notes are provided regarding the above-described embodiments. (Appendix 1) a translation buffer for storing translation pairs of virtual and physical addresses of pages; a page table cache that stores data in a page table at a level other than the last level in association with a physical address of the data in the page table; storing a hash of the virtual address of the source of translation and process management information in each entry of the page table cache; Upon execution of a maintenance instruction specifying at least one of the hash of the virtual address or the process control information to erase the translation pair from the translation buffer, In the page table cache, an entry in which at least one of the hash of the virtual address and the process management information matches is deleted. An information processing device comprising a processor.

[0152] (Appendix 2) the processor: Identifying a match target from the hash of the virtual address and the process management information based on an instruction type related to the maintenance command. 2. The information processing device according to claim 1,

[0153] (Appendix 3) the processor: A delete signal generation circuit is provided that generates a control signal for setting a bit indicating invalidity for the entry that matches the specified match determination target. 3. The information processing device according to claim 2,

[0154] (Appendix 4) a translation buffer for storing translation pairs of virtual and physical addresses of pages; In an information processing device having a page table cache that stores data in a page table at a level other than the last level in association with a physical address of the data in the page table, storing a hash of the virtual address of the source of translation and process management information in each entry of the page table cache; Upon execution of a maintenance instruction specifying at least one of the hash of the virtual address or the process control information to erase the translation pair from the translation buffer, In the page table cache, an entry in which at least one of the hash of the virtual address and the process management information matches is deleted. A control method characterized in that processing is executed by a processor.

[0155] (Appendix 5) Identifying a match target from the hash of the virtual address and the process management information based on an instruction type related to the maintenance command. 5. The control method according to claim 4, wherein the processing is executed by the processor.

[0156] (Appendix 6) Generate a control signal for setting a bit indicating invalidity for the matched entry for the identified match determination target. The processor executes the process. 6. The control method according to claim 5, [Explanation of symbols]

[0157] 1. Information processing equipment 10 processors 101 Command control section 102 Arithmetic section 103 L1 cache 104 L2 cache 105 Main memory 201 L1 data cache 202 Table Walk Circuit 203 Page Table Cache 204 TLB 301 VA / IPA register 302 TTBR Register 303 VTTBR Register 304 Page Table Data Register 305 Control Circuit 306 Hashing Circuit 307 Address Calculation Circuit 308 Output Address Register 309,402 selectors 403 NOR circuit 701 TLB main unit 702 TLB maintenance instruction control circuit 801 TLBI control circuit 802 Register 803 Hashing Circuit 505 Delete signal generation circuit 507,5061-1~5061-4,5061 Comparison circuit 503,2031 buffers 502, 508, 5042, 5043, 5062 AND circuit 5041,5063 OR circuit

Claims

1. a translation buffer for storing translation pairs of virtual and physical addresses of pages; a page table cache that stores data in a page table at a level other than the last level in association with a physical address of the data in the page table; storing a hash of the virtual address of the source of translation and process management information in each entry of the page table cache; Upon execution of a maintenance instruction specifying at least one of a hash of the virtual address or the process control information to erase the translation pair from the translation buffer, In the page table cache, an entry in which at least one of the hash of the virtual address and the process management information matches is deleted. An information processing device comprising a processor.

2. the processor: Identifying a match target from the hash of the virtual address and the process management information based on an instruction type related to the maintenance command.

2. The information processing apparatus according to claim 1, wherein:

3. the processor: A delete signal generation circuit is provided that generates a control signal for setting a bit indicating invalidity for the entry that matches the specified match determination target.

3. The information processing apparatus according to claim 2, wherein:

4. a translation buffer for storing translation pairs of virtual and physical addresses of pages; In an information processing device having a page table cache that stores data in a page table at a level other than the last level in association with a physical address of the data in the page table, storing a hash of the virtual address of the source of translation and process management information in each entry of the page table cache; Upon execution of a maintenance instruction specifying at least one of a hash of the virtual address or the process control information to erase the translation pair from the translation buffer, In the page table cache, an entry in which at least one of the hash of the virtual address and the process management information matches is deleted. A control method characterized in that processing is executed by a processor.

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