Logical-to-physical address indirection table in persistent memory of solid-state drives

Abstract

To provide a solid state drive including a logical-to-physical (L2P) indirect reference table.SOLUTION: An L2P indirect reference table stored in a persistent memory includes a plurality of entries. A solid state drive in which each entry stores a physical block address in a block addressable memory assigned to a logical block address includes a solid state drive controller circuit which is communicably coupled with the persistent memory and the block addressable memory. The solid state drive controller circuit includes a volatile memory for storing a logical-to-physical address indirect reference table cache and a circuit to monitor the logical-to-physical address indirect reference table cache, and for writing dirty logical-to-physical entries in the logical-to-physical address indirect reference table cache to the logical-to-physical address indirect reference table in the persistent memory.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to logical-to-physical (L2P) address indirection tables stored in persistent memory of storage devices, particularly solid-state drives. [Background technology]

[0002] A computer system typically includes volatile system memory, such as dynamic random access memory (DRAM), and a storage device, which may be a solid-state drive (SSD) that includes block-addressable non-volatile memory.

[0003] A logical block is the smallest addressable unit of data for read and write commands to access the block-addressable non-volatile memory of a solid-state drive. The address of a logical block is commonly referred to as a logical block address (LBA).

[0004] A logical-to-physical (L2P) address indirection table stores physical block addresses in block-addressable non-volatile memory within the solid-state drive corresponding to each LBA. The size of the L2P address table depends on the user capacity of the solid-state drive. Typically, the size of the L2P address table is approximately 1 megabyte (MB) for every gigabyte (GB) of user capacity within the solid-state drive. [Brief explanation of the drawings]

[0005] Features of embodiments of the claimed invention will become apparent as the following detailed description proceeds and by reference to the drawings, in which like numerals refer to like parts and in which:

[0006] [Figure 1] FIG. 1 is a block diagram of an embodiment of a solid-state drive. [Figure 2]2 is an example of a solid-state drive L2P indirect reference table shown in FIG. 1. [Figure 3] 1 is a flow graph of operations performed within a solid-state drive in response to a write command received from an operating system running on a host system. [Figure 4] 1 is a flow graph of operations performed within a solid-state drive in response to a read command received from an operating system running on a host system. [Figure 5] 1 is a flow graph of operations performed within a solid state drive in response to a trim command received from an operating system running on a host system. [Figure 6] FIG. 1 is a block diagram of an embodiment of a computer system including persistent memory in a solid-state drive for storing an L2P indirection table.

[0007] While the following detailed description proceeds with reference to exemplary embodiments of the claimed invention, many alternatives, modifications, and variations thereon will be apparent to those skilled in the art. Accordingly, it is intended that the claimed invention be broadly construed and defined as set forth in the appended claims. DETAILED DESCRIPTION OF THE INVENTION

[0008] The L2P address table (also referred to as an L2P indirection table or L2P table) is stored in byte-addressable volatile memory (e.g., dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM)). The L2P table is stored in the byte-addressable volatile memory to accelerate reading of physical block addresses from the L2P indirection table to access physical blocks of block-addressable non-volatile memory (e.g., NAND flash memory) within the solid-state drive. The byte-addressable volatile memory for storing the L2P indirection table may be included in the solid-state drive or in a host communicatively coupled to the solid-state drive.

[0009] The L2P indirection table may be stored in a host memory buffer, e.g., a portion of the system DRAM. With every write (update) to the L2P indirection table in the host memory buffer, the L2P indirection table stored in the block-addressable non-volatile memory of the solid-state drive is simultaneously written (write-through mode). The performance of writing to the L2P table is based on the longest write time, i.e., the time to write to the block-addressable non-volatile memory or the host memory buffer.

[0010] The L2P indirection table may be stored in byte-addressable volatile memory within the solid-state drive. However, the size of the L2P indirection table depends on the user capacity of the solid-state drive (e.g., approximately 1 megabyte (MB) for every gigabyte (GB) of user capacity). An increase in non-volatile memory (also referred to as user capacity) within the solid-state drive requires a corresponding increase in byte-addressable volatile memory for storing the L2P indirection table.

[0011] In one embodiment, performance of writes to the L2P indirection table is improved by storing the L2P indirection table in persistent memory within a solid-state drive.

[0012] Various embodiments and aspects of the present invention will be described with reference to the details set forth below, and the accompanying drawings illustrate various embodiments. The following description and drawings are illustrative of the present invention and should not be construed as limiting the present invention. Numerous specific details are set forth in order to provide a thorough understanding of various embodiments of the present invention. However, in certain instances, well-known or conventional details are not described in order to simplify the description of the embodiments of the present invention.

[0013] References herein to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment of the invention. The appearances of the phrase "in one embodiment" in various places in the specification do not necessarily all refer to the same embodiment.

[0014] 1 is a block diagram of an embodiment of a solid-state drive 100. The solid-state drive 100 includes a solid-state drive controller circuit 104, persistent memory 106, and block-addressable non-volatile memory 108.

[0015] The solid-state drive controller circuit 104 includes a host interface circuit 102, a persistent memory controller circuit 110, a non-volatile block addressable memory controller circuit 112, a processor 122, firmware 140, hardware assist circuitry 116, and static random access memory 130. The solid-state drive controller circuit 104 may be included in a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0016] A host system may communicate with solid-state drive 100 via a high-speed serial computer expansion bus 120, such as a Peripheral Component Interconnect Express (PCIe) bus. Host interface circuit 102 manages communications over the Peripheral Component Interconnect Express (PCIe) bus. In one embodiment, the host system communicates over the Peripheral Component Interconnect Express (PCIe) bus using the Non-Volatile Memory Express (NVMe) standard protocol. The Non-Volatile Memory Express (NVMe) standard protocol defines a register-level interface for host software to communicate with solid-state drive (SSD) 100 over the Peripheral Component Interconnect Express (PCIe) bus. The NVM Express standard is available at www.nvmexpress.org. The PCIe standard is available at pcisig.com.

[0017] The NVM Express interface allows host software to communicate with the solid-state drive 100 over a high-speed serial computer expansion bus 120 based on a paired submission queue and completion queue mechanism. The submission queue (SQ) 144 and completion queue (CQ) 142 are allocated in memory. The submission queue 144 is a circular buffer of fixed slot size used by the host software to submit commands for execution by the solid-state drive controller circuit 104. The completion queue 142 is a circular buffer with a fixed slot size used to post the status of completed commands.

[0018] The NVMe command set is used for paired submission and completion queues. Host software inserts commands from the NVMe command set into a submission queue 144 for execution by the solid-state drive controller circuit 104. The solid-state drive controller circuit 104 inserts completions into the associated completion queue 142.

[0019] A portion of static random access memory 130 is allocated to an L2P indirection table cache 132, which stores a portion of persistent memory (PM) L2P indirection table 118 stored in persistent memory 106. Another portion of static random access memory 130 is allocated as a buffer 134 for storing data transferred over high-speed serial computer expansion bus 120. In one embodiment, static random access memory 130 is one or more megabytes (MB).

[0020] Another portion of static random access memory 130 is allocated as a physical-to-logical (P2L) indirection table 136. Both L2P indirection table cache 132 and physical-to-logical (P2L) indirection table 136 store physical block addresses in block-addressable non-volatile memory within the solid-state drive that correspond to logical block addresses. Entries in P2L indirection table 136 are static (not updated after being written). Entries in L2P indirection table cache 132 are dynamically updated.

[0021] Static random access memory 130 is volatile memory. Volatile memory is memory whose state (and therefore the data stored therein) is indeterminate when power to the device is interrupted. SRAM is a type of volatile memory that uses latching circuits to store each bit. SRAM is typically used as cache memory because, in contrast to dynamic random access memory (DRAM), data stored in SRAM does not need to be periodically refreshed.

[0022] Persistent memory 106 and block addressable nonvolatile memory 108 are nonvolatile memories. A nonvolatile memory (NVM) device is a memory whose state is determinable even when power to the device is interrupted. In one embodiment, block addressable nonvolatile memory 108 is a NAND flash memory, or more specifically, a multi-threshold level NAND flash memory (e.g., single-level cell (“SLC”), multi-level cell (“MLC”), tri-level cell (“TLC”), quad-level cell (“QLC”), penta-level cell (“PLC”), or some other NAND flash memory).

[0023] The block-addressable non-volatile memory 108 includes at least one non-volatile memory die, e.g., a NAND flash die. Typically, data is written (striped) across many NAND flash dies in an SSD to optimize write bandwidth. The non-volatile memory on the non-volatile memory die includes multiple blocks, each block includes multiple pages. Each page in the multiple pages stores data and associated metadata. In one embodiment, the non-volatile memory die has 2048 blocks, each block has 64 pages, and each page can store 2048 bytes of data and 64 bytes of metadata.

[0024] The persistent memory 106 is a byte-addressable, write-in-place, nonvolatile memory. Examples of byte-addressable, write-in-place, nonvolatile memory devices include three-dimensional cross-point memory devices, single or multi-level phase change memories (PCM) or phase change memories with switches (PCMS), INTEL OPTANE, nonvolatile memory devices using chalcogenide phase change materials (e.g., chalcogenide glasses), resistive memories including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memories (CB-RAM), nanowire memories, ferroelectric random access memories (FeRAM, RAM), magnetoresistive random access memories (MRAM) incorporating memristor technology, spin-transfer torque (STT)-MRAM, spintronic magnetic junction memory-based devices, magnetic tunnel junction (MTJ)-based devices, domain wall (DW) and spin orbit transfer (SOT)-based devices, thyristor-based memory devices, or any combination of the above, or other memories.

[0025] A hardware assist circuit 116 (also referred to as circuit 116) manages data transfers between persistent memory 106 and block-addressable non-volatile memory 108. A portion of persistent memory 106 is allocated to store PM L2P indirection table 118. A portion of block-addressable non-volatile memory 108 is used to store master L2P indirection table 148. The size of PM L2P indirection table 118 depends on the capacity of block-addressable non-volatile memory 108 based on a ratio of 1:1000. For example, PM L2P indirection table 118 in persistent memory 106 is 1 megabyte (MB) for every 1 gigabyte (GB) of block-addressable non-volatile memory 108. PM L2P indirection table 118 is a copy of master L2P indirection table 148. Both the PM L2P indirection table 118 and the master L2P indirection table 148 are stored in non-volatile memory and are periodically synchronized during operation of the solid-state drive 100 .

[0026] The remainder of persistent memory 106 may be used to store PM L2P indirection tables 118, user data, persistent memory metadata, and host metadata. Persistent Memory / Host Metadata: In one embodiment, approximately 5% of persistent memory is used to store PM L2P indirection tables 118, approximately 5% is used to store persistent memory / host metadata, and approximately 90% is used to store user data.

[0027] In one embodiment, user data stored in persistent memory 106 may include frequently accessed user data, operating system files, and executable programs. Frequently accessed user data may be referred to as "hot" user data. Infrequently accessed data, also referred to as "cold" user data, may be stored in block-addressable non-volatile memory 108. Persistent memory 106 may be referred to as "storage accelerator memory" because the read latency of persistent memory 106 is less than the read latency of block-addressable non-volatile memory 108.

[0028] In other embodiments, the persistent memory 106 may be SLC NAND and the block addressable nonvolatile memory may be NAND with more than one bit per cell (e.g., MLC, TLC, QLC, PLC NAND). The read latency of SLC NAND is faster than NAND with more than one bit per cell.

[0029] A non-volatile block addressable memory controller circuit 112 within the solid-state drive controller circuit 104 queues and processes commands (e.g., read, write "program") and erase commands to user data stored in the block addressable non-volatile memory 108.

[0030] The solid-state drive 100 does not include dynamic random access memory (DRAM) and may be referred to as a DRAM-less solid-state drive.

[0031] Figure 2 is an example of the PM L2P indirection table 118 shown in Figure 1, which may be stored in the persistent memory 106 shown in Figure 1. Each L2P entry ("row") 204 in the PM L2P indirection table 118 of a solid-state drive stores a physical location ("PLOC") of the block-addressable non-volatile memory 108 within the solid-state drive 100. The physical location corresponds to a logical block address (LBA) (table index from index 0 to MAXLBA). The L2P entry 204 also includes metadata ("META").

[0032] In one embodiment in which the block addressable non-volatile memory 108 in the solid-state drive 100 includes one or more NAND flash dies, the PLOC is the physical location in one or more NAND flash dies where the data is stored at a particular LBA. For example, in the L2P entry 204, the physical location A ("PLOC-A") corresponding to LBA 0 may be NAND flash die-0, block-1, page-1, offset-0.

[0033] Metadata is data that provides information about other data. For example, one bit of the metadata may be a "lock bit" to prevent read / write access to the PLOC in an L2P entry 204 in the L2P indirection table 200. Another bit of the metadata may be a "dirty bit," the state of which indicates whether the user data for the L2P entry 204 has been flushed to the block-addressable non-volatile memory 108 in the solid-state drive 100. The dirty bit of an L2P entry 204 is set to "dirty" if the L2P entry 204 has been written.

[0034] In one embodiment, there are multiple levels of L2P indirection tables: L2P indirection table cache 132, PM L2P indirection table 118, and master L2P indirection table 148. Firmware 140 executed by processor 122 performs an initial lookup for an L2P entry in L2P indirection table cache 132 in static random access memory 130 and a subsequent lookup in PM L2P indirection table 118 in persistent memory 106. If an L2P location is not in L2P indirection table cache 132 in static random access memory 130 or not in PM L2P indirection table 118 in persistent memory 106, the L2P entry is located in master L2P indirection table 148 in block addressable non-volatile memory 108.

[0035] FIG. 3 is a flow graph of the operations performed within solid-state drive 100 in response to a write command received from an operating system running on a host system.

[0036] As previously mentioned, the submission queue is a circular buffer with a fixed slot size. An operating system running within the host system may insert commands into the submission queue for execution by the solid-state drive controller circuit 104. Firmware 140 within processor 122 may fetch commands sequentially from the submission queue and execute the commands in any order.

[0037] At block 300, if there are write commands on the submission queue to be processed, processing continues at block 302.

[0038] In block 302, firmware 140 in processor 122 executes a write command fetched from submission queue 144 in host interface circuit 102. Data received from the host via host interface circuit 102 and destined to be written to solid-state drive 100 is written to buffer 134, and a P2L entry is inserted into P2L indirection table 136.

[0039] In block 304 , the data stored in the buffer 134 is moved to the block addressable non-volatile memory 108 and the P2L entries in the P2L indirection table 136 are inserted into the L2P indirection table cache 132 .

[0040] At block 306, the entries in the L2P indirection table cache 132 are moved to the PM L2P indirection table 118 in persistent memory 106. The number of accumulated entries in the L2P indirection table cache 132 depends on the minimum transfer size for persistent memory 106. Processing continues at block 300 to process another write request from the submission queue.

[0041] 4 is a flow graph of operations performed within solid-state drive 100 in response to a read command received from an operating system running on a host system. In one embodiment, the read command is an NVMe read command. The NVMe read command may be sent to both persistent memory 106 and block-addressable non-volatile memory 108. The NVMe read command may result in the reading of metadata stored in persistent memory 106.

[0042] An operating system running on the host system may insert a read command into a submission queue for execution by firmware 140 in processor 122. Solid-state drive controller circuit 104 fetches the read command from the submission queue. The read command includes a logical block address of data to be read from block-addressable non-volatile memory 108 or persistent memory 106 in solid-state drive 100.

[0043] At block 400 , if there is a read command in the submission queue to be processed, the solid-state drive controller circuit 104 fetches the read command from the submission queue and processing continues at block 402 .

[0044] At block 402, the solid-state drive controller circuit 104 in the solid-state drive 100 retrieves a P2L entry corresponding to the logical block address from the P2L indirection table 136 of the static random access memory 130 in the solid-state drive 100. If a P2L entry exists that corresponds to the logical block address of the data to be read, processing continues at block 404. Otherwise, processing continues at block 406.

[0045] At block 404, the physical address of the physical block corresponding to the logical block address is read from the L2P entry in the P2L indirection table 136. Data is read from the block addressable non-volatile memory 108 at the physical block of the P2L entry in the P2L indirection table 136 that corresponds to the logical block address. Processing continues at block 400 with fetching another read command from the submission queue.

[0046] At block 406, the solid state drive controller circuit 104 in the solid state drive 100 retrieves an L2P entry corresponding to the logical block address from the L2P indirection table cache 132 of the static random access memory 130 in the solid state drive 100. If an L2P entry exists that corresponds to the logical block address of the data to be read, processing continues at block 408. Otherwise, processing continues at block 410.

[0047] At block 408, the physical address of the physical block corresponding to the logical block address is read from the L2P entry of the L2P indirection table cache 132 in the static random access memory 130. Data is read from the block addressable non-volatile memory 108 at the physical block of the L2P entry in the L2P indirection table cache 132 that corresponds to the logical block address. Processing continues at block 400 with fetching another read command from the submission queue.

[0048] At block 410, the solid-state drive controller circuit 104 in the solid-state drive 100 retrieves an L2P entry corresponding to the logical block address from the PM L2P indirection table 118 in the persistent memory 106 in the solid-state drive 100. If an L2P entry exists that corresponds to the logical block address of the data to be read, processing continues at block 412. Otherwise, processing continues at block 400.

[0049] At block 412, the physical address of the physical block corresponding to the logical block address is read from the L2P entry in the PM L2P indirection table 118. The data is read from the physical block in the block-addressable non-volatile memory 108. Processing continues at block 400 with fetching another read command from the submission queue.

[0050] The solid-state drive controller circuit 104 can read and write pages of data from blocks of data in the block-addressable non-volatile memory 108, but can only erase at the block level. The solid-state drive controller circuit 104 cannot overwrite data in the block-addressable non-volatile memory until the data is erased. To ensure that read / write performance is not affected by erase operations, erase operations, also known as "garbage collection," are aggregated. The operating system identifies files and data that are no longer needed and can be erased by issuing a trim command to the solid-state drive 100.

[0051] 5 is a flow graph of operations performed within solid-state drive 100 in response to a trim command received from an operating system running on a host system. An example of a trim command is an NVMe deallocate command. The trim command identifies blocks within block-addressable non-volatile memory 108 that can be erased.

[0052] At block 500 , if there is a trim command in the submission queue to be processed, the solid-state drive controller circuit 104 fetches the trim command from the submission queue and processing continues at block 502 .

[0053] At block 502, the P2L indirection table 136 of the static random access memory 130 in the solid state drive 100 is searched for a P2L entry or entries corresponding to the logical block address or range of logical block addresses to be erased. If a P2L entry exists that corresponds to the logical block address, processing continues at block 504. Otherwise, processing continues at block 406.

[0054] The P2L indirection table entry corresponding to the logical block address is cleared at block 504. Processing continues at block 500.

[0055] At block 506, the solid-state drive controller circuit 104 in the solid-state drive 100 retrieves an L2P entry corresponding to the logical block address from the L2P indirection table cache 132 of the static random access memory 130 in the solid-state drive 100. If an L2P entry exists that corresponds to the logical block address of the data to be read, processing continues at block 508. Otherwise, processing continues at block 510.

[0056] At block 508, the L2P entries in the L2P indirection table cache 132 in the static random access memory 130 are cleared. Processing continues at block 500.

[0057] At block 510, the solid-state drive controller circuit 104 in the solid-state drive 100 retrieves an L2P entry corresponding to the logical block address from the PM L2P indirection table 118 in the persistent memory 106 in the solid-state drive 100. If an L2P entry exists that corresponds to the logical block address of the data to be read, processing continues at block 512. Otherwise, processing continues at block 500.

[0058] At block 512, the L2P entry of the PM L2P indirection table 118 in persistent memory 106 is cleared. For example, all bits in the entry may be cleared by writing all bits to a logical one or a logical zero. Processing continues at block 500.

[0059] Storing the L2P indirection table in persistent memory reduces the frequency and increases the granularity of updates to the PM L2P indirection table 118 in persistent memory 106. Additionally, using the hardware assist circuitry 116 to update the master L2P indirection table 148 in block addressable non-volatile memory 108 provides more bandwidth for updating the master L2P indirection table 148 as well as storing data in the block addressable non-volatile memory 108.

[0060] 6 is a block diagram of an embodiment of a computer system 600 that includes persistent memory 106 within a solid-state drive 100 for storing a PM L2P indirection table 118. Computer system 600 may correspond to a computing device including, but not limited to, a server, a workstation computer, a desktop computer, a laptop computer, and / or a tablet computer.

[0061] Computer system 600 includes a system-on-chip (SOC or SoC) 604 that combines a processor, graphics, memory, and input / output (I / O) control logic into a single SoC package. SoC 604 includes at least one central processing unit (CPU) module 608, a volatile memory controller 614, and a graphics processor unit (GPU) 610. In other embodiments, volatile memory controller 614 may be external to SoC 604. CPU module 608 includes at least one processor core 602 and a level 2 (L2) cache 606.

[0062] Although not shown, each of the processor cores 602 may include one or more instruction / data caches, execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating point units, retirement units, etc. According to one embodiment, the CPU module 608 may correspond to a single-core or multi-core general-purpose processor, such as those offered by Intel® Corporation.

[0063] The graphics processor unit (GPU) 610 may include one or more GPU cores and a GPU cache that may store graphics-related data for the GPU cores. The GPU cores may include one or more execution units and one or more instruction and data caches. The graphics processor unit (GPU) 610 may also include other graphics logic units, such as one or more vertex processing units, rasterization units, media processing units, and codecs, which are not shown in FIG. 6 .

[0064] Within I / O subsystem 612, one or more I / O adapters 616 reside to convert the host communication protocol utilized within processor core 602 to a protocol compatible with a particular I / O device. Some of the protocols for which adapters may be utilized for conversion include Peripheral Component Interconnect (PCI) Express (PCIe), Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), and Institute of Electrical and Electronics Engineers (IEEE) 1594 "Firewire."

[0065] The I / O adapter 616 may communicate with external I / O devices 624, which may include, for example, user interface devices including a display and / or touchscreen display 640, printers, keypads, keyboards, communication logic, wired and / or wireless, and storage devices including hard disk drives (“HDDs”), solid state drives (“SSDs”), removable storage media, digital video disk (DVD) drives, compact disk (CD) drives, redundant array of independent disks (RAID), tape drives, or other storage devices. Multiple storage devices may be communicatively and / or physically coupled together through one or more buses using one or more of a variety of protocols, including, but not limited to, Serial Attached SCSI (Small Computer System Interface) (SAS), Peripheral Component Interconnect Express (PCIe), NVM Express (NVMe) over PCIe (Peripheral Component Interconnect Express), and Serial Advanced Technology Attachment (SATA).

[0066] There may also be one or more wireless protocol I / O adapters. Examples of wireless protocols include IEEE 802.15 and Bluetooth 4.0 used in personal area networks, IEEE 802.11-based wireless protocols used in wireless local area networks, and cellular protocols, among others.

[0067] The I / O adapter 616 may also communicate with a solid-state drive (“SSD”) 100 including a solid-state drive controller circuit 104 and persistent memory 106 to store the PM L2P indirection table 118 described in connection with FIG. 1 .

[0068] I / O adapter 616 may include a Peripheral Component Interconnect Express (PCIe) adapter communicatively coupled to host interface circuit 102 within solid-state drive 100 using NVMe (NVM Express) via the PCIe (Peripheral Component Interconnect Express) protocol over high-speed serial computer expansion bus 120. The Non-Volatile Memory Express (NVMe) standard defines a register-level interface for host software to communicate with non-volatile memory subsystems (e.g., solid-state drives (SSDs) over Peripheral Component Interconnect Express (PCIe), a high-speed serial computer expansion bus). The NVM Express standard is available at www.nvmexpress.org. The PCIe standard is available at www.pcisig.com.

[0069] Volatile memory is memory whose state (and therefore the data stored therein) is indeterminate when power to the device is interrupted. Dynamic volatile memory requires the data stored in the device to be updated in order to maintain its state. Examples of dynamic volatile memory include DRAM (Dynamic Random Access Memory) or some variants such as Synchronous DRAM (SDRAM). The memory subsystem described herein may be based on DDR3 (Double Data Rate version 3, originally released by JEDEC (Joint Electron Device Engineering Council) on June 27, 2007), DDR4 (DDR version 4, initial specification published by JEDEC in September 2012), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3, JESD209-3B published by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4 first published by JEDEC in August 2014), WIO2 (Wide Input / Output version 2, JESD229-2 first published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD325 first published by JEDEC in October 2013), DDR5 (DDR It may be compatible with many memory technologies, such as LPDDR5 (currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM Version 2) currently under discussion by JEDEC or others, or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. JEDEC standards are available at www.jedec.org.

[0070] Operating system 642 is software that manages computer hardware, including memory allocation and access to I / O devices. Examples of operating systems include Microsoft® Windows®, Linux®, iOS®, and Android®.

[0071] The flow diagrams illustrated herein provide examples of sequences of various processing operations. The flow diagrams may depict operations to be performed by software or firmware routines, as well as physical operations. In one embodiment, the flow diagrams may depict the states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although the order of operations is shown in a particular sequence or order, this can be changed unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples, and processes may be performed in a different order, and some operations may be performed in parallel. Also, one or more operations may be omitted in various embodiments, and therefore not all operations are required in all embodiments. Other process flows are possible.

[0072] To the extent various operations or functions are described herein, they may be described or defined as software code, instructions, configuration, and / or data. Content may be directly executable ("object" or "executable"), source code, or differential code ("delta" or "patch" code). The software content of the embodiments described herein may be provided via an article of manufacture with content stored thereon, or by operating a communications interface and transmitting data over the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations, and machine-readable storage includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), including recordable and non-recordable media (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism for interfacing to either a hardwired, wireless, optical, or other medium for communicating with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. A communications interface may be configured by providing configuration parameters and / or sending signals that prepare the communications interface to provide data signals describing software content. A communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0073] The various components described herein may be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. A component may be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0074] In addition to what is described herein, various modifications can be made to the disclosed embodiments and implementations of the invention without departing from their scope.

[0075] Therefore, the illustrations and examples herein should be construed in an illustrative, and not a limiting sense. The scope of the present invention should be defined solely by reference to the claims that follow. [Other possible items] [Item 1] a block addressable non-volatile memory for storing data; a persistent memory for storing a logical-to-physical address indirection table, the logical-to-physical address indirection table having a plurality of entries, each entry storing a physical block address in the block-addressable non-volatile memory assigned to a logical block address; a solid-state drive controller circuit communicatively coupled to the persistent memory and the block-addressable non-volatile memory; A solid state drive comprising: The solid state drive controller circuit includes: a volatile memory for storing a logical-to-physical address indirection table cache; an assist circuit communicatively coupled to the volatile memory, the assist circuit monitoring the logical-to-physical address indirection table cache and writing dirty logical-to-physical entries in the logical-to-physical address indirection table cache to the logical-to-physical address indirection table in the persistent memory; having Solid state drive. [Item 2] 2. The solid state drive of claim 1, wherein the volatile memory includes a buffer that temporarily stores data written by the assist circuit in the block addressable nonvolatile memory. [Item 3] 2. The solid state drive of claim 1, wherein in response to a command to write data to a logical address in the block addressable nonvolatile memory, data is written to a physical address in the block addressable nonvolatile memory, and an entry in the logical-to-physical address indirect reference table cache associated with the physical address and the logical address is set to dirty. [Item 4] 2. The solid state drive of claim 1, wherein in response to a command to read data from a logical block address in the block-addressable nonvolatile memory, an entry for a physical block address in the block-addressable nonvolatile memory associated with the logical block address is searched in the logical-to-physical address indirect reference table cache. [Item 5] 2. The solid state drive of claim 1, wherein in response to a command to read data from a logical block address in the block addressable nonvolatile memory, an entry for a physical block address in the block addressable nonvolatile memory associated with the logical block address is searched in the logical-to-physical address indirection table in persistent memory. [Item 6] 2. The solid state drive of claim 1, wherein in response to a command to erase data from a logical block address in the block addressable nonvolatile memory, an entry for a physical block address in the block addressable nonvolatile memory associated with the logical block address is searched in the logical-to-physical address indirect reference table in persistent memory. [Item 7] 2. The solid state drive of item 1, wherein the block addressable nonvolatile memory is NAND and the persistent memory is a three-dimensional crosspoint. [Item 8] storing data in a block addressable non-volatile memory; storing a logical-to-physical address indirection table in persistent memory, the logical-to-physical address indirection table having a plurality of entries, each entry storing a physical block address in the block-addressable non-volatile memory assigned to a logical block address; storing a logical-to-physical address indirection table cache in a volatile memory; monitoring the logical-to-physical address indirection table cache and writing dirty logical-to-physical entries in the logical-to-physical address indirection table cache to the logical-to-physical address indirection table in the persistent memory; [Item 9] 9. The method according to claim 8, wherein the volatile memory includes a buffer that temporarily stores data to be written to the block-addressable nonvolatile memory. [Item 10] writing data to a physical address in the block addressable nonvolatile memory in response to a command to write data to a logical address in the block addressable nonvolatile memory; setting entries in the logical-to-physical address indirection table cache associated with the physical address and the logical address to dirty; Item 10. The method of item 9, further comprising: [Item 11] in response to a command to read data from a logical block address in the block-addressable nonvolatile memory, searching the logical-to-physical address indirection table cache for an entry for a physical block address in the block-addressable nonvolatile memory associated with the logical block address. Item 11. The method of item 10, further comprising: [Item 12] in response to a command to read data from a logical block address in the block-addressable non-volatile memory, searching the logical-to-physical address indirection table in persistent memory for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address. Item 12. The method of item 11, further comprising: [Item 13] in response to a command to erase data from a logical block address in the block-addressable non-volatile memory, searching the logical-to-physical address indirection table in persistent memory for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address. Item 13. The method of item 12, further comprising: [Item 14] Item 9. The method of item 8, wherein the block addressable nonvolatile memory is NAND and the persistent memory is a three-dimensional cross-point memory. [Item 15] a processor; a solid state drive communicatively coupled to the processor; A system comprising: The solid state drive is a block addressable non-volatile memory for storing data; a persistent memory for storing a logical-to-physical address indirection table, the logical-to-physical address indirection table having a plurality of entries, each entry storing a physical block address in the block-addressable non-volatile memory assigned to a logical block address; a solid-state drive controller circuit communicatively coupled to the persistent memory and the block-addressable non-volatile memory; and The solid state drive controller circuit includes: a volatile memory for storing a logical-to-physical address indirection table cache; an assist circuit communicatively coupled to the volatile memory, the assist circuit monitoring the logical-to-physical address indirection table cache and writing dirty logical-to-physical entries in the logical-to-physical address indirection table cache to the logical-to-physical address indirection table in the persistent memory; Including, the system. [Item 16] Item 16. The system of item 15, wherein the volatile memory includes a buffer that temporarily stores data written by the assist circuit in the block-addressable nonvolatile memory. [Item 17] Item 16. The system of item 15, wherein in response to a command to write data to a logical address in the block addressable nonvolatile memory, data is written to a physical address in the block addressable nonvolatile memory, and an entry in the logical-to-physical address indirect reference table cache associated with the physical address and the logical address is set dirty. [Item 18] Item 16. The system of item 15, wherein in response to a command to read data from a logical block address in the block-addressable nonvolatile memory, the logical-to-physical address indirection table cache is searched for an entry for a physical block address in the block-addressable nonvolatile memory associated with the logical block address. [Item 19] Item 16. The system of item 15, wherein in response to a command to read data from a logical block address in the block-addressable non-volatile memory, an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address is searched in the logical-to-physical address indirection table in persistent memory. [Item 20] 16. The system of claim 15, wherein in response to a command to erase data from a logical block address in the block-addressable non-volatile memory, the logical-to-physical address indirection table in persistent memory is searched for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address.

Claims

1. a block addressable non-volatile memory for storing data; a persistent memory for storing a logical-to-physical address indirection table, the logical-to-physical address indirection table having a plurality of entries, each entry storing a physical block address in the block-addressable non-volatile memory assigned to a logical block address; a solid-state drive controller circuit communicatively coupled to the persistent memory and the block-addressable non-volatile memory; A solid state drive comprising: The solid state drive controller circuit a volatile memory for storing a logical-to-physical address indirection table cache; an assist circuit communicatively coupled to the volatile memory, the assist circuit monitoring the logical-to-physical address indirection table cache and writing dirty logical-to-physical entries in the logical-to-physical address indirection table cache to the logical-to-physical address indirection table in the persistent memory; having Solid state drive.

2. The solid-state drive of claim 1 , wherein the volatile memory includes a buffer that temporarily stores data written by the assist circuit in the block-addressable nonvolatile memory.

3. 3. The solid state drive of claim 1, wherein in response to a command to write data to a logical address in the block addressable nonvolatile memory, data is written to a physical address in the block addressable nonvolatile memory, and an entry in the logical-to-physical address indirect reference table cache associated with the physical address and the logical address is set to dirty.

4. 4. The solid state drive of claim 1, wherein in response to a command to read data from a logical block address in the block addressable nonvolatile memory, an entry for a physical block address in the block addressable nonvolatile memory associated with the logical block address is searched in the logical-to-physical address indirect reference table cache.

5. 5. The solid-state drive of claim 1, wherein in response to a command to read data from a logical block address in the block-addressable non-volatile memory, an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address is searched in the logical-to-physical address indirection table in persistent memory.

6. 6. The solid state drive of claim 1, wherein in response to a command to erase data from a logical block address in the block addressable non-volatile memory, an entry for a physical block address in the block addressable non-volatile memory associated with the logical block address is searched in the logical-to-physical address indirection table in persistent memory.

7. 7. The solid state drive of claim 1, wherein the block addressable non-volatile memory is NAND and the persistent memory is 3D crosspoint.

8. storing data in a block addressable non-volatile memory; storing a logical-to-physical address indirection table in persistent memory, the logical-to-physical address indirection table having a plurality of entries, each entry storing a physical block address in the block-addressable non-volatile memory assigned to a logical block address; storing a logical-to-physical address indirection table cache in a volatile memory; monitoring the logical-to-physical address indirection table cache and writing dirty logical-to-physical entries in the logical-to-physical address indirection table cache to the logical-to-physical address indirection table in the persistent memory; A method comprising:

9. 9. The method of claim 8, wherein the volatile memory includes a buffer that temporarily stores data to be written to the block-addressable non-volatile memory.

10. writing data to a physical address within said block addressable non-volatile memory in response to a command to write data to a logical address within said block addressable non-volatile memory; setting entries in the logical-to-physical address indirection table cache associated with the physical address and the logical address to dirty; The method of claim 8 or 9, further comprising:

11. in response to a command to read data from a logical block address in the block-addressable nonvolatile memory, searching the logical-to-physical address indirection table cache for an entry for a physical block address in the block-addressable nonvolatile memory associated with the logical block address. The method of any one of claims 8 to 10, further comprising:

12. in response to a command to read data from a logical block address in the block-addressable non-volatile memory, searching the logical-to-physical address indirection table in persistent memory for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address. The method of any one of claims 8 to 11, further comprising:

13. in response to a command to erase data from a logical block address in the block-addressable non-volatile memory, searching the logical-to-physical address indirection table in persistent memory for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address.

13. The method of claim 8, further comprising:

14. 14. The method of claim 8, wherein the block addressable non-volatile memory is a NAND and the persistent memory is a three-dimensional cross-point memory.

15. Apparatus comprising means for carrying out the method according to any one of claims 8 to 14.

16. a processor; a solid state drive communicatively coupled to the processor; A system comprising: The solid state drive is a block addressable non-volatile memory for storing data; a persistent memory for storing a logical-to-physical address indirection table, the logical-to-physical address indirection table having a plurality of entries, each entry storing a physical block address in the block-addressable non-volatile memory assigned to a logical block address; a solid-state drive controller circuit communicatively coupled to the persistent memory and the block-addressable non-volatile memory; and The solid state drive controller circuit a volatile memory for storing a logical-to-physical address indirection table cache; an assist circuit communicatively coupled to the volatile memory, the assist circuit monitoring the logical-to-physical address indirection table cache and writing dirty logical-to-physical entries in the logical-to-physical address indirection table cache to the logical-to-physical address indirection table in the persistent memory; Including, the system.

17. 17. The system of claim 16, wherein the volatile memory includes a buffer that temporarily stores data written by the assist circuitry in the block-addressable non-volatile memory.

18. 18. The system of claim 16 or 17, wherein in response to a command to write data to a logical address in the block addressable non-volatile memory, data is written to a physical address in the block addressable non-volatile memory and an entry in the logical-to-physical address indirection table cache associated with the physical address and the logical address is set dirty.

19. 19. The system of claim 16, wherein in response to a command to read data from a logical block address in the block-addressable non-volatile memory, the logical-to-physical address indirection table cache is searched for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address.

20. 20. The system of claim 16, wherein in response to a command to read data from a logical block address in the block-addressable non-volatile memory, the logical-to-physical address indirection table in persistent memory is searched for an entry for a physical block address in the block-addressable non-volatile memory associated with the logical block address.

21. 21. The system of claim 16, wherein in response to a command to erase data from a logical block address in the block addressable non-volatile memory, the logical-to-physical address indirection table in persistent memory is searched for an entry for a physical block address in the block addressable non-volatile memory associated with the logical block address.

22. A computer program for causing a machine to carry out the method according to any one of claims 8 to 14.

23. A machine-readable recording medium storing the computer program of claim 22.

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