Apparatus and method for performing a predetermined operation using a circuit

Abstract

To provide a method and device for performing a prescribed operation by using a circuit in which a parasitic capacitance exists.SOLUTION: In a circuit 800 with a parasitic capacitance Cp existing, a time point when a sampling capacitor voltage Vbot applied to a sampling capacitor Ss reaches a first reference voltage is determined as a switching time point in a forward process, and the sampling capacitor is connected to the ground or prescribed voltage to cause a power source part 830 to perform floating at the switching time point. Further, a time point when a power source part voltage Vtop applied to the power source part reaches a second reference voltage is determined as an end time point, and a prescribed operation is performed on the basis of the end time point in a reverse direction process after the switching time point.SELECTED DRAWING: Figure 8A

Description

[Technical Field]

[0001] The present disclosure relates to an apparatus and method for performing a predetermined operation using a circuit. [Background technology]

[0002] Multiply-and-accumulate (MAC) operations, also known as multiply-and-accumulate (MAC) operations, affect the performance of various applications. For example, in machine learning, multiple layers of MAC operations can be performed.

[0003] The input signals are considered to form input vectors. The input signals may be data for an image, a byte stream, or other data set. The input signals are multiplied by a matrix of values or weights. The output signals are the result of a MAC operation on the input signals and their corresponding output vectors. The output vectors are provided as input vectors for the next layer of MAC operations.

[0004] Such a process is repeated for multiple layers. Because a large number of MAC operations are performed, the performance of the application is mainly determined by the performance of the MAC operations. Therefore, it is desirable to perform the MAC operations efficiently and reliably with low power consumption and high speed.

[0005] Meanwhile, parasitic capacitance exists in the circuit that performs MAC operation, and the parasitic capacitance can cause errors in the MAC operation results. Therefore, there is a need for research to reduce errors in the operation results due to the parasitic capacitance. Summary of the Invention [Problem to be solved by the invention]

[0006] It is an object of the present invention to provide an apparatus and method for performing a predetermined operation using a circuit, and to provide a computer-readable recording medium having recorded thereon a program for executing the method on a computer. The technical problem to be solved is not limited to the above-mentioned technical problem, and other technical problems may exist. [Means for solving the problem]

[0007] As a technical means for solving the above technical problem, a first aspect of the present disclosure may provide a method for performing a predetermined operation using a circuit, wherein one end of a resistor group including a plurality of resistors connected in series is connected to a power supply unit and the other end of the resistor group is connected to a sampling capacitor, and parasitic capacitance exists at each node between the plurality of resistors, the method including: determining, in a forward direction process, a time point when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage, as a switching time point; connecting the sampling capacitor to ground or a predetermined voltage at the switching time point, thereby floating the power supply unit; determining, in a reverse direction process after the switching time point, a time point when a power supply unit voltage applied to the power supply unit reaches a second reference voltage, as an end time point; and performing a predetermined operation based on the end time point.

[0008] Also, a method can be provided in which the first reference voltage is a value obtained by subtracting a predetermined percentage (%) from the DC voltage supplied to the power supply unit, and the second reference voltage is a value obtained by subtracting "100 - the predetermined percentage" (%) from the DC voltage supplied to the power supply unit.

[0009] Also, the step of performing the predetermined calculation may include a step of performing a product-sum calculation or calculating a total resistance value of the resistor group based on the end time point.

[0010] A second aspect of the present disclosure can provide a method for performing a predetermined operation using a circuit, wherein a resistor group including a plurality of resistors connected in series has one end connected to a power supply and the other end connected to a sampling capacitor, a parasitic capacitance exists at each node between the plurality of resistors, the resistor group is divided into a first resistor group and a second resistor group, the first resistor group and the second resistor group are connected in parallel, and an arrangement order of the resistors in the first resistor group is opposite to an arrangement order of the resistors in the second resistor group, the method including: determining, as an end time point, a time point when a sampling capacitor voltage applied to the sampling capacitor reaches a reference voltage; and performing a predetermined operation based on the end time point.

[0011] a sampling capacitor connected in series with the plurality of resistors; a parasitic capacitance present at each node between the plurality of resistors; a first comparator that compares a sampling capacitor voltage applied to the sampling capacitor with a first reference voltage in a forward direction and outputs first time information of a time point when the sampling capacitor voltage reaches the first reference voltage; a processor that connects the sampling capacitor to ground or a predetermined voltage when the first time information is output, thereby floating the power supply unit; and a second comparator that compares a power supply voltage applied to the power supply with a second reference voltage in a reverse direction after the first time information is output, and outputs second time information of a time point when the power supply voltage reaches the second reference voltage, wherein the processor performs a predetermined operation based on the second time information.

[0012] A fourth aspect of the present disclosure may provide an apparatus including a circuit for performing a predetermined operation, the apparatus including: a power supply unit connected to one end of the circuit; a resistor group including a plurality of resistors connected in series from one end of the circuit to the other end; a sampling capacitor connected in series with the plurality of resistors; parasitic capacitance present at each node between the plurality of resistors; a comparator that compares a sampling capacitor voltage applied to the sampling capacitor with a reference voltage and outputs time information of a point in time when the sampling capacitor voltage reaches the reference voltage; and a processor that performs a predetermined operation based on the time information, wherein the resistor group is divided into a first resistor group and a second resistor group, the first resistor group and the second resistor group are connected in parallel, and an arrangement order of the resistors in the first resistor group is opposite to an arrangement order of the resistors in the second resistor group.

[0013] A fifth aspect of the present disclosure can provide a computer-readable recording medium having recorded thereon a program for causing a computer to execute the method of the first or second aspect. [Effects of the Invention]

[0014] According to the present disclosure described above, it is possible to reduce calculation errors caused by parasitic capacitance present in a circuit.

[0015] Furthermore, according to the above-mentioned disclosure, in a circuit in which parasitic capacitance exists, by sequentially performing a forward process and a reverse process, even if at least some of the resistors in the circuit have different resistance values, the same calculation result can be obtained as long as the total resistance value of the resistors is the same. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a diagram illustrating a circuit for performing a predetermined operation according to one embodiment. [Figure 2] 1 is a diagram illustrating an example of performing a product-sum operation using a resistive memory device according to an embodiment; [Figure 3] 1 is a diagram illustrating a multiply-accumulate circuit having multiple input lines and multiple output lines according to an embodiment; [Figure 4] 1 is a diagram illustrating a time-to-digital converter according to an embodiment. [Figure 5] 1 is a diagram illustrating a conversion operation of a time-to-digital converter according to an embodiment. [Figure 6] 1 is a diagram illustrating a sampling capacitor voltage measured in a circuit without parasitic capacitance, according to one embodiment. [Figure 7A] 1 is a diagram illustrating a sampling capacitor voltage measured in a circuit in which parasitic capacitance exists, according to one embodiment. [Figure 7B] 1 is a diagram illustrating a sampling capacitor voltage measured in a circuit in which parasitic capacitance exists, according to one embodiment. [Figure 8A] 1 is a diagram illustrating a method for performing a predetermined operation using a circuit having parasitic capacitance, according to an embodiment; [Figure 8B] 1 is a diagram illustrating a method for performing a predetermined operation using a circuit having parasitic capacitance, according to an embodiment; [Figure 9] 1 is a diagram illustrating a circuit for performing a predetermined operation through a forward process and a backward process according to an embodiment. [Figure 10] 1 is a diagram illustrating a circuit for performing a predetermined operation through a forward process according to an embodiment. [Figure 11] 1 is a flowchart illustrating a method for performing a predetermined operation using a circuit according to an embodiment. [Figure 12] 1 is a flowchart illustrating a method for performing a predetermined operation using a circuit according to an embodiment. [Figure 13] 10 is a diagram illustrating an example of a neural network operation implemented by a product-sum operation circuit according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0017] The appearances of phrases such as "in some embodiments" or "in one embodiment" in various places in this specification do not necessarily refer to the same embodiment.

[0018] Some embodiments of the present disclosure are illustrated using functional blocks and various processing steps. Some or all of these functional blocks may be embodied in any number of hardware and / or software components that perform specific functions. For example, the functional blocks of the present disclosure may be embodied in one or more microprocessors or in circuitry for a given function. For example, the functional blocks of the present disclosure may be embodied in any number of programming or scripting languages. The functional blocks may also be embodied in algorithms executed by one or more processors. The present disclosure may employ conventional techniques for electronic configuration, signal processing, and / or data processing. Terms such as "mechanism," "element," "means," and "component" are used broadly and are not limited to mechanical or physical components.

[0019] Furthermore, connecting lines or connecting members between components shown in the drawings are merely illustrative of functional connections and / or physical or circuit connections, and in an actual device, connections between components are represented by various alternative or additional functional connections, physical connections, or circuit connections.

[0020] The present disclosure will now be described in detail with reference to the accompanying drawings.

[0021] FIG. 1 is a diagram illustrating a circuit for performing a predetermined operation according to one embodiment.

[0022] Referring to FIG. 1, a circuit 100 includes a resistor group 110 and a sampling capacitor 120 .

[0023] The resistor group 110 includes a plurality of resistors connected in series. One end of the resistor group 110 is connected to the power supply unit 150, and the other end of the resistor group 110 is connected to the sampling capacitor 120.

[0024] Each of the plurality of resistors included in the resistor group 110 is also a resistive memory element. The resistive memory element is an element that can be switched between different resistance states depending on a voltage or current applied across both ends, and may have a single-layer structure or a multi-layer structure including various materials having multiple resistance states, for example, metal oxides such as transition metal oxides and perovskite-based materials, phase-change materials such as chalcogenide-based materials, ferroelectric materials, ferromagnetic materials, etc. The operation of the resistive memory element to change from a high resistance state to a low resistance state is called a set operation, and the operation of changing from a low resistance state to a high resistance state is called a reset operation.

[0025] A specific example in which each of the resistors included in the resistor group 110 operates as a resistive memory element will be described later with reference to FIG.

[0026] The sampling capacitor 120 is connected in series with the resistors included in the resistor group 110. The sampling capacitor 120 is charged by applying a DC voltage to the power supply unit 150. The sampling capacitor voltage V bot is a voltage corresponding to the amount of charge stored in the sampling capacitor 120, and may change over time with a time constant determined by the capacitance of the sampling capacitor 120 and the total resistance value of the resistor group 110.

[0027] Specifically, the sampling capacitor voltage V bot can be expressed as the following Equation 1. In Equation 1, VDD is the DC voltage applied to the power supply unit 150, C s is the capacitance of the sampling capacitor 120, R i denotes the plurality of resistors included in the resistor group 110.

[0028]

number

[0029] The comparator 130 detects the sampling capacitor voltage V corresponding to the amount of charge stored in the sampling capacitor 120. bot and the reference voltage V ref After comparing with the above, the comparison result is output.

[0030] For example, in a situation where the sampling capacitor 120 is being charged, the comparator 130 detects the sampling capacitor voltage V bot and the reference voltage V ref and compare the sampling capacitor voltage V bot is the reference voltage V ref The output signal of the comparator 130 is communicated to a time-to-digital converter (TDC) 140.

[0031] The time-to-digital converter 140 converts the time taken from the reference time t0 to the end time t1 at which the output signal is received from the comparator 130 into a digital value, and outputs the digital value.

[0032] A predetermined operation is performed based on the digital value output from the time-to-digital converter 140. In one embodiment, the operation result may be a product-sum operation result. In another embodiment, the operation result may be the total resistance value of the circuit 100.

[0033] FIG. 2 is a diagram illustrating an example of performing a product-sum operation using a resistive memory device according to an embodiment.

[0034] Referring to FIG. 2, each of the plurality of resistors can operate as a resistive memory element.

[0035] In an initial state, the plurality of resistors may all be in a state of relatively low conductivity, i.e., a high resistance state. If at least some of the plurality of resistors are in a low resistance state, an initialization operation is further required to set them to a high resistance state.

[0036] Each of the plurality of resistors may have a predetermined threshold required for a change in resistance and / or conductivity. More specifically, if a voltage or current smaller than the predetermined threshold is applied across the plurality of resistors, the conductivity of the plurality of resistors may not change, and if a voltage or current larger than the predetermined threshold is applied across the plurality of resistors, the conductivity of the plurality of resistors may change.

[0037] In this state, to output specific data as a result of a specific column wire 220, an input signal corresponding to the specific data is applied to the row wires 210. At this time, the input signal is expressed as application of an electrical pulse to each row wire 210. For example, when an input signal corresponding to data '0011' is applied to the row wires 210, no electrical pulse is applied to the row wires 210 corresponding to '0', e.g., the first and second row wires 210A and 210B, and only the row wires 210 corresponding to '1', e.g., the third and fourth row wires 210C and 210D, are applied with an appropriate voltage or current for output.

[0038] As an example, if a column wiring 220 that outputs specific data has already been determined, the column wiring 220 is driven so that a voltage greater than or equal to the voltage required during the set operation (hereinafter referred to as the set voltage) is applied to a plurality of resistors located at the intersection with the row wiring 210 corresponding to '1', and the remaining column wiring 220 is driven so that a voltage lower than the set voltage is applied to the remaining plurality of resistors.

[0039] For example, if the magnitude of the set voltage is Vset and the column wire 220 that outputs data '0011' is determined to be the third column wire 220C, the magnitude of the electrical pulse applied to the third and fourth row wires 210C and 210D is greater than Vset, and the voltage applied to the third column wire 220C is 0V, so that the first and second synapses 231 and 232 located at the intersections of the third column wire 220C and the third and fourth row wires 210C and 210D are applied with a voltage greater than Vset. As a result, the first and second synapses 231 and 232 are also in a low resistance state.

[0040] The conductance of the first and second synapses 231 and 232 in the low resistance state gradually increases as the number of electrical pulses increases. The magnitude and width of the applied electrical pulses are substantially constant. The voltage applied to the remaining column wires, i.e., the first, second, and fourth column wires 220A, 220B, and 220D, may have a value between 0V and Vset, e.g., 1 / 2Vset, so that the remaining resistors, excluding the first and second synapses 231 and 232, are applied with a voltage lower than Vset. Therefore, the resistance state of the remaining resistors, excluding the first and second synapses 231 and 232, remains unchanged. The flow of current or electrons in this case is indicated by the dotted arrows.

[0041] FIG. 3 is a diagram illustrating a multiply-accumulate circuit having multiple input lines and multiple output lines according to one embodiment.

[0042] The multiply-accumulate circuit 300 according to one embodiment includes a plurality of input lines capable of individually receiving input signals and a plurality of output lines for individually outputting output signals, each of which includes a plurality of resistors, a sampling capacitor 320, and a comparator 330. Each of the plurality of input lines intersects with a plurality of output lines.

[0043] 3 includes m input lines and n output lines, a plurality of resistors, a plurality of capacitors, a plurality of comparators, a time-to-digital converter 340, and an output section 350.

[0044] The resistors may be arranged along the output lines and the input lines, for example, along the output lines and for each of the input lines, with each resistor configured to receive a voltage via the input line in which the resistor 310 is arranged.

[0045] For example, a resistor placed along the j-th input line 391 reduces the j-th input voltage signal b j In response to the start signal, the input voltage signals b1 to b m The resistors may have voltages that indicate binary values. For example, an input voltage signal that indicates a bit value of 1 may represent any voltage, and an input voltage signal that indicates a bit value of 0 may represent a floating voltage. The structure in which multiple resistors are arranged may also be referred to as a memory array 390.

[0046] The plurality of capacitors may be individually arranged for each of the plurality of output lines, and each of the plurality of capacitors is connected to the other end of the resistor arranged along the output line on which the corresponding sampling capacitor 320 is arranged, and to the comparator 330.

[0047] Each of the plurality of capacitors can be charged in response to a voltage received across the corresponding resistor. For example, the sampling capacitor 320 disposed on the i-th output line 392 can be charged by a voltage applied to the resistor disposed on the i-th output line 392.

[0048] In one embodiment, the multiple capacitors can have the same capacitance because multiple output lines share the output of a single global counter, and each output line must have a charging or discharging time of the same scale. The charging and discharging times can be scaled proportionally to the time constants corresponding to the combined resistance and capacitance.

[0049] The plurality of comparators may be individually arranged for each of the plurality of output lines, and each of the plurality of comparators is connected to the other end of the resistor arranged along the output line on which the corresponding comparator 330 is arranged, and to the sampling capacitor 320.

[0050] Each of the plurality of comparators can output a result of comparing the sampling capacitor voltage of the corresponding sampling capacitor 320 with a reference voltage. For example, the comparator 330 arranged on the ith output line 392 compares the sampling capacitor voltage of the sampling capacitor 320 arranged on the ith output line 392 with a reference voltage. The comparator 330 arranged on the ith output line 392 outputs the ith count end signal STOP in response to the sampling capacitor voltage exceeding the reference voltage. i Output.

[0051] The time-to-digital converter 340 receives the count end signal for each of the plurality of output lines and converts the time information into a digital value. For example, the time-to-digital converter 340 outputs a digital value corresponding to the time information for each of n output lines. The time-to-digital converter 340 outputs n digital values corresponding to the time information. For example, the time-to-digital converter 340 receives the ith count end signal STOP iIn response to receiving a start time corresponding to the start signal START and a count end signal STOP i The i-th time information T indicates the time difference between the end point corresponding to out,i Generate the i-th time information T out,i can also be expressed as the i-th charging time.

[0052] The output unit 350 can output the values mapped to the digital values generated by the time-to-digital converter as output values OUTs of each output line. Thus, the output unit 350 can output the digital value indicating the time information as the output value OUTs indicating a number corresponding to the product-sum operation result. For example, the product-sum operation circuit can output the ith time information T through a mapping table (e.g., a look-up table). out,i The ith output value OUT mapped to i Since an output value is output for each output line, the output section 350 can output n output values for n output lines.

[0053] The following describes a single global counter included in the time-to-digital converter 340.

[0054] FIG. 4 is a diagram illustrating a time-to-digital converter according to an embodiment.

[0055] An exemplary configuration of the time-to-digital converter described in Figure 3 will now be described. The time-to-digital converter includes a single global counter 441 and a reference unit 442.

[0056] The single global counter 441 can output a digital value indicating the time elapsed since a reference time point. The single global counter 441 is connected to comparators of multiple output lines. For example, the single global counter 441 counts the number of clocks CLK generated since the reference time point. Therefore, the single global counter 441 can count the time (e.g., charging time or discharging time) elapsed from the same reference time point for each output line in clock units without any additional synchronization operation.

[0057] The reference unit 442 can refer to the digital value output by the single global counter 441 at the time when the comparison result is output. The reference unit 442 may include a plurality of hold circuits that refer to the comparison results of the comparators of the plurality of output lines. Each of the plurality of hold circuits refers to the time when the comparison result is output from the comparator included in the corresponding output line among the plurality of output lines.

[0058] For example, the ith hold circuit corresponding to the ith output line is connected to the output of the ith comparator, and receives the ith count end signal STOP from the ith comparator. i In response to receiving the ith time information T out,i For example, each hold circuit holds the number of clocks CLK counted by the single global counter 441 at the end point when the count end signal is received. The number of clocks CLK held at the end point corresponds to time information (e.g., charge time or discharge time).

[0059] The single global counter 441 can count the reference clock CLK regardless of whether the multiple hold circuits are held, and each hold circuit of the multiple hold circuits can operate independently of the remaining hold circuits. For example, even if the hold circuit holds time information corresponding to the time when the count end signal is received, the single global counter 441 can continuously count the clock CLK.

[0060] FIG. 5 is a diagram illustrating a conversion operation of a time-to-digital converter according to an embodiment.

[0061] The sampling capacitor voltage 510 of the sampling capacitor placed on any one output line gradually rises along the characteristic response corresponding to the time constant as shown in Figure 5. This is because the capacitor is gradually charged.

[0062] 4 can generate clocks, and the single global counter can count the number of clocks from the start point START. The single global counter counts the number of clocks when the sampling capacitor voltage 510 is equal to the reference voltage V ref The number of clocks can be counted continuously even after the end point STOP, when the count becomes equal to the time t1.

[0063] The hold circuit of the reference section holds a digital value indicated by the number of clocks counted from the start point START to the end point STOP.

[0064] For example, in the example shown in FIG. 5, six clocks are generated from the start point START to the end point STOP, and the hold circuit outputs a digital value of "6."

[0065] FIG. 6 is a diagram illustrating a sampling capacitor voltage measured in a circuit without parasitic capacitance, according to one embodiment.

[0066] 6, a first circuit 600 without parasitic capacitance is shown. The first circuit 600 includes a resistor group 610 and a sampling capacitor 620.

[0067] The resistor group 610 includes a plurality of resistors connected in series. One end of the resistor group 610 is connected to the power supply unit 630, and the other end of the resistor group 610 is connected to the sampling capacitor 620.

[0068] The sampling capacitor 620 is connected in series with the resistors included in the resistor group 610. The sampling capacitor 620 is charged by applying a DC voltage to the power supply unit 630. The sampling capacitor voltage V bot is a voltage corresponding to the amount of charge stored in the sampling capacitor 620, and may change over time with a time constant determined by the capacitance of the sampling capacitor 620 and the total resistance value of the resistor group 610.

[0069] Specifically, the sampling capacitor voltage V bot can be expressed as the above-mentioned Equation 1. Even if at least some of the resistors included in the resistor group 610 have different resistance values, if the total resistance value of the resistors is the same, the sampling capacitor voltage V bot In other words, if the total resistance of the multiple resistors is the same in both cases where a resistor with a large resistance value is located close to the power supply unit 630 and where a resistor with a small resistance value is located close to the power supply unit 630, then τ in Equation 1 ideal is the same, so the sampling capacitor voltage V bot will have the same graph, which can also be confirmed through Equation 1.

[0070] 7A and 7B are diagrams illustrating a sampling capacitor voltage measured in a circuit in which a parasitic capacitance exists, according to one embodiment.

[0071] 7A is a diagram illustrating a second circuit 700 having parasitic capacitance according to one embodiment. The second circuit 700 includes a resistor group 710 and a sampling capacitor 720. However, compared to the first circuit 600 of FIG. 6, the second circuit 700 of FIG. 7A has parasitic capacitance. A circuit used in an actual implementation will have parasitic capacitance, similar to the second circuit 700.

[0072] The parasitic capacitance present in the second circuit 700 causes the sampling capacitor voltage V bot can be expressed as the following Equation 2. Equation 2 is based on the Elmore delay model.

[0073] In the following equation 2, VDD is the DC voltage applied to the power supply unit 730, C s is the capacitance of the sampling capacitor 720, R i means a plurality of resistors included in the resistor group 710. p denotes the parasitic capacitance.

[0074]

number

[0075] Even if the total resistance value of the plurality of resistors included in the resistor group 710 is the same, if at least some of the plurality of resistors have different resistance values, the sampling capacitor voltage V bot may have different graphs.

[0076] Specifically, referring to Equation 2, even if the total resistance value of the plurality of resistors is the same, if a resistor with a large resistance value is located close to the power supply unit 730, τ real Since becomes large, the sampling capacitor voltage V bot On the other hand, if a resistor with a small resistance value is located close to the power supply unit 730, the delay in the graph will be longer. real becomes small, so the sampling capacitor voltage V bot The graph delay is reduced.

[0077] If the total resistance of the circuit is the same, the same sampling capacitor voltage V will be generated regardless of whether the resistor with the larger resistance is located closer to the power supply or closer to the sampling capacitor. bot When the delay of the graph is the same, no error occurs. However, in actual circuits, there is a parasitic capacitance, and the time constant τ real As a result, the sampling capacitor voltage V bot The graph delay will change, which means that output errors will occur.

[0078] FIG. 7B is a diagram illustrating an output error of a circuit in the presence of parasitic capacitance, according to one embodiment.

[0079] 7B, the DC voltage applied to the power supply unit 730 is 1V, and the reference voltage is set to 0.67mV. A first resistor and a second resistor are used as resistors in the resistor group 710. Hereinafter, it is assumed that the value (Ω) of the first resistor is smaller than the value (Ω) of the second resistor.

[0080] The first graph 751 and the second graph 752 are the sampling capacitor voltages V measured in different circuits. bot Specifically, the first graph 751 shows a case where 32 first resistors are positioned in the direction from the power supply unit 730 to the sampling capacitor 720, followed by 32 second resistors. The second graph 752 shows a case where 32 second resistors are positioned in the direction from the power supply unit 730 to the sampling capacitor 720, followed by 32 first resistors.

[0081] In the first graph 751 and the second graph 752, although the total resistance values (32 first resistors and 32 second resistors) of the resistors included in the resistor group 710 are the same, it can be seen that the delay in the second graph 752 is longer than the delay in the first graph 751. This is because the resistors with larger resistance values in the second graph 752 are located closer to the power supply unit 730 than in the first graph 751.

[0082] As described in FIGS. 3 to 5, the comparator detects the sampling capacitor voltage V bot In response to the voltage exceeding the reference voltage, the time-to-digital converter can output a digital value based on the time difference between a start point corresponding to the start signal and an end point corresponding to the end signal, and the output unit can output a product-sum operation result corresponding to the digital value as the operation result.

[0083] That is, the calculation result output at the output section is the sampling capacitor voltage V bot exceeds the reference voltage, but since the first end point of the first graph 751 and the second end point of the second graph 752 are different from each other, the calculation result derived from the first graph 751 and the calculation result derived from the second graph 752 are also different from each other.

[0084] 8A and 8B are diagrams illustrating a method for performing a predetermined operation using a circuit having parasitic capacitance according to an embodiment.

[0085] 8A is a diagram illustrating a circuit 800 in the presence of parasitic capacitance, according to one embodiment. The circuit 800 includes a resistor group 810 and a sampling capacitor 820.

[0086] The resistor group 810 includes a plurality of resistors R1, . . . , R nOne end of the resistor group 810 is connected to the power supply unit 830, and the other end of the resistor group 810 is connected to the sampling capacitor 820. In addition, a plurality of resistors R1, ..., R n At each node between p exists.

[0087] After the sampling capacitor 820 is reset, a DC voltage VDD is applied to the power supply unit 830 .

[0088] In the forward process, the processor samples the capacitor voltage V bot The processor may determine the switching time as the time when the sampling capacitor voltage V reaches the first reference voltage. bot The reference time point may be the time point when the DC voltage VDD is applied to the power supply unit 830, or may be the time point when a predetermined time has elapsed after the DC voltage VDD is applied.

[0089] At the switching time, the processor can couple the sampling capacitor 820 to ground or a predetermined voltage and float the power supply unit 830. For example, the predetermined voltage can be 1 mV, but the predetermined voltage is not limited to a particular value.

[0090] As described in FIG. 7A, the parasitic capacitance present in circuit 800 reduces the forward process sampling capacitor voltage V bot can be expressed as the above-mentioned Equation 2. Furthermore, the forward delay τ1 can be expressed as the following Equation 3.

[0091]

number

[0092]

number

[0093]

number

[0094] That is, the circuit 800 has a parasitic capacitance C p When both the forward delay τ1 and the reverse delay τ2 are used despite the existence of the resistors in the resistor group 810, even if at least some of the resistors in the resistor group 810 have different resistance values, if the total resistance value of the resistors is the same, the power supply voltage V top The end point at which the voltage reaches the second reference voltage is the same.

[0095] Meanwhile, the first reference voltage, which is the reference for determining the switching time point, is a value obtained by subtracting a predetermined percentage (%) from the DC voltage VDD supplied to the power supply unit 830. Also, the second reference voltage, which is the reference for determining the end time point, is a value obtained by subtracting 100-predetermined percentage (%) from the DC voltage VDD supplied to the power supply unit 830.

[0096] For example, if the DC voltage VDD is 1 V and the predetermined percentage (%) is 67%, the first reference voltage is 0.67 V and the second reference voltage is 0.33 V. Alternatively, if the DC voltage VDD is 1 V and the predetermined percentage (%) is 50%, the first reference voltage is 0.5 V and the second reference voltage is 0.5 V. In particular, if the predetermined percentage (%) is 50%, the first reference voltage and the second reference voltage have the same value, so that the switching time and the end time can be determined using only one reference voltage.

[0097] The processor can perform a predetermined operation based on the end time point. The processor can perform a predetermined operation based on the time it takes from the reference time point to the end time point. As described in Figures 7A and 7B, the processor can output a calculation result based on the time it takes. In one embodiment, the calculation result may be a multiply-accumulate result. In another embodiment, the calculation result may be the total resistance value of the resistor group 810.

[0098] The calculation result is determined based on the end time. When both the forward delay τ1 and the backward delay τ2 are used, even if at least some of the resistors included in the resistor group 810 have different resistance values, the calculation result is the same as long as the total resistance value of the resistors is the same.

[0099] Meanwhile, in Equation 5, the sample capacitance C s 0. In other words, the circuit 800 can operate even when the parasitic capacitance C p The above content can be expressed as the following Equation 6.

[0100]

number

[0101] 8B, the DC voltage applied to the power supply unit 830 is 1V, the first reference voltage 860 is set to 0.67mV, and the second reference voltage 870 is set to 0.33mV. A first resistor and a second resistor are used as resistors in the resistor group 810. Hereinafter, it is assumed that the value (Ω) of the first resistor is smaller than the value (Ω) of the second resistor.

[0102] The first circuit is a case where 48 first resistors are located in the direction from the power supply unit 830 to the sampling capacitor 820, followed by 16 second resistors. The second circuit is a case where 16 second resistors are located in the direction from the power supply unit 830 to the sampling capacitor 820, followed by 48 first resistors.

[0103] Graph 1-1 851a and graph 1-2 851b respectively show the forward and reverse processes performed in the first circuit. Graph 1-1 851a shows the sampling capacitor voltage V bot The first-second graph 851b shows the power supply voltage V top Represents.

[0104] Graph 2-1 852a and Graph 2-2 852b respectively show the forward and reverse processes performed in the second circuit. Graph 2-1 852a shows the sampling capacitor voltage V bot Graph 2-2 852b shows the power supply voltage V top Represents.

[0105] In the first circuit and the second circuit, the total resistance value of the plurality of resistors included in the resistor group 810 (48 first resistors and 16 second resistors) is the same.

[0106] In the forward process of the first circuit, the sampling capacitor voltage V botThe first switching point 851c is when the power supply voltage V reaches the first reference voltage 860. In the reverse direction after the first switching point 851c, the power supply voltage V top reaches the second reference voltage 870 is the end point 880.

[0107] In the forward process of the second circuit, the sampling capacitor voltage V according to the second-first graph 852a bot The second switching point 852c occurs when the power supply voltage V reaches the first reference voltage 860. In the reverse direction after the second switching point 852c, the power supply voltage V top reaches the second reference voltage 870 is the end point 880.

[0108] Looking at the forward process, it can be seen that the delay of the 2-1 graph 852a is longer than the delay of the 1-1 graph 851a. This is because the 1-1 graph 851a and the 2-1 graph 852a are different in the sampling capacitor voltage V bot This is because in the 2-1 graph 852a, a resistor with a large resistance value is located closer to the power supply unit 830. That is, the 1-1 graph 851a reaches the first reference voltage 860 earlier than the 2-1 graph 852a.

[0109] Looking at the reverse process, it can be seen that the delay of the second graph 852b is shorter than the delay of the first graph 851b. This is because the first graph 851b and the second graph 852b are connected to the power supply voltage V top This is because the resistor with the larger resistance value is located closer to the sampling capacitor 820 in the second graph 852b.

[0110] However, if both the forward and backward processes are considered, it can be seen that the end point 880 for the first and second circuits is the same.

[0111] The result of the operation performed using the first circuit and the second circuit is determined based on the end point 880. When both the forward process and the reverse process are performed, even if at least some of the resistors included in the resistor group 810 have different resistance values, the result of the operation performed using the first circuit and the second circuit is the same as long as the total resistance value of the resistors is the same.

[0112] FIG. 9 is a diagram illustrating a circuit for performing a predetermined operation through a forward process and a backward process according to an embodiment.

[0113] Referring to FIG. 9, a circuit 900 includes a resistor group 910 and a sampling capacitor 920 .

[0114] Resistor group 910 includes a plurality of resistors R1, . . . , R n One end of the resistor group 910 is connected to the power supply unit 950, and the other end of the resistor group 910 is connected to the sampling capacitor 920. In addition, a plurality of resistors R1, ..., R n At each node between p exists.

[0115] In one embodiment, the circuit 900 may further include a first comparator 931 and a second comparator 932. The first comparator 931 and the second comparator 932 may be configured with operational amplifiers.

[0116] The first comparator 931 detects the sampling capacitor voltage V bot and the first reference voltage V ref1 The second comparator 932 can output the result of comparing the power supply voltage V top and the second reference voltage V ref2 The results of the comparison can be output.

[0117] Specifically, after the sampling capacitor 920 is reset, the DC voltage VDD is applied to the power supply unit 950. In the forward direction process after the reference time point t0, the first comparator 931 detects the sampling capacitor voltage V botis the first reference voltage V ref1 Here, the reference time point t0 may be the time point when the DC voltage VDD is applied to the power supply unit 950, or may be the time point when a predetermined time has elapsed after the DC voltage VDD is applied.

[0118] When the first time information t1 is output, the sampling capacitor 920 is connected to the ground or a predetermined voltage, and the power supply unit 950 is floated.

[0119] In the reverse direction, the second comparator 932 detects the power supply voltage V top is the second reference voltage V ref2 The second time information t2 at the time point when the time reaches the predetermined value can be output.

[0120] The time-to-digital converter 940 can output a digital value based on the reference time t0 and the second time information t2. Specifically, the time-to-digital converter 940 can output the time difference between the reference time t0 and the second time information t2 as a digital value.

[0121] An output unit (not shown) can output the operation result mapped to the digital value output from the time-to-digital converter 940. In one embodiment, the operation result may be a multiply-accumulate operation result. In another embodiment, the operation result may be the total resistance value of the circuit 900.

[0122] On the other hand, in FIG. 9, the explanation was given on the assumption that two comparators are used, but the sampling capacitor voltage V bot and the first reference voltage V ref1 The point at which the power supply voltage V top and the second reference voltage V ref2 Since there is a time difference between the time when the signal is compared, it is possible to use one comparator.

[0123] FIG. 10 is a diagram illustrating a circuit for performing a predetermined operation through a forward process according to an embodiment.

[0124] 10 is a diagram illustrating a circuit 1000 having parasitic capacitance, according to one embodiment. For ease of explanation, the parasitic capacitance is not shown in the circuit 1000 of FIG.

[0125] The circuit 1000 includes a first resistor group 1011 and a second resistor group 1012. The first resistor group 1011 and the second resistor group 1012 are each a plurality of resistors R1, ..., R n One end of the first resistor group 1011 and the second resistor group 1012 is connected to the power supply unit 1030, and the other end is connected to the sampling capacitor 1020. In addition, a plurality of resistors R1, ..., R n At each node between p exists.

[0126] The total resistance value of the first resistor group 1011 is the same as the total resistance value of the second resistor group 1012. However, the resistor arrangement order of the first resistor group 1011 is the opposite of the resistor arrangement order of the second resistor group 1012.

[0127] Specifically, referring to FIG. 10, the resistors of the first resistor group 1011 are arranged in a direction from the power supply unit 1030 to the sampling capacitor 1020 as R1, R2, . . . , R n-1 ,R n while the resistors in the second resistor group 1012 are arranged in the order R n ,R n-1 ,...,R2,R1 in that order.

[0128] A method for performing a predetermined operation using the circuit 1000 of FIG. 10 is as follows.

[0129] After the sampling capacitor 1020 is reset, a DC voltage VDD is applied to the power supply unit 1030 .

[0130] After the reference time point, the processor samples the capacitor voltage V botThe end point can be determined when the DC voltage VDD reaches the reference voltage. The reference point can be the point when the DC voltage VDD is applied to the power supply unit 1030, or a predetermined time after the DC voltage VDD is applied.

[0131] The processor can perform a predetermined operation based on the end time point. The processor can perform a predetermined operation based on the time it takes from the reference time point to the end time point. As described in Figures 7A and 7B, the processor can output a calculation result based on the time it takes. In one embodiment, the calculation result may be a multiply-accumulate result. In another embodiment, the calculation result may be the total resistance value of the resistor group 1010.

[0132] In Figure 8A, a predetermined operation is performed by performing a forward process and a reverse process on the circuit 300. In contrast, in Figure 10, a predetermined operation can be performed by performing only a forward process without a reverse process by using a first resistor group 1011 and a second resistor group 1012, which have the exact opposite resistor arrangement order.

[0133] FIG. 11 is a flowchart illustrating a method for performing a predetermined operation using a circuit according to an embodiment.

[0134] The circuit includes a resistor group and a sampling capacitor. The resistor group includes a plurality of resistors connected in series. One end of the resistor group is connected to a power supply and the other end of the resistor group is connected to the sampling capacitor. Also, a parasitic capacitance exists at each node between the plurality of resistors.

[0135] Referring to FIG. 11, in step 1110, the sampling capacitor is reset and a DC voltage is applied to the power supply.

[0136] In step 1120, the forward process proceeds. Specifically, in step 1120, the comparator detects the sampling capacitor voltage V bot and the first reference voltage V ref1 can be compared.

[0137] Sampling capacitor voltage V bot and the first reference voltage V ref1 As a result of the comparison with the sampling capacitor voltage V bot is the first reference voltage V ref1 If so, step 1120 is repeated.

[0138] Sampling capacitor voltage V bot and the first reference voltage V ref1 As a result of the comparison with the sampling capacitor voltage V bot is the first reference voltage V ref1 If so, proceed to step 1130.

[0139] In step 1130, the sampling capacitor is tied to ground or a predetermined voltage and the power supply is allowed to float.

[0140] The reverse process is carried out in step 1140. Specifically, in step 1140, the comparator detects the power supply voltage V across the power supply. top and the second reference voltage V ref2 can be compared.

[0141] Power supply voltage V top and the second reference voltage V ref2 As a result of the comparison, the power supply voltage V top is the second reference voltage V ref2 If so, step 1140 is repeated.

[0142] Power supply voltage V top and the second reference voltage V ref2 As a result of the comparison, the power supply voltage V top is the second reference voltage V ref2 If it is less than 1, proceed to step 1150.top is the second reference voltage V ref2 When it reaches this point, it is the end point.

[0143] In step 1150, the comparator may output time information corresponding to the end point.

[0144] The processor may perform a predetermined operation based on the time information corresponding to the end time. In one embodiment, the processor may perform a multiply-and-accumulate operation based on the time information corresponding to the end time. In another embodiment, the processor may calculate a total resistance value of the circuit based on the time information corresponding to the end time.

[0145] FIG. 12 is a flowchart illustrating a method for performing a predetermined operation using a circuit according to an embodiment.

[0146] The circuit includes a resistor group and a sampling capacitor. The resistor group includes a plurality of resistors connected in series. One end of the resistor group is connected to a power supply and the other end of the resistor group is connected to the sampling capacitor. Also, a parasitic capacitance exists at each node between the plurality of resistors.

[0147] 12, the forward process is performed in step 1210. Specifically, in step 1210, the processor may determine the time when the sampling capacitor voltage applied to the sampling capacitor reaches the first reference voltage as the switching time.

[0148] The processor may measure the sampling capacitor voltage from a reference point in time, which may be the point in time when the DC voltage VDD is applied to the power supply unit, or may be a point in time a predetermined time after the DC voltage VDD is applied.

[0149] In step 1220, the processor may couple the sampling capacitor to ground or a predetermined voltage at the switching point and float the power supply unit.

[0150] The reverse process is performed in step 1230. Specifically, the processor may determine the end point of the reverse process after the switching point when the power supply voltage across the power supply reaches the second reference voltage.

[0151] The first reference voltage in step 1210 is a value obtained by subtracting a predetermined percentage from the DC voltage supplied to the power supply unit, and the second reference voltage in step 1230 is a value obtained by subtracting 100-the predetermined percentage from the DC voltage supplied to the power supply unit.

[0152] In step 1240, the processor may perform a predetermined operation based on the termination time.

[0153] The processor can perform a multiply-accumulate operation or calculate the total resistance value of the resistor group based on the end time.

[0154] When both the forward and reverse processes are performed, even if at least some of the resistors included in the resistor group have different resistance values, the calculation result is the same as long as the total resistance value of the resistors is the same.

[0155] FIG. 13 is a diagram illustrating an example of a neural network operation implemented by a product-sum operation circuit according to an embodiment.

[0156] The neural network 1300 is an example of a deep neural network (DNN). DNNs include a fully connected network, a deep convolutional network, and a recurrent neural network. The neural network 1300 can perform object classification, object recognition, voice recognition, image recognition, and the like by mapping input data and output data that have a nonlinear relationship to each other based on deep learning. Deep learning is a machine learning technique for solving problems such as image recognition or voice recognition from big data sets, and can map input data and output data to each other through supervised learning or unsupervised learning.

[0157] For convenience of explanation, Figure 13 shows a hidden layer including two layers, but the hidden layer may include multiple layers. Also, Figure 13 shows neural network 1300 including a separate input layer 1310 for receiving input data, but input data may be directly input to the hidden layer. In neural network 1300, artificial nodes in layers other than the output layer can be connected to artificial nodes in the next layer via links for transmitting output signals. The number of links corresponds to the number of artificial nodes included in the next layer.

[0158] Each artificial node in the hidden layer receives the output of an activation function related to the weighted inputs of the artificial node in the previous layer. The weighted inputs are the inputs of the artificial node in the previous layer multiplied by a weight. The weights are called parameters of the neural network 1300. Activation functions include sigmoid, hyperbolic tangent (tanh), and ReLU (rectified linear unit), and the activation function can create nonlinearity in the neural network 1300. Each artificial node in the output layer receives the weighted inputs of the artificial node in the previous layer.

[0159] The above-described multiply-accumulate circuit can be applied to in-memory computation for driving deep learning algorithms. For example, the calculation of weighted inputs transmitted between nodes 1321 of the neural network 1300 is performed by MAC computation, which repeats multiplication and addition. The output of any one node 1321 of the neural network 1300 can be expressed as Equation 7 below.

[0160]

number

[0161] According to one embodiment, the resistors of the sum-of-products circuit may have resistances corresponding to the connection weights of the connection lines connecting the nodes in the neural network 1300, which is configured with one or more layers including the nodes. An input voltage signal provided along the input line on which the resistors are arranged may be calculated based on the node value x j Therefore, the sum-of-products circuit can perform at least a portion of the operations required to implement the neural network 1300. For reference, in the sum-of-products circuit, the resistance values of the resistors are not fixed, but may be changed to values corresponding to the weight values stored in the memory as described above.

[0162] However, the application of the product-sum calculation circuit according to one embodiment is not limited to this, and it can also be used for calculation operations that require processing multiple input data quickly and with low power consumption using analog circuit characteristics.

[0163] According to one embodiment, the multiply-accumulate circuit may have a low-power architecture that combines an analog adder and a digital conversion circuit in an in-memory calculation structure using a time-to-digital converter (TDC). As described above, the multiply-accumulate circuit may calculate multiple column data (e.g., data corresponding to output lines) using one TDC and a single global counter. This is because the start signal START is synchronized, and only the count value corresponding to the stop signal STOP can be independently referenced for each column. Therefore, a single TDC can cover parallel calculations of the entire array in memory.

[0164] In the case of a conventional ADC (analog-to-digital conversion) structure, an ADC is required for each individual column, and a complex structure is required to increase bit precision, resulting in large power and area requirements. However, a TDC structure such as a multiply-accumulate circuit according to one embodiment digitizes the sum using a simple counter, resulting in a simple circuit. Furthermore, since a single TDC covers the entire array operation, power consumption and size are reduced.

[0165] The present embodiment may also be embodied in the form of a recording medium containing computer-executable instructions, such as a program module executed by a computer. A computer-readable medium is any available medium accessible by a computer, including both volatile and nonvolatile media, and both detachable and non-detachable media. The computer-readable medium may also include both computer recording media and communication media. The computer recording media includes both volatile and non-volatile, detachable and non-detachable media embodied in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Communication media typically include computer-readable instructions, data structures, other data in a modulated data signal, such as a program module, or other transmission mechanism, and include any information transmission media.

[0166] In this specification, a "unit" may also refer to a hardware component such as a processor or a circuit, and / or a software component executed by a hardware component such as a processor.

[0167] The above description of the present specification is for illustrative purposes only, and those skilled in the art will understand that the present invention can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. For example, each component described as a single component may be implemented in a distributed form, and similarly, each component described as a distributed component may be implemented in a combined form.

[0168] The scope of the present embodiments is indicated by the claims set forth below rather than the above detailed description, and should be interpreted as including all modifications and variations derived from the meaning and scope of the claims and their equivalent concepts. [Industrial Applicability]

[0169] The present invention is applicable to, for example, technical fields related to information analysis. [Explanation of symbols]

[0170] 800 Circuits with Parasitic Capacitance 810 Resistance Group 820 Sampling Capacitor 830 Power supply section C p Parasitic Capacitance C s Sample Capacitance R1, R2, R3, R n-1 ,R n resistance V bot Sampling Capacitor Voltage VDD DC voltage V top Power supply voltage

Claims

1. 1. A method for performing a predetermined operation using a circuit, comprising: The circuit includes a resistor group including a plurality of resistors connected in series, a power supply connected to one end of the resistor group, and a sampling capacitor connected to the other end of the resistor group, and a parasitic capacitance exists at each node between the plurality of resistors; The method comprises: determining a time point when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage in a forward process as a switching time point; At the time of switching, connecting the sampling capacitor to ground or a predetermined voltage and floating the power supply unit; determining a time point at which a power supply voltage applied to the power supply unit reaches a second reference voltage during the reverse direction process after the switching time point as an end time point; and performing the predetermined operation based on the end time.

2. the first reference voltage is a value obtained by subtracting a predetermined percentage (%) from the DC voltage supplied to the power supply unit, 2. The method according to claim 1, wherein the second reference voltage is a value obtained by subtracting (100-the predetermined percentage) from the DC voltage supplied to the power supply unit.

3. The step of performing the predetermined operation includes:

3. The method according to claim 1, further comprising the step of performing a multiply-and-accumulate operation or calculating a total resistance value of the resistor group based on the end time point.

4. 1. A method for performing a predetermined operation using a circuit, comprising: The circuit includes a resistor group including a plurality of resistors connected in series, a power supply connected to one end of the resistor group, and a sampling capacitor connected to the other end of the resistor group, and a parasitic capacitance exists at each node between the plurality of resistors; the resistor groups are divided into a first resistor group and a second resistor group, the first resistor group and the second resistor group are connected in parallel, and an arrangement order of resistors in the first resistor group is opposite to an arrangement order of resistors in the second resistor group; The method comprises: determining an end point when the sampling capacitor voltage across the sampling capacitor reaches a reference voltage; and performing the predetermined operation based on the end time.

5. 5. The method according to claim 4, wherein the reference voltage is a value obtained by subtracting a predetermined percentage from the DC voltage supplied to the power supply unit.

6. The step of performing the predetermined operation includes:

6. The method according to claim 4, further comprising the step of performing a multiply-and-accumulate operation or calculating a total resistance value of the resistor group based on the end time point.

7. In a device that performs a predetermined operation using a circuit, a power supply connected to one end of the circuit; a resistor group including a plurality of resistors connected in series from one end of the circuit to the other end; a sampling capacitor connected in series with the plurality of resistors; a parasitic capacitance present at each node between the plurality of resistors; a sampling capacitor voltage across the sampling capacitor in a forward direction; a first comparator for comparing the sampling capacitor voltage with a first reference voltage and outputting first time information of a time point when the sampling capacitor voltage reaches the first reference voltage; a processor that connects the sampling capacitor to ground or a predetermined voltage and floats the power supply unit when the first time information is output; a power supply voltage applied to the power supply in a reverse direction after the first time information is output; a second comparator that compares the power supply voltage with a second reference voltage and outputs second time information of a time point when the power supply voltage reaches the second reference voltage; The processor performs the predetermined operation based on the second time information.

8. the first reference voltage is a value obtained by subtracting a predetermined percentage (%) from the DC voltage supplied to the power supply unit, 8. The device according to claim 7, wherein the second reference voltage is a value obtained by subtracting 100 from the predetermined percentage (%) of the DC voltage supplied to the power supply unit.

9. The processor:

9. The device according to claim 7, wherein a multiply-and-accumulate operation is performed or a total resistance value of the resistor group is calculated based on the second time information.

10. In an apparatus including a circuit for performing a predetermined operation, a power supply connected to one end of the circuit; a resistor group including a plurality of resistors connected in series from one end of the circuit to the other end; a sampling capacitor connected in series with the plurality of resistors; a parasitic capacitance present at each node between the plurality of resistors; a comparator that compares a sampling capacitor voltage applied to the sampling capacitor with a reference voltage and outputs time information of a point in time when the sampling capacitor voltage reaches the reference voltage; a processor that performs the predetermined calculation based on the time information; The resistor group is divided into a first resistor group and a second resistor group, the first resistor group and the second resistor group are connected in parallel, and the resistor arrangement order of the first resistor group is opposite to the resistor arrangement order of the second resistor group.

11. 11. The device according to claim 10, wherein the reference voltage is a value obtained by subtracting a predetermined percentage from the DC voltage supplied to the power supply unit.

12. The processor:

12. The device according to claim 10, wherein a product-sum operation is performed or a total resistance value of the resistor group is calculated based on the time information.

13. A computer-readable recording medium having recorded thereon a program for executing the method according to any one of claims 1 to 6.

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