Composite Electronic Components

Abstract

To provide a composite electronic component capable of reducing noises by narrowing an area of a substrate.SOLUTION: A composite electronic component includes: a substrate having a GND pattern; a coil component that includes at least three terminals, and is mounted onto a first front surface of the substrate; and an overlapping arrangement component that is mounted onto the first front surface so that at least one part in view from a first direction vertical to the first front surface overlaps the coil component. The substrate includes: at least three coil patterns that are formed onto the first front surface and connected to the terminal; at least two component patterns that are formed onto the first front surface, and connected to the overlapping arrangement component; and a GND via that connects one of the component patterns with the GND pattern. The GND via is arranged to a substrate outer side region as a region on an outer side of a polygon connecting all of the coil patterns in the substrate in view of the first direction to the shortest principal length.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a composite electronic component including a substrate and components mounted on the substrate. [Background technology]

[0002] Coil components including inductors such as choke coils and transformers may be used alone, but they may also be mounted on a substrate together with other electronic components such as capacitors to form composite electronic components. Such composite electronic components, consisting of a substrate and multiple elements and electronic components mounted on the substrate, form a circuit with a specific function, such as a low-pass filter that reduces noise.

[0003] One such composite electronic component that has been proposed is one in which a relatively large coil component is placed below another electronic component that is shorter in height on a substrate so that they overlap when viewed perpendicularly to the mounting surface (see Patent Document 1, etc.).

[0004] Such an overlapping type composite electronic component has the advantage of being able to reduce the area of the board compared to a non-overlapping type composite electronic component. However, conventional overlapping type composite electronic components have sometimes been unable to sufficiently reduce noise generated in electrical signals transmitted through the circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-193000 Summary of the Invention [Problem to be solved by the invention]

[0006] The present disclosure provides a composite electronic component that can reduce noise by reducing the area of the substrate. [Means for solving the problem]

[0007] A composite electronic component according to a first aspect of the present disclosure includes: a substrate having a GND pattern; a coil component having at least three terminals and mounted on a first surface of the substrate; an overlapping arrangement component that is an electronic component shorter in height than the coil component and is mounted on the first surface so that at least a portion of the electronic component overlaps the coil component when viewed from a first direction perpendicular to the first surface; the substrate has at least three coil patterns formed on the first surface and connected to the terminals, at least two component patterns formed on the first surface and connected to the overlapping components, and a GND via that electrically connects one of the component patterns to the GND pattern; The GND via is arranged in a substrate outer region, which is a region outside a polygon that connects all of the coil patterns on the substrate with the shortest perimeter, when viewed from the first direction.

[0008] In such a composite electronic component, the area of the board can be reduced because it has overlapping components, and the area where the GND pattern in the board overlaps with other patterns (including wiring) can be reduced by arranging the GND vias in the outer area of the board. This reduces the generation of stray capacitance inside the composite electronic component, and effectively reduces noise generated in electrical signals transmitted through the circuit that the composite electronic component constitutes.

[0009] Furthermore, for example, the coil component may be a common mode filter (common mode choke coil).

[0010] A composite electronic component including a coil component that is a common mode filter can improve its performance as a noise filter by reducing noise that occurs in electrical signals transmitted through the circuit that the composite electronic component constitutes.

[0011] Furthermore, for example, the overlapping component may be a capacitor.

[0012] Such a composite electronic component constitutes a circuit combining a coil component and a capacitor, and can be suitably used as a noise filter or the like for reducing noise.

[0013] For example, the semiconductor device may further include a resistive element mounted on the first surface so that at least a portion of the resistive element overlaps with the coil component when viewed from the first direction, On the substrate, one end of the resistive element may be wired to one of the coil patterns, and the other end of the resistive element may be wired to another one of the component patterns.

[0014] Furthermore, a composite electronic component in which a resistance element is arranged so as to overlap a coil component is advantageous from the viewpoint of reducing the area of a substrate or high-density mounting.

[0015] Furthermore, for example, at least a portion of the resistance element may be arranged in a substrate inner region, which is a region inside the polygon on the substrate, when viewed from the first direction.

[0016] By disposing the resistive element in the inner region of the substrate, it is possible to prevent the occurrence of stray capacitance between the resistive element and the wiring connected to the resistive element and the GND pattern, thereby effectively reducing noise.

[0017] Furthermore, for example, at least a portion of the other one of the component patterns may be disposed in a substrate inner region that is a region inside the polygon on the substrate when viewed from the first direction.

[0018] By using this arrangement, the wiring distance to the overlapping components can be shortened, and stray capacitance can be prevented from occurring between the wiring from the coil pattern to the component pattern and the GND pattern, thereby effectively reducing noise.

[0019] For example, the semiconductor device may further include an ESD protection element mounted on the first surface so that at least a portion of the ESD protection element overlaps with the coil component when viewed from the first direction, In the substrate, the ESD protection element may be wired to one of the coil patterns.

[0020] Furthermore, a composite electronic component in which an ESD protection element is arranged so as to overlap a coil component is advantageous from the viewpoint of reducing the area of a board or high-density mounting. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a schematic diagram of a composite electronic component according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing a substrate included in the composite electronic component shown in FIG. [Figure 3] FIG. 3 is an equivalent circuit diagram of the composite electronic component shown in FIG. [Figure 4] FIG. 4 is a conceptual diagram showing the arrangement of electronic components and patterns in the composite electronic component shown in FIG. [Figure 5] FIG. 5 is a conceptual diagram of the composite electronic components according to the example and the comparative example. [Figure 6] FIG. 6 is a diagram showing noise generated in the composite electronic component according to the example. [Figure 7] FIG. 7 is a diagram showing noise generated in the composite electronic component according to the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, the present invention will be described based on the embodiments shown in the drawings.

[0023] Fig. 1 is a schematic diagram of a composite electronic component 10 according to an embodiment of the present disclosure. For ease of explanation, Fig. 1 shows a state in which a coil component 40 is offset relative to a substrate 20 in a first direction D1 perpendicular to a first surface 20a, which is the mounting surface of the substrate 20. However, in an actual composite electronic component 10, the coil component 40 is connected to the first surface 20a, which is the mounting surface of the substrate 20.

[0024] 1, the composite electronic component 10 includes a substrate 20 and a coil component 40 mounted on a first surface 20a of the substrate 20. The composite electronic component 10 also includes a capacitor 50 as an overlapping component mounted on the first surface 20a of the substrate 20, and resistor elements 60 and 66 also mounted on the first surface 20a of the substrate 20. The composite electronic component 10 also includes ESD protection elements 70 and 76 mounted on the first surface 20a of the substrate 20.

[0025] The substrate 20 shown in FIG. 1 is formed of a printed circuit board, a lead frame, a BT substrate, or the like, and has a GND pattern 30 made of conductive wiring inside or on the back side (negative Z-axis direction side) (see FIG. 4). Also, as shown in FIG. 2, a first surface 20a, which is one surface of the flat substrate 20, has multiple patterns (first to fourth coil patterns 21a to 21d, first to second component patterns 23a to 23b, first to second resistor patterns 25a to 25b, 26a to 26b, first to second ESD patterns 28a to 28b, 29a to 29b) formed thereon. These patterns are made of conductive wiring exposed on the first surface 20a. The GND pattern 30 shown in FIG. 4 is not exposed on the first surface 20a.

[0026] The substrate 20 shown in FIG. 1 includes conductor patterns (such as first to fourth coil patterns 21a to 21d) exposed on the first surface 20a, a GND pattern 30 not exposed on the first surface 20a, a GND via 32 and ESD GND vias 34 and 35 (described later), other conductor wiring not exposed on the first surface 20a, and insulating layers that insulate or cover the respective patterns and wiring. The substrate 20 may be a single-sided substrate in which the only mounting surface is the first surface 20a, or a double-sided substrate in which the surface opposite the first surface 20a is also a mounting surface. The arrangement of each pattern on the substrate 20 will be described in detail later.

[0027] In the description of the composite electronic component 10 shown in FIG. 1, the direction parallel to the first direction D1 perpendicular to the first surface 20a of the substrate 20 is defined as the Z-axis direction, the direction perpendicular to the Z-axis direction and parallel to the winding axis direction of the coil component 40 is defined as the X-axis direction, and the direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0028] The coil component 40 shown in Fig. 1 has at least three terminals (four in this embodiment), a core 43, and a winding 42. As shown in Fig. 3, which is an equivalent circuit diagram of the composite electronic component 10, the coil component 40 is a common mode filter (common mode choke coil) in which two independent windings 42 are magnetically coupled by the core 43. The composite electronic component 10 also combines the coil component 40 as a common mode filter with a capacitor 50 as a bypass capacitor, resistive elements 60 and 66, and the like, to form an EMC component or the like that reduces noise. The composite electronic component 10 is electrically connected to, for example, a transceiver 80 or the like.

[0029] However, the coil component 40 used in the composite electronic component 10 is not limited to only a common mode filter, but may be another inductor element including a winding (coil), or may be a composite element including an inductor element and another element. Furthermore, the composite electronic component 10 is not limited to only an EMC countermeasure component.

[0030] 1, the coil component 40 has four terminals: a first terminal 41a, a second terminal 41b, a third terminal 41c, and a fourth terminal 41d (see FIG. 4 for the first terminal 41a). The coil component 40 has a substantially rectangular parallelepiped outer shape, and the first to fourth terminals 41a to 41d are arranged at the four corners of the coil component 40. The first terminal 41a and the third terminal 41c are electrically connected to one winding 42 included in the coil component 40, and the second terminal 41b and the fourth terminal 41d are electrically connected to the other winding 42 included in the coil component 40.

[0031] The coil component 40 is fixed to the first surface 20a of the substrate 20 by connecting the first to fourth terminals 41a, 41b, 41c, and 41d to the first to fourth coil patterns 21a, 21b, 21c, and 21d formed on the first surface 20a of the substrate 20. The coil component 40 can be mounted on the substrate 20 by, for example, reflow soldering, but is not particularly limited to, this method.

[0032] 1, the lower end of the winding 42 of the coil component 40 is located higher than the lower ends of the first to fourth terminals 41a, 41b, 41c, and 41d fixed to the first surface 20a of the substrate 20. Therefore, in the composite electronic component 10, a gap is formed between the winding 42 of the coil component 40 and the first surface 20a of the substrate 20, and the capacitor 50, the resistive elements 60, 66, etc. are disposed in this gap.

[0033] The capacitor 50 as an overlapping component is an electronic component that is shorter in height (length in the first direction D1 when mounted) than the coil component 40, and at least a portion of it overlaps the coil component 40 when viewed from the first direction D1 perpendicular to the first surface 20a.

[0034] Capacitor 50 is a chip capacitor that is surface-mounted on substrate 20 and has a substantially rectangular parallelepiped outer shape. Fig. 4 is a conceptual diagram showing the arrangement of electronic components on substrate 20 of composite electronic component 10 and the structure within substrate 20. Fig. 4 is a view of composite electronic component 10 as seen from the first direction D1 (positive direction of the Z axis) side, with coil component 40 shown in perspective (only the outline of the coil component 40 is shown by a two-dot chain line).

[0035] 4, capacitor 50 has first terminal 51a and second terminal 51b formed at one end. Capacitor 50 is fixed to first surface 20a of substrate 20 by connecting first terminal 51a and second terminal 51b to first and second component patterns 23a and 23b formed on first surface 20a of substrate 20. Note that the overlapping component is not limited to capacitor 50, and may be an electronic component other than capacitor 50.

[0036] 1, the composite electronic component 10 has two resistive elements 60, 66. As shown in FIGS. 1 and 4, the resistive elements 60, 66 are mounted on the first surface 20a of the substrate 20 so that at least a portion of each of the resistive elements 60, 66 overlaps the coil component 40 when viewed from the first direction D1. The resistive elements 60, 66 are chip components having a substantially rectangular parallelepiped outer shape, but the resistive elements 60, 66 are not limited to chip components.

[0037] 4, the resistor element 60 has a first terminal 61a provided at one end and a second terminal 61b provided at the other end. The resistor element 60 is fixed to the first surface 20a of the substrate 20 by connecting the first terminal 61a and the second terminal 61b to first and second resistor patterns 25a and 25b (see FIG. 2) formed on the first surface 20a of the substrate 20. Similarly to the resistor element 60, the resistor element 66 having a first terminal 67a and a second terminal 67b is fixed to the substrate 20 via the first and second resistor patterns 26a and 26b (see FIG. 2).

[0038] 1, the composite electronic component 10 has two ESD protection elements 70, 76. As shown in FIGS. 1 and 4, the ESD protection elements 70, 76 are mounted on the first surface 20a of the substrate 20 so that at least a portion of each of the ESD protection elements 70, 76 overlaps the coil component 40 when viewed from the first direction D1. The ESD protection elements 70, 76 are chip components formed from a multilayer chip varistor, a Zener diode, or the like, and have an approximately rectangular parallelepiped outer shape, but the ESD protection elements 70, 76 are not limited to chip components.

[0039] As shown in FIG. 4, the ESD protection element 70 has a first terminal 71a provided at one end and a second terminal 71b provided at the other end. The ESD protection element 70 is fixed to the first surface 20a of the substrate 20 by connecting the first terminal 71a and the second terminal 71b to first and second ESD patterns 28a and 28b (see FIG. 2) formed on the first surface 20a of the substrate 20. The ESD protection element 76, which has a first terminal 77a and a second terminal 77b, is also fixed to the substrate 20 via first and second ESD patterns 29a and 29b (see FIG. 2) in the same manner as the ESD protection element 70. The capacitor 50, the resistor elements 60 and 66, and the ESD protection elements 70 and 76 are also mounted on the first surface 20a of the substrate 20 by, for example, reflow soldering, in the same manner as the coil component 40.

[0040] Fig. 2 is a view of the substrate 20 of the composite electronic component 10 shown in Fig. 1, viewed from a first direction D1 (positive direction of the Z axis) perpendicular to the first surface 20a. As shown in Fig. 2, the substrate 20 has at least three (four in this embodiment) first to fourth coil patterns 21a to 21d formed on the first surface 20a and connected to the first to fourth terminals 41a to 41d of the coil component 40.

[0041] The substrate 20 also has at least two (two in the embodiment) first and second component patterns 23a, 23b formed on the first surface 20a and connected to the first terminal 51a and second terminal 51b of the capacitor 50, which is an overlapping component. Furthermore, on the first surface 20a of the substrate 20, four first resistor patterns 25a, 26a and second resistor patterns 25b, 26b connected to the first terminals 61a, 67a and second terminals 61b, 67b of the resistor elements 60, 66, and four first ESD patterns 28a, 29a and second ESD patterns 28b, 28b connected to the first terminals 71a, 77a and second terminals 71b, 77b of the ESD protection elements 70, 76 are formed.

[0042] 2, the first to fourth coil patterns 21a to 21d, the first and second component patterns 23a and 23b, the first resistor patterns 25a and 26a and the second resistor patterns 25b and 26b, and the first ESD patterns 28a and 29a and the second ESD patterns 28b and 28b exposed on the first surface 20a are connected to wiring (shown by dotted lines in FIG. 2) inside the substrate 20. Some of these patterns are also electrically connected by wiring inside the substrate 20.

[0043] 4, on the substrate 20, a first terminal 61a, which is one end of the resistive element 60, is wired to the first coil pattern 21a, which is one of the coil patterns 21a to 21d. Also, on the substrate 20, a second terminal 61b, which is the other end of the resistive element 60, is wired to the first component pattern 23a, which is one of the component patterns 23a and 23b and is not connected to the GND via 32. Similarly to the resistive element 60, the first terminal 67a and the second terminal 67b of the resistive element 66 are wired to the second coil pattern 21b, which is another one of the coil patterns 21a to 21d, and the first component pattern 23a.

[0044] 4, for example, on the substrate 20, the first terminal 71a of the ESD protection element 70 is wired to the first coil pattern 21a, which is one of the coil patterns 21a to 21d. Also, the first terminal 77a of the ESD protection element 76 is wired to the second coil pattern 21b, which is another one of the coil patterns 21a to 21d.

[0045] 2, the substrate 20 has a GND via 32 that electrically connects the second component pattern 23b, which is one of the component patterns 23a, 23b, to a GND pattern 30 (see FIG. 4) of the substrate 20. The GND via 32 is made of a conductor or the like that penetrates an insulating layer (not shown) of the substrate 20, and is formed inside the substrate 20 in the first direction D1 (Z-axis direction). The GND via 32 connects, in the Z-axis direction, the second component pattern 23b on the first surface 20a or a wiring connected thereto near the first surface 20a, to the GND pattern 30 that is formed on the back side (negative Z-axis direction side) of the second component pattern 23b and the wiring, with an insulating layer sandwiched between them.

[0046] In addition to the GND via 32, the substrate 20 also has ESD GND vias 34 and 35 that electrically connect the second ESD patterns 28b and 29b (see FIG. 2) to the GND pattern 30. Like the GND via 32, the ESD GND vias 34 and 35 are also made of a conductor or the like that penetrates an insulating layer (not shown) of the substrate 20.

[0047] By mounting coil component 40, capacitor 50, resistive elements 60, 66, and ESD protection elements 70, 76 on substrate 20 as shown in FIG. 4, composite electronic component 10 having the equivalent circuit shown in FIG. 3 is formed.

[0048] 2, the GND via 32 is arranged in a substrate outer region 38, which is a region outside a polygon 36 (a rectangle in this embodiment) that connects all of the coil patterns 21a to 21d with the shortest perimeter on the substrate 20, when viewed from the first direction D1 (Z-axis direction). In FIG. 2, the polygon 36 is indicated by a two-dot chain line.

[0049] 4, in the substrate 20, by arranging the GND via 32 in the substrate outer region 38, it is possible to prevent the region where the GND pattern 30 is formed (the region indicated by diagonal hatching in FIG. 4) from overlapping with the substrate inner region 37 (the region indicated by a dotted pattern in FIG. 4), which is the region inside the polygon 36, when viewed from the first direction D1. Note that when ESD protection elements 70, 76 are mounted on the substrate 20, the ESD GND vias 34, 35 are also arranged in the substrate outer region 38, similar to the GND via 32.

[0050] A composite electronic component 10 having such a substrate 20 reduces the area where the GND pattern 30 overlaps or is close to other patterns (including wiring), etc., reduces the generation of stray capacitance around the GND pattern 30, and effectively reduces noise generated in electrical signals transmitted through circuits made up of the composite electronic component 10. A composite electronic component 10 in which the coil component 40 is a common mode filter can realize an EMC countermeasure component that effectively reduces noise.

[0051] 4, at least a portion of the resistive elements 60 and 66, as viewed from the first direction D1 (Z-axis direction), is arranged in the substrate inner region 37, which is the region inside the polygon 36. Furthermore, of the component patterns 23a and 23b, at least a portion (the entire first component pattern 23a in this embodiment) of the first component pattern 23a, which is the side not connected to the GND via 32, is also arranged in the substrate inner region 37 as viewed from the first direction D1 (Z-axis direction).

[0052] 4, by arranging at least a portion of the resistive elements 60, 66 and the first component pattern 23a in the substrate inner region 37, it is possible to shorten the wiring distance within the substrate 20 and contribute to the miniaturization of the composite electronic component 10. Furthermore, in the composite electronic component 10, the GND pattern 30 does not overlap with the substrate inner region 37, which prevents the problem of stray capacitance occurring between the patterns and wiring arranged in the substrate inner region 37 and the GND pattern 30, thereby reducing noise.

[0053] The composite electronic component 10 will be described in further detail below using examples, but the technology of the present disclosure is not limited to these examples.

[0054] FIG. 5 is a conceptual diagram showing a composite electronic component 10 ( FIG. 5( a)) used in measurements according to the example and a composite electronic component 110 ( FIG. 5( b)) used in measurements according to the comparative example. In the example, as shown in FIG. 5( a), noise was measured using a composite electronic component 10 in which GND vias 32 are arranged in a substrate outer region 38, similar to the composite electronic component 10 shown in FIG. 4, and in which the substrate inner region 37 and the GND pattern 30 do not overlap. On the other hand, in the comparative example, noise was measured using a composite electronic component 110 in which GND vias 132 are arranged in a substrate inner region 37, and in which the substrate inner region 37 and the GND pattern 130 overlap, as shown in FIG. 5( b). The composite electronic component 110 according to the comparative example is similar to the composite electronic component 10 according to the example, except for the arrangement of the GND vias 132 and the shape of the GND pattern 130.

[0055] A graph of the noise measurement results for the example shown in Fig. 5(a) is shown in Fig. 6, and a graph of the noise measurement results for the comparative example shown in Fig. 5(b) is shown in Fig. 7. In Fig. 6 and Fig. 7, the radiation intensity of VCCI-B is shown together with the noise measurement results.

[0056] As shown in Fig. 6, in the example shown in Fig. 5(a), the noise intensity is reduced to a level that satisfies the VCCI-B standard in all frequency bands from 30 MHz to 1 GHz. In contrast, in the comparative example shown in Fig. 5(b), the noise intensity exceeds the VCCI-B standard in the frequency band around 110 MHz, resulting in a result where the noise intensity is stronger overall than in the example. The difference between the measurement results of the example shown in Fig. 6 and the measurement results of the comparative example shown in Fig. 7 is thought to be due to the difference in how stray capacitance occurs in the composite electronic components 10 and 110.

[0057] Although the composite electronic component 10 has been described above using embodiments and examples, it goes without saying that the scope of the present disclosure is not limited to these embodiments and examples and includes many other embodiments and modifications. For example, as shown in FIG. 2, in the composite electronic component 10, polygon 36 is a square, but the shape of the polygon varies depending on the number and arrangement of the coil patterns. For example, the polygon connecting all of the coil patterns with the shortest perimeter could be a triangle or a polygon with five or more sides. [Explanation of symbols]

[0058] 10, 110...Composite electronic components 20...Substrate 20a...First surface 21a...First coil pattern 21b... Pattern for second coil 21c...Third coil pattern 21d...4th coil pattern 23a...First part pattern 23b...Pattern for second part 25a, 26a...First resistor pattern 25b, 26b...Second resistor pattern 28a, 29a...First ESD pattern 28b, 29b...Second ESD pattern 30, 130...GND pattern 32, 132...GND via 34, 35...ESD GND via 36…Polygon 37...Inner area of the board 38...Outer area of the board 40...Coil parts 41a...1st terminal 41b…Second terminal 41c…3rd terminal 41d...Fourth terminal 42...winding 43...Core 50...Capacitor 51a...1st terminal 51b…Second terminal 60, 66...Resistance element 61a, 67a...First terminal 61b, 67b...2nd terminal 70, 76...ESD protection elements 71a, 77a...1st terminal 71b, 77b...2nd terminal D1...first direction 80...Transceiver

Claims

1. a substrate having a GND pattern; a coil component having at least three terminals and mounted on a first surface of the substrate; an overlapping arrangement component that is an electronic component shorter in height than the coil component and is mounted on the first surface so that at least a portion of the electronic component overlaps the coil component when viewed from a first direction perpendicular to the first surface; the substrate has at least three coil patterns formed on the first surface and connected to the terminals, at least two component patterns formed on the first surface and connected to the overlapping components, and a GND via that electrically connects one of the component patterns to the GND pattern; The GND via is disposed in a substrate outer region, which is a region outside a polygon that connects all of the coil patterns on the substrate with the shortest perimeter when viewed from the first direction.

2. 2. The composite electronic component according to claim 1, wherein the coil component is a common mode filter.

3. 2. The composite electronic component according to claim 1, wherein the overlapping component is a capacitor.

4. a resistive element mounted on the first surface so that at least a portion of the resistive element overlaps with the coil component when viewed from the first direction; 2. The composite electronic component according to claim 1, wherein, on the substrate, one end of the resistor element is wired to one of the coil patterns, and the other end of the resistor element is wired to another one of the component patterns.

5. The composite electronic component according to claim 4 , wherein at least a portion of the resistor element is disposed in a substrate inner region that is a region inside the polygon on the substrate when viewed from the first direction.

6. 2. The composite electronic component according to claim 1, wherein at least a portion of the other one of the component patterns is disposed in a substrate inner region that is an inner region of the polygon on the substrate when viewed from the first direction.

7. an ESD protection element mounted on the first surface so that at least a portion of the ESD protection element overlaps with the coil component when viewed from the first direction; 2. The composite electronic component according to claim 1, wherein the ESD protection element is wired to one of the coil patterns on the substrate.

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