Wafer Alignment Using Multiple Scanning Electron Microscopy

Abstract

The method includes controlling a multi-scanning electron microscope (mSEM) (32) to capture a first image (601) of a wafer (100) mounted on a motorized processing stage (90) while the motorized processing stage (90) is in a first position, the first image (601) including at least a portion of a notch (201) of the wafer (100); determining a radial axis (205) of the wafer (100) based on the first image (601); and controlling the motorized processing stage (90) to shift the wafer (100) along the radial axis (205) by half a diameter of the wafer (100) so that the motorized processing stage (90) is in a second position; controlling the mSEM (32) to capture a second image (602) of the wafer (100) while the processing stage (90) is in a second position, the second image (602) including wafer structures (112, 112-1 to 112-4, 113, 261, 262, 272); determining a reference position (209) of the wafer (100) based on structural recognition of the wafer structures (112, 112-1 to 112-4, 113, 261, 262, 272) in the second image (602); and aligning a wafer coordinate system (192) of the wafer (100) to a stage coordinate system (191) of the powered processing stage (90) based on the reference position (209) and the radial axis (205).

Description

[Technical Field]

[0001] This application relates generally to the art of wafer alignment. More particularly, the present invention relates to wafer alignment using multi-scanning electron microscopy. [Background technology]

[0002] State-of-the-art semiconductor structures are built with minimum feature sizes, or critical dimensions, down to about 5 nanometers, with devices having even smaller critical dimensions being developed. Fabrication of such semiconductor structures can involve approximately 1000 fabrication steps, starting with a blank wafer and forming an array of semiconductor dies, each of which contains a semiconductor structure. The fabrication steps include, for example, approximately 100 lithography steps. In modern manufacturing lines, up to 200 wafers can go through each lithography step per hour.

[0003] Each semiconductor die, and sometimes each semiconductor structure, has a well-defined location within a wafer coordinate system, which defines a lateral position on the planar surface of the wafer. The wafer coordinate system may be aligned, for example, with (i) the center of the wafer or other central reference location, and (ii) a notch in the wafer.

[0004] To obtain a high yield of semiconductor structures, approaching 100%, it is typically necessary to carefully monitor variations in any fabrication step that could indicate process variations that result in defects. Therefore, high-speed in-line metrology is used between or integrated into different fabrication steps. This metrology is sometimes also called wafer inspection. Metrology tools are used to detect signs of process variations or defect candidates in structures after a specified fabrication step. Typical silicon wafers used in the manufacture of semiconductor structures have diameters of up to 12 inches (300 mm). With small feature sizes, defect candidates on the order of the critical dimension must be identified over a very large area in a short time.

[0005] For wafer inspection, some type of image of the wafer surface is typically captured using an imaging modality, such as scanning electron microscopy (SEM) or X-ray diffraction. The field-of-view (FOV) of the imaging modality is in a defined alignment with a motorized handling stage to which the wafer can be attached. Typically, such motorized handling stages have at least two or three or more degrees of freedom (e.g., lateral displacement, vertical displacement, rotation, and tilt). Motorized handling stages can be positioned with high precision, for example, using closed-loop feedback control for any associated motion. Motion of the wafer handling stage is specified in a stage coordinate system associated with the motorized handling stage.

[0006] Thus, semiconductor wafer inspection is critical to semiconductor process control and manufacturing. There are many steps and types of analysis involved in defect monitoring and yield management services. Wafer inspection forms one of the key components of this task. Due to the extremely small dimensions of features and defects (on the order of nanometers), it is essential to have a good reference point for maneuvering, i.e., positioning the motorized processing stage, along with the die and wafer. Wafer alignment is used to register the wafer coordinate system with the stage coordinate system. Such alignment can be used to create a wafer map, i.e., a mapping between positions in the stage coordinate system and positions in the wafer coordinate system. Thus, wafer alignment and wafer map creation form the basis of the diagnostic / characterization methodology that must be followed, because the FOV of the imaging modality used for wafer inspection is aligned within the stage coordinate system.

[0007] According to standard techniques, performing wafer alignment can be a time-consuming task. For example, different microscopy techniques offering a wide variety of specifications in terms of (i) resolution and (ii) FOV often need to be combined. Coarse alignment is typically performed using a microscopy technique offering a wide FOV, which often suffers from limited resolution. A typical example is optical microscopy. Fine alignment is then performed using a further microscopy technique, such as SEM, which offers higher resolution but is often limited in terms of the available FOV. At this time, switching between the two microscopy techniques introduces inaccuracies or translational shifts that make wafer alignment difficult to complete. In particular, the fields of view between multiple imaging modalities may not be aligned. Furthermore, the pose of the detector optics of each of the multiple imaging modalities relative to the wafer may change due to, for example, non-uniaxial alignment. For example, in this case, capturing multiple images for fine alignment may be required to detect the alignment markers. Due to the limited FOV of the microscopy techniques used for fine alignment, ambiguities in the repeat placement of alignment markers or semiconductor structures may sometimes result in erroneous alignment results.

[0008] The following references are known: US Pat. No. 10,199,330 and US Pat. No. 10,199,316. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent Publication No. 10,199,330 [Patent Document 2] U.S. Patent Publication No. 10,199,316 Summary of the Invention

[0010] Therefore, there is a need for advanced techniques for wafer alignment, and in particular, advanced techniques that overcome or mitigate at least some of the drawback limitations identified above.

[0011] This need is met by the features of the independent claims. The features of the dependent claims define embodiments.

[0012] The method includes controlling a multi-scanning electron microscope (mSEM) to capture a first image of a wafer. The wafer is mounted on a motorized processing stage. The mSEM is controlled to capture the first image while the motorized processing stage is in a first position. The first image includes at least a portion of a notch in the wafer. The method also includes determining a radial axis of the wafer based on the first image. The method further includes controlling the motorized processing stage to shift the wafer along the radial axis by half a wafer diameter, with the motorized processing stage in a second position. The method further includes controlling the mSEM to capture a second image of the wafer while the motorized processing stage is in the second position. The second image includes a wafer structure. The method also includes determining a reference position of the wafer based on structure recognition of the wafer structure in the second image. The method further includes aligning a wafer coordinate system of the wafer to a stage coordinate system of the motorized processing stage based on the reference position and the radial axis.

[0013] The computer program, computer program product, or computer-readable storage medium includes program code executable by at least one processor. Execution of the program code causes the at least one processor to perform a method. The method includes controlling a multiple scanning electron microscope (mSEM) to capture a first image of a wafer. The wafer is attached to a motorized processing stage. The mSEM is controlled to capture the first image while the motorized processing stage is in a first position. The first image includes at least a portion of a notch in the wafer. The method also includes determining a radial axis of the wafer based on the first image. The method further includes controlling the motorized processing stage to shift the wafer along the radial axis by half a wafer diameter, while the motorized processing stage is in a second position. The method further includes controlling the mSEM to capture a second image of the wafer while the motorized processing stage is in the second position. The second image includes a wafer structure. The method also includes determining a reference position of the wafer based on structural recognition of the wafer structure in the second image. The method further includes aligning a wafer coordinate system of the wafer to a stage coordinate system of the powered processing stage based on the reference position and the radial axis.

[0014] The processing device includes a control circuit. The control circuit is configured to control a multi-scanning electron microscope (mSEM) to capture a first image of a wafer mounted on the motorized processing stage while the motorized processing stage is in a first position. The first image includes at least a portion of a notch in the wafer. The control circuit is further configured to determine a radial axis of the wafer based on the first image. The control circuit is further configured to control the motorized processing stage to shift the wafer along the radial axis by half a diameter of the wafer, such that the motorized processing stage is in a second position. The control circuit is further configured to control the mSEM to capture a second image of the wafer while the motorized processing stage is in the second position, the second image including a wafer structure. The control circuit is further configured to determine a reference position of the wafer based on structural recognition of the wafer structure in the second image. The control circuit is further configured to align a wafer coordinate system of the wafer to a stage coordinate system of the motorized processing stage based on the reference position and the radial axis.

[0015] It is to be understood that the features mentioned above and those which will be described hereinafter may be used not only in the respective combinations shown, but also in other combinations or in isolation without departing from the scope of the invention. [Brief explanation of the drawings]

[0016] [Figure 1] 1A and 1B are diagrams that schematically illustrate wafer and stage coordinate systems, according to various examples. [Figure 2] FIG. 1 is a diagram that schematically illustrates a die coordinate system, according to various examples. [Figure 3] 1A-1C are diagrams that schematically illustrate wafer fabrication and wafer inspection, in accordance with various examples. [Figure 4] FIG. 1 is a diagram that schematically illustrates a system, in accordance with various examples. [Figure 5] 1 is a flowchart of a method, according to various examples. [Figure 6]1A-1C are diagrams that schematically illustrate a notch and a center of a wafer, according to various examples. [Figure 7] 1A-1C are diagrams that schematically illustrate a notch and a center of a wafer, according to various examples. [Figure 8] 1 is a diagram that schematically illustrates semiconductor dies around a center of a wafer, in accordance with various examples. DETAILED DESCRIPTION OF THE INVENTION

[0017] Some examples of the present disclosure generally provide a plurality of circuits or other electrical devices. All references to circuits and other electrical devices and the functionality provided by each are not intended to be limited to encompass only those illustrated and described herein. While specific numerals may be assigned to various disclosed circuits or other electrical devices, such numerals are not intended to limit the scope of operation for the circuits and other electrical devices. Such circuits and electrical devices can be combined with each other and / or separated in any manner based on the particular type of electrical implementation desired. It should be understood that any circuit or other electrical device disclosed herein can include any number of microcontrollers, graphics processing units (GPUs), integrated circuits, memory devices (e.g., FLASH, random access memory (RAM), read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or other suitable variants thereof), and software that act together to perform the operations disclosed herein. Additionally, any one or more of the electrical devices may be configured to execute program code embedded in a non-transitory computer-readable medium that is programmed to perform any number of functions as disclosed.

[0018] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood that the following description of the embodiments should not be taken in a limiting sense. The scope of the present invention is not intended to be limited by the embodiments described hereinafter or by the drawings, which shall be taken as merely illustrative.

[0019] The drawings should be considered schematic representations, and the elements illustrated in the drawings are not necessarily drawn to scale. Rather, the various elements are represented so that their function and general purpose will be apparent to one skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be implemented by an indirect connection or coupling. Coupling between components may also be established via wireless connections. The functional blocks may be implemented in hardware, firmware, software, or a combination thereof.

[0020] Techniques for wafer alignment are described hereinafter. The techniques described herein facilitate generating a wafer map. A wafer map may represent a mapping of (i) positions in a stage coordinate system of a motorized processing stage to (ii) positions in a wafer coordinate system associated with a wafer. Wafer maps may be used in wafer inspection, for example, to align one or more positions on a wafer with the FOV of an associated imaging modality.

[0021] According to the techniques described herein, a multiple scanning electron microscope (mSEM) can be used for wafer alignment.

[0022] In particular, various examples are based on the observation that, in a reference implementation, wafer alignment is a two-step process involving first coarse alignment using an optical microscope and second fine alignment using a scanning electron microscope. According to various examples described herein, an mSEM can be used to complete the entire process required for wafer alignment, thus avoiding the coarse alignment using an optical microscope. An mSEM is an implementation of a charged particle microscope. In an mSEM, a wafer is irradiated with an array of electron beams as primary radiation, including, for example, more than 40 or even more than 90 electron beams. The beams are scanned together over the wafer to collectively form a large-area image of the wafer. For each scanning position, multiple beams are used to acquire the image, providing a large FOV. The image is formed based on secondary particles or radiation emitted from the wafer in response to irradiation by the primary radiation, i.e., the electron beam. The secondary radiation can be in the form of secondary electrons, backscattered electrons, X-rays, and / or luminescent radiation. The composition, energy, and angle of the secondary radiation can be controlled by the energy of the primary radiation and are indicative of the material composition and surface quality of the scanned wafer surface. mSEM allows for high-speed scanning of the wafer surface, making it highly suitable for high-throughput wafer metrology. For example, the FOV of an mSEM can be on the order of 100 micrometers by 100 micrometers or even 120 micrometers by 120 micrometers, while the FOV of a conventional scanning electron microscope can be on the order of 1 micrometer by 1 micrometer. The resolution of each mSEM image can be on the order of 5 nm by 5 nm.

[0023] Using an mSEM for wafer alignment allows both fine and coarse alignment to be performed in one go. In particular, global and local features can be identified from the mSEM image, for example, without the need for complementary optical images. This makes wafer alignment robust and simplified. In further detail, it is possible to reduce translational errors encountered when using multiple imaging modalities that are not aligned in a single axis. The large FOV of an mSEM can be used to locate unique structures on the wafer, such as alignment markers or semiconductor structures or other wafer structures, and use such structures for wafer alignment. Furthermore, when used in conjunction with image processing algorithms such as feature recognition, the large FOV also ensures uniqueness; typically, the context of repeating structures on the wafer can be captured by such a large FOV of an mSEM, thus resolving ambiguities due to the repeating nature of the repeating structures. The high resolution of the mSEM allows for precise alignment by using small features of the structure.

[0024] 1 schematically illustrates aspects related to a stage coordinate system 191 and a wafer coordinate system 192. The stage coordinate system 191 is associated with a motorized wafer processing stage 90 (hereinafter simply the stage).

[0025] Wafer 100 is mounted on stage 90. Wafer 100 includes an array 111 of semiconductor dies 112. Array 111 defines a repeating order of semiconductor dies 112. Wafer 100 also includes a notch 201 that, together with the center of wafer 100, defines wafer coordinate system 192 (in the example of FIG. 1, wafer coordinate system 192 is defined by lateral dimensions; a vertical dimension perpendicular to the drawing plane of FIG. 1 is not illustrated).

[0026] In the example of FIG. 1, the origin of wafer coordinate system 192 is aligned with notch 201, but in other examples, the origin of wafer coordinate system 192 may be aligned separately, for example, with the center of wafer 100 or another reference position.

[0027] Wafer alignment techniques are described below. Wafer alignment refers to the process of aligning the wafer coordinate system 192 with the stage coordinate system 191.

[0028] After the wafer 100 is mounted on the stage 90, the orientation of the wafer coordinate system 192 relative to the stage coordinate system 191 is unknown, or at least not known with the accuracy required for fabrication or metrology. For example, there may be a rotation of the primary axes of the wafer coordinate system 192 in the lateral plane relative to the primary axes of the stage coordinate system 191. Also, to name a few examples that may result in differences between the stage coordinate system 191 and the wafer coordinate system 192, the primary lateral axes of the wafer coordinate system 192 may be tilted out of the lateral plane of the stage coordinate system 191 (i.e., the wafer surface is tilted out of the mounting surface of the stage 90 due to non-planar mounting). The effects of such differences can be compensated for based on wafer alignment by aligning the wafer coordinate system 192 to the stage coordinate system 191. A coordinate transformation can be determined between the wafer coordinate system 192 and the stage coordinate system 191, and / or vice versa.

[0029] Sometimes, a die coordinate system may be used in addition to the stage coordinate system 191 and the wafer coordinate system, and the die coordinate system may be aligned to the stage coordinate system as part of wafer alignment. More details regarding the die coordinate system are described in connection with FIG. 2.

[0030] 2 schematically illustrates aspects related to die coordinate system 193. Die coordinate system 193 is associated with semiconductor die 112 of array 111. In particular, each semiconductor die 112 of array 111 may have its own associated die coordinate system 193. The positions of one or more semiconductor structures 113 within each semiconductor die 112 may be defined relative to the respective die coordinate system 193. The semiconductor die 112 may be repeating, i.e., each semiconductor die 112 may include the same arrangement of the same one or more semiconductor structures 113.

[0031] Generally, each semiconductor die 112 may have a respective die coordinate system 193 defined relative to a reference position of the respective semiconductor die 112, e.g., a corresponding origin located at a corner or center thereof. The multiple die coordinate systems 193 may be transformed relative to one another by a translational shift between the respective reference positions of the multiple semiconductor dies 112.

[0032] The die coordinate systems 193 are sometimes also labeled local coordinate systems because they define the local positions of the semiconductor structures 113 on each of the dies 112, while the wafer coordinate system 192 is sometimes referred to as a global coordinate system because it defines the positions of the dies 112 of the array 111 globally, i.e., at the wafer level of the wafer 100.

[0033] According to various examples, for example, as part of wafer alignment, die coordinate systems 193 of semiconductor dies 112 can be aligned to stage coordinate system 191. This can include finding an appropriate reference position for each semiconductor die 112.

[0034] For example, stage 90 can then be positioned by appropriately controlling the motors of stage 90 so that a selection of semiconductor structures 113 is in the center of the FOV of the respective imaging modality (which has an FOV aligned with stage 90). Wafer inspection can then be performed.

[0035] As a general rule, a typical lateral length scale of semiconductor structures 113 may be on the order of nanometers to tens of nanometers or tens of nanometers. A typical lateral length scale of semiconductor die 112 may be on the order of tens of micrometers to 100 micrometers, i.e., at least 1,000 times larger than the typical length scale of semiconductor structures 113. Thus, by using an mSEM, it is possible to have a resolution large enough to image details of each semiconductor structure 113, as well as a FOV large enough to image a significant percentage of semiconductor die 112. This facilitates coarse and fine alignment.

[0036] Wafer alignment as discussed herein can be used for in-line metrology during the manufacture of semiconductor structures. An example of the manufacture of such semiconductor structures as an application environment for various embodiments is illustrated in FIG.

[0037] 3, the fabrication of a semiconductor structure begins with a blank wafer 100. Examples of such wafers include silicon wafers or gallium arsenide wafers, although any semiconductor wafer may be used.

[0038] First, the wafer 100 is subjected to so-called front-end processing 11. Front-end processing refers to all processing steps in which structures are formed on the wafer before the structures on the wafer are mechanically separated (released) from one another. For mass production, multiple identical structures are formed on the wafer, which are then separated into individual semiconductor structures.

[0039] The front-end processing 11 includes multiple fabrication steps 13. Such fabrication steps 13 may include etching, layer deposition of semiconductor or metal layers, diffusion or implantation for e.g., doping, cleaning, wafer planarization, resist coating and resist treatment, lithography exposure, etc. Through these fabrication steps 13, structures are formed on the wafer 100, e.g., an array 111 of semiconductor dies (see FIG. 1).

[0040] After a particular fabrication step 13, the wafer is subjected to in-line metrology / wafer inspection 14. In addition to, or as an alternative to, in-line metrology 14, measurements may be performed "in situ," i.e., during one or more of the fabrication steps 13.

[0041] In wafer inspection, methods and devices such as those described above and further below are used to perform wafer alignment. Wafer inspection may include various measurements of physical parameters, such as film thickness, film uniformity, particle or contamination detection, or measuring electrical parameters such as resistance or capacitance. Using metrology, the dimensions of structures formed on the wafer may be determined by acquiring an image of the wafer. The image may be obtained at a well-defined location on the wafer because the wafer coordinate system 192 (and optionally, the die coordinate system 193) is aligned with the stage coordinate system 191. Optionally, a defect map 16 of the wafer may be acquired, i.e., information about locations on the wafer where structures are not formed as desired may be obtained. The defect map may be defined relative to the wafer coordinate system 192. Determining the presence or absence of a defect can be performed by comparing the image data with previously collected data for a similar area of another object (die-to-die), or it can be performed by comparison with corresponding locations in a reference database (die-to-database) or design data (die-to-CAD). All data can be handled and controlled within databases, including a defect database that forms a set of representative defects, a CAD database that collects information about ideal or representative structures, and process recipes.

[0042] For wafer inspection during the fabrication step 13 or in in-line wafer inspection 14, these measurements can be performed directly or using special test structures, either on product wafers, i.e., wafers intended for manufacturing semiconductor structures for sale, or alternatively on special non-functional monitor wafers (also called dummy wafers). Specially designed test structures are also known as process control monitors (PCMs).

[0043] Once defects are detected, the wafer 100 on which the defects are detected may be provided to at-line wafer defect review and classification 17. "At-line" in this case indicates that the wafer 100 is removed from the normal production process for further inspection. In particular, during review and classification 17, locations identified within the wafer defect map may be reviewed to identify and classify those indicative of process variations or defects. Images may be acquired at well-defined locations on the wafer 100 because the wafer coordinate system 192 (and optionally, the die coordinate system 193) is aligned with the stage coordinate system 191. Thus, the stage 90 may be moved to the appropriate position for each imaging modality.

[0044] As a result, feedback instructions 15 to fabrication can be provided, for example, to modify fabrication parameters to take into account process variations, or instructions can also be provided, for example, to perform maintenance due to possible defective components in the corresponding fabricated device.

[0045] This repeats until all processing layers are determined to be complete in check 18. Following this, a wafer probe test 19 may be performed, in which, for example, structures on the wafer are electrically contacted by probes to perform test measurements.

[0046] Front-end processing 11 is followed by back-end processing 12, in which the wafer is diced into separate chips along the die paths between alignment dies 112 and the chips are packaged. Further testing of the fabricated semiconductor structures can occur during back-end processing.

[0047] As will be appreciated from the above, metrology and wafer inspection may depend on precise wafer alignment, and because the FOV of the imaging modality used as part of the metrology is defined within the stage coordinate system 191, it is important to precisely align the wafer coordinate system 192, and optionally any die coordinate system 193, to the stage coordinate system. This aids in being able to subsequently pinpoint the location of defects, which can, for example, help identify the pass / fail status of each wafer or help identify the root cause of associated defects. The techniques described herein facilitate such precise wafer alignment. More details regarding precise wafer alignment are now described in conjunction with the following figures.

[0048] 4 illustrates a system 30. The system 30 can be used for wafer alignment according to various examples. The system 30 includes a processing device 31, an image acquisition device 32, and a stage control device 33. The processing device 31, the image acquisition device 32, and the stage control device 33 each include respective communication interfaces 901, 911, 921 and can communicate with one another via the communication interfaces 901, 911, 921.

[0049] Although FIG. 4 illustrates a scenario in which a single image acquisition device 32 is used, sometimes multiple image acquisition devices may be used.

[0050] The image acquisition device 32 can be an optical image acquisition device using short wavelength light, such as for spectroscopic measurements or X-ray-based measurements such as X-ray transmission or diffraction microscopy, or a charged particle-based device, such as a scanning electron microscope or focused ion beam microscope, using electrons or other particles such as gallium or helium ions. These charged particle-based devices are collectively referred to as charged particle microscopes. One specific implementation of a charged particle microscope is an mSEM. Hereinafter, the technology will be described with reference to a technology in which the image acquisition device 32 is implemented as an mSEM. An mSEM provides a pixel density, i.e., high resolution, high enough to capture the smallest relevant details, e.g., smallest occurring defects or deviations, from a semiconductor structure 113. Meanwhile, an mSEM provides a FOV large enough to capture the spatial context of individual structures, e.g., by capturing a significant area / region of multiple semiconductor structures 113, or a die 112, or multiple alignment markers. FIG. 4 illustrates the optical elements 912 of the mSEM 32.

[0051] The stage control device 33 includes motors 922 that can be used to reposition the stage 90, for example, along the primary lateral axis of the stage coordinate system 191. The positioning accuracy can be in the sub-micrometer range.

[0052] The processing device 31 includes a processor 902 and a memory 903, both of which form a control circuit. For example, the control circuit can transmit control data to the stage control device 33 to control the stage 90 to reposition the wafer 100. The control circuit of the processing device 31 can also receive images from the optical element 912 of the mSEM 32. For example, the control circuit can be implemented to perform feature recognition of features contained in such images. The control circuit can be configured to perform wafer alignment by aligning the wafer coordinate system 192 to the stage coordinate system 191 and, optionally, one or more of the die coordinate systems 193 to the stage coordinate system 191. Then, when a particular location on the wafer 100, e.g., a particular semiconductor structure 113, is to be positioned within the FOV of a given imaging modality for wafer inspection, the control circuit can calculate a required shift in the stage coordinate system 191 based on the associated location in the wafer coordinate system 192 and / or the respective die coordinate system 193. Appropriate control data can then be transmitted to the motors 922 of the stage control device 33 .

[0053] Further details regarding the functionality of system 30 are described below in conjunction with FIG.

[0054] 5 is a flowchart of a method according to various examples. For example, the method of FIG. 5 may be performed by control circuitry of processing device 31. For example, the method of FIG. 5 may be performed by processor 902 upon loading program code from memory 903.

[0055] In box 1001, a wafer loading check is performed. For example, this may include checking whether the loading dock is closed and whether wafer 100 is properly attached to stage 90. Box 1001 may also include initializing stage 90, for example, by positioning stage 90 to a defined initial position in stage coordinate system 191.

[0056] When executing box 1001, wafer coordinate system 192 is not aligned with stage coordinate system 191. Therefore, the position of the center of the FOV of mSEM 32 on wafer 100 is known with low accuracy, i.e., an order of magnitude lower than the typical feature size of semiconductor structures 113. Typically, the alignment accuracy in the absence of a specific wafer alignment process (i.e., based on mechanical alignment when mounting wafer 100 on stage 90) is poorer than 100 micrometers and is limited by manual handling accuracy or loading equipment accuracy.

[0057] In box 1002, an optical microscope is used to identify the notch 201 in the wafer 100. This can be used for coarse alignment so that the FOV of the mSEM 32 is centered on a saddle point 202 in the notch 201 (example saddle points 202 are illustrated in Figures 6 and 7).

[0058] Thus, in box 1002, the optical microscope can be controlled to capture an optical image of the wafer 100 and then recognize the notch 201 within the optical image. Then, based on the recognition of the notch and based on a predetermined alignment of the mSEM's FOV and the stage coordinate system 191, the stage 90 can be controlled to traverse to a first position. The mSEM's FOV can be centered on the saddle point 202 of the notch 201 when the stage 90 is in the first position. For example, a computer-implemented feature recognition algorithm can be used.

[0059] The default alignment of the mSEM's FOV and stage coordinate system 191 may be defined by a fixed mechanical orientation of the mSEM optics 912 relative to the stage 90.

[0060] Next, in box 1003, the mSEM 32 may be controlled to capture a first image 601 of the wafer 100 while the stage 90 is in the first position. This first image 601 includes at least a portion of the notch 201. In particular, the first image 601 may include / image the saddle point 202 of the notch 201.

[0061] The saddle point 202 may then be used to determine the radial axis 205 (see FIGS. 6 and 7), see box 1004. More generally, the radial axis 205 that intersects the notch 201 and the center 209 of the wafer 100 may be determined based on a first image captured by the mSEM 32.

[0062] For example, a tangent 206 of the notch 201 may be determined based on the saddle point 202, and then a radial axis 205 may be determined to be orthogonal to the tangent 206. The radial axis 205 may also be determined as the axis of symmetry of the notch 201.

[0063] As a general rule, the tangent 206 and radial axis 205 may be parallel to the primary axes of the wafer coordinate system 192. Thus, box 1004 may help determine the orientation of the wafer coordinate system 192.

[0064] Once the radial axis 205 is determined, then in box 1005, the stage 90 is controlled to shift the wafer 100 along this radial axis 205 by half the diameter of the wafer 100. The diameter of the wafer 100 may be known a priori. Wafer sizes are typically standardized to, for example, 150 mm or 300 mm diameter.

[0065] Also, any offset perpendicular to the radial axis 205 may be compensated for in box 1005 .

[0066] Then, after traversing along the radial axis 205, the stage 90 is positioned at a second position. While the stage 90 is in the second position, the mSEM 32 is controlled to capture one or more second images 602 of the wafer 100.

[0067] The second image includes a reference position of the wafer 100. The reference position of the wafer 100 may correspond to the center 209 of the wafer 100 (see FIGS. 6 and 7). In other examples, the reference position may have a certain predetermined offset relative to the center 209. Hereinafter, for the sake of simplicity, it is assumed that the reference position corresponds to the center 209, although in other examples, other reference positions may be used.

[0068] The one or more second images 602 include wafer structures disposed at or around the center 209. Examples of such wafer structures are die passages, alignment markers, semiconductor structures 113, corners of semiconductor die 112, etc. The relative distances of such wafer structures to the center 209 may be known, for example, from a reference database or design data. Thus, based on structure recognition of device structures in the one or more second images, it is possible to determine the center 209 of wafer 100 in second image 602. As a general rule, structure recognition may be performed by a computer using an appropriate structure recognition algorithm.

[0069] Any stretch / skew of the wafer coordinate system 192 relative to the stage coordinate system 191 can then be determined, for example, based on a comparison of the actual distance between the saddle point 202 and the center 209 and the travel distance of the stage 90 .

[0070] Thus, once the center 209 of the wafer 100 is determined (or more specifically, once the position of the center 209 within the second image 602 is determined), the wafer coordinate system 192 can be aligned to the stage coordinate system 191 based on the center 209 and the radial axis 205. For example, the rotation between the wafer coordinate system 192 and the stage coordinate system 191 can be determined based on the alignment of the radial axis 205. By comparing the travel distance between the first and second positions of the stage 90 to the nominal dimension between the saddle point 202 and the center 209, any stretching or compression of the distance in the wafer coordinate system 102 versus the distance in the stage coordinate system 191 can be identified. For example, a transformation matrix can be obtained that transforms the wafer coordinate system 192 to the stage coordinate system 191, or vice versa. These are just a few examples of how to perform alignment of the wafer coordinate system 192 to the stage coordinate system 191. Other implementations are conceivable. General techniques for wafer alignment are known and can be reused here.

[0071] Details regarding determining the center 209 in box 1006 are illustrated in connection with FIG. 8 . FIG. 8 is a schematic diagram of the wafer 100 at and around the center 209. In particular, adjacent semiconductor dies 112-1 through 112-4 are illustrated. Orthogonal die streets 261 through 262 exist between the adjacent semiconductor dies 112-1 through 112-4. Alignment markers 272 exist between the die streets 261 through 262 and the semiconductor dies 112-1 through 112-4. The alignment markers 272 may have a repeating arrangement, as illustrated in FIG. 8 . The location of the center 209 in the second image 602 may be determined by performing structural recognition of the orthogonal die streets 261 through 262 and then identifying the centers of each intersection between the orthogonal die streets 261 through 262, thereby determining the center 209. For example, the die passages 261-262 may be recognized based on test structures within the die passages 261-262 (test structures not illustrated in FIG. 8) and / or based on adjacent alignment markers 272.

[0072] 5, the result of executing box 1007 is wafer alignment. Sometimes it may be desirable to also include aligning one or more die coordinate systems 193 to the stage coordinate system 191. The following boxes 1008-1010 may then be executed. Another reason for executing boxes 1008-1010 may be to increase the accuracy of the alignment of the wafer coordinate system 192 to the stage coordinate system 191.

[0073] In box 1008, one or more additional axes of the wafer 100 are determined. This may be based on the wafer coordinate system 192. With the initial alignment available (from box 1007), it is also possible to control the stage 90 to traverse along one or more additional axes in box 1009. While traversing along the one or more additional axes, the mSEM 32 is controlled to capture one or more third images 603 (the stage 90 may stop when capturing the one or more third images 603). The third images 603 include the semiconductor structures 113 of the die 112. In box 1010, the semiconductor structures 113 are recognized (i.e., the position of the semiconductor structures 113 within the third images 603 is determined using structure recognition), and then in box 1011, the correspondingly defined die coordinate system 193 can be aligned with the stage coordinate system 191. Again, any shift or translation can be identified by (i) the actual traveled distance between center 209 and dies 112-1 to 112-4 and semiconductor structure 113, and (ii) the deviation between the nominal dimensions, e.g., obtained from a CAD or database.

[0074] More details regarding these additional axes are described in connection with FIG. 8 . In particular, FIG. 8 illustrates a first exemplary implementation of such additional axis 215 and a second exemplary implementation of such additional axis 216. Additional axis 215 is a radial axis that intersects center 209. Axis 215 is aligned with die passage 262 and is therefore orthogonal to radial axis 205. In another example, it is also possible to determine additional axis 216 that has an offset 219 compared to axis 215. For example, offset 219 can be determined based on the width of die passages 261, 262, or more generally, based on the distance between adjacent semiconductor dies 112-1 to 112-4. The width of die passages 261, 262 correlates with the distance between adjacent semiconductor dies 112-1 to 112-4. Thus, the FOV 301 of the mSEM 32 can be aligned with the corners 271 of the semiconductor dies 112-1 and 112-3 when traversing along the additional axis 216. Therefore, better coverage of the semiconductor structures 113 within the semiconductor dies can be obtained when using the offset additional axis 216. This is because, as illustrated in FIG. 8 , when the width of the die passages 261 and 262 is, for example, about 60% to 140% of the width of the offset 219, the FOV 301 of the mSEM is typically at the same scale. It is possible to capture multiple third images for multiple adjacent semiconductor dies 112-1 and 112-3 arranged along the additional axes 215 and 216. The repeating semiconductor structures 113 of the adjacent semiconductor dies can then be recognized in the multiple third images, for example, by comparing the multiple third images with each other, and used for wafer alignment.

[0075] The specific position of each die 112-1 to 112-4 can then be determined, which can be used to align the respective die coordinate system 193 to the stage coordinate system 191 and / or to the wafer coordinate system 192. Also, the accuracy of the alignment of the wafer coordinate system 192 to the stage coordinate system 191 can be increased.

[0076] In summary, the above technique for wafer alignment is described. Pre-alignment using an optical microscope is used. Subsequent steps associated with wafer alignment do not rely on the use of an optical microscope, but rather use mSEM images. Such a technique has the advantage of avoiding offsets due to non-uniaxial alignment of optical microscopes and other imaging modalities, such as limited-FOV SEMs. The technique can be implemented quickly and reliably.

[0077] While the present invention has been shown and described with reference to certain preferred embodiments, equivalents and modifications will occur to those skilled in the art upon reading and understanding this specification. The present invention includes all such equivalents and modifications, and is limited only by the scope of the appended claims.

[0078] For example, although certain implementations are illustrated with respect to automatic feature recognition, in some instances feature recognition may be performed manually.

Claims

1. controlling a multiple scanning electron microscope, mSEM (32), to capture a first image (601) of a wafer (100) mounted on a motorized processing stage (90) while the motorized processing stage (90) is in a first position, the first image (601) including at least a portion of a notch (201) of the wafer (100); determining a radial axis (205) of the wafer (100) based on the first image (601); controlling the powered processing stage (90) to shift the wafer (100) along the radial axis (205) by half a diameter of the wafer (100) so that the powered processing stage (90) is in a second position; controlling the mSEM (32) to capture a second image (602) of the wafer (100) while the motorized processing stage (90) is in the second position, the second image (602) including wafer structures (112, 112-1 through 112-4, 113, 261, 262, 272); determining a reference position (209) of the wafer (100) based on structural recognition of the wafer structures (112, 112-1 to 112-4, 113, 261, 262, 272) in the second image (602); aligning a wafer coordinate system (192) of the wafer (100) with a stage coordinate system (191) of the motorized processing stage (90) based on the reference position (209) and the radial axis (205); A method comprising:

2. The method of claim 1, wherein the wafer structure targeted for structure recognition comprises orthogonal die passages (261, 262) between adjacent semiconductor dies (112, 112-1 to 112-4).

3. the wafer (100) comprises an array of semiconductor dies (112, 112-1 to 112-4); The method comprises: determining one or more further axes (215, 216) of said wafer (100); controlling the powered processing stage (90) to traverse along the one or more further axes (215, 216); controlling the mSEM (32) to capture one or more third images (603) while traversing along the one or more further axes (215, 216), the one or more third images (603) including semiconductor structures (113) of the semiconductor dies of the array; determining the semiconductor structure (113) based on further structure recognition within the one or more third images (603); Based on the recognition, aligning die coordinate systems (193) of the semiconductor dies (112, 112-1 to 112-4) with the stage coordinate system (191); 3. The method of claim 1 or 2, further comprising:

4. The method of claim 3 , wherein the one or more further axes include an axis (216) having an offset (219) relative to the central radial axis (215).

5. The method of claim 4, wherein the offset (219) is determined based on a width of a die passage (261, 262) between adjacent semiconductor dies (112, 112-1 to 112-4) of the array.

6. The method according to claim 4 or 5, wherein the field of view (301) of the mSEM (32) is in the range of 60% to 140% of the offset (219).

7. a plurality of third images (603) are captured for a plurality of adjacent semiconductor dies (112, 112-1 to 112-4) of the array adjacent to one another along the one or more further axes (215, 216); The method according to any one of claims 4 to 6, wherein the semiconductor structure (113) is determined in the plurality of third images (603) by comparing the plurality of third images (603) with each other.

8. the first image (601) includes a saddle point (202) of the notch (201); The method according to any one of claims 1 to 7, wherein the radial axis (205) of the wafer (100) is determined based on the saddle point (202).

9. controlling an optical microscope to capture an optical image of the wafer (100); Recognizing the notch (201) in the optical image; 9. The method of claim 1, further comprising: controlling the motorized processing stage (90) to traverse to the first position based on the recognition of the notch (201) and based on a predetermined alignment of the field of view of the mSEM and the stage coordinate system (191).

10. controlling a multiple scanning electron microscope, mSEM (32), to capture a first image (601) of a wafer (100) mounted on a motorized processing stage (90) while the motorized processing stage (90) is in a first position, the first image (601) including at least a portion of a notch (201) of the wafer (100); determining a radial axis (205) of the wafer (100) based on the first image (601); controlling the powered processing stage (90) to shift the wafer (100) along the radial axis (205) by half a diameter of the wafer (100) so that the powered processing stage (90) is in a second position; controlling the mSEM (32) to capture a second image (602) of the wafer (100) while the motorized processing stage (90) is in the second position, the second image (602) including wafer structures (112, 112-1 through 112-4, 113, 261, 262, 272); determining a reference position (209) of the wafer (100) based on structural recognition of the wafer structures (112, 112-1 to 112-4, 113, 261, 262, 272) in the second image (602); Aligning a wafer coordinate system (192) of the wafer (100) with a stage coordinate system (191) of the powered processing stage (90) based on the reference position (209) and the radial axis (205); A processing device (31) comprising control circuits (902, 903) configured to:

11. The processing device (31) of claim 10, wherein the control circuit (902, 903) is configured to perform the method of any one of claims 1 to 9.

12. A system (30) comprising a processing device (31) according to claim 10 or 11 and an mSEM (32).

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