Fault-tolerant T-gates via pseudoprobability decomposition.

Abstract

The combined quantum error correction and quantum error mitigation techniques are used to perform simulations of fault-tolerant T-gates with low sampling overhead using pseudo-probability decomposition. In some embodiments, T-gates can be simulated using two logic bits and magic state preparation, which alleviates the need for magic state distillation and results in low sampling overhead. Alternatively, T-gates can be simulated based on code transformations performed on surface codes. Noise is removed from T-gates using pseudo-probability decomposition based on learned logical error rates.

Description

[Technical Field]

[0001] The present disclosure relates to quantum computing, and more particularly to techniques that facilitate error mitigation in quantum computing devices. Summary of the Invention

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements of particular embodiments or the claims, or to delineate any scope thereof. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, device, computer-implemented method, or computer program product, or combination thereof, that facilitates error mitigation for quantum computing devices is described.

[0003] According to one embodiment, the system may include a simulation component that simulates a T-gate encoded using logical qubits encoded in an error-correcting code and at least one of a magic state or a code variant of a surface code; and a correction component that corrects noise on the encoded T-gate using quasiprobability decomposition.

[0004] According to another embodiment, a computer-implemented method may include simulating, by the system, a logical qubit encoded in an error-correcting code and a T-gate encoded using at least one of a magic state or a code variant of a surface code; and correcting, by the system, noise on the encoded T-gate using pseudoprobability decomposition.

[0005] According to another embodiment, a computer program product may include a computer-readable storage medium (or media) having program instructions embodied thereon, the program instructions being executable by a processor to cause the processor to simulate a T-gate encoded with at least one of a logical qubit encoded in an error-correcting code and a magic state or a code variant of a surface code; and to correct noise on the encoded T-gate using pseudoprobability decomposition. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 shows an example of a non-limiting implementation of a T-gate using only magic states and Clifford operations.

[0007] [Figure 2] FIG. 1 illustrates a block diagram of an example of a non-limiting system in which a fault-tolerant T-gate can be constructed.

[0008] [Figure 3] FIG. 1 shows a representation of a noisy T-gate that can be equated to an ideal T-gate in the presence of noise N.

[0009] [Figure 4] FIG. 1 illustrates a representation of an example of a non-limiting circuit illustrating pseudo-probabilistic decomposition.

[0010] [Figure 5a] FIG. 10 shows a plot of sampling overhead γε as a function of physical error rate ε using a surface encoding T-gate simulation approach for the case where ε i = ε I = 0 and ε 2 = ε.

[0011] [Figure 5b]FIG. 10 shows a plot of sampling overhead γε as a function of physical error rate ε using a surface encoding T-gate simulation approach for the case where ε i = ε I = ε 2 / 10 and ε 2 = ε.

[0012] [Figure 6] 1 shows an implementation of a fault-tolerant T-gate using code transformation.

[0013] [Figure 7] FIG. 1 illustrates a representation of an exemplary 5×5 surface code.

[0014] [Figure 8] FIG. 1 illustrates an example of a non-limiting sequence for implementing a fault-tolerant T-gate using sign transformation.

[0015] [Figure 9] FIG. 1 illustrates a flow diagram of an example of a non-limiting computer-implemented method by which a fault-tolerant T-gate can be created.

[0016] [Figure 10] FIG. 1 illustrates a block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein may be facilitated.

[0017] [Figure 11] FIG. 1 illustrates a cloud computing environment in accordance with one or more embodiments described herein.

[0018] [Figure 12] FIG. 2 illustrates an abstraction model layer according to one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0019] The following detailed description is merely exemplary and is not intended to limit the embodiments, or the application or uses of embodiments, or combinations thereof. Furthermore, there is no intention to be bound by any express or implied information presented in the preceding Background or Overview sections or in the Detailed Description section.

[0020] One or more embodiments will now be described with reference to the drawings. Like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances one or more embodiments may be practiced without these specific details.

[0021] Classical computers operate on binary digits (or bits), which store or represent information as binary states, to perform calculations and information processing functions. In contrast, quantum computing devices operate on qubits (or qubits), which store or represent information as both binary states and superpositions of binary states. As such, quantum computing devices exploit quantum mechanical phenomena such as entanglement and interference.

[0022] Quantum computing uses qubits as its essential units instead of classical computational bits. A qubit (e.g., a quantum binary digit) is the quantum mechanical analog of a classical bit. While a classical bit can utilize only one of two basis states (e.g., 0 or 1), a qubit can utilize a superposition of their basis states (e.g., α|0〉+β|1〉, where α and β are |α| 2 +|β| 2Quantum computers can use qubits (a complex scalar such that ≡ = 1), theoretically allowing a given number of qubits to hold exponentially more information than the same number of classical bits. Therefore, quantum computers (e.g., computers that use qubits instead of or in addition to classical bits) could theoretically quickly solve problems that would be extremely difficult for classical computers. Because bits in classical computers are simply binary digits with a value of either 0 or 1, nearly any device with two distinct states can serve to represent a classical bit—for example, a switch, valve, magnet, coin, or other such two-state device. Qubits, with their quantum mystique, can occupy a superposition of states 0 and 1. This is different from having intermediate values between 0 and 1. When the state of a qubit is measured, the result is either 0 or 1. However, during the course of a computation, a qubit can behave as if it represents a mixture of two states, e.g., 63% 0 and 37% 1.

[0023] A typical quantum program coordinates quantum and classical portions of a computation. When considering a typical quantum program, it is useful to identify the processes and abstractions involved in specifying a quantum algorithm, translating the algorithm into an executable form, running experiments or simulations, and analyzing the results. These processes rely on an intermediate representation of the computation. An intermediate representation (IR) is neither its source language description nor the target machine instructions, but something in between. Compilers may use some IR in the process of transforming and optimizing the program. The input to these compilers is source code describing the quantum algorithm and compile-time parameters, and the output is a combined quantum / classical program expressed using high-level IR. In contrast to classical computers, quantum computers are probabilistic, so that measurements of algorithmic outputs provide a reasonable solution within an algorithm-specific confidence interval. The computation is then repeated until a solution with satisfactory probability can be achieved.

[0024] Quantum computers can perform tasks significantly faster than classical computing devices. However, the fragile nature of quantum information makes quantum computers inherently noisy. The theory of quantum error correction and fault-tolerant quantum computing proposes methods by which complex computations can be reliably performed on defective devices. The threshold theorem states that the noise level of a physical gate exceeds a certain threshold ε greater than zero. th A lower δ guarantees that computations of arbitrary length are possible with arbitrarily low error rates. The cost for a fault-tolerant implementation of a particular circuit is the polylogarithmic space overhead. More precisely, to guarantee an eventual failure probability δ for a circuit C with |C| locations, O(log log(|C| / δ)) levels of encoding may be required, resulting in a space overhead of O(polylog(|C| / δ)). Currently, this overhead prevents fault-tolerant quantum computing.

[0025] For gates that can be implemented transversally, by definition, these gates are fault-tolerant because they do not spread substantial errors, and therefore have relatively small fault overhead. However, the Eastin-Knill theorem shows that quantum error-correcting codes cannot implement a universal set of gates transversally. In addition, for (self-dual) CSS codes such as surface codes, the set of Clifford gates is known to be transversal. To obtain a universal set of gates, according to Eastin-Knill, it is necessary to combine Clifford gates with additional gates, such as T-gates (non-Clifford gates), which cannot be implemented transversally in CSS codes.

[0026] Implementing a fault-tolerant T-gate with little overhead is not a trivial task. According to one approach, a technique called magic state distillation can be used to prepare a low-noise magic state in a fault-tolerant manner, which can then be converted into a T-gate with a Clifford circuit. FIG. 1 shows an exemplary implementation of a T-gate 102 using only magic states and Clifford operations. This approach can ease the problem of implementing a fault-tolerant T-gate (i.e., a T-gate that can reliably perform computations even on faulty devices) to the task of preparing a fault-tolerant magic state. The latter task can be achieved by magic state distillation, which converts several noisy magic states into a smaller number of higher-fidelity magic states. While magic state distillation is an elegant approach to achieving universal fault-tolerant quantum computing, the magic state distillation process used to obtain a low-noise magic state can lead to significant overhead in practice.

[0027] To address these and other issues, one or more embodiments described herein are directed to systems and methods for constructing fault-tolerant T-gates based on the pseudoprobability decomposition (QPD) method in a manner that reduces sampling overhead relative to current approaches. These systems and methods can implement a combination of quantum error correction (QEC) and quantum error mitigation (QEM)—e.g., the QPD method—to simulate fault-tolerant T-gates. In some embodiments, T-gates can be simulated using two logical bits and a magic state preparation that avoids magic state distillation and results in low sampling overhead. Alternatively, T-gates can be simulated based on code transformations performed on surface codes. This latter approach incurs slightly larger sampling overhead relative to the magic state approach, but only utilizes a single logical qubit.

[0028] Using pseudo-probabilistic decomposition, fault-tolerant T-gates can be simulated using a twiring-based tomography step, with sampling overhead scaling approximately as (1 + ε)t, where t is the number of T-gates and ε is the physical error rate. Approaches based on code transformation can use subsystem code and the transformation can be performed in software.

[0029] 2 illustrates a block diagram of an example non-limiting system 200 in which a fault-tolerant T-gate may be constructed in accordance with one or more embodiments described herein. The system 202 includes a memory 220 for storing computer-executable components and one or more processors 218 (e.g., one or more classical processors) operably coupled to the memory 220 via one or more communication buses 216 for executing the computer-executable components stored in the memory 220. As illustrated in FIG. 2, the computer-executable components include a simulation component 204 and a correction component 206.

[0030] Simulation component 204 can simulate a quantum T-gate using at least one of a magic state or a code variant of a surface code. Correction component 206 can correct noise on the quantum T-gate using pseudoprobability decomposition. In general, techniques implemented by embodiments of system 202 can simulate fault-tolerant T-gates with relatively low sampling overhead, in part by eliminating the need to perform magic state distillation, since these techniques can yield fault-tolerant T-gates even when noisy magic states are used.

[0031] As mentioned above, current quantum computers cannot outperform classical computers in computing tasks due to their susceptibility to noise and errors. Fault tolerance (FT) with quantum error correction (QEC) may provide a long-term solution to mitigate such noise and error sensitivity. However, FT with QEC is generally beyond the reach of current quantum computers and consumes significant computing resources.

[0032] Quantum error mitigation (QEM) can provide an intermediate solution to mitigate noise and error sensitivity in near-future quantum computers without promising perfect FT. Quasiprobability decomposition (QPD) is one such QEM technique.

[0033] The QPD method can be implemented without error even on noisy hardware, for example, when implementing a linear operator F on n qubits in a quantum computer. More precisely, the pseudoprobability method is a method for solving the problem of quantum states F(ρ in ) itself (where ρ in Instead of having access to the initial state of n qubits, we have access to a random state that can be sampled independently for each experimental run. This random state guarantees that F(ρ) for every measurement outcome. in ) However, this comes at a cost in the form of sampling overhead or C factor, which can be described in terms of the number of additional shots that must be performed.

[0034] According to the Gottesman-Knill theorem, quantum circuits using only Clifford gates can be efficiently simulated on classical computers. To fully utilize the capabilities of quantum computing, quantum computers must be able to implement a universal set of gates, including non-Clifford gates. However, implementing non-Clifford gates in a fault-tolerant manner is costly because non-Clifford gates cannot be implemented transversally. For some quantum circuits containing non-Clifford gates, 90%–99% of the available computing resources are dedicated to the task of achieving fault tolerance (e.g., using magic state distillation).

[0035] According to the first step of the approach applied to system 202, a T-gate is implemented (e.g., by simulation component 204). In one or more embodiments, this T-gate is implemented using the Clifford circuit and the

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[0036]

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[0037] For simplicity, we assume that the chosen code allows a noiseless implementation of the logic gate S=diag(1,i),X,CNOT, the preparation of logic |0? and |+? states, and the measurement of logic qubits in the Z and X bases. The state ρ is

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[0038] Therefore, the simulation component 204 can prepare the twiled state τ by first preparing ρ and then applying a logic A gate with probability 1 / 2. Since |0≡Z|π / 4≡, the twiled state τ can be prepared with probability

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[0039] The CNOT gate 108 propagates the Pauli-Z error from the magic state |π / 4? to the data qubit. The error does not affect the measurement. Therefore, using the twiled state τ instead of the ideal magic state |π / 4? in the T gate 102 shown in FIG. 1, the simulation component 204 calculates

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[0040] Second, error mitigation techniques are used to

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[0041]

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[0042] Therefore, equation (10) becomes:

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[0043] The correction component 204 then prepares the logic state |+? in a fault-tolerant manner;

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[0044] Logical Error Rate

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[0045] QPD (sometimes called probabilistic error cancellation) is a quantum hardware {ε i 4 is a representation of an exemplary circuit 402 illustrating the QPD method. Assuming that gate U 404 is executed and a measurement characterized by operator O 406 is performed, the expected value of the result of this measurement is

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[0046] In many quantum circuits, only the expectation value is of interest. The QPD method allows us to estimate this expectation value even when [U](ρ) cannot be implemented exactly in hardware. The first step of the QPD method is to determine whether the quantum hardware has access to quantum channels ε1,ε2,ε3,...ε M It is assumed that it is possible to implement

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[0047] With this decomposition, each time the quantum circuit is executed, i∈{1,...,M} has distribution p i The gate U404 is selected randomly with probability

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[0048] By properly weighting the measurements at the ends of the circuit, system 202 can perform Monte Carlo sampling to obtain an unbiased estimate of the true expected outcome of an ideal quantum circuit. The number of samples taken to reach a certain accuracy is O(γ 2 ) where γ is the sampling overhead of the QPD method.

[0049] Assuming U is the unitary operator corresponding to the noisy T-gate 302, this method can be utilized by the correction component 206 to obtain

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[0050] In this case, the sampling overhead is

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[0051] Figure 5a shows the ε i =ε I = 0 and ε = ε, the sampling overhead γ given by equation (26) as a function of the physical error rate ε via the surface encoding described in equation (4). ε 5b is a plot 502 of ε i =ε I = ε / 10 and ε = ε. ε This is plot 504.

[0052] In general, error mitigation using QPD methods involves:

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[0053] However, errors can occur in traversal operations and can be suppressed arbitrarily. Therefore, the actual final state is

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[0054]

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[0055] In the realistic case where |C|=poly(t), the code size scales polynomially with the number of locations |C|, rather than polylogarithmically as in standard fault-tolerant settings. However, recall that the nature of the QPD method means that only circuits with sufficiently small sampling overhead are considered. That is, if γ≦κ and κ>0 are not too large, then ε≧Δ / κ, and therefore

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[0056] According to the above-described approach, simulation component 204 simulates a T-gate using a magic state (as described above in connection with FIG. 1 ), and correction component 206 learns the logic error rate (and corresponding noise map N) on the T-gate and applies QPD to reduce this noise (as described above in connection with FIG. 4 ). This approach can result in a fault-tolerant T-gate even if the prepared magic state is noisy. Therefore, magic state distillation does not need to be used to prepare the magic state, resulting in a significant reduction in computational overhead relative to approaches that require magic state distillation to obtain a low-noise magic state.

[0057] The magic state approach described above, which may be used by some embodiments of simulation component 204 to simulate a T gate, utilizes two logical qubits 104 and 106 encoded with an error-correcting code. As an alternative to this approach, some embodiments of simulation component 204 may use another approach to implement a fault-tolerant T gate that utilizes only a single logical qubit encoded with an error-correcting code. This may reduce the requirements for experimentally demonstrating a fault-tolerant T gate. This alternative approach is based on code transformation of a surface code. FIG. 6 illustrates the implementation of a fault-tolerant T gate using code transformation. According to this approach, a code transformation is performed on a surface code 602a to represent a weight-1 logical Z operator, a logical T gate is simulated as a physical T gate in the resulting transformed code 602b, and then the transformed code 602b is transformed back to its original form.

[0058] 7 is a representation of an example 5×5 surface code 702 of distance d=3 that includes data qubits 710 (black dots), syndrome qubits 708 (white dots), Z stabilizer 706, and X stabilizer 704. Surface code 702 is thus 4d 2 It uses -4d+1 qubits and has transverse X, Y, Z, S, and H gates. However, the approach described herein is essentially agnostic to which code is used. In some scenarios, it may be beneficial to use other types of codes, such as rotated codes or dual surface codes.

[0059] In this noise model, for the CNOT, MeasX, MeasZ, PrepX, PrepZ operations and idle operations, the depolarized channel is assigned to the output qubit of CNOT.

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[0060] The preparation gate then outputs a state orthogonal to the ideal output with probability ε, and the measurement gate outputs an incorrect assignment with probability ε.

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[0061] 8 illustrates an exemplary sequence for implementing a fault-tolerant T-gate using code transformation according to one or more embodiments. This sequence, or another suitable code transformation sequence, may be performed by simulation component 204 in one or more embodiments. In this illustrated example, code transformation was performed on a surface code for a 9x9 subsystem with distance d=5. In general, the sequence described below can simulate the execution of a T-gate encoded for a surface code of distance d with code transformation.

[0062] In step 802a, each physical qubit may be initialized in the |+? state, and d syndrome readout rounds may be performed. This initializes the logical qubit in the |+? state. In step 802b, the stabilizer on the upper boundary is turned off. Then, in step 802c, a physical T-gate is applied to the northwest corner. Then, in step 802d, the stabilizer on the upper boundary is turned on, and d syndrome readout rounds are performed. Then, each physical qubit may be measured in the X basis, and error-corrected eigenvalues of the logical X operator may be calculated. If the measured eigenvalue is −1, a logical Z error may be declared. For the numerical calculations summarized by Fig. 7, this numerical simulation of κ is

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[0063] The code transformation approach can be applied in software by hiding one round of syndromes measured at the upper boundary from the decoding algorithm, so that the actual syndrome measurement circuitry does not need to be modified.

[0064] By combining quantum error correction with quantum error correction via QPD methods (an approach also referred to as QPD-assisted QEC), embodiments of the system 202 described herein enable the construction of fault-tolerant T-gates with a relatively small amount of sampling overhead compared to current technology. When the magic state approach described herein is used to simulate T-gates, applying QPD methods to reverse the effects of noise on the T-gates can result in fault-tolerant T-gates even using noisy magic states. This eliminates the need for magic state distillation on the magic state, correspondingly reducing sampling overhead. Alternatively, the code transformation approach described herein can be used to simulate fault-tolerant T-gates using only one logical qubit, rather than two logical qubits as in the magic state approach. While the sampling overhead increases relative to the magic state approach, the code transformation approach can still provide low sampling overhead compared to current approaches. In terms of hardware, QPD-assisted QEC can be implemented using only fault-tolerant T-gates, and in contrast to conventional QEC, magic state distillation is not required, thereby eliminating the need for a magic state factory.

[0065] As in classical simulation, the total simulation time overhead for QPD-assisted QEC scales exponentially as a function of the number of T-gates. The cost of the QPD-assisted QEC error mitigation technique is the sampling overhead γ ε ≥ 1, which depends on the physical error rate ε of the basic gate and adds exponentially as a function of the number of T gates (T count). For a circuit with T count t, the total sampling overhead is

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[0066] The sampling overhead is

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[0067] FIG. 9 illustrates a methodology according to one or more embodiments of the present application. For simplicity of explanation, the methodologies illustrated herein are illustrated and described as a series of acts; however, it will be understood and appreciated that the subject innovation is not limited by the order of acts, as some acts may occur in a different order than illustrated and described herein, or simultaneously with other acts, or in combinations thereof. For example, those skilled in the art will understand and appreciate that a methodology may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts are required to implement a methodology according to the invention. Furthermore, interaction diagrams may represent methodologies, or methods, according to the present disclosure, where disparate entities enact disparate portions of the methodology. Furthermore, two or more of the disclosed example methods may be implemented in combination with each other to achieve one or more features or advantages described herein.

[0068] FIG. 9 illustrates an exemplary methodology 900 for creating a fault-tolerant T gate according to one or more embodiments described herein. Initially, at 902, an encoded T gate is simulated (e.g., by simulation component 204) using logical qubits encoded in an error-correcting code and at least one of a magic state or a code variant of a surface code or another given code. In some embodiments in which a simulation using a magic state is performed, the magic state can be prepared without magic state distillation, resulting in a noisy magic state. In some embodiments in which a simulation with a code variant is performed, a code variant can be performed on the code, for example, to represent a weight −1 logical Z operator, and a logical T gate can be simulated as a physical T gate in the resulting variant code. At 904, the encoded T gate simulated in step 902 is corrected for noise using pseudoprobability decomposition (e.g., by correction component 204).

[0069] To provide a context for various aspects of the disclosed subject matter, Figure 10 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. While embodiments have been described above in the general context of computer-executable instructions executable on one or more computers, those skilled in the art will recognize that embodiments may also be implemented in combination with other program modules, or as a combination of hardware and software, or a combination thereof.

[0070] 10, an exemplary environment 1000 for implementing various embodiments of the aspects described herein includes a computer 1002, which includes a processing unit 1004, a system memory 1006, and a system bus 1008. The system bus 1008 couples system components, including but not limited to the system memory 1006, to the processing unit 1004. The processing unit 1004 can be any of a variety of commercially available processors. Dual microprocessors and other multi-processor architectures can also be utilized as the processing unit 1004.

[0071] The system bus 1008 may be any of several types of bus structures that may be further interconnected to a memory bus, a peripheral bus, and a local bus (with or without a memory controller) using any of a variety of commercially available bus architectures. The system memory 1006 includes ROM 1010 and RAM 1012. The basic input / output system (BIOS), which may be stored in non-volatile memory such as ROM, erasable programmable read-only memory (EPROM), or EEPROM, contains the basic routines that help transfer information between elements within the computer 1002, such as during start-up. The RAM 1012 may also include high-speed RAM, such as static RAM, for caching data.

[0072] The computer 1002 further includes an internal hard disk drive (HDD) 1014 (e.g., EIDE, SATA), one or more external storage devices 1016 (e.g., a magnetic floppy disk drive (FDD) 1016, a memory stick or flash drive reader, a memory card reader, etc.), and an optical disk drive 1020 (e.g., capable of reading from or writing to CD-ROM disks, DVDs, BDs, etc.). While the internal HDD 1014 is shown as located within the computer 1002, the internal HDD 1014 may also be configured for external use in a suitable chassis (not shown). Additionally, although not shown in the environment 1000, a solid-state drive (SSD) may be used in addition to or in place of the HDD 1014. The HDD 1014, the external storage device 1016, and the optical disk drive 1020 may be connected to the system bus 1008 by an HDD interface 1024, an external storage interface 1026, and an optical disk drive interface 1028, respectively. The interface 1024 for external drive implementations may include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0073] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, etc. For computer 1002, the drives and storage media accommodate the storage of any data in a suitable digital format. While the above description of computer-readable storage media refers to each type of storage device, those skilled in the art will recognize that other types of computer-readable storage media, whether currently existing or developed in the future, can be used in the exemplary operating environment, and further, any such storage media may include computer-executable instructions for performing the methods described herein.

[0074] A number of program modules may be stored in the drives and RAM 1012, including an operating system 1030, one or more application programs 1032, other program modules 1034, and program data 1036. It is also possible that all or portions of the operating system, applications, modules, or data, or any combination thereof, may be cached in RAM 1012. The systems and methods described herein may be implemented using various commercially available operating systems or combinations of operating systems.

[0075] The computer 1002 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate a hardware environment for the operating system 1030, and the emulated hardware may optionally differ from the hardware shown in FIG. 10 . In one such embodiment, the operating system 1030 may include a virtual machine (VM) among multiple VMs hosted on the computer 1002. Additionally, the operating system 1030 may provide a runtime environment, such as the Java Runtime Environment or the .NET Framework, for the application program 1032. The runtime environment is a consistent execution environment that allows the application program 1032 to run on any operating system that includes the runtime environment. Similarly, the operating system 1030 may support containers, and the application program 1032 may be in the form of a container, which is a lightweight, standalone, executable software package that includes, for example, the application's code, runtime, system tools, system libraries, and settings.

[0076] Additionally, computer 1002 can be enabled with a security module such as a Trusted Processing Module (TPM). For example, in a TPM, a startup component hashes the next startup component and waits for the result to match a secured value before loading the next startup component. This process can be applied at any layer of computer 1002's code execution stack, such as the application execution level or the operating system (OS) kernel level, thereby enabling security at any level of code execution.

[0077] A user may enter commands and information into the computer 1002 through one or more wired / wireless input devices, such as a keyboard 1038, a touchscreen 1040, and a pointing device such as a mouse 1042. Other input devices (not shown) may include a microphone, an infrared (IR), radio frequency (RF) or other remote control, a joystick, a virtual reality controller or headset, or a combination thereof, a gamepad, a stylus pen, an image input device such as a camera, a gesture sensor input device, a visual motion sensor input device, an emotion or face detection device, a biometric input device such as a fingerprint or iris scanner, or the like. These and other input devices are often connected to the processing unit 1004 via an input device interface 1044, which may be coupled to the system bus 1008, but may also be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH interface, etc.

[0078] A monitor 1044 or other type of display device may also be connected to the system bus 1008 via an interface, such as a video adapter 1046. In addition to the monitor 1044, computers typically include other peripheral output devices (not shown), such as speakers, printers, etc.

[0079] The computer 1002 may operate in a networked environment using logical connections via wired, wireless communications, or a combination thereof, to one or more remote computers, such as a remote computer 1048. The remote computer 1048 may be a workstation, a server computer, a router, a personal computer, a portable computer, a microprocessor-based entertainment appliance, a peer device, or other common network node, and typically includes many or all of the elements described relative to the computer 1002, although for purposes of simplicity, only a memory / storage device 1050 is illustrated. The logical connections depicted include wired / wireless connectivity to a local area network (LAN) 1052, larger networks, e.g., a wide area network (WAN) 1054, or a combination thereof. Such LAN and WAN networking environments are commonplace in offices and companies and facilitate enterprise-wide computer networks, such as intranets, all of which may connect to a global communication network, e.g., the Internet.

[0080] When used in a LAN networking environment, the computer 1002 may be connected to the local network 1052 through a wired, wireless, or combination thereof communication network interface or adapter 1056. The adapter 1056 may facilitate wired or wireless communication to the LAN 1052 and may also include a wireless access point (AP) disposed thereon for communicating with the adapter 1056 in a wireless mode.

[0081] When used in a WAN networking environment, the computer 1002 may include a modem 1058 or may be connected to a communications server on the WAN 1054 via other means for establishing communications over the WAN 1054, such as via the Internet. The modem 1058, which may be internal or external and a wired or wireless device, may be connected to the system bus 1008 via the input device interface 1042. In a networked environment, program modules depicted relative to the computer 1002, or portions thereof, may be stored in the remote memory / storage device 1050. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between computers may be used.

[0082] When used in either a LAN or WAN networking environment, the computer 1002 may access a cloud storage system or other network-based storage system in addition to or in place of the external storage device 1016, as described above. Generally, a connection between the computer 1002 and the cloud storage system may be established over the LAN 1052 or the WAN 1054, for example, by way of an adapter 1056 or a modem 1058, respectively. Upon connecting the computer 1002 to an associated cloud storage system, the external storage interface 1026 may manage the storage provided by the cloud storage system as it manages other types of external storage, with the aid of the adapter 1056 or the modem 1058, or a combination thereof. For example, the external storage interface 1026 may be configured to provide access to cloud storage sources as if the sources were physically connected to the computer 1002.

[0083] The computer 1002 may be operable to communicate with any wireless device or entity operably arranged in wireless communication, such as, for example, a printer, a scanner, a desktop or portable computer or combination thereof, a portable data assistant, a communications satellite, any appliance or location associated with a radio-detectable tag (e.g., a kiosk, a newsstand, a store shelf, etc.), and a telephone. This may include Wireless Fidelity (Wi-Fi®) and BLUETOOTH wireless technologies. That is, communication may be in a predefined structure, similar to a traditional network, or may simply be ad-hoc communication between at least two devices.

[0084] 11 , an exemplary cloud computing environment 1100 is shown. As shown, the cloud computing environment 1100 includes one or more cloud computing nodes 1102 with which local computing devices used by cloud consumers, such as a personal digital assistant (PDA) or cellular phone 1104, a desktop computer 1106, a laptop computer 1108, or an automobile computer system 1110, or combinations thereof, may communicate. The nodes 1102 may communicate with each other. They may be physically or virtually grouped (not shown) in one or more networks (such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as described above). This enables the cloud computing environment 1100 to provide infrastructure, platform, or software, or combinations thereof, as a service, thereby eliminating the need for cloud consumers to maintain resources on their local computing devices. It should be understood that the types of computing devices 1104-1110 illustrated in FIG. 11 are intended to be exemplary only, and that computing node 1102 and cloud computing environment 1100 can communicate with any type of computerized device through any type of network or network-addressable connection (e.g., using a web browser), or both.

[0085] Referring now to Figure 12, a set of functional abstraction layers provided by cloud computing environment 1000 (Figure 11) is shown. Repetitive descriptions of similar elements utilized in other embodiments described herein will be omitted for the sake of brevity. It should be understood in advance that the components, layers, and functions shown in Figure 12 are intended to be merely exemplary, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0086] Hardware and software layer 1202 includes hardware and software components. Examples of hardware components include mainframe 1204 and reduced instruction set computer (RISC) architecture-based servers 1206, servers 1208, blade servers 1210, storage devices 1212, and networks and network components 1214. In some embodiments, software components include network application server software 1216 and database software 1218.

[0087] Virtualization layer 1220 provides an abstraction layer from which the following examples of virtual entities may be provided: virtual servers 1222, virtual storage 1224, virtual networks including virtual private networks 1226, virtual applications and operating systems 1228, and virtual clients 1230.

[0088] In one example, management layer 1232 may provide the functionality described below. Resource provisioning 1234 provides dynamic acquisition of computing resources and other resources used to accomplish tasks within the cloud computing environment. Metering and pricing 1236 provides cost tracking as resources are utilized within the cloud computing environment and accounting or billing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud users and tasks, and protection of data and other resources. User portal 1238 provides users and system administrators with access to the cloud computing environment. Service level management 1240 provides allocation and management of cloud computing resources to meet required service levels. Service level agreement (SLA) planning and fulfillment 1242 provides proactive coordination and procurement of anticipated future cloud computing resource needs according to SLAs.

[0089] Workload tier 1244 provides examples of functionality for which a cloud computing environment may be utilized. Examples of workloads and functions that may be provided from this tier include mapping and navigation 1246; software development and lifecycle management 1248; virtual classroom instruction delivery 1250; data analytics processing 1252; transaction processing 1254; and transfer learning processing 1256. Various embodiments of the present invention may utilize the cloud computing environment described with reference to Figures 11 and 12 to determine the similarity between a given machine learning task and previous machine learning tasks and, based on the determined similarity, perform transfer learning processing on an artificial intelligence model generated by automated machine learning.

[0090] What has been described above includes examples of the subject innovation. Of course, it is not possible to describe every conceivable combination of components or methodologies for purposes of describing the disclosed subject matter, but one of ordinary skill in the art will recognize that many more combinations and permutations of the subject innovation are possible. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0091] In particular, and with regard to the various functions performed by the above-described components, devices, circuits, systems, etc., the terms used to describe such components (including references to "means") are intended, unless otherwise indicated, to correspond to any component that performs the function in the exemplary embodiments illustrated herein of the disclosed subject matter and performs the predetermined function (e.g., functional equivalent) of the described component, even if it is not structurally equivalent to the disclosed structure. In this regard, it will be recognized that the disclosed subject matter includes not only systems, but also computer-readable media having computer-executable instructions for performing the acts or events of the various methods of the disclosed subject matter, or combinations thereof.

[0092] Additionally, while a particular feature of the disclosed subject matter may be disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of other implementations, as desired or advantageous for any given or particular application. Furthermore, to the extent that the terms "includes," "including," and variations thereof are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term "comprising."

[0093] The word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to illustrate a concept.

[0094] Various aspects or features described herein may be implemented as a method, apparatus, or article of manufacture using standard programming or engineering techniques, or a combination thereof. The term "article of manufacture," as used herein, is intended to encompass a computer program accessible from any computer-readable device, carrier, or medium. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips,...), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs),...), smart cards, flash memory devices (e.g., cards, sticks, key drives,...), and the like.

[0095] The present invention may be a system, method, apparatus, or computer program product, or combination thereof, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media may also include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or raised structures in grooves with instructions recorded thereon, and any suitable combination of the above. Computer-readable storage medium, as used herein, should not be construed as being, per se, a transitory signal such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over a wire.

[0096] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or may be downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium within the respective computing / processing device for storage. The computer-readable program instructions for carrying out operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk®, C++, or the like, conventional procedural programming languages such as the C programming language, or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider).In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry.

[0097] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine. The instructions, executed by the processor of the computer or other programmable data processing apparatus, thereby form means for implementing the function / acts specified in a block or blocks of the flowchart illustrations or block diagrams, or combinations thereof. These computer-readable program instructions may also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner. A computer-readable storage medium having instructions stored thereon thereby comprises a product including instructions that implement an aspect of the function / acts specified in a block or blocks of the flowchart illustrations or block diagrams, or combinations thereof. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device implement the function / acts specified in a block or blocks of the flowchart or block diagram, or a combination thereof.

[0098] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to execute a series of operating procedures to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / operations specified in one or more blocks of the flowcharts or block diagrams, or both.

[0099] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions described in the blocks may occur out of the order depicted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, depending on the functionality involved, or the blocks may even be executed in the reverse order. It should also be noted that each block of a block diagram or flowchart illustration, or combination thereof, and combinations of blocks in block diagrams or flowchart illustrations, or combinations thereof, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or that implements a combination of special-purpose hardware and computer instructions.

[0100] Although the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on a computer or multiple computers, or both, those skilled in the art will recognize that the present disclosure can also be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will recognize that the computer-implemented methods of the present invention can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices. For example, in one or more embodiments, computer-executable components can be executed from memory that can include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. Furthermore, one or more embodiments described herein may execute code of computer-executable components in a distributed manner (e.g., multiple processors combining or acting cooperatively to execute code from one or more distributed memory units). As used herein, the term "memory" may encompass a single memory or memory unit in one location, or multiple memories or memory units in one or more locations.

[0101] As used herein, terms such as “component,” “system,” “platform,” and “interface” may refer to and / or include computer-related entities or entities associated with an operating machine having one or more specific functionalities. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or any combination thereof. By way of illustration, both an application running on a server and the server may be a component. One or more components may reside within a process, thread of execution, or any combination thereof; a component may be localized on one computer, distributed between two or more computers, or any combination thereof. In another example, each component may execute from various computer-readable media having various data structures stored thereon. Components may communicate via local and / or remote processes, such as according to signals comprising one or more data packets (e.g., data from one component interacting with another component in a network such as the Internet, a local system, a distributed system, or other systems via signals, or a combination thereof). As another example, a component may be a device having inherent functionality provided by mechanical parts operated by electrical or electronic circuits operated by software or firmware applications executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware applications.As yet another example, a component may be a device that provides its inherent functionality without mechanical parts through electronic components, which may include a processor or other means for executing software or firmware that provides at least a portion of the functionality of the electronic component. In some aspects, a component may emulate an electronic component via, for example, a virtual machine in a cloud computing system.

[0102] Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from context, "X utilizes A or B" is intended to mean any of the natural inclusive permutations. That is, if X utilizes A, X utilizes B, or X utilizes both A and B, then "X utilizes A or B" is satisfied under any of the foregoing examples. Furthermore, as used in this specification and the accompanying drawings, the articles "a" and "an" should generally be construed to mean "one or more" unless otherwise specified or clear from context that the singular is intended. As used herein, the terms "example" and "exemplary" or both are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0103] The term "processor" as used herein may refer to virtually any computing processing unit or device, including, but not limited to, a single-core processor, a single processor with software multithreading execution capabilities, a multi-core processor, a multi-core processor with software multithreading execution capabilities, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory" or a "memory component" entity embodied in a component that includes memory. It should be understood that memory or memory components or combinations thereof described herein may be either volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may act as external cache memory, for example. By way of example, and not limitation, RAM is available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0104] The foregoing includes only example systems and computer-implemented methods. Of course, for purposes of describing the present disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, to the extent that terms such as "including," "having," "comprising," and the like are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional phrase in the claims.

[0105] The description of various embodiments is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications of, or technical improvements to, the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. According to this specification, the following items are also disclosed. [Item 1] a processor for executing computer-executable components stored in a memory, the computer-executable components comprising: a simulation component that simulates the encoded T-gate using logic qubits encoded in an error-correcting code and at least one of a magic state or a code variant of a surface code; and A correction component that corrects noise on the encoded T-gate using pseudo-probability decomposition. Including, the system. [Item 2] the simulation component simulates the encoded T-gate as a quantum circuit utilizing two logical qubits, including a Clifford gate; and Item 1. The system of item 1, wherein one of the two logical qubits constitutes the magic state. [Item 3] The quantum circuit includes a controlled-not (CNOT) gate and a controlled phase-shift gate; a first of the two logical qubits that constitute the magic state is provided to the controlled phase-shift gate and provided as a control to the CNOT gate; the second of the two logical qubits is provided to the CNOT gate; and Item 3. The system of item 2, wherein a measurement of the output of the CNOT gate is provided as a control to the controlled phase shift gate. [Item 4] The above simulation components are: performing a first code transformation on the given code to exhibit a weight-1 logical Z operator, resulting in a transformed code; simulating logical T-gates as physical T-gates in the modified code; and performing a second code transformation on said transformed code to return said code to the form it was in prior to said performing said first code transformation. 4. The system of claim 1, wherein the encoded T-gate is simulated using the code transformation by: [Item 5] The correction component is: Learning the error rate of the encoded T-gate and generating a noise map, N, based on the error rate; and By the above pseudoprobability decomposition, N -1 5. The system of any one of items 1 to 4, wherein the noise on the encoded T-gates is corrected by applying an inverse of the noise map, [Item 6] The correction component is: [Number 64] JPEG0007725167000058.jpg1681 Find a decomposition for the above pseudoprobabilistic decomposition for [Number 65] JPEG0007725167000059.jpg1637 [Number 66] JPEG0007725167000060.jpg1523 where U is the unitary operator corresponding to the encoded T gate above, M is the decomposition size, a i is the pseudo-random coefficient, ε i is a quantum channel that can be implemented in quantum hardware, and 6. The system of any one of items 1 to 5, wherein γ is a sampling overhead. [Item 7] For each execution of a quantum circuit containing the encoded T-gate, the correction component: variance p i Randomly select i by Gate U is ε i Replaced by; and The measurement results are expressed as γsign(a i ), 7. The system according to any one of items 1 to 6. [Item 8] 8. The system of claim 1, wherein simulating the coded T-gate using at least one of the magic state or code transformation, and correcting the noise using pseudo-probability decomposition, mitigates the use of magic state distillation for fault-tolerant simulation of the coded T-gate. [Item 9] simulating, with the system, a logical qubit encoded in an error-correcting code and a T-gate encoded with at least one of a magic state or a code variant of a surface code; and correcting noise on the encoded T-gates using pseudo-probability decomposition by the system. 1. A computer-implemented method comprising: [Item 10] The simulating step includes simulating the encoded T-gate as a quantum circuit utilizing two logical qubits, including a Clifford gate; and Item 10. The computer-implemented method of item 9, wherein one of the two logical qubits constitutes the magic state. [Item 11] The quantum circuit includes a controlled-not (CNOT) gate and a controlled phase-shift gate; a first of the two logical qubits that constitute the magic state is provided to the controlled phase-shift gate and provided as a control to the CNOT gate; the second of the two logical qubits is provided to the CNOT gate; and Item 11. The computer-implemented method of item 10, wherein a measurement of the output of the CNOT gate is provided as a control to the controlled phase shift gate. [Item 12] simulating the encoded T-gate using the code transformation comprises: performing, by said system, a first code transformation on the given code to exhibit a weight-1 logical Z operator, resulting in a transformed code; simulating, by said system, logical T-gates as physical T-gates in said transformed code; and performing, by the system, a second code transformation on the transformed code to return the code to the form it was in before performing the first code transformation. 12. The computer-implemented method of any one of items 9 to 11, comprising: [Item 13] The above correction step is: learning, by the system, the error rate of the encoded T-gate and generating a noise map, N, based on the error rate; and By the above system, and by the above pseudoprobability decomposition, N -1 13. The computer-implemented method of any one of items 9 to 12, comprising correcting the noise on the encoded T-gates by applying an inverse of the noise map, where [Item 14] The correcting step is performed by the system by: [Number 67] JPEG0007725167000061.jpg1681 finding a decomposition for said pseudo-probabilistic decomposition according to [Number 68] JPEG0007725167000062.jpg1538 [Number 69] JPEG0007725167000063.jpg1423 where U is the unitary operator corresponding to the encoded T gate above, M is the decomposition size, a i is the pseudo-random coefficient, ε i is a quantum channel that can be implemented in quantum hardware, and 14. The computer-implemented method of any one of items 9 to 13, wherein γ is a sampling overhead. [Item 15] The correcting step comprises, for each execution of a quantum circuit including the encoded T-gate: By the above system, the distribution p i randomly selecting i by By the above system, gate U is set to ε i and The measurement results are expressed as γsign(a i 15. The computer-implemented method of any one of items 9 to 14, comprising weighting the [Item 16] 16. The computer-implemented method of any one of items 9 to 15, wherein simulating the encoded T-gate using at least one of the magic state or the code variant and correcting the noise using pseudo-probability decomposition mitigates the use of magic state distillation for fault-tolerant simulation of the encoded T-gate. [Item 17] 17. The computer-implemented method of any one of items 9 to 16, wherein the system is a system of any one of items 1 to 8. [Item 18] The processor simulating, by the processor, a T-gate encoded with a logical qubit encoded in an error-correcting code and at least one of a magic state or a code variant of a surface code; and correcting noise on said encoded T-gates using pseudo-probability decomposition by said processor. A computer program for executing [Item 19] The processor includes: performing a procedure for simulating the encoded T-gate as a quantum circuit utilizing two logical qubits, including a Clifford gate, one of the two logical qubits constituting the magic state; Item 19. The computer program according to item 18. [Item 20] The quantum circuit includes a controlled-not (CNOT) gate and a controlled phase-shift gate; a first of the two logical qubits that constitute the magic state is provided to the controlled phase-shift gate and provided as a control to the CNOT gate; the second of the two logical qubits is provided to the CNOT gate; and 20. The computer program of claim 19, wherein the measurement of the output of the CNOT gate is provided as a control to the controlled phase shift gate. [Item 21] The processor includes: for a given code, performing a first code transformation to exhibit a weight-1 logical Z operator, resulting in a transformed code; a procedure for simulating a logical T-gate as a physical T-gate in the modified code; and performing a second code transformation on the transformed code to return the code to the form it had before performing the first code transformation; 21. A computer program according to any one of items 18 to 20, causing the computer to execute a procedure of simulating the coded T-gate using the code transformation by

Claims

1. a processor executing computer-executable components stored in a memory, the computer-executable components comprising: a simulation component that simulates an encoded T-gate using logic qubits encoded in an error-correcting code and magic states prepared without magic state distillation; and a correction component that corrects noise on the encoded T-gates using pseudo-probability decomposition; Including, the system.

2. the simulation component simulates the encoded T-gate as a quantum circuit utilizing two logical qubits, including a Clifford gate; and 2. The system of claim 1, wherein one of the two logical qubits constitutes the magic state.

3. the quantum circuit includes a controlled not (CNOT) gate and a controlled phase-shift gate; a first of the two logical qubits that constitute the magic state is provided to the controlled phase-shift gate and provided as a control to the CNOT gate; a second of the two logical qubits is provided to the CNOT gate; and 3. The system of claim 2, wherein a measurement of the output of the CNOT gate is provided as a control to the controlled phase shift gate.

4. The simulation component further simulates the encoded T-gate using a code transformation of the surface code; The simulation component For a given code, performing a first code transformation to exhibit a weight-1 logical Z operator, resulting in a transformed code; simulating logical T-gates as physical T-gates in the transformed code; and performing a second code transformation on the transformed code to return the code to the form it was in prior to performing the first code transformation.

4. The system of claim 1, wherein the encoded T-gate is simulated using the code transformation by:

5. The correction component: learning an error rate of the encoded T-gate and generating a noise map, N, based on the error rate; and By the pseudoprobability decomposition, N －１ 5. The system of claim 1, wherein the noise on the encoded T-gates is corrected by applying an inverse of the noise map, where:

6. The correction component: [Number 58] find a decomposition for the pseudoprobabilistic decomposition according to [Number 59] [Number 60] where U is the unitary operator corresponding to the encoded T-gate, M is the decomposition size, a ｉ is the pseudo-random coefficient, ε ｉ is a quantum channel that can be implemented in quantum hardware, and The system of claim 1 , wherein γ is a sampling overhead.

7. For each execution of a quantum circuit including the encoded T-gate, the correction component: variance p ｉ Randomly select i by Gate U is ε ｉ Replaced by; and The measurement results are expressed as γsign(a ｉ ) and weighted by A system according to any one of claims 1 to 6.

8. 8. The system of claim 1, wherein simulating the coded T-gate using the magic state and correcting the noise using pseudo-probability decomposition mitigates the use of magic state distillation for fault-tolerant simulation of the coded T-gate.

9. simulating, with the system, a T-gate encoded with logic qubits encoded in an error-correcting code and magic states prepared without magic state distillation; and correcting noise on the encoded T-gates using pseudo-probability decomposition by the system.

1. A computer-implemented method comprising:

10. The simulating step includes simulating the encoded T-gate as a quantum circuit utilizing two logical qubits, including a Clifford gate; and 10. The computer-implemented method of claim 9, wherein one of the two logical qubits constitutes the magic state.

11. the quantum circuit includes a controlled not (CNOT) gate and a controlled phase-shift gate; a first of the two logical qubits that constitute the magic state is provided to the controlled phase-shift gate and provided as a control to the CNOT gate; a second of the two logical qubits is provided to the CNOT gate; and 11. The computer-implemented method of claim 10, wherein a measurement of the output of the CNOT gate is provided as a control to the controlled phase shift gate.

12. The step of simulating the encoded T-gate comprises simulating the encoded T-gate using a code transformation of the magic state and the surface code, simulating the encoded T-gate using the code transformation comprises: performing, by the system, a first code transformation on the given code to exhibit a weight −1 logical Z operator, resulting in a transformed code; simulating, by the system, logical T-gates as physical T-gates in the transformed code; and performing, by the system, a second code transformation on the transformed code to return the code to the form it was in before performing the first code transformation; 12. The computer-implemented method of claim 9, comprising:

13. The correcting step includes: learning, by the system, the error rate of the encoded T-gate and generating a noise map, N, based on the error rate; and The system uses the pseudoprobability decomposition to －１ 13. The computer-implemented method of claim 9, comprising correcting the noise on the encoded T-gates by applying an inverse of the noise map, where

14. The correcting step is performed by the system by: [Number 61] finding a decomposition for said pseudo-probabilistic decomposition according to [Number 62] [Number 63] where U is the unitary operator corresponding to the encoded T-gate, M is the decomposition size, a ｉ is the pseudo-random coefficient, ε ｉ is a quantum channel that can be implemented in quantum hardware, and 14. The computer-implemented method of claim 9, wherein γ is a sampling overhead.

15. The correcting step comprises, for each execution of a quantum circuit including the encoded T-gate: The system allows for distribution p ｉ randomly selecting i by By the system, the gate U is set to ε ｉ and The system calculates the measurement results as γsign(a ｉ 15. The computer-implemented method of claim 9, comprising weighting the

16. 16. The computer-implemented method of claim 9, wherein simulating the encoded T-gate using the magic state and correcting the noise using pseudo-probability decomposition mitigates the use of magic state distillation for fault-tolerant simulation of the encoded T-gate.

17. 17. A computer-implemented method according to any one of claims 9 to 16, wherein the system is a system according to any one of claims 1 to 8.

18. The processor simulating, by the processor, a T-gate encoded with logical qubits encoded in an error-correcting code and magic states prepared without magic state distillation; and correcting, by said processor, noise on said encoded T-gates using pseudo-probability decomposition. A computer program for executing

19. the processor, performing a procedure to simulate the encoded T-gate as a quantum circuit utilizing two logical qubits, including a Clifford gate, one of the two logical qubits constituting the magic state; 19. A computer program according to claim 18.

20. the quantum circuit includes a controlled not (CNOT) gate and a controlled phase-shift gate; a first of the two logical qubits that constitute the magic state is provided to the controlled phase-shift gate and provided as a control to the CNOT gate; a second of the two logical qubits is provided to the CNOT gate; and 20. The computer program of claim 19, wherein a measurement of the output of the CNOT gate is provided as a control to the controlled phase shift gate.

21. The procedure for simulating the encoded T-gate is a procedure for simulating the encoded T-gate using a code transformation of the magic state and the surface code, the processor, for a given code, performing a first code transformation to exhibit a weight -1 logical Z operator, resulting in a transformed code; simulating logical T-gates as physical T-gates in the transformed code; and performing a second code transformation on the transformed code to return the code to the form it had before performing the first code transformation; 21. A computer program product as claimed in any one of claims 18 to 20, causing a computer to perform a procedure of simulating the encoded T-gate using the code transformation by:

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