semiconductor integrated circuit device

Abstract

An IO cell (10a) comprises an output circuit (11) including an ESD protection diode (1b), a protection resistor (Rsp), and an output transistor (P1). The protection resistor (Rsp) is configured from a plurality of resistive elements (RU) formed on a first wiring layer (RMetal) which is formed in a back end of line (BEOL). The resistive element (RU) is connected to wiring formed on a second wiring layer (M4) through a via. In the second wiring layer (M4), a first power supply wiring (75) for supplying first power supply (VDDIO) is formed over the ESD protection diode (1b). The first power supply wiring (75) partially overlaps the resistive element (RU) in an X direction.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit device in which a core region and an I / O region are arranged on a chip, and in particular to a layout structure of I / O cells arranged in the I / O region. [Background technology]

[0002] In a semiconductor integrated circuit, input / output cells (I / O cells, IO cells) are arranged around a core region, and signals are input / output to and from the outside of the semiconductor integrated circuit device and power is supplied via the I / O cells.

[0003] In recent miniaturization processes, transistor gates are widely constructed using high-k gate insulating films and metal gates. This allows the use of non-silicided polysilicon, which is formed in the FEOL (Front End of Line) process as a resistor element. Currently, it is difficult to use capacitor resistors. Resistive elements formed of metal compounds such as titanium nitride, etc., formed between metal wiring layers in the end of line (wiring process) have come to be used.

[0004] Patent Document 1 discloses a semiconductor integrated circuit device in which a resistance element formed between metal wiring layers in the BEOL is arranged above a diode element serving as an ESD (Electro-Static Discharge) protection element, for example. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Publication No. 2019 / 0304905 Summary of the Invention [Problem to be solved by the invention]

[0006] In the miniaturization process, the ESD resistance of semiconductor integrated circuits is decreasing, and in their design, detailed consideration of the wiring structure is required to improve ESD resistance as much as possible. However, such consideration is not included in Patent Document 1.

[0007] An object of the present disclosure is to provide a configuration for improving ESD resistance in a semiconductor integrated circuit device that uses a resistive element formed in the back-end line. [Means for solving the problem]

[0008] In a first aspect of the present disclosure, there is provided a semiconductor integrated circuit device having a plurality of IO cells arranged in a first direction, at least one of the plurality of IO cells including an output circuit, the output circuit being configured with an external output terminal, a first ESD (Electro-Static Discharge) protection diode having a first node connected to the external output terminal and a second node connected to a first power supply, and a plurality of resistive elements formed in a first wiring layer formed in a wiring process (BEOL: Back End of Line), the plurality of resistive elements of the first protective resistor being connected to a wiring formed in a second wiring layer via a via, and a first power supply wiring for supplying the first power supply being formed on the first ESD protection diode in the second wiring layer, the plurality of resistive elements of the first protective resistor being connected to a wiring formed in a second wiring layer via a via, and the first power supply wiring overlapping in the first direction with any of the plurality of resistive elements of the first protective resistor.

[0009] According to this embodiment, the IO cell includes an output circuit including a first ESD protection diode, a first protection resistor, and a first output transistor. The first protection resistor is composed of multiple resistance elements formed in a first wiring layer formed in a wiring process (BEOL). The multiple resistance elements included in the first protection resistor are connected to wiring formed in a second wiring layer through vias. In the second wiring layer, a first power supply wiring that supplies a first power source is formed above the first ESD protection diode, and the first power supply wiring overlaps with any of the multiple resistance elements included in the first protection resistor in the first direction in which the IO cells are arranged. This allows for ample power supply wiring that supplies the first power source to be provided in the wiring layer above the first ESD protection diode. Therefore, the resistance value of the path from the first power source to the first ESD protection diode can be reduced, thereby achieving excellent ESD protection characteristics.

[0010] In a second aspect of the present disclosure, there is provided a semiconductor integrated circuit device having a plurality of IO cells arranged in a first direction, at least one of the plurality of IO cells including an output circuit, the output circuit being composed of an external output terminal, a first ESD (Electro-Static Discharge) protection diode having a first node connected to the external output terminal and a second node connected to a first power supply, and a plurality of resistive elements formed in a first wiring layer formed in a wiring process (BEOL: Back End of Line), the first protective resistor having one end connected to the external output terminal, and a first output transistor connected between the other end of the first protective resistor and the first power supply, the plurality of resistive elements of the first protective resistor being connected to wiring formed in a second wiring layer via vias, and a first power supply wiring that supplies the first power supply is formed above the first output transistor in the second wiring layer, and the first power supply wiring overlaps with any of the plurality of resistive elements of the first protective resistor in the first direction.

[0011] According to this embodiment, the IO cell includes an output circuit including a first ESD protection diode, a first protection resistor, and a first output transistor. The first protection resistor is composed of multiple resistance elements formed in a first wiring layer formed in a wiring process (BEOL). The multiple resistance elements of the first protection resistor are connected to wiring formed in a second wiring layer through vias. In the second wiring layer, a first power supply wiring that supplies a first power source is formed above the first output transistor, and the first power supply wiring overlaps with any of the multiple resistance elements of the first protection resistor in the first direction in which the IO cells are arranged. This allows for ample power supply wiring that supplies the first power source to be provided in the wiring layer above the first output transistor. Therefore, a sufficient large current can be passed through the first output transistor, reducing wiring resistance and suppressing voltage drop, thereby suppressing deterioration of the operating frequency and improving the quality of the signal waveform. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to further improve the ESD resistance of a semiconductor integrated circuit device that uses a resistive element formed in the back-end line. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view schematically showing the overall configuration of a semiconductor integrated circuit device according to an embodiment; [Figure 2] Circuit configuration diagram of an output circuit according to the first embodiment [Figure 3] 1. Schematic Example of IO Cell Layout in the First Embodiment [Figure 4] A detailed plan view of the IO cell layout of Figure 3. [Figure 5] Cross-section showing details of the IO cell layout in Figure 3 [Figure 6] Plan view showing the layout of the output transistors [Figure 7] Plan view showing ESD protection diode layout [Figure 8]A detailed plan view of the IO cell layout of Figure 3. [Figure 9] Plan view showing the layout of the output transistors [Figure 10] Plan view showing ESD protection diode layout [Figure 11] Circuit configuration diagram of an output circuit according to a second embodiment [Figure 12] 1. Schematic example of IO cell layout in the second embodiment [Figure 13] A plan view showing the details of the IO cell layout of Figure 12. [Figure 14] 1. Outline example of IO cell layout in modified example DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, "VDDIO" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, it is assumed that the transistors are formed on a P-type substrate and an N-type well. The transistors may be formed on a P-type well or on an N-type substrate.

[0015] (First embodiment) FIG. 1 is a plan view schematically illustrating the overall configuration of a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device 1 illustrated in FIG. 1 includes a core region 2 in which an internal core circuit is formed, and an I / O region 3 provided between the core region 2 and a chip edge and in which an interface circuit (I / O circuit) is formed. An IO cell array 10A is provided in the I / O region 3 so as to surround the peripheral portion of the semiconductor integrated circuit device 1 in an annular shape. Although the illustration is simplified in FIG. 1, the IO cell array 10A includes a plurality of IO cells 10 that constitute the interface circuit. Although not illustrated in FIG. 1, the semiconductor integrated circuit device 1 also includes a plurality of external connection pads. The IO cell array 10A may be provided in part of the peripheral portion of the semiconductor integrated circuit device 1.

[0016] The IO cells 10 include signal IO cells and power IO cells. The signal IO cells include circuits necessary for transmitting signals between the semiconductor integrated circuit device 1 and the outside or between the semiconductor integrated circuit device 1 and the core region 2, such as a level shifter circuit, an output buffer circuit, an ESD protection circuit, etc. The power IO cells supply each power source supplied to the external connection pads to the inside of the semiconductor integrated circuit device 1, and include an ESD protection circuit, etc.

[0017] 2 is a circuit configuration diagram of the output circuit 11 included in the IO cell 10. Note that an actual output circuit includes circuit elements other than those shown in FIG. 2, but these are not shown in FIG.

[0018] 2 includes an external output terminal PAD, output transistors P1 and N1, ESD (Electro Static Discharge) protection diodes 1a and 1b, and protection resistors Rsn and Rsp. The output transistor P1 is a P-conductivity type transistor, and the output transistor N1 is an N-conductivity type transistor.

[0019] The output transistors P1 and N1 output an output signal to the external output terminal PAD in accordance with a signal received at their gates. The output transistor P1 has a source connected to VDDIO and a drain connected to the external output terminal PAD via a protective resistor Rsp. The output transistor N1 has a source connected to VSS and a drain connected to the external output terminal PAD via a protective resistor Rsn. In this embodiment, the protective resistors Rsp and Rsn are connected to the BEOL (Back End The output transistor N1 is configured by a plurality of resistor elements formed in a wiring layer formed in a wiring process (of line: wiring process). The node between the output transistor N1 and the protective resistor Rsn is referred to as node A, and the node between the output transistor P1 and the protective resistor Rsp is referred to as node B.

[0020] The ESD protection diode 1a is provided between VSS and the external output terminal PAD, with its anode connected to VSS and its cathode connected to the external output terminal PAD. The ESD protection diode 1b is provided between VDDIO and the external output terminal PAD, with its anode connected to the external output terminal PAD and its cathode connected to VDDIO. When high-voltage noise is input to the external output terminal PAD, current flows to VDDIO and VSS via the ESD protection diodes 1a and 1b, thereby protecting the output transistors P1 and N1.

[0021] Fig. 3 shows an example of an outline of the layout of an IO cell. The layout of Fig. 3 corresponds to an IO cell 10a, which is one of the IO cells 10 arranged along the bottom side of the semiconductor integrated circuit device 1 in Fig. 1. Here, the X direction (corresponding to the first direction) is the direction along the outer side of the semiconductor integrated circuit device 1, and is the direction in which the multiple IO cells 10 are arranged. The Y direction (corresponding to the second direction) is the direction perpendicular to the X direction.

[0022] An IO cell generally has a high power supply voltage region including an ESD protection circuit and an output buffer for outputting signals to the outside of the semiconductor integrated circuit device, and a low power supply voltage region including circuits for inputting and outputting signals to the inside of the semiconductor integrated circuit device. The IO cell 10a in Fig. 3 is divided in the Y direction into two low power supply voltage regions 6a and 6b and a high power supply voltage region 7. The low power supply voltage region 6a is located on the core region 2 side, and the low power supply voltage region 6b is located on the chip edge side. The high power supply voltage region 7 is located between the low power supply voltage regions 6a and 6b.

[0023] The low power supply voltage region 6a is located near the output transistor P1 and includes, for example, a circuit that generates a signal that is input to the gate of the output transistor P1. The low power supply voltage region 6b is located near the output transistor N1 and includes, for example, a circuit that generates a signal that is input to the gate of the output transistor N1.

[0024] The IO cell 10a shown in FIG. 3 includes the output circuit 11 shown in FIG. 2. In the high power supply voltage region 7, an output transistor N1, ESD protection diodes 1a, 1b, and an output transistor P1 are arranged in this order from the chip edge. In the high power supply voltage region 7, resistor elements RU are arranged in an array in the XY direction above the region other than the region where the output transistor N1, ESD protection diodes 1a, 1b, and output transistor P1 are arranged. The resistor elements RU arranged in the upper part of the region near the output transistor P1 are connected to each other to form a protective resistor Rsp. By arranging the protective resistor Rsp above the region where other circuit devices such as transistors are arranged, the area of ​​the IO cell 10a can be reduced. The resistor elements RU arranged in the upper part of the region near the output transistor N1 are connected to each other to form a protective resistor Rsn. By arranging the protective resistor Rsn above the region where other circuit devices such as transistors are arranged, the area of ​​the IO cell 10a can be reduced.

[0025] The connection topology of the resistor elements RU may be any of series connection, parallel connection, or a combination of series and parallel connection. Furthermore, a portion of the resistor element RU constituting the protective resistor Rsp may be disposed above the low power supply voltage region 6a. A portion of the resistor element RU constituting the protective resistor Rsn may be disposed above the low power supply voltage region 6b.

[0026] 4 and 5 are diagrams showing the details of the layout of the IO cell. Fig. 4 is a plan view showing the structure of the M3 to M5 wiring layers in portion A1 of Fig. 3, and Fig. 5 is a cross-sectional view showing the cross-sectional structure along line XX' in Fig. 4.

[0027] The RMetal wiring layer is formed between the M4 wiring layer and the M3 wiring layer, and is a wiring layer for forming the resistor element RU. The RMetal wiring layer is formed in the BEOL (Back End of Line: wiring process). The resistor element RU formed in the RMetal wiring layer is connected to the wiring of the M4 wiring layer through a via.

[0028] In the M5 wiring layer, M5 wires 21, 22, and 23 extending in the Y direction are formed. The M5 wires 21 and 23 correspond to node B. The M5 wire 22 corresponds to the external output terminal PAD and is connected to an IO pad (not shown). The M5 wires 21 and 23 extend from the region where the protection resistor Rsp is formed to above the output transistor P1. The M5 wire 22 extends from the region where the protection resistor Rsp is formed to above the output transistor P1 and above the ESD protection diode 1b.

[0029] Above the output transistor P1, M4 wirings 24 and 25 extending in the Y direction and M3 wirings 51 and 52 extending in the X direction are formed. The M4 wiring 24 overlaps the M5 wiring 21 in a plan view and is connected to the M5 wiring 21 through a via. The M4 wiring 25 overlaps the M5 wiring 23 in a plan view and is connected to the M5 wiring 23 through a via. The M3 wiring 51 is connected to the M4 wirings 24 and 25 through a via. The M3 wiring 52 is connected to the M4 wirings 24 and 25 through a via.

[0030] Resistor elements RU are formed in the RMetal wiring layer. Two resistor elements RU are connected in series between the external output terminal PAD and node B. That is, the resistor elements RU are connected between node B and the external output terminal PAD along the following path: M5 wiring 21 (node ​​B) → via (M5-M4) → M4 wiring → via (M4-RMetal) → resistor element RU → via (M4-RMetal) → M4 wiring → via (M4-RMetal) → resistor element RU → via (M4-RMetal) → M4 wiring → via (M5-M4) → M5 wiring 22 (PAD). Similarly, two resistor elements RU are connected in series between the M5 wiring 22 (PAD) and M5 wiring 23 (node ​​B). A protective resistor Rsp is configured by a plurality of resistor elements RU.

[0031] Here, the reason why two resistor elements RU are connected in series between the external output terminal PAD and node B is to efficiently dissipate heat. That is, with the structure shown in FIG. 4, heat generated in the resistor element RU can be efficiently dissipated from the M4 wiring connected to both ends of the resistor element RU. Note that three or more resistor elements RU may be connected in series between the external output terminal PAD and node B. Alternatively, one resistor element RU may be connected between the external output terminal PAD and node B.

[0032] In the region where the protective resistor Rsp is formed, M4 wires 71 and 72 extending in the Y direction are arranged on the left side of the M5 wire 21 in the drawing, and M4 wires 73 and 74 extending in the Y direction are arranged on the right side of the M5 wire 23 in the drawing. The M4 wires 71 and 74 are power supply wires that supply VDDIO, and the M4 wires 72 and 73 are power supply wires that supply VSS. In the region where the protective resistor Rsp is formed, M3 wires 45 and 46 extending in the X direction are arranged to reinforce the power supply. The M3 wire 45 is connected to the M4 wire 72,73 The M3 wiring 46 is connected to the M4 wiring through a via. 71,74 The M3 wirings 45 and 46 are wirings for reinforcing the power supply, and therefore may be omitted.

[0033] Above the output transistor P1 and the ESD protection diode 1b, M3 wiring 53 and M4 wiring 75 are formed in a grid pattern as wirings that supply VDDIO. The M3 wiring 53 and M4 wiring 75 are connected to each other through vias. The M4 wiring 75 overlaps with the resistive element RU in the X direction. In other words, the M4 wiring 75 that supplies VDDIO is formed at the X coordinate position where the resistive element RU is formed.

[0034] A part of the resistive element RU constituting the protective resistor Rsp may be formed on the output transistor P1 or on the ESD protection diode 1b.

[0035] 6 shows the layout of the output transistor P1. A plurality of P-conductivity type fins 66 are formed, each extending in the X direction and arranged side by side in the Y direction, and a plurality of gate wirings 67 are formed, each extending in the Y direction and arranged side by side in the X direction. The fins 66 and gate wirings 67, which overlap in plan view, form a transistor. The transistors are connected in parallel by wiring (not shown). The drain of each transistor is connected to the external output terminal PAD via a protective resistor Rsp.

[0036] FIG. 7 shows the layout of the ESD protection diode 1b. The ESD protection diode 1b includes a cathode portion 36 formed by an N-conductivity type fin 37 and anode portions 38a and 38b formed by P-conductivity type fins 39a and 39b. The fins 37, 39a, and 39b extend in the X direction. The cathode portion 36 is connected to VDDIO, and the anode portions 38a and 38b are connected to the external output terminal PAD. A diode is formed between the N-conductivity type fin 37 and the P-conductivity type fins 39a and 39b.

[0037] 8 is a plan view showing the structure of the M3 to M5 wiring layers in portion A2 of FIG. 3. FIG. 8 shows the layout of the region where the protection resistor Rsn is formed and the region above the output transistor N1 and ESD protection diode 1a. The layout of FIG. 8 corresponds to the layout of FIG. 4, which is inverted upside down (in the Y direction) with VDDIO set to VSS and node B set to node A. The layout of FIG. 8 can be easily understood from the explanation of the layout of FIG. 4, so a detailed explanation will be omitted here.

[0038] Resistor elements RU are formed in the RMetal wiring layer. Two resistor elements RU are connected in series between the external output terminal PAD and node A. A plurality of resistor elements RU constitute a protective resistor Rsn.

[0039] Above the output transistor N1 and the ESD protection diode 1a, the M3 wiring 54 and the M4 wiring 76 are formed in a grid pattern as wirings that supply VSS. The M3 wiring 54 and the M4 wiring 76 are connected to each other through vias. The M4 wiring 76 overlaps with the resistor element RU in the X direction. In other words, the M4 wiring 76 that supplies VSS is formed at the X coordinate position where the resistor element RU is formed.

[0040] A part of the resistive element RU constituting the protective resistor Rsn may be formed on the output transistor N1 or on the ESD protection diode 1a.

[0041] 9 shows the layout of the output transistor N1. As shown in FIG. 9, the output transistor N1 is formed with a plurality of N-conductivity type fins 61 each extending in the X direction and arranged side by side in the Y direction, and a plurality of gate wirings 62 each extending in the Y direction and arranged side by side in the X direction. The fins 61 and gate wirings 62 overlapping in plan view form a transistor. The transistors are connected in parallel by wiring (not shown). The drain of each transistor is connected to the external output terminal PAD via a protective resistor Rsn.

[0042] FIG. 10 shows the layout of the ESD protection diode 1a. As shown in FIG. 10, the ESD protection diode 1a includes an anode portion 31 formed by a P-conductivity type fin 32 and cathode portions 33a and 33b formed by N-conductivity type fins 34a and 34b. The fins 32, 34a, and 34b extend in the X direction. The anode portion 31 is connected to VSS, and the cathode portions 33a and 33b are connected to the external output terminal PAD. A diode is formed between the P-conductivity type fin 32 and the N-conductivity type fins 34a and 34b.

[0043] This embodiment provides the following advantages. Specifically, in the configuration of this embodiment, the resistive elements RU constituting the protection resistors Rsp and Rsn are arranged above an area other than the areas where the output transistors P1 and N1 and the ESD protection diodes 1a and 1b are arranged. Therefore, VDDIO and VSS power supply wiring can be provided in ample amounts in the wiring layer above the output transistors P1 and N1 and the ESD protection diodes 1a and 1b.

[0044] This allows a large current to flow through the output transistors P1 and N1. This reduces wiring resistance and suppresses voltage drops, preventing degradation of the operating frequency and improving the quality of signal waveforms. Furthermore, the resistance of the paths from the power supply to the ESD protection diodes 1a and 1b can be suppressed, providing excellent ESD protection characteristics.

[0045] (Second embodiment) FIG. 11 is a circuit configuration diagram of an output circuit 12 according to this embodiment. The circuit configuration in FIG. 11 is substantially the same as the circuit configuration in FIG. 2 according to the first embodiment, except for the insertion position of the protective resistor. That is, in the output circuit 12 of FIG. 11, a protective resistor Rs is provided instead of the protective resistors Rsn and Rsp in FIG. 2. In FIG. 11, the drains of the output transistors P1 and N1 are connected to each other, and the protective resistor Rs is provided between the external output terminal PAD and the drains of the output transistors P1 and N1. The node between the drains of the output transistors P1 and N1 and the protective resistor Rs is referred to as node C.

[0046] FIG. 12 shows an example of an outline of an IO cell layout. The layout in FIG. 12 corresponds to an IO cell 10a, which is one of the IO cells 10 arranged along the bottom side of the semiconductor integrated circuit device 1 in FIG. 1. The IO cell layout in FIG. 12 differs from the IO cell layout in FIG. 3 in the arrangement of the high power supply voltage region and the low power supply voltage region. The IO cell 10a in FIG. 12 is divided into a low power supply voltage region 8 and a high power supply voltage region 9 in the Y direction. The low power supply voltage region 8 is located on the core region 2 side, and the high power supply voltage region 9 is located on the chip edge side.

[0047] The IO cell 10a shown in FIG. 12 is configured with the output circuit 12 of FIG. 11. In the high power supply voltage region 9, an ESD protection diode 1a, an ESD protection diode 1b, an output transistor P1, and an output transistor N1 are arranged in this order from the chip edge. In the high power supply voltage region 9, resistive elements RU are arranged in an array in the XY direction above an area other than the area where the ESD protection diode 1a, the ESD protection diode 1b, the output transistor P1, and the output transistor N1 are arranged. The resistive elements RU are connected to each other to form a protective resistor Rs. By arranging the protective resistor Rs above an area where devices such as transistors that constitute other circuits are arranged, the area of ​​the IO cell 10a can be reduced.

[0048] The connection of the resistor elements RU may be in series, in parallel, or in a combination of series and parallel. A part of the resistor elements RU constituting the protective resistor Rs may be disposed above the low power supply voltage region 8.

[0049] Furthermore, the arrangement of the ESD protection diode 1a, the ESD protection diode 1b, the output transistor P1, and the output transistor N1 is not limited to that shown in Fig. 12. For example, the positions of the output transistor P1 and the output transistor N1 may be interchanged, and the positions of the ESD protection diode 1a and the ESD protection diode 1b may be interchanged.

[0050] Fig. 13 is a plan view showing the details of the layout of the IO cell, and is a plan view showing the structure of the M3 to M5 wiring layers in portion A3 of Fig. 12. Note that the cross-sectional structure and the configuration of the layers below Fig. 13 are the same as those in the first embodiment, and are therefore not shown here.

[0051] The layout in Fig. 13 is the same as the layout in Fig. 4 in the first embodiment, except that the M5 wirings 21 and 23 correspond to the node C instead of the node B.

[0052] Resistor elements RU are formed in the RMetal wiring layer. Two resistor elements RU are connected in series between the external output terminal PAD and node C. That is, the resistor elements RU are connected between node C and the external output terminal PAD along the following path: M5 wiring 21 (node ​​C) → via (M5-M4) → M4 wiring → via (M4-RMetal) → resistor element RU → via (M4-RMetal) → M4 wiring → via (M4-RMetal) → resistor element RU → via (M4-RMetal) → M4 wiring → via (M5-M4) → M5 wiring 22 (PAD). Similarly, a resistor element RU is connected between the M5 wiring 22 (PAD) and the M5 wiring 23 (node ​​C). A protective resistor Rs is configured by a plurality of resistor elements RU.

[0053] Above the output transistor P1 and the ESD protection diode 1b, M3 wiring 55 and M4 wiring 77 are formed in a grid pattern as wirings for supplying VDDIO. The M3 wiring 55 and M4 wiring 77 are connected to each other through vias. The M4 wiring 77 overlaps with the resistive element RU in the X direction. In other words, the M4 wiring 77 for supplying VDDIO is formed at the X coordinate position where the resistive element RU is formed.

[0054] Above the output transistor N1 and the ESD protection diode 1a, M4 wirings 78 and 79 are formed as wirings for supplying VSS. The M4 wirings 78 and 79 overlap with the resistor element RU in the X direction. In other words, the M4 wirings 78 and 79 for supplying VSS are formed at the X coordinate position where the resistor element RU is formed.

[0055] Note that a part of the resistive element RU constituting the protective resistor Rs may be formed on the output transistors P1 and N1 or on the ESD protection diodes 1a and 1b.

[0056] This embodiment provides the same advantageous effects as the first embodiment. That is, in the configuration according to this embodiment, the resistive element RU constituting the protective resistor Rs is arranged above an area other than the area where the output transistors P1, N1 and the ESD protection diodes 1a, 1b are arranged. Therefore, it is possible to provide ample power supply wiring for VDDIO and VSS in the wiring layer above the output transistors P1, N1 and the ESD protection diodes 1a, 1b.

[0057] This allows a large current to flow through the output transistors P1 and N1. This reduces wiring resistance and suppresses voltage drops, preventing degradation of the operating frequency and improving the quality of signal waveforms. Furthermore, the resistance of the paths from the power supply to the ESD protection diodes 1a and 1b can be suppressed, providing excellent ESD protection characteristics.

[0058] (Modification of the second embodiment) Fig. 14 shows an outline of an IO cell layout according to a modification of the second embodiment. In the layout of Fig. 14, the position of the output transistor N1 is shifted upward in comparison with the layout of Fig. 12. The protective resistor Rs is placed in the region between the output transistor N1 and the output transistor P1.

[0059] In addition to the effects of the second embodiment, this modification provides the following effect. Since the output transistor N1 and the output transistor P1 are disposed on both sides of the protective resistor Rs, the wiring length between the protective resistor Rs and the output transistor N1 and the wiring length between the protective resistor Rs and the output transistor P1 can be made approximately equal. This can improve the imbalance of wiring parasitic components.

[0060] It should be noted that a part of the resistive element RU constituting the protective resistor Rs may be disposed above the output transistors N1 and P1.

[0061] In the above-described embodiment, the ESD protection diodes 1a and 1b and the output transistors N1 and P1 are configured by fins, but this is not limitative.

[0062] In the output circuit in the above-described embodiments, both the P-conductivity type transistor and the N-conductivity type output transistor are single-stage transistors, but this is not limitative and may be a configuration in which multiple stages of transistors, such as two or three stages, are connected in series. In addition, the output circuit in the above-described embodiments may be an input / output circuit including an input circuit.

[0063] In the above embodiment, the RMetal wiring layer is formed between the M4 wiring layer and the M3 wiring layer, but this is not limited to this. The RMetal wiring layer may be formed in the BEOL. [Industrial Applicability]

[0064] The present disclosure can improve the ESD resistance of a semiconductor integrated circuit device that uses a resistive element formed in the BEOL, and is therefore useful for improving the performance of, for example, a system LSI. [Explanation of symbols]

[0065] 1. Semiconductor integrated circuit device 1a,1b ESD protection diodes 10,10a IO cell 11,12 Output circuit 75,76,77,78,79 Power wiring N1, P1 output transistor PAD external output terminal Rsn,Rsp,Rs Protection resistance RU Resistor

Claims

1. A semiconductor integrated circuit device including a plurality of IO cells arranged in a first direction, At least one of the plurality of IO cells includes an output circuit; The output circuit External output terminal, a first ESD (Electro-Static Discharge) protection diode having a first node connected to the external output terminal and a second node connected to a first power supply; a first protection resistor including a plurality of resistance elements formed in a first wiring layer formed in a wiring process (BEOL: Back End of Line), one end of which is connected to the external output terminal; a first output transistor connected between the other end of the first protection resistor and the first power supply; the plurality of resistance elements included in the first protection resistor are connected to wiring formed in a second wiring layer through vias; a first power supply wiring for supplying the first power supply is formed on the first ESD protection diode in the second wiring layer; The first power supply wiring overlaps with any of the plurality of resistance elements included in the first protection resistor in the first direction. Semiconductor integrated circuit device.

2. 2. The semiconductor integrated circuit device according to claim 1, The plurality of resistance elements included in the first protection resistor include two or more resistance elements connected in series between the external output terminal and the first output transistor. Semiconductor integrated circuit device.

3. 2. The semiconductor integrated circuit device according to claim 1, The plurality of resistance elements included in the first protection resistor are arranged in an array in the first wiring layer in the first direction and a second direction perpendicular to the first direction. Semiconductor integrated circuit device.

4. 2. The semiconductor integrated circuit device according to claim 1, The output circuit a second ESD protection diode having a first node connected to a second power supply and a second node connected to the external output terminal; a second protection resistor configured by a plurality of resistance elements formed in the first wiring layer, one end of which is connected to the external output terminal; a second output transistor connected between the other end of the second protection resistor and the second power supply, the plurality of resistance elements included in the second protection resistor are connected to wiring formed in the second wiring layer through vias, a second power supply wiring for supplying the second power supply is formed on the second ESD protection diode in the second wiring layer; The second power supply wiring overlaps with any one of the plurality of resistance elements included in the second protection resistor in the first direction. Semiconductor integrated circuit device.

5. 2. The semiconductor integrated circuit device according to claim 1, The output circuit a second ESD protection diode having a first node connected to a second power supply and a second node connected to the external output terminal; a second output transistor connected between the other end of the first protection resistor and the second power supply, a second power supply wiring for supplying the second power supply is formed on the second ESD protection diode in the second wiring layer; The second power supply wiring overlaps with any of the plurality of resistance elements included in the first protection resistor in the first direction. Semiconductor integrated circuit device.

6. A semiconductor integrated circuit device including a plurality of IO cells arranged in a first direction, At least one of the plurality of IO cells includes an output circuit; The output circuit External output terminal, a first ESD (Electro-Static Discharge) protection diode having a first node connected to the external output terminal and a second node connected to a first power supply; a first protection resistor including a plurality of resistance elements formed in a first wiring layer formed in a wiring process (BEOL: Back End of Line), one end of which is connected to the external output terminal; a first output transistor connected between the other end of the first protection resistor and the first power supply; the plurality of resistance elements included in the first protection resistor are connected to wiring formed in a second wiring layer through vias; a first power supply wiring for supplying the first power supply is formed on the first output transistor in the second wiring layer; The first power supply wiring overlaps with any of the plurality of resistance elements included in the first protection resistor in the first direction. Semiconductor integrated circuit device.

7. 7. The semiconductor integrated circuit device according to claim 6, The plurality of resistance elements included in the first protection resistor include two or more resistance elements connected in series between the external output terminal and the first output transistor. Semiconductor integrated circuit device.

8. 7. The semiconductor integrated circuit device according to claim 6, The plurality of resistance elements included in the first protection resistor are arranged in an array in the first wiring layer in the first direction and a second direction perpendicular to the first direction. Semiconductor integrated circuit device.

9. 7. The semiconductor integrated circuit device according to claim 6, The output circuit a second ESD protection diode having a first node connected to a second power supply and a second node connected to the external output terminal; a second protection resistor configured by a plurality of resistance elements formed in the first wiring layer, one end of which is connected to the external output terminal; a second output transistor connected between the other end of the second protection resistor and the second power supply, the plurality of resistance elements included in the second protection resistor are connected to wiring formed in the second wiring layer through vias; a second power supply wiring for supplying the second power supply is formed on the second output transistor in the second wiring layer; The second power supply wiring overlaps with any one of the plurality of resistance elements included in the second protection resistor in the first direction. Semiconductor integrated circuit device.

10. 7. The semiconductor integrated circuit device according to claim 6, The output circuit a second ESD protection diode having a first node connected to a second power supply and a second node connected to the external output terminal; a second output transistor connected between the other end of the first protection resistor and the second power supply, a second power supply wiring for supplying the second power supply is formed on the second output transistor in the second wiring layer; The second power supply wiring overlaps with any of the plurality of resistance elements included in the first protection resistor in the first direction. Semiconductor integrated circuit device.

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