Information processing program, information processing method, and information processing device

Abstract

The present invention increases the efficiency of simulation of quantum calculations.　An information processing device (10) detects, on the basis of the quantum bit number of a quantum bit to be operated on by a quantum gate included in a first quantum circuit (2), a first quantum gate (4) which includes, as an operation target, a first quantum bit (7) that produces transmission / reception of state data between a plurality of calculation nodes (1a, 1b, ...) during operation. Next, the information processing device (10) inserts, before the first quantum gate (4) of the first quantum circuit (2), a second quantum gate (5) which indicates a replacement operation between the state of a second quantum bit (8) which is to be operated on at the first quantum gate (4) and the state of a third quantum bit (9) for which operation is possible without transmission / reception of state data between the plurality of calculation nodes (1a, 1b, ...). The information processing device (10) then changes the operation target of the first quantum gate (4) from the second quantum bit (8) to the third quantum bit (9).

Description

[Technical Field]

[0001] The present invention relates to an information processing program, an information processing method, and an information processing device. [Background technology]

[0002] There is a simulation technology that can reproduce quantum computations performed by quantum computers on classical computers based on quantum circuits. Hereinafter, classical computers that perform such simulations will be called quantum gate simulators.

[0003] A quantum computer has a state where 0 / 1 is superimposed by quantum superposition. A quantum gate simulator that reproduces this on a classical computer achieves simulation by storing data indicating all possible quantum states in memory. When the number of quantum bits to be simulated is n (n is a natural number), the quantum gate simulator can simulate 2 n The amount of calculation required by the quantum gate simulator also increases as the number of qubits increases.

[0004] The computational complexity of quantum computing depends on the configuration of the quantum circuit. Therefore, various techniques have been proposed to optimize quantum circuits for the purpose of improving computational efficiency. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2022-501731 [Patent Document 2] Special Publication No. 2022-500776 [Patent Document 3] US Patent Application Publication No. 2021 / 0286601 [Patent Document 4] U.S. Patent Application Publication No. 2020 / 0219003 [Patent Document 5] U.S. Patent Application Publication No. 2021 / 0334081 [Patent Document 6] US Patent Application Publication No. 2020 / 0104747 Summary of the Invention [Problem to be solved by the invention]

[0006] As the number of qubits operated in a quantum circuit increases, it becomes difficult to realize a quantum gate simulator on a single computer. Therefore, quantum gate simulators are realized using computer systems that operate multiple computers (computation nodes) in parallel. As the number of qubits increases, the amount of data representing the quantum state also increases, so the data is also distributed and stored in the memory of each of the multiple computation nodes.

[0007] To improve the efficiency of parallel computing on multiple computing nodes, it is important to improve the efficiency of computations involving data communication between the computing nodes. However, in conventional quantum gate simulators, the efficiency of communication processing between the computing nodes for data stored in a distributed manner across multiple computing nodes has been insufficient. As a result, quantum computing simulations using quantum gate simulators with multiple computing nodes have been inefficient.

[0008] In one aspect, the present invention aims to improve the efficiency of quantum computing simulations. [Means for solving the problem]

[0009] In one proposal, an information processing program is provided that causes a computer to perform the following processing. The computer acquires a first quantum circuit to be simulated by multiple computation nodes that perform quantum computing simulations. When the computer allocates storage destinations for state data for each combination of states of multiple quantum bits indicated in the first quantum circuit to multiple computation nodes based on the quantum bit numbers of the quantum bits to be manipulated by the quantum gates included in the first quantum circuit, the computer detects a first quantum gate that includes a first quantum bit as its operation target, which causes transmission and reception of state data between the multiple computation nodes when operated. The computer inserts a second quantum gate before the first quantum gate in the first quantum circuit, which indicates an exchange operation between the state of a second quantum bit to be manipulated by the first quantum gate and the state of a third quantum bit that can be manipulated without transmitting and receiving state data between the multiple computation nodes. The computer then changes the operation target of the first quantum gate from the second quantum bit to the third quantum bit. [Effects of the Invention]

[0010] According to one aspect, it is possible to improve the efficiency of quantum computing simulations. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 illustrates an example of an information processing method according to the first embodiment. [Figure 2] FIG. 1 illustrates an example of a system configuration. [Figure 3] FIG. 2 illustrates an example of hardware of a control node. [Figure 4] FIG. 2 illustrates an example of a hardware configuration of a computing node. [Figure 5] FIG. 10 is a diagram illustrating an example of the functions that each node has for realizing a quantum gate simulator. [Figure 6] FIG. 10 is a diagram illustrating an example of distributed storage of state data. [Figure 7]FIG. 10 is a diagram illustrating an example of a process for changing a cross-node gate operation to an intra-node gate operation. [Figure 8] FIG. 10 is a diagram illustrating an example of a cross-node swap operation. [Figure 9] FIG. 10 is a diagram illustrating an example of a combining process of a SWAP operation. [Figure 10] FIG. 10 is a diagram illustrating an example of the correspondence between “src” and “dst” according to Fused_SWAP. [Figure 11] FIG. 10 is a diagram illustrating a first example of a method for calculating “dst” based on “src.” [Figure 12] FIG. 10 is a diagram illustrating a second example of a method for calculating “dst” based on “src.” [Figure 13] FIG. 10 is a diagram illustrating an example of Fused_SWAP when another quantum bit is sandwiched between two quantum bit groups to be exchanged. [Figure 14] FIG. 10 is a diagram illustrating a third example of a method for calculating “dst” based on “src.” [Figure 15] FIG. 10 is a diagram (1 / 3) showing an example of a procedure for transmitting state data between computing nodes using Fused_SWAP. [Figure 16] FIG. 2 is a diagram (2 / 3) showing an example of a procedure for transmitting state data between computing nodes using Fused_SWAP. [Figure 17] FIG. 3 is a diagram (3 / 3) showing an example of a procedure for transmitting state data between computing nodes using Fused_SWAP. [Figure 18] FIG. 10 is a diagram illustrating an example of a data transmission and reception method using a SWAP pair. [Figure 19] FIG. 1 is a diagram illustrating an example of data transmission using scatter-gather. [Figure 20] FIG. 10 is a diagram showing an example of Fused_SWAP when a small value is selected as the quantum bit number on the inner side. [Figure 21] FIG. 10 is a diagram showing an example of Fused_SWAP when a large value is selected as the quantum bit number on the inner side. [Figure 22]This is a diagram explaining why the number of data communications increases when the inner quantum bit number is selected from small values. [Figure 23] FIG. 10 is a diagram showing an example of a quantum circuit after optimization when the inner quantum bit number is selected. [Figure 24] FIG. 10 is a diagram illustrating an example of a principle for calculating communication pairs using a bipartite graph. [Figure 25] FIG. 10 is a diagram illustrating a first example of exception handling of Fused_SWAP. [Figure 26] FIG. 10 is a diagram illustrating a second example of exception handling of Fused_SWAP. [Figure 27] 10 is a flowchart showing an example of a processing procedure for quantum gate simulation using a quantum circuit to which Fused_SWAP is applied. [Figure 28] 10 is a flowchart illustrating an example of a procedure for quantum circuit optimization processing. [Figure 29] 10 is a flowchart illustrating an example of a processing procedure of a quantum gate simulation. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented in combination with a plurality of other embodiments within a range that does not contradict each other. [First embodiment] The first embodiment aims to improve the efficiency of communication between computation nodes by optimizing quantum circuits, thereby improving the overall computational efficiency of quantum computation simulations.

[0013] Fig. 1 is a diagram showing an example of an information processing method according to a first embodiment. Fig. 1 shows an information processing device 10 for implementing the information processing method according to the first embodiment. The information processing device 10 can implement the information processing method by, for example, executing a predetermined information processing program.

[0014] A plurality of computation nodes 1a, 1b, ... are connected to the information processing device 10. The plurality of computation nodes 1a, 1b, ... are classical computers that perform a quantum computation simulation. When a quantum computation simulation is performed, the storage destinations of state data for each combination of states of the plurality of quantum bits shown in the first quantum circuit 2 are allocated to the plurality of computation nodes 1a, 1b, ....

[0015] To realize the information processing method, the information processing device 10 has a memory unit 11 and a processing unit 12. The memory unit 11 is, for example, a memory or a storage device included in the information processing device 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10.

[0016] The storage unit 11 stores a first quantum circuit 2 to be simulated by a plurality of computation nodes 1a, 1b, . . . and a second quantum circuit 3 obtained by optimizing the first quantum circuit 2.

[0017] The processing unit 12 acquires the first quantum circuit 2. Next, the processing unit 12 detects a first quantum gate 4 that includes a predetermined first quantum bit 7 as an operation target, based on the quantum bit number of the quantum bit to be operated by the quantum gate included in the first quantum circuit 2. The first quantum bit 7 is a quantum bit that, when operated, causes transmission and reception of state data between the multiple computation nodes 1 a, 1 b, .... The processing unit 12 then inserts a second quantum gate 5 before the first quantum gate 4 of the first quantum circuit 2. The second quantum gate 5 is an exchange gate (SWAP gate) that indicates an exchange operation between the state of the second quantum bit 8 that is the operation target of the first quantum gate 4 and the state of a third quantum bit 9 that can be operated without transmitting and receiving state data between the multiple computation nodes 1 a, 1 b, ....

[0018] The processing unit 12 also changes the operation target of the first quantum gate 4 from the second quantum bit 8 to the third quantum bit 9. Furthermore, the processing unit 12 inserts a third quantum gate 6, which exhibits the same exchange operation as the second quantum gate 5, after the first quantum gate 4 in the first quantum circuit 2.

[0019] In this way, an optimized second quantum circuit 3 is generated. In the second quantum circuit 3, the operation target of the first quantum gate 4 is the third quantum bit 9. This eliminates the need to send and receive state data across computation nodes in the quantum computation according to the first quantum gate 4. In other words, each of the multiple computation nodes 1a, 1b, etc. simply performs the quantum computation according to the first quantum gate 4 and updates the state data it holds based on the computation result. This improves processing efficiency.

[0020] In addition, the second quantum gate 5 and the third quantum gate 6 can be configured with one or more SWAP gates. When multiple SWAP gates are connected in succession, the amount of data to be communicated can be reduced by replacing them with a combined operation.

[0021] For example, assume that the quantum bit numbers of the multiple second quantum bits 8 to be operated on by any of the consecutively detected first quantum gates 4 are consecutive. In this case, the processing unit 12 determines the final destination of the state data to be transmitted when the exchange operations corresponding to each of the consecutively detected first quantum gates 4 are performed consecutively. The processing unit 12 then inserts a function (Fused_SWAP, described later) as a second quantum gate before the multiple first quantum gates, instructing the multiple computation nodes 1a, 1b, ... to transmit the state data to be transmitted to the determined destination. This function is used to collectively execute the calculations of multiple SWAP gates in a quantum computation simulation.

[0022] In this way, by executing the processing of multiple SWAP gates together in a single function, the processing of the SWAP gates is made more efficient and the amount of data sent and received between computing nodes for the SWAP is also reduced.

[0023] Furthermore, by appropriately allocating state data to each of the computation nodes 1a, 1b, etc., it is possible to easily detect a quantum gate that operates on a quantum bit whose quantum bit number is equal to or less than a predetermined value as the first quantum gate, as shown in Figure 1.

[0024] For example, the processing unit 12 assigns an address consisting of a bit string indicating the states of multiple quantum bits to the state data for each combination of states. In the bit string of the address, values ​​indicating the states of quantum bits with smaller quantum bit numbers are assigned to lower bits. It is assumed that state data groups having a common value for a predetermined number of first bits from the most significant part of the address are stored in the same computation node. In the example of FIG. 1, state data groups having addresses with a common four most significant bits (bits corresponding to quantum bit numbers "26" to "29") are stored in the same computation node. In this case, a quantum gate operating on a quantum bit corresponding to any of the first bits of the address is detected as the first quantum gate 4. In this way, the first quantum gate 4 can be easily detected.

[0025] In this way, when a set of state data having a common value for a predetermined number of first bits from the most significant part of the address is stored in the same computation node, processing unit 12 selects third quantum bit 9 from among quantum bits whose quantum bit numbers are equal to or less than a predetermined value. For example, processing unit 12 selects a quantum bit corresponding to any of the least significant second bits other than the first bit of the address as third quantum bit 9. In this way, third quantum bit 9 can be easily selected.

[0026] Furthermore, when a set of state data having a common value for a predetermined number of first bits from the most significant part of the address is stored in the same computation node, processing unit 12 selects a quantum bit with as large a quantum bit number as possible as third quantum bit 9. For example, processing unit 12 selects as third quantum bit 9 a quantum bit corresponding to any of the second bits of the address, the quantum bit with the largest quantum bit number, excluding second quantum bit 8.

[0027] This allows status data with consecutive addresses to be transmitted when multiple swaps are executed at once, thereby improving the efficiency of transmitting status data.

[0028] Furthermore, the processing unit 12 instructs the computation nodes 1a, 1b, ... to simulate quantum computation based on the optimized second quantum circuit 3. At this time, the processing unit 12 can also transmit, for example, a program for the simulation to the computation nodes 1a, 1b, ..., thereby causing them to perform an efficient simulation based on the optimized second quantum circuit 3. The program transmitted to the computation nodes 1a, 1b, ... includes an execution program for a function for collectively executing multiple swaps.

[0029] For example, before starting a simulation, the processing unit 12 distributes and stores state data for each combination of states among the multiple computation nodes 1 a, 1 b, etc. Then, the processing unit 12 causes the multiple computation nodes 1 a, 1 b, etc. to execute a simulation according to the second quantum circuit 3 after the second quantum gate is inserted.

[0030] When executing the second quantum gate, each of the multiple computation nodes 1a, 1b,... that execute the simulation generates a destination address by swapping partial bit strings in the address of the state data to be transmitted. For example, each of the multiple computation nodes 1a, 1b,... exchanges, among the first bit strings in the first address of the state data to be transmitted, a first partial bit string corresponding to the second quantum bit 8 and a second partial bit string corresponding to the third quantum bit 9. Each of the multiple computation nodes 1a, 1b,... transmits the state data to be transmitted by specifying, as the destination, a second address indicated by the second bit string obtained by exchanging the partial bit strings.

[0031] By having each of the multiple computing nodes 1a, 1b, . . . execute such processing, the swap processing can be performed efficiently. The processing unit 12 also causes each of the multiple computation nodes 1a, 1b,... to generate a pair with a communication partner and transmit state data to the partner of the pair for each communication pair. At this time, each of the multiple computation nodes 1a, 1b,... transmits its own state data to the address of the state data transmitted by the partner of the pair. For example, each of the multiple computation nodes 1a, 1b,... may have multiple partner computation nodes to which it transmits state data to be transmitted when executing the second quantum gate. In this case, each of the multiple computation nodes 1a, 1b,... divides the transmission process of the state data to be transmitted into multiple communication steps. Here, it is assumed that the first computation node and the second computation node form a communication pair in a specific communication step. At this time, the processing unit 12 causes the first computation node to execute a process of transmitting the first state data to be transmitted, which is stored at the third address, to the second computation node, specifying the fourth address as the destination. The processing unit 12 also causes the second computing node to execute a process of transmitting the second transmission target state data at the fourth address to the first computing node by specifying the third address as the destination. In this way, under the control of the processing unit 12, mutual communication between the communication pair is performed for each communication step.

[0032] By having each of the multiple computation nodes 1a, 1b, etc., send state data to the other node in each communication pair, the buffer capacity used for sending and receiving data can be reduced, making communication more efficient.

[0033] Second Embodiment In the second embodiment, a quantum circuit is optimized for a quantum gate simulator implemented on multiple computation nodes, and quantum computation based on the quantum circuit is executed in parallel on multiple computation nodes.

[0034] 2 is a diagram showing an example of a system configuration. Multiple computation nodes 200a, 200b, etc. are connected to each other via an interconnect 30 that enables high-speed communication. The interconnect 30 is a network in which processors are interconnected by, for example, a six-dimensional mesh / torus.

[0035] Each of the computation nodes 200a, 200b, etc. is also connected to a control network 20. The network 20 is further connected to a control node 100 and a terminal 31. The control node 100 is a computer that issues job execution instructions to the computation nodes 200a, 200b, etc. The terminal 31 is a computer that registers information about jobs to be executed by the computation nodes 200a, 200b, etc. in the control node 100 based on user operations.

[0036] For example, a user can cause the system shown in Fig. 2 to execute quantum computation based on a quantum circuit by having the computation nodes 200a, 200b, etc. simulate the operation of a quantum computer. In this case, for example, the user creates a quantum circuit using the terminal 31. Then, in response to an operation from the user, the terminal 31 transmits quantum circuit data indicating the created quantum circuit to the control node 100. The control node 100 instructs the computation nodes 200a, 200b, etc. to simulate quantum computation based on the quantum circuit.

[0037] 3 is a diagram illustrating an example of hardware of a control node. The entire control node 100 is controlled by a processor 101. A memory 102 and multiple peripheral devices are connected to the processor 101 via a bus 109. The processor 101 may be a multiprocessor. The processor 101 is, for example, a central processing unit (CPU), a micro processing unit (MPU), or a digital signal processor (DSP). At least some of the functions realized by the processor 101 executing a program may be realized by an electronic circuit such as an application specific integrated circuit (ASIC) or a programmable logic device (PLD).

[0038] The memory 102 is used as a main storage device of the control node 100. The memory 102 temporarily stores at least a part of the OS (Operating System) program and application programs to be executed by the processor 101. The memory 102 also stores various data used in processing by the processor 101. As the memory 102, for example, a volatile semiconductor storage device such as a RAM (Random Access Memory) is used.

[0039] The peripheral devices connected to the bus 109 include a storage device 103, a GPU (Graphics Processing Unit) 104, an input interface 105, an optical drive device 106, a device connection interface 107, and a network interface 108.

[0040] The storage device 103 writes and reads data electrically or magnetically to and from a built-in recording medium. The storage device 103 is used as an auxiliary storage device for the control node 100. The storage device 103 stores OS programs, application programs, and various data. Note that the storage device 103 may be, for example, a hard disk drive (HDD) or a solid state drive (SSD).

[0041] The GPU 104 is an arithmetic unit that performs image processing and is also called a graphics controller. The GPU 104 is connected to a monitor 21. The GPU 104 displays an image on the screen of the monitor 21 in accordance with an instruction from the processor 101. The monitor 21 may be a display device using organic EL (Electro Luminescence) or a liquid crystal display device.

[0042] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 and the mouse 23 to the processor 101. The mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0043] The optical drive device 106 uses a laser beam or the like to read data recorded on an optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded so that it can be read by reflected light. The optical disc 24 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (Rewritable), and the like.

[0044] The device connection interface 107 is a communication interface for connecting peripheral devices to the control node 100. For example, a memory device 25 or a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 26 is a device for writing data to the memory card 27 or reading data from the memory card 27. The memory card 27 is a card-type recording medium.

[0045] The network interface 108 is connected to the network 20. The network interface 108 transmits and receives data to and from other computers or communication devices via the network 20. The network interface 108 is a wired communication interface connected by a cable to a wired communication device such as a switch or a router. The network interface 108 may also be a wireless communication interface connected by radio waves to a wireless communication device such as a base station or an access point.

[0046] The control node 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the control node 100 can be recorded on various recording media. For example, the program to be executed by the control node 100 can be stored in a storage device 103. The processor 101 loads at least a part of the program in the storage device 103 into the memory 102 and executes the program. The program to be executed by the control node 100 can also be recorded on a portable recording medium such as an optical disk 24, a memory device 25, or a memory card 27. The program stored on the portable recording medium becomes executable after being installed on the storage device 103, for example, under the control of the processor 101. The processor 101 can also read and execute the program directly from the portable recording medium.

[0047] 4 is a diagram showing an example of the hardware configuration of a computing node. The computing node 200a has a CPU / memory unit 201 and a router 202. The CPU / memory unit 201 and the router 202 are connected by a plurality of communication interfaces (NICs) 203. The CPU / memory unit 201 is also connected to a NIC 204 for connection to the control network 20.

[0048] The CPU / memory unit 201 includes a CPU with multiple cores and memory. The CPU / memory unit 201 generates a process (a processing execution unit) for each core. When a process for each core of the CPU / memory unit 201 performs synchronous processing with a process in another computation node, it communicates with the other computation nodes 200b, ... via a router 202.

[0049] The router 202 communicates with adjacent computation nodes in, for example, each of the three-dimensional directions. The router 202 transmits data to be transmitted from the CPU / memory unit 201 to another computation node to an adjacent computation node in a direction corresponding to the position of that computation node within the interconnect 30. Furthermore, when the router 202 receives data for a process in the CPU / memory unit 201 from an adjacent computation node, it transmits the data to the CPU / memory unit 201. Furthermore, when the data received from an adjacent computation node is data destined for another computation node, the router 202 transmits the data to an adjacent computation node in a direction corresponding to the position of the destination computation node within the interconnect 30.

[0050] The other computation nodes 200b,... have the same hardware configuration as the computation node 200a. When the hardware computation nodes 200a, 200b,... as shown in Figure 4 are mesh / torus connected in three dimensions, a three-dimensional mesh / torus network is formed. When multiple groups of computation nodes connected in three dimensions with a mesh / torus are generated, and these multiple computation node groups are further mesh / torus connected in three dimensions, a six-dimensional mesh / torus network is formed.

[0051] The processing functions of the second embodiment can be realized by the above-described hardware control node 100 and the calculation nodes 200a, 200b, etc. The information processing device 10 shown in the first embodiment can also be realized by the same hardware as the control node 100 or the calculation node 200a.

[0052] Here, a description will be given of factors that reduce the computational efficiency when quantum computation is simulated using the computation nodes 200a, 200b, . . . , which are classical computers. When the number of qubits to be operated on in a quantum circuit for calculation increases, the amount of data representing the qubit states becomes too large to fit into the memory of a single calculation node. Therefore, data representing the qubit states is distributed and stored among multiple calculation nodes 200a, 200b,... When each calculation node 200a, 200b,... performs a gate operation that cannot be calculated using only the data stored in its own memory, it communicates with other calculation nodes to obtain data to be used in the calculation from other calculation nodes. For example, if the gate operation targets qubits whose qubit numbers are below a predetermined value, the calculation corresponding to that gate operation can be performed without communication between calculation nodes. On the other hand, if the gate operation targets qubits whose qubit numbers are above a predetermined value, the calculation requires communication between calculation nodes. Hereinafter, gate operations that require communication between calculation nodes will be referred to as "cross-node gate operations." In contrast, gate operations that allow computation without communication between computation nodes are called "intra-node gate operations."

[0053] Simulating quantum computations that manipulate many quantum bits results in the calculation of extremely large matrices. Therefore, communication associated with cross-node gate operations becomes a bottleneck in improving computational efficiency. Therefore, in the system of the second embodiment, for example, the control node 100 optimizes the quantum circuit in advance so that cross-node gate operations can be performed efficiently. For example, the control node 100 optimizes the quantum circuit so that it performs an exchange process between the state of the quantum bit that is the target of the cross-node gate operation and the state of the quantum bit that can be operated by the intra-node gate operation. By executing a simulation based on the optimized quantum circuit, the state data used in the calculation of the cross-node gate operation is consolidated in local memory at each computation node 200a, 200b, etc. As a result, intra-node gate operations can be performed instead of cross-node gate operations.

[0054] Furthermore, the control node 100 configures the quantum circuit so that the exchange of state data corresponding to multiple cross-node gate operations is executed collectively. By executing the exchange of state data collectively, the total amount of communication can be reduced compared to the total amount of communication that occurred for each cross-node gate operation. In particular, communication is likely to become a bottleneck in quantum gate simulators, and reducing the total amount of communication can significantly improve performance.

[0055] 5 is a diagram showing an example of the functions that each node has for realizing a quantum gate simulator. The control node 100 has a storage unit 110, a simulation instruction unit 120, and a quantum circuit optimization unit 130. The storage unit 110 stores quantum circuit data 111 that indicates the quantum circuit to be calculated.

[0056] The simulation instructing unit 120 acquires quantum circuit data 111 from the terminal 31 used by the user and stores it in the storage unit 110. The simulation instructing unit 120 also instructs the quantum circuit optimizing unit 130 to optimize the quantum circuit indicated in the acquired quantum circuit data 111. The simulation instructing unit 120 then generates a job for executing a simulation based on the quantum circuit indicated by the quantum circuit data 111, and instructs the computation nodes 200a, 200b, ... to execute the job.

[0057] The quantum circuit optimization unit 130 performs optimization processing on the quantum circuit indicated in the quantum circuit data 111 so that quantum computation simulations can be efficiently performed by the computation nodes 200a, 200b, etc. For example, the quantum circuit optimization unit 130 inserts a SWAP gate before a cross-node gate operation and converts the cross-node gate operation into an intra-node gate operation. The quantum circuit optimization unit 130 updates the quantum circuit data 111 in accordance with the optimized quantum circuit.

[0058] The computation node 200a includes a simulation unit 210a and a state data storage unit 220a. The simulation unit 210a cooperates with other computation nodes to execute a simulation of quantum computation according to the quantum circuit indicated in the quantum circuit data 111. The state data storage unit 220a stores state data of the quantum state assigned to the computation node 200a.

[0059] Like the computing node 200a, the computing node 200b also has a simulation unit 210b and a state data storage unit 220b. The simulation unit 210b and the state data storage unit 220b each have the same functions as the elements with the same names in the computing node 200a. Other computing nodes not shown also have the same functions as the computing nodes 200a and 200b.

[0060] The processes that execute the simulation units on each of the multiple computation nodes 200a, 200b, etc. are assigned process numbers that can be identified within the system. For example, the process that executes the simulation unit 210a on computation node 200a has the process number "0." The process that executes the simulation unit 210b on computation node 200b has the process number "1." Each simulation unit 210a, 210b, etc. in computation nodes 200a, 200b, etc. can specify the process with which it communicates by its process number. Note that inter-process communication across computation nodes is performed at high speed by the interconnect 30.

[0061] The functions of the elements shown in FIG. 5 can be realized, for example, by causing a computer to execute a program module corresponding to the element. When a quantum computing simulation based on a quantum circuit is executed in such a system, state data indicating the states of the quantum bits is distributed and stored in the state data storage units 220a, 220b, etc. of the respective computation nodes 200a, 200b, etc. The state data storage units 220a, 220b, etc. are provided in semiconductor memories that can be read and written at high speed.

[0062] 6 is a diagram showing an example of distributed storage of state data. For example, state data for each combination of quantum bit states to be operated by a quantum circuit is distributed and stored in the computation nodes 200a, 200b, etc. Each state data is assigned an address.

[0063] For example, the state data storage unit 220a of the computation node 200a stores state data from addresses "0" to "i-1." For example, the state data "a0" at address "0" represents the probability amplitude when all quantum bits are in the state |0>. The state data "a1" at address "1" represents the probability amplitude when the state of the first quantum bit (quantum bit number "0") is |1> and all other quantum bits are in the state |0>. The size of each state data is, for example, 32 bytes.

[0064] An address is a value that indicates the state (state of other qubits) corresponding to the state data to which the address is assigned, converted into a decimal number. For example, the address of the state data for the state |01000> is the binary number "00010" converted into a decimal number, which is "3", with the order of the state numbers reversed (the smaller qubit number is rearranged to the lower digit).

[0065] 6, the state data storage unit 220a of the computing node 200a stores i pieces of state data (i is a natural number). In this case, the state data storage unit 220b of the computing node 200b stores i pieces of state data from address "i" to "2×i-1". Similarly, each of the other computing nodes stores i pieces of state data.

[0066] In this way, state data for each state that multiple quantum bits can take is distributed and stored in multiple computation nodes 200a, 200b,... In this case, each computation node 200a, 200b,... can perform intra-node gate operations that can be calculated using only the state data it possesses, without communicating with other computation nodes. Such intra-node gate operations are gate operations that operate on quantum bits with quantum bit numbers equal to or less than a predetermined value.

[0067] In contrast, gate operations that operate on quantum bits with quantum bit numbers greater than a predetermined value are cross-node gate operations that require data communication with other computation nodes. Cross-node gate operations can be changed to intra-node gate operations by performing a SWAP process beforehand.

[0068] FIG. 7 is a diagram showing an example of a process for changing a cross-node gate operation to an intra-node gate operation. FIG. 7 shows a quantum circuit 41 for operating 30 quantum bits. In this case, the number of possible combinations of quantum bit states is 2. 30 Here, 2 4 2 for each compute node 26 It is assumed that each piece of state data is stored.

[0069] For example, computation node 200a stores state data corresponding to the case where the states of quantum bit numbers "26" to "29" are |0> (|··0000>), while computation node 200b stores state data corresponding to the case where the state of quantum bit number "26" is |1> and the states of quantum bit numbers "26" to "29" are |0> (|··1000>).

[0070] In such a case, a gate operation that operates on 26 quantum bits from quantum bits "0" to "25" becomes an intra-node gate operation. For example, quantum circuit 41 includes a CNOT gate between quantum bits with adjacent quantum bit numbers. A CNOT gate is represented by a black circle set on the control quantum bit side, a white circle (with a cross inside) set on the target quantum bit side, and a line connecting them. A CNOT gate is a gate operation that inverts the state of the target quantum bit when the control quantum bit is |1>.

[0071] Each of the computation nodes 200a, 200b, etc., mutually swaps the values ​​of two pieces of state data corresponding to the states of all the qubits, where the state of the control qubit is |1> and only the state of the target qubit is different, according to the CNOT gate. Therefore, if the state data whose values ​​are to be swapped are stored within the same computation node, the operation of that CNOT gate becomes an intra-node gate operation.

[0072] The number of state data stored in each of the computing nodes 200a, 200b, etc. is 2. m In the example of FIG. 7, there are two nodes 200a, 200b, and so on. 26It is assumed that state data is stored. In this case, the operation of a CNOT gate that operates on quantum bits with quantum bit number "25" or less is an intra-node gate operation. The operation of any other CNOT gate is a cross-node gate operation (cross-node CNOT).

[0073] Hereinafter, quantum bits with quantum bit numbers equal to or less than the quantum bit number ("25" in the example of Figure 7) that serves as the discrimination criterion between intra-node gate operations and cross-node gate operations will be referred to as "inner." Also, quantum bits with quantum bit numbers greater than the discrimination criterion will be referred to as "outer."

[0074] In the quantum circuit 41 shown in FIG. 7, there are consecutive cross-node CNOTs. In such a case, the quantum circuit optimization unit 130 optimizes the cross-node CNOT so that it transitions to a calculation in which the inner-side quantum bit is the operation target using a SWAP gate (cross-node SWAP), which is a cross-node gate operation. In the optimized quantum circuit 42, for the quantum bit to be operated in the cross-node CNOT, the state is exchanged between the inner-side quantum bit and the outer-side quantum bit, and all CNOT gate operations are performed on the inner-side quantum bit. This allows the communication that occurred at each cross-node CNOT to be consolidated into an exchange process using a SWAP gate.

[0075] The cross-node SWAP operation is inserted before and after the cross-node CNOT in the quantum circuit 41. Whether or not state data is subject to the cross-node SWAP operation can be determined based on the binary representation of the address of the state data.

[0076] Fig. 8 is a diagram showing an example of a cross-node swap operation. Fig. 8 shows a state address table 50. The state address table 50 shows the address value assigned to each state data and the value in exponential notation.

[0077] 8, quantum computing using five quantum bits is assumed. When the number of quantum bits is five, there are 32 possible combinations of states for each quantum bit, and 32 pieces of state data at addresses "0" to "31" are distributed and stored in multiple computation nodes 200a, 200b, ...

[0078] Status data is classified into ranks "0" to "3." In the example in Figure 8, addresses "0" to "7" are classified into rank "0." Addresses "8" to "15" are classified into rank "1." Addresses "16" to "23" are classified into rank "2." Addresses "24" to "31" are classified into rank "3."

[0079] State data with the same rank are stored in the same computation node. The simulation process in each computation node processes the state data of the rank corresponding to that computation node.

[0080] When the address is converted to binary, the value of each digit indicates the state of the quantum bit corresponding to that digit. The value of the lower digit corresponds to the quantum bit with the smaller quantum bit number. In the example of Figure 8, the first digit of the binary notation of the address corresponds to the quantum bit with quantum bit number "0". The second digit corresponds to the quantum bit with quantum bit number "1". The third digit corresponds to the quantum bit with quantum bit number "2". The fourth digit corresponds to the quantum bit with quantum bit number "3". The fifth digit corresponds to the quantum bit with quantum bit number "4".

[0081] In the example of Figure 8, four computing nodes are used to simulate a quantum circuit. In this case, eight pieces of state data are stored in each computing node. Then, "8 = 2 3 " and the quantum bits with quantum bit numbers "2" (3-1) or less are the inner quantum bits.

[0082] A SWAP gate is a two-qubit operation, and two qubits are specified as the target of the operation. For example, a SWAP operation can be expressed as SWAP(p,q), where p and q in parentheses are integers indicating the qubit numbers of the target of the operation.

[0083] In a SWAP(p,q) operation, the quantum bits with quantum bit number "p" and quantum bit number "q" are the objects of operation. The state data for which the XOR (exclusive OR) of the values ​​indicating the quantum bit states of quantum bit number "p" and quantum bit number "q" is "1" is the object of exchange by the SWAP operation. The state data with the address of the value obtained by performing a NOT operation on the values ​​corresponding to the quantum bits with quantum bit number "p" and quantum bit number "q" at the address (in binary notation) of the state data to be exchanged by the SWAP operation is the state data to be exchanged. The NOT operation is a logical operation that changes "0" to "1" and "1" to "0". The SWAP operation is then completed by exchanging the state data to be exchanged with the state data to be exchanged.

[0084] For example, consider the case where a SWAP(2,3) operation is performed. In this case, the state data for which the XOR of the value corresponding to quantum bit "2" and the value corresponding to quantum bit "3" at the address is "1" is the target of the SWAP operation. In the example of Figure 8, the state data at addresses "4" to "11" and "20" to "27" are the targets of the operation. The state data with addresses that have the values ​​obtained by performing a NOT operation on the value corresponding to quantum bit "2" and the value corresponding to quantum bit "3" at the address of the state data to be operated on is the state data that is swapped.

[0085] In the example of Figure 8, the qubits with qubit numbers "2" and below are inner qubits. Therefore, SWAP(2,3) is a cross-node SWAP that manipulates outer and inner qubits. In the case of a cross-node SWAP, the destination of the state data that is the subject of the SWAP operation is state data stored on a computation node other than the computation node on which that state data is stored.

[0086] For example, the exchange destination for each of the status data at addresses "4" to "7" is the status data at addresses "8" to "11." Conversely, the exchange destination for each of the status data at addresses "8" to "11" is the status data at addresses "4" to "7." Furthermore, the exchange destination for each of the status data at addresses "20" to "23" is the status data at addresses "24" to "27." Conversely, the exchange destination for each of the status data at addresses "24" to "27" is the status data at addresses "20" to "23."

[0087] In this way, based on the address of each state data, it is possible to determine whether that state data is the target of a SWAP operation, and if so, which state data will be swapped with it. Furthermore, when SWAP operations are performed consecutively on consecutive quantum bits as shown in Figure 7, consecutive SWAPs can be combined.

[0088] Fig. 9 is a diagram showing an example of the combining process of the SWAP operation. In the state address table 50 shown in Fig. 9, the rank and address columns are omitted, and the binary notation of the address and the quantum bit number of the quantum bit corresponding to each digit are shown.

[0089] The example in FIG. 9 shows the exchange relationship of state data in each SWAP operation when SWAP(1,3) is followed by SWAP(2,4). For example, the status data of address "12" (binary notation "01100") becomes the status data of address "6" (binary notation "00110") through SWAP(1,3). Also, the status data of address "13" (binary notation "01101") becomes the status data of address "7" (binary notation "00111") through SWAP(1,3).

[0090] Furthermore, the status data of address "6" (binary notation "00110") becomes the status data of address "18" (binary notation "10010") through SWAP(2,4). Furthermore, the status data of address "7" (binary notation "00111") becomes the status data of address "19" (binary notation "10011") through SWAP(2,4).

[0091] In SWAP(1,3) and SWAP(2,4), the quantum bit numbers "1" and "2" of one of the targets of the operation are consecutive, and the quantum bit numbers "3,4" of the other are also consecutive. When these two SWAP operations are consecutive, it is possible to define a SWAP operation that combines these SWAP operations. Hereinafter, the combined SWAP operation will be referred to as Fused_SWAP(p,bs). p is the quantum bit number of the base quantum bit. bs is the number of SWAP operations to be combined (the number of consecutive quantum bit numbers (block size) that will be specified as the target of the operation after combining). Combining SWAP(1,3) and SWAP(2,4) shown in Figure 9 results in Fused_SWAP(1,2).

[0092] In Fused_SWAP(1,2), the source and destination state data are specified by "src" (source) and "dst" (destination) rather than by an exchange pair. For example, in the example shown in Figure 9, when "src" is "01100", "dst" is "10010". When "src" is "01101", "dst" is "10011". This relationship between "src" and "dst" can be found for each state data that is the source in Fused_SWAP(1,2).

[0093] FIG. 10 is a diagram showing an example of the correspondence between "src" and "dst" by Fused_SWAP. In FIG. 10, an arrow connects the address value (binary notation) on the "src" side of Fused_SWAP(1,2) with the address value (binary notation) on the "dst" side. By updating each piece of state data corresponding to the "dst" address with each piece of state data corresponding to the "src" address shown in FIG. 10, processing according to the operation of Fused_SWAP(1,2) is completed.

[0094] The result of such a Fused_SWAP(p, bs) process is equivalent to the result of the following process: Fused_SWAP(int p, int bs){ for(int x=p; x <p+bs; x++){SWAP(x,x+bs);} } In other words, Fused_SWAP(p,bs) can achieve the same processing results as repeatedly executing consecutive SWAPs before combining. Furthermore, Fused_SWAP(p,bs) calculates "src" and "dst" to determine the destination of the state data and the processing results, so even if multiple SWAP operations are combined, each state data only needs to be sent once. Therefore, the number of communications can be reduced compared to repeatedly executing SWAPs.

[0095] Next, we will explain how to calculate "dst" from "src" according to arbitrary p and bs in Fused_SWAP. 11 is a diagram showing a first example of a method for calculating "dst" based on "src." In the example of FIG. 11, p is an arbitrary value, and bs is "4." For example, the simulation unit 210a of the computing node 200a performs the following process in accordance with the function Fused_SWAP(p, 4).

[0096] The simulation unit 210a sets two windows 51 and 52, separated by bs, on the bit string of the binary representation of the address "src." Each bit in the bit string corresponds to a quantum bit number. The first window 51 is set at the position of quantum bit number "p," and the second window 52 is set at the position of quantum bit number "p+bs."

[0097] The first window 51 transitions from the position of quantum bit number "p" to the position of "p+bs-1." The second window 52 transitions from the position of quantum bit number "p+bs" to the position of "p+2bs-1."

[0098] The simulation unit 210a determines whether or not state data at the address "src" is to be moved by a SWAP operation between the quantum bits corresponding to the bits at the positions of the two windows 51 and 52 while transitioning the positions of the two windows 51 and 52. Specifically, the simulation unit 210a determines that no state data movement will be performed if the bit values ​​at the positions of the two windows 51 and 52 are the same. Furthermore, the simulation unit 210a determines that no state data movement will be performed if the bit values ​​at the positions of the two windows 51 and 52 are different (XOR is "1").

[0099] The simulation unit 210a then sets "dst" to a bit string obtained by NOTing (inverting the bits) the bit values ​​at positions in the two windows 51 and 52 where the XOR is "1" within the two windows 51 and 52. In the example of Fig. 11, the bit string of "src" is "010100001001000...", and the bit string of "dst" finally obtained is "010010010001000...".

[0100] In the example of Figure 11, to make it easier to understand how to determine the value of "dst", "dst" is obtained from "src" by comparing the values ​​between the two windows 51 and 52 one by one, but it is also possible to calculate "dst" more simply.

[0101] Fig. 12 is a diagram showing a second example of a method for calculating "dst" based on "src." The example shown in Fig. 12 is a method for calculating "dst" by exchanging bit values ​​within the bit string of "src."

[0102] In the bit string of "scr" at a certain address, there are four possible combinations of bit values ​​in the two windows 51 and 52. If the bit value in the first window 51 is "0" and the bit value in the second window 52 is also "0", a SWAP between the quantum bits corresponding to those bits will not move the state data corresponding to the address being judged. If there is no movement of state data, there is no need to manipulate the bit values ​​to obtain "dst". However, since the values ​​of both bits are "0", exchanging the values ​​of those bits will not change the content of the bit string. In other words, it is permissible to exchange the bit values. The same is true if the bit value in the first window 51 is "1" and the bit value in the second window 52 is also "1".

[0103] If the bit value in the first window 51 is "1" and the bit value in the second window 52 is "0", a SWAP between the qubits corresponding to those bits moves the state data corresponding to the address being judged. When moving state data, the values ​​of both bits are exchanged to obtain "dst". The same is true when the bit value in the first window 51 is "0" and the bit value in the second window 52 is "1".

[0104] In this way, it can be considered that for all combinations of bit values ​​in windows 51 and 52, bit value exchange occurs to obtain "dst." Also, as shown in FIG. 11, each SWAP before being combined into Fused_SWAP is independent. In other words, it is not affected by bit inversion of addresses resulting from another SWAP. Therefore, in order to obtain "dst," simulation unit 210a exchanges the values ​​of partial bit string 53 and partial bit string 54 of the bit string of "src." The range of quantum bit numbers corresponding to bits included in partial bit string 53 is [p, p+bs). The range of quantum bit numbers corresponding to bits included in partial bit string 54 is [p+bs, p+2bs). The result of the exchange is the bit string representing "dst."

[0105] In the Fused_SWAP explained so far, the two groups of qubits to be exchanged are the group of qubit numbers "p" to "p+bs-1" and the group of qubit numbers "p+bs" to "p+2bs-1." Although we have explained the case where no other qubits are sandwiched between the two qubit groups, Fused_SWAP is also possible when another qubit is sandwiched between the two qubit groups.

[0106] 13 is a diagram showing an example of a Fused_SWAP in which another quantum bit is sandwiched between two quantum bit groups to be exchanged. In the example of Fig. 13, quantum circuit 43 is generated based on quantum circuit 41, in which a cross-node swap is inserted between quantum bits with quantum bit numbers "19" to "23" and quantum bits with quantum bit numbers "25" to "29". In quantum circuit 43, a quantum bit with quantum bit number "24" is sandwiched between the two quantum bit groups to be exchanged.

[0107] In such cases, add the argument q to the Fused_SWAP function, making it Fused_SWAP(p,q,bs). q is the qubit number of the first qubit in the qubit group that includes the outer qubit. In the example in Figure 13, it would be "p=19", "q=25", and "bd=5". Even if another qubit is sandwiched between the two qubit groups to be swapped, "dst" can be easily calculated from "src".

[0108] 14 is a diagram showing a third example of a method for calculating "dst" based on "src." As with the example shown in FIG. 12, even if another quantum bit is sandwiched between the two quantum bit groups to be exchanged, "dst" can be obtained by exchanging the values ​​of partial bit strings 55 and 56 in the bit string of "src." The quantum bit numbers corresponding to the bits included in partial bit string 55 are in the range [p, p+bs). The quantum bit numbers corresponding to the bits included in partial bit string 56 are in the range [q, q+bs).

[0109] Next, we will explain how to exchange state data. As shown in Figure 8, a simulation is executed in parallel by multiple processes, and each process runs on its own computation node. Therefore, communication between processes is communication across computation nodes. With Fused_SWAP, a large amount of state data is transferred across computation nodes, as shown in Figure 10. When communicating across computation nodes, if the buffer capacity used for sending and receiving data is too large, data transfer becomes inefficient.

[0110] Therefore, each of the computation nodes 200a, 200b, etc. matches the state data to be sent to other computation nodes with the state data to be updated based on the state data received from other computation nodes, and executes sending and receiving of state data in parallel. Below, the procedure for sending state data between computation nodes using Fused_SWAP will be described with reference to Figures 15 to 17.

[0111] FIG. 15 is a diagram (1 / 3) showing an example of the procedure for transmitting state data between computing nodes using Fused_SWAP. FIG. 15 shows the correspondence between "src" and "dst" in transmitting state data when Fused_SWAP (p=1, bs=2) is performed. In the case of Fused_SWAP (p=1, bs=2), state data for two elements with consecutive addresses can be sent together in one data block. Therefore, in the state address table 50a shown in FIG. 15, for each rank, an index (idx) within that rank is assigned to each pair of consecutive addresses (noted in binary).

[0112] State data is stored in the computation data for each rank, and if "src" and "dst" belong to different ranks, state data is transmitted across computation nodes. In the example of Figure 15, each computation node transmits state data three times.

[0113] To improve the efficiency of sending and receiving state data, each computing node simultaneously sends the state data to the destination of the communication pair with which it is exchanging state data. In Fig. 15, the transmission of the data block in the first step (step=1) is indicated by a bold arrow.

[0114] For example, in the transmission of state data in the first step, the computation node that stores state data of rank "0" transmits the data block of its own state data of index "1." The destination is the storage area of ​​the state data of index "0" in the computation node that stores state data of rank "1." At the same time, the computation node that stores state data of rank "1" transmits the data block of its own state data of index "0." The destination is the storage area of ​​the state data of index "1" in the computation node that stores state data of rank "0."

[0115] In this way, a data block sent within the same step is paired with the destination data block that is updated by that data block. Such a pair of data blocks is called a SWAP pair.

[0116] 16 is a diagram (2 / 3) showing an example of a procedure for transmitting state data between compute nodes using Fused_SWAP. In Fig. 16, the transmission of data blocks in the second step (step=2) is indicated by a bold arrow.

[0117] 17 is a diagram (3 / 3) showing an example of a procedure for transmitting state data between compute nodes using Fused_SWAP. In FIG. 17, the transmission of a data block in the third step (step=3) is indicated by a bold arrow.

[0118] Each computation node transmits state data in units of data blocks as shown in Figures 15 to 17. Each computation node can autonomously determine which data block to transmit to which computation node using a predetermined formula without exchanging information with other computation nodes.

[0119] For example, each computing node calculates the number of steps of the transmission process by the formula "2 bs The calculation node calculates the communication partner for the "step" step using the following formula: my_rank^(step<<(tag1-inner_qb) In this formula, "^" indicates exclusive OR between bits. "<<" indicates a left shift of a bit. "step<<(tag1-inner_qb)" means that the bit string of "step" is shifted to the left by the number of "tag1-inner_qb". "my_rank" is the "rank" of the computation node that sends the data block. "tag1" is the smallest quantum bit number among the quantum bit numbers of the quantum bits to be operated on in the quantum gate that requires SWAP. In the examples of Figures 15 to 17, "tag1=3". Also, in the examples of Figures 15 to 17, "inner_qb=3".

[0120] Furthermore, the calculation node calculates the index value of the data block to be sent in the "step" step using the following formula. ((tag1-inner_qb)>>my_rank)^step ">>" is a bit shift to the right. "tag1-inner_qb)>>my_rank" means to shift the bit string of "my_rank" to the right by the number of "tag1-inner_qb".

[0121] For example, if "step=2 (second step)" and "rank=1", the data block will be sent to the computation node with "rank=3", and the data block to be sent will be the data block with "idx=3" (see Figure 16).

[0122] In this way, each computing node can autonomously identify the data block of the other node in the swap pair using a predetermined calculation formula. Then, by the computing nodes that have each data block of the swap pair sending that data block in the same step, each computing node can receive the data block of the other node in the swap pair with a small buffer capacity.

[0123] 18 is a diagram showing an example of a data transmission / reception method using a SWAP pair. For example, assume that a data block 61 stored in a computing node 200a and a data block 62 stored in a computing node 200b form a SWAP pair. The computing node 200a is provided with buffers 211a and 212a having a double buffer configuration. The computing node 200b is also provided with buffers 211b and 212b having a double buffer configuration. The buffers 211a, 212a, 211b, and 212b have the same capacity.

[0124] The computing node 200a transmits data of a predetermined length (the size of the buffers 211b and 212b) from the beginning of the data block 61 to the computing node 200b. For example, the first transmitted data is stored in the buffer 211b, and the second transmitted data is stored in the buffer 212b. Similarly, the computing node 200b transmits data of a predetermined length (the size of the buffers 211a and 212a) from the beginning of the data block 62 to the computing node 200a. For example, the first transmitted data is stored in the buffer 211a, and the second transmitted data is stored in the buffer 212a.

[0125] While transmitting the second data, the computing node 200a copies the previously received data stored in the buffer 211a to the beginning of the data block 61. Similarly, while transmitting the second data, the computing node 200b copies the previously received data stored in the buffer 211b to the beginning of the data block 62.

[0126] By transmitting and receiving the data blocks 61 and 62 of the SWAP pair in this way, the buffer capacity required for each of the computation nodes 200a and 200b can be reduced. For example, if each computation node transmits a data block without considering the SWAP pair, each computation node 200a, 200b, etc. will be provided with a sending buffer and a receiving buffer. These buffers are required to have a capacity sufficient to store all of the data blocks to be transmitted and received in Fused_SWAP. If a large amount of memory storage capacity is consumed by the buffers, the number of quantum bits available for quantum computation in the simulation will be reduced.

[0127] On the other hand, if the data block is sent and received as shown in Figure 18 while taking into account the SWAP pair, the data in the area where the received data should be stored has already been sent, and the received data can be immediately written to the target data block. The buffer size is sufficient as long as it has enough bandwidth. Reducing the buffer capacity used for Fused_SWAP allows for more efficient memory utilization and increases the number of qubits available for quantum computing.

[0128] Furthermore, by using a scatter-gather transfer method via a buffer, efficient data transfer is possible even if the data to be transmitted is stored in discontinuous locations. FIG. 19 is a diagram showing an example of data transmission using scatter-gather. For example, suppose that computation node 200a and computation node 200b mutually transmit data blocks of a swap pair. Computation node 200a stores the data in the data block to be transmitted to computation node 200b in a discontinuous area of ​​memory. Computation node 200b also stores the data in the data block to be transmitted to computation node 200a in a discontinuous area of ​​memory.

[0129] At this time, the computing node 200a stores the data to be sent to the computing node 200b in a continuous area in the communication buffer 213a, and transmits the stored data continuously from the communication buffer 213a to the computing node 200b. Similarly, the computing node 200b stores the data to be sent to the computing node 200a in a continuous area in the communication buffer 213b, and transmits the stored data continuously from the communication buffer 213b to the computing node 200a. For example, the data in the communication buffer 213a and the communication buffer 213b is passed between them by MPI (Message Passing Interface).

[0130] Data transmitted from the communication buffer 213a to the computing node 200b is distributed and stored at the location of the target data in the computing node 200b. Similarly, data transmitted from the communication buffer 213b to the computing node 200a is distributed and stored at the location of the target data in the computing node 200a.

[0131] By transferring data using scatter-gather in this way, the number of communications can be reduced, resulting in improved communication efficiency. In addition, in Fused_SWAP, the number of state data included in the data block sent in one data transmission step is determined by the inner quantum bit number. Specifically, it is determined by the difference between "inner_qb" (the number of inner quantum bits) and "p+bs". Therefore, the number of data communications can also be reduced by selecting the inner quantum bit number to be swapped in Fused_SWAP. Below, we will explain an appropriate method for selecting the inner quantum bit number with reference to Figures 20 and 21.

[0132] Fig. 20 is a diagram showing an example of Fused_SWAP when a small value is selected as the quantum bit number on the inner side. Fig. 20 shows a state address table 50b when the number of state data stored in one computation node is 4. The addresses of "src" and "dst" in the case of Fused_SWAP (p=0, q=3, bs=1) are connected by a line.

[0133] In this example, "inner_bp=2", "P=0", and "bs=1". Therefore, the difference between "inner_qb" and "p+bs" is "1". In this case, the addresses of the state data to be sent are discontinuous, and the state data is sent one by one to the destination computing node. Therefore, the number of steps in data communication is "2".

[0134] Figure 21 is a diagram showing an example of Fused_SWAP when a large value is selected as the quantum bit number on the inner side. In Figure 21, the addresses of "src" and "dst" in the case of Fused_SWAP (p=1, q=3, bs=1) are connected by a line. In this example, "inner_bp=2", "P=1", and "bs=1". Therefore, the difference between "inner_qb" and "p+bs" is "2". In this case, the addresses of the state data to be sent are consecutive, two by two, and the state data can be collected into a data block containing two and sent to the destination computation node. Therefore, the number of steps in data communication is "1".

[0135] FIG. 22 is a diagram that explains why the number of data communications increases by selecting the inner side quantum bit number from a small value. As shown in FIG. 22, in the case of Fused_SWAP (p=20, q=27, bs=3), there is a difference of 3 quantum bits between the quantum bit on the inner side and inner_qb. Even if the bit strings with quantum bit numbers lower than "22" and the bit strings with quantum bit numbers "26" and above share the same address, the number of bits (k) corresponding to the difference between inner_qb and the quantum bit on the inner side, k (k is a natural number), is used (2 k ) combinations exist. Then, there are 2 combinations between the addresses of the state data to be swapped. k As a result, it becomes difficult to transmit a large amount of status data in one data block.

[0136] The fewer the number of data blocks, the more efficient the data communication. In other words, it is more efficient to swap data in a continuous area than to swap data in discrete areas. Therefore, it is appropriate to select a quantum bit with as high a quantum bit number as possible as the inner quantum bit in Fused_SWAP.

[0137] Figure 23 is a diagram showing an example of a quantum circuit after optimization when an inner-side quantum bit number is selected. As shown in Figure 23, the quantum circuit optimization unit 130 designates as the inner-side quantum bit the largest possible quantum bit number as the quantum bit to be swapped. In the quantum circuit 42 shown in Figure 23, no quantum bits that are not subject to swapping are sandwiched between the outer-side quantum bit to be swapped and the inner-side bit to be swapped. Therefore, efficient data transfer is possible by combining multiple state data into one data block.

[0138] The number of qubits to be swapped depends on the number of qubits on the outer side. Therefore, the qubit number "p" of the first qubit on the inner side is determined taking into account the number of qubits on the outer side. Note that although the qubit with qubit number "25" is an inner qubit, it is used in a cross-node CNOT gate (it is inappropriate to swap with qubits on the inner side). Therefore, in Fused_SWAP, the qubit with qubit number "25" is included as a target for swapping with other inner qubits, along with the outer qubits.

[0139] When the quantum circuit optimization unit 130 inserts Fused_SWAP into the quantum circuit 42, it changes the designation of the quantum bit that was originally the target of the gate operation. For example, if CNOT(25,26) was specified immediately after the first Fused_SWAP, it is changed to CNOT(20,21). This enables each computation node to perform computations corresponding to the CNOT gate using state data stored locally.

[0140] After changing the operation on the outer quantum bit to the inner quantum bit and performing the operation, the quantum circuit optimization unit 130 inserts the same Fused_SWAP operation as the first Fused_SWAP into the quantum circuit 42. By executing Fused_SWAP twice, the state can be restored so that the state data is the same as that of the quantum circuit 41 before optimization and the measurement results can be obtained.

[0141] Furthermore, the selection of a communication pair (two computation nodes that transmit data to each other) for each communication step, as shown in Figures 15 to 17, can be appropriately determined even if it is more complex. For example, the communication pair can be calculated using a bipartite graph.

[0142] FIG. 24 is a diagram showing an example of the principle of calculating communication pairs using a bipartite graph. For example, when the number of computation nodes performing quantum gate simulation is four, communication pairs are obtained using a bipartite graph 70 consisting of two node sets, each containing four nodes (white circles in FIG. 24). The four nodes in the node sets of the bipartite graph 70 correspond to computation nodes. In the bipartite graph 70, nodes corresponding to computation nodes with which data communication is performed using Fused_SWAP are connected by edges (lines connecting nodes).

[0143] Here, edge coloring of the bipartite graph 70 is performed to obtain communication pairs for each communication step. Edge coloring of the bipartite graph 70 is a process of finding a combination in which, in a bipartite graph 70 consisting of a node set of N nodes (N is a natural number) and another node set of N nodes, each node has k edges, such that one edge is sent from each node. It is known that edge coloring of the bipartite graph 70 always allows k colorings.

[0144] In edge coloring, for example, combinations in which one edge emerges from each node of the bipartite graph 70 are searched for, and the corresponding combinations are colored. Next, the colored edges are removed, and the remaining edges are colored again. By repeating this process k times, k different colorings are obtained. In the example of Figure 24, the colored edges are shown with thick lines. Since three edges emerge from each node of the bipartite graph 70, it is colored in three colors.

[0145] The problem of the combination of communication partners can be solved by performing communications corresponding to edges colored with the same color in the edge coloring in the same communication step. Note that if it is more efficient for each computing node to communicate with multiple computing nodes in a single communication step, data communications according to multiple coloring patterns may be performed in parallel.

[0146] Next, we will explain the exception handling for the inner and outer quantum bits of Fused_SWAP. Figure 25 shows a first example of exception handling for Fused_SWAP. Communication occurs in Fused_SWAP when the quantum bit number of the quantum bit that is the target of the gate operation exceeds a specific value. This specific value is the quantum bit number within the range in which quantum computation is possible within the computation node, and is given as "inner_qb."

[0147] In the quantum circuit 42, the number of quantum bits is "30" and "inner_qb=26." The quantum circuit 42 includes a cross-node SWAP due to the insertion of Fused_SWAP (p=20, bs=5).

[0148] In this case, the SWAP integrated into Fused_SWAP(p=20,bs=5) includes SWAP(20,25). This SWAP operation is a closing operation within one computation node. Communication within a computation node is approximately 100 times faster than communication between computation nodes. On the other hand, in the processing of Fused_SWAP, it is inefficient to distinguish between SWAPs within a computation node and SWAPs between computation nodes and to consider the presence or absence of MPI communication. Therefore, when a SWAP within a computation node is included in Fused_SWAP, the quantum circuit optimization unit 130 may perform exception handling so that all Fused_SWAP targets become inner-outer pairs.

[0149] For example, the quantum circuit optimization unit 130 performs optimization so that the inner-inner SWAP is executed before the Fused_SWAP. In the example of Fig. 25, the SWAP (20, 25) is executed before the Fused_SWAP.

[0150] The quantum circuit optimization unit 130 shifts the quantum bit number to be processed by Fused_SWAP by the amount of the inner-inner SWAP that will be performed first. The value of "bs" is subtracted by the amount of the shift in the quantum bit number. In the example of FIG. 25, the function Fused_SWAP(p=20, bs=5) is changed to Fused_SWAP(p=21, q=26, bs=4).

[0151] When this type of exception handling is performed, there is a gap between the inner and outer sides of the Fused_SWAP (a quantum bit not subject to the SWAP is sandwiched in between), but it has the advantage that all Fused_SWAPs can be calculated as inner-outer pairs. Conversely, if the degree of "inner_qb" is low, the outer-outer SWAP operation can be performed before the Fused_SWAP.

[0152] FIG. 26 is a diagram showing a second example of exception handling for Fused_SWAP. In the example of FIG. 26, "inner_qb=24" is used. When performing a Fused_SWAP(p=20,bs=5) operation, the quantum bit with quantum bit number "24" on the outer side is included in the inner side SWAP target. In this case, the function of Fused_SWAP can be modified so that SWAP(24,29) is performed before Fused_SWAP, and all of the inner-outer swaps of Fused_SWAP can be performed. Fused_SWAP becomes Fused_SWAP(p=20,q=25,bs=4). When extracting the outer-outer swap, it is not necessary to move the number of the first quantum bit to be processed in Fused_SWAP.

[0153] Next, we will explain in detail the processing procedure for quantum gate simulation using a quantum circuit to which Fused_SWAP is applied. 27 is a flowchart showing an example of the processing procedure of a quantum gate simulation using a quantum circuit to which Fused_SWAP is applied. The processing shown in FIG. 27 will be explained below in order of step number.

[0154] [Step S101] The simulation instruction unit 120 of the control node 100 acquires a quantum circuit defined by a user. For example, the simulation instruction unit 120 acquires data of a quantum circuit created by a user from the terminal 31. The simulation instruction unit 120 may also generate a quantum circuit in response to input from the user via the terminal 31. The simulation instruction unit 120 stores the acquired quantum circuit in the storage unit 110.

[0155] [Step S102] The simulation instruction unit 120 instructs the quantum circuit optimization unit 130 to optimize the acquired quantum circuit. The quantum circuit optimization unit 130 optimizes the quantum circuit using Fused_SWAP so that cross-node gate operations become intra-node gate operations. The quantum circuit optimization unit 130 updates the quantum circuit in the storage unit 110 with the optimized quantum circuit. The details of the processing procedure for quantum circuit optimization by the quantum circuit optimization unit 130 will be described later (see FIG. 28).

[0156] [Step S103] The simulation instructing unit 120 transmits the optimized quantum circuit and a quantum computing simulation program using the quantum circuit to the multiple computing nodes 200a, 200b, and instructs the computing nodes to execute a quantum gate simulation. At this time, the simulation instructing unit 120 transmits to each computing node a simulation program including a program for processing the Fused_SWAP function.

[0157] [Step S104] Each of the computation nodes 200a, 200b, etc. executes a quantum gate simulation. The quantum gate simulation process will be described in detail later (see FIG. 29).

[0158] [Step S105] The simulation instruction unit 120 acquires the calculation results of the quantum gate simulation from the calculation nodes 200a, 200b, etc. The calculation results are, for example, an array of the states (|0> or |1>) of each quantum bit measured with the highest probability after performing a quantum calculation based on a quantum circuit. The simulation instruction unit 120 outputs the acquired calculation results.

[0159] Next, the quantum circuit optimization process will be described in detail. 28 is a flowchart showing an example of the procedure for quantum circuit optimization processing. The processing shown in FIG. 28 will be explained below in order of step number.

[0160] [Step S111] The quantum circuit optimization unit 130 reads out a quantum circuit from the storage unit 110 and detects quantum gates that require a swap, starting from the top of the quantum circuit. A quantum gate that requires a swap is, for example, a quantum gate in which at least some of the quantum bits to be operated on are outer quantum bits.

[0161] [Step S112] The quantum circuit optimization unit 130 determines whether a quantum gate requiring a swap has been detected. If a quantum gate requiring a swap has been detected, the quantum circuit optimization unit 130 proceeds to step S113. If a quantum gate requiring a swap has not been detected, the quantum circuit optimization unit 130 proceeds to step S121.

[0162] [Step S113] The quantum circuit optimization unit 130 determines whether the quantum gate following the quantum gate requiring a swap also requires a swap. If a swap is required, the quantum circuit optimization unit 130 proceeds to step S114. If a swap is not required, the quantum circuit optimization unit 130 proceeds to step S118.

[0163] [Step S114] The quantum circuit optimization unit 130 determines whether the quantum bits to be operated on in consecutive quantum gates requiring a swap are consecutive. For example, the quantum circuit optimization unit 130 determines that the quantum bits are consecutive when the quantum bit numbers of the control quantum bits in consecutive quantum gates requiring a swap are consecutive and the quantum bit numbers of the target quantum bits are consecutive. If the quantum bits are consecutive, the quantum circuit optimization unit 130 proceeds to step S115. If the quantum bits are discontinuous, the quantum circuit optimization unit 130 proceeds to step S118.

[0164] [Step S115] The quantum circuit optimization unit 130 inserts Fused_SWAP gate operations corresponding to consecutive quantum gates requiring a swap before those quantum gates in the quantum circuit. At this time, the inner quantum bit with the largest possible quantum bit number is selected as the quantum bit to which the state of the quantum bit to be operated by the quantum gate requiring a swap is swapped.

[0165] [Step S116] The quantum circuit optimization unit 130 changes the quantum bit number of the operation target of the quantum gate requiring a swap to the quantum bit number of the swap partner according to Fused_SWAP.

[0166] [Step S117] To restore the order of the quantum bits, the quantum circuit optimization unit 130 inserts the same Fused_SWAP gate operation as in step S115 after the quantum gate requiring SWAP. After that, the quantum circuit optimization unit 130 proceeds to step S111.

[0167] [Step S118] The quantum circuit optimization unit 130 inserts a SWAP gate operation corresponding to the quantum gate requiring a SWAP before that quantum gate in the quantum circuit. For example, if the operation targets of the quantum gate requiring a SWAP are two outer quantum bits with discontinuous quantum bit numbers, a SWAP gate is inserted that swaps each quantum bit with the inner quantum bit. Note that if the operation targets of consecutive SWAP-requiring gates are the same quantum bits, a SWAP gate that swaps the outer quantum bits that are operated consecutively with the inner quantum bit can be inserted before those consecutive SWAP-requiring gates.

[0168] [Step S119] The quantum circuit optimization unit 130 changes the quantum bit number of the operation target of the quantum gate requiring a swap to the quantum bit number of the swap partner. [Step S120] To restore the order of the quantum bits, the quantum circuit optimization unit 130 inserts the same SWAP gate operation as in step S118 after the quantum gate requiring SWAP. After that, the quantum circuit optimization unit 130 proceeds to step S111.

[0169] [Step S121] The quantum circuit optimization unit 130 updates the quantum circuit in the storage unit 110 with the modified quantum circuit. In this way, a quantum circuit is generated that does not have any gates across nodes other than the SWAP gate.

[0170] 29 is a flowchart showing an example of a processing procedure for quantum gate simulation. The processing shown in FIG. 29 will be explained below in order of step numbers, assuming that it is executed by the simulation unit 210a of the computation node 200a.

[0171] [Step S131] The simulation unit 210a calculates changes in the states of quantum bits according to quantum gates, starting from the top of the quantum circuit. [Step S132] The simulation unit 210a determines whether the next operation to be executed is Fused_SWAP. If it is Fused_SWAP, the simulation unit 210a proceeds to step S133. If it is not Fused_SWAP, the simulation unit 210a proceeds to step S139.

[0172] [Step S133] The simulation unit 210a bs Steps S134 to S138 are executed for each communication step. [Step S134] The simulation unit 210a identifies the rank of the partner with which state data is exchanged in the current communication step according to a predetermined calculation formula. For example, the simulation unit 210a sets the rank of its own computation node 200a to "my_rank." The simulation unit 210a also sets the number of quantum bits on the inner side to "inner_qb." The simulation unit 210a also sets the smallest quantum bit number among the quantum bit numbers of the quantum bits to be operated on in the quantum gate requiring SWAP to "tag1." For example, when Fused_SWAP(p,q,bs) is executed, the value of q is "tag1." When Fused_SWAP(p,bs) is executed, the value of "p+bs" is "tag1." The simulation unit 210a then calculates "my_rank^(step<<(tag1-inner_qb)" and sets the calculation result as the rank of the transmission partner computation node.

[0173] [Step S135] The simulation unit 210a uses a predetermined formula to identify the state data to be exchanged. For example, the simulation unit 210a calculates "((tag1-inner_qb)>>my_rank)^step" and identifies the state data corresponding to the index (idx) indicated by the calculation result as the state data to be exchanged.

[0174] [Step S136] Based on the address of the state data to be exchanged, the simulation unit 210a identifies the address of the destination of the state data. For example, the simulation unit 210a determines the destination address by swapping two partial bit strings, each of which is specified by Fused_SWAP, from the address (bit string) of the state data to be exchanged.

[0175] [Step S137] The simulation unit 210a exchanges state data with a process corresponding to the exchange partner's rank (a process executing a simulation unit on another computation node).

[0176] [Step S138] The simulation unit 210a bs When the processes of steps S134 to S138 for one communication step are completed, the process proceeds to step S131.

[0177] [Step S139] The simulation unit 210a determines whether the calculations corresponding to the quantum gates in the quantum circuit have been completed. If the calculations have not been completed, the simulation unit 210a proceeds to step S131. If the calculations have been completed, the simulation unit 210a proceeds to step S140.

[0178] [Step S140] The simulation unit 210a outputs the calculation results according to the quantum circuit. In this way, the computational efficiency of quantum gate simulations using classical computers based on quantum circuits can be improved. That is, by inserting a cross-node SWAP quantum gate before each quantum gate for cross-node gate operations, the calculation of subsequent gate operations can be performed without communication between the computation nodes. Therefore, the calculation of gate operations can be performed efficiently.

[0179] For example, consider a case where multiple quantum gates operating on outer quantum bits, which is a cross-node gate operation, are connected in a row, and the quantum bit numbers operated by these quantum gates are common to "a" and "b." In this case, by inserting a single SWAP gate before these quantum gates that swaps the quantum bits with quantum bit numbers "a" and "b" with the inner quantum bit, it becomes possible to perform calculations involving the operation of multiple quantum gates without communication between computation nodes.

[0180] Furthermore, when the quantum bits of consecutive quantum gates that require a SWAP are consecutive, using Fused_SWAP makes it possible to efficiently transfer data for the SWAP. For example, let's say that the amount of state data held by one computation node is M (M is a natural number). When a normal SWAP is repeated, the SWAP moves only the state data where the XOR of the specified quantum bit is "1", so in one SWAP, each computation node transfers M / 2 of the amount of state data. Therefore, if there are N quantum bits to be swapped (N is a natural number), then (M / 2) x N pieces of data will be transferred. If we consider the computational complexity as N, the computational complexity is O(N) in order notation.

[0181] Fused_SWAP moves non-zero XOR data of two bit strings (e.g., [p:p+N] and [q:q+N]) with N bits in each string (bs=N since N swaps are performed). The number of data to be moved by Fused_SWAP is M(1-(1 / 2) N ) data. If we consider the computational complexity as N, the amount of calculation is O(1) in order notation. In other words, Fused_SWAP does not change the execution time even if multiple SWAPs are integrated.

[0182] In this way, Fused_SWAP allows multiple SWAPs to be executed together, shortening the processing time of the SWAPs inserted to eliminate cross-node gates from the quantum circuit. Furthermore, the elimination of cross-node gates shortens the time required for quantum gate simulation of the entire quantum circuit.

[0183] Other Embodiments In the second embodiment, the quantum circuit is optimized by the control node 100, but the quantum circuit can also be optimized by any of the computation nodes 200a, 200b, ... For example, one of the multiple computation nodes that perform the simulation can be set as the main computation node, and the main computation node can optimize the quantum circuit and transmit the optimized quantum circuit to the other computation nodes.

[0184] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents. [Explanation of symbols]

[0185] 1a, 1b,... Compute node 2 The first quantum circuit 3 The second quantum circuit 4 The first quantum gate 5. The second quantum gate 6 The third quantum gate 7. The First Qubit 8. Second Qubit 9 The Third Qubit 10. Information processing equipment 11 Storage section 12 Processing section

Claims

1. obtaining a first quantum circuit to be simulated by a plurality of computation nodes that perform a quantum computation simulation; when the storage destinations of state data for each combination of states of the plurality of quantum bits indicated in the first quantum circuit are allocated to the plurality of computation nodes based on the quantum bit numbers of the quantum bits to be operated by the quantum gates included in the first quantum circuit, detecting a first quantum gate that includes, as an operation target, a first quantum bit that causes transmission and reception of the state data between the plurality of computation nodes when operated; inserting a second quantum gate before the first quantum gate of the first quantum circuit, the second quantum gate indicating an exchange operation between the state of a second quantum bit to be operated by the first quantum gate and the state of a third quantum bit that can be operated without transmitting and receiving the state data between the plurality of computation nodes; changing the operation target of the first quantum gate from the second quantum bit to the third quantum bit; Have the computer execute the process, In the process of inserting the second quantum gate, if the quantum bit numbers of the plurality of second quantum bits to be operated on by any of the successively detected first quantum gates are consecutive, determine a final destination of state data to be transmitted when the exchange operations corresponding to each of the successively detected first quantum gates are successively performed, and insert a function, as the second quantum gate, before the successively detected first quantum gate, that instructs the plurality of computation nodes to transmit the state data to the determined destination; Information processing program.

2. In the process of detecting the first quantum gate, The state data for each combination of states is a bit string indicating the states of the plurality of quantum bits, and the bit string is assigned to a lower bit as the value indicating the state of a quantum bit with a smaller quantum bit number is associated as an address, and when it is determined that a state data group having a common value for a predetermined number of first bits from the most significant bit of the address is stored in the same calculation node, a quantum gate that operates on a quantum bit corresponding to any of the first bits of the address is detected as the first quantum gate. The information processing program according to claim 1.

3. In the process of inserting the second quantum gate, a quantum bit corresponding to any lower second bit other than the first bit of the address is selected as the third quantum bit.

3. The information processing program according to claim 2.

4. In the process of inserting the second quantum gate, a consecutive quantum bit having a larger quantum bit number, excluding the second quantum bit, is selected as the third quantum bit from among the quantum bits corresponding to any of the second bits of the address.

4. The information processing program according to claim 3.

5. obtaining a first quantum circuit to be simulated by a plurality of computation nodes that perform a quantum computation simulation; when the storage destinations of state data for each combination of states of the plurality of quantum bits indicated in the first quantum circuit are allocated to the plurality of computation nodes based on the quantum bit numbers of the quantum bits to be operated by the quantum gates included in the first quantum circuit, detecting a first quantum gate that includes, as an operation target, a first quantum bit that causes transmission and reception of the state data between the plurality of computation nodes when operated; inserting a second quantum gate before the first quantum gate of the first quantum circuit, the second quantum gate indicating an exchange operation between the state of a second quantum bit to be operated by the first quantum gate and the state of a third quantum bit that can be operated without transmitting and receiving the state data between the plurality of computation nodes; changing the operation target of the first quantum gate from the second quantum bit to the third quantum bit; Have the computer execute the process, In the process of detecting the first quantum gate, The state data for each combination of states is a bit string indicating the states of the plurality of quantum bits, and the bit string is assigned to a lower bit as the value indicating the state of a quantum bit with a smaller quantum bit number is associated as an address, and when it is determined that a state data group having a common value for a predetermined number of first bits from the most significant bits of the address is stored in the same calculation node, a quantum gate that operates on a quantum bit corresponding to any of the first bits of the address is detected as the first quantum gate, In the process of inserting the second quantum gate, among the quantum bits corresponding to any of the lower second bits other than the first bit of the address, consecutive quantum bits in ascending order of quantum bit number, excluding the second quantum bit, are selected as the third quantum bit. Information processing program.

6. inserting a third quantum gate that exhibits the same exchange operation as the second quantum gate after the first quantum gate in the first quantum circuit; 6. The information processing program according to claim 1, further causing the computer to execute a process.

7. Distributing and storing the state data for each combination of states in the plurality of computing nodes; causing the plurality of computation nodes to execute a simulation according to a second quantum circuit after the second quantum gate is inserted; When the plurality of computation nodes execute the second quantum gate, each of the plurality of computation nodes executes a process of transmitting the state data to be transmitted by specifying, as a destination, a second address indicated by a second bit sequence obtained by exchanging, among a first bit sequence of a first address of the state data to be transmitted, a first partial bit sequence corresponding to the second quantum bit and a second partial bit sequence corresponding to the third quantum bit.

2. The information processing program according to claim 1, further causing the computer to execute a process.

8. In the process of causing each of the plurality of computing nodes to execute the process of transmitting the transmission target status data, When there are a plurality of counterpart computing nodes to which each of the plurality of computing nodes transmits the transmission target state data when executing the second quantum gate, the transmission process of the transmission target state data is divided into a plurality of communication steps, and in the same communication step, the first computing node is made to execute a process of transmitting the first transmission target state data of the third address to the second computing node by specifying the fourth address as a destination, and the second computing node is made to execute a process of transmitting the second transmission target state data of the fourth address to the first computing node by specifying the third address as a destination.

8. The information processing program according to claim 7, further causing the computer to execute a process.

9. obtaining a first quantum circuit to be simulated by a plurality of computation nodes that perform a quantum computation simulation; when the storage destinations of state data for each combination of states of the plurality of quantum bits indicated in the first quantum circuit are allocated to the plurality of computation nodes based on the quantum bit numbers of the quantum bits to be operated by the quantum gates included in the first quantum circuit, detecting a first quantum gate that includes, as an operation target, a first quantum bit that causes transmission and reception of the state data between the plurality of computation nodes when operated; inserting a second quantum gate before the first quantum gate of the first quantum circuit, the second quantum gate indicating an exchange operation between the state of a second quantum bit to be operated by the first quantum gate and the state of a third quantum bit that can be operated without transmitting and receiving the state data between the plurality of computation nodes; changing the operation target of the first quantum gate from the second quantum bit to the third quantum bit; In the process of inserting the second quantum gate, if the quantum bit numbers of the plurality of second quantum bits to be operated on by any of the successively detected first quantum gates are consecutive, determine a final destination of state data to be transmitted when the exchange operations corresponding to each of the successively detected first quantum gates are successively performed, and insert a function, as the second quantum gate, before the successively detected first quantum gate, that instructs the plurality of computation nodes to transmit the state data to the determined destination; An information processing method in which processing is performed by a computer.

10. a processing unit that acquires a first quantum circuit to be simulated by a plurality of computation nodes that simulate quantum computing, and when storage destinations for state data for each combination of states of a plurality of quantum bits indicated in the first quantum circuit are allocated to the plurality of computation nodes based on quantum bit numbers of quantum bits to be operated by a quantum gate included in the first quantum circuit, detects a first quantum gate that includes a first quantum bit as an operation target, which causes transmission and reception of the state data between the plurality of computation nodes when operated, inserts a second quantum gate before the first quantum gate of the first quantum circuit, which indicates an exchange operation between the state of a second quantum bit to be operated by the first quantum gate and the state of a third quantum bit that can be operated without transmitting and receiving the state data between the plurality of computation nodes, and changes the operation target of the first quantum gate from the second quantum bit to the third quantum bit; and When the quantum bit numbers of the plurality of second quantum bits to be operated by any of the consecutively detected first quantum gates are consecutive, the processing unit determines a final destination of state data to be transmitted when the exchange operations corresponding to each of the consecutively detected first quantum gates are consecutively performed, and inserts, as the second quantum gate, a function that instructs the plurality of computing nodes to transmit the state data to be transmitted to the determined destination. Information processing device.

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