Application Programming Interface for Identifying Feature Versions

Abstract

Apparatus, systems, and techniques for determining one or more memory address values ​​corresponding to one or more computing functions provided by one or more application programming interfaces for facilitating parallel computing. In at least one embodiment, the one or more application programming interfaces for facilitating parallel computing determine the one or more memory address values ​​based at least in part on one or more function calls to one or more functions provided by the one or more application programming interfaces for facilitating parallel computing using one or more parallel processing units, such as a graphics processing unit.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 175,013, filed April 14, 2021, entitled "ENHANCEMENTS TO API FUNCTION ADDRESS QUERIES," the entire contents of which are incorporated herein by reference.

[0002] At least one embodiment relates to processing resources used to execute one or more computing functions provided by one or more application programming interfaces to facilitate parallel computing, for example, the one or more application programming interfaces to facilitate parallel computing determining one or more memory address values ​​based at least in part on one or more function calls to one or more functions provided by the one or more application programming interfaces to facilitate parallel computing according to various novel techniques described herein. [Background technology]

[0003] Programming code is often reused in different computer programs. However, over time, the code may be updated for various reasons, such as performance, hardware compatibility, and / or to take advantage of new hardware features. As a result, reusing code for a particular application can be complicated and potentially error-prone due to the complexity of having various versions of the code available. [Brief explanation of the drawings]

[0004] [Figure 1]A block diagram illustrating one or more application programming interfaces (APIs) or API functions provided by a driver and / or runtime to be implemented as a result of calls by a software program, according to at least one embodiment. [Figure 2A] FIG. 1 is a block diagram illustrating a system loader exposing one or more APIs, according to at least one embodiment. [Figure 2B] FIG. 1 is a block diagram illustrating a system loader that does not expose an API, according to at least one embodiment. [Figure 3] FIG. 1 illustrates a process for querying one or more libraries for one or more memory locations of one or more APIs or API functions, according to at least one embodiment. [Figure 4] FIG. 1 illustrates an exemplary data center, according to at least one embodiment. [Figure 5] FIG. 1 illustrates a processing system according to at least one embodiment. [Figure 6] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 7] FIG. 1 illustrates a system according to at least one embodiment. [Figure 8] FIG. 1 illustrates an exemplary integrated circuit according to at least one embodiment. [Figure 9] FIG. 1 illustrates a computing system according to at least one embodiment. [Figure 10] FIG. 1 illustrates an APU, according to at least one embodiment. [Figure 11] FIG. 1 illustrates a CPU according to at least one embodiment. [Figure 12] FIG. 2 illustrates an exemplary accelerator integration slice, according to at least one embodiment. [Figure 13A] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 13B] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 14A] FIG. 1 illustrates a graphics core according to at least one embodiment. [Figure 14B] FIG. 1 illustrates a GPGPU, according to at least one embodiment. [Figure 15A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 15B] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 15C] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 16] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 17] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 18] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 19] FIG. 1 illustrates a graphics processor core according to at least one embodiment. [Figure 20] FIG. 1 illustrates a PPU, according to at least one embodiment. [Figure 21] FIG. 1 illustrates a GPC, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a streaming multiprocessor according to at least one embodiment. [Figure 23] FIG. 1 illustrates a software stack for a programming platform according to at least one embodiment. [Figure 24] FIG. 24 illustrates a CUDA implementation of the software stack of FIG. 23, according to at least one embodiment. [Figure 25] FIG. 24 illustrates an ROCm implementation of the software stack of FIG. 23, according to at least one embodiment. [Figure 26] FIG. 24 illustrates an OpenCL implementation of the software stack of FIG. 23 according to at least one embodiment. [Figure 27] FIG. 1 illustrates software supported by a programming platform according to at least one embodiment. [Figure 28] FIG. 27 illustrates compiling code for execution on the programming platform of FIGS. 23-26 according to at least one embodiment. [Figure 29] FIG. 27 illustrates in more detail compiling code for execution on the programming platform of FIGS. 23-26 according to at least one embodiment. [Figure 30] FIG. 1 illustrates translating source code prior to compiling the source code, according to at least one embodiment. [Figure 31A] FIG. 1 illustrates a system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment. [Figure 31B] FIG. 31B illustrates a system configured to compile and execute the CUDA source code of FIG. 31A using a CPU and a CUDA-enabled GPU, according to at least one embodiment. [Figure 31C] FIG. 31B illustrates a system configured to compile and execute the CUDA source code of FIG. 31A using a CPU and a non-CUDA-enabled GPU, according to at least one embodiment. [Figure 32] FIG. 31D illustrates an example kernel translated by the CUDA-to-HIP translation tool of FIG. 31C, in accordance with at least one embodiment. [Figure 33] FIG. 31D illustrates the non-CUDA GPU of FIG. 31C in more detail, according to at least one embodiment. [Figure 34]FIG. 34 illustrates how threads of an exemplary CUDA grid are mapped to different compute units of FIG. 33, according to at least one embodiment. [Figure 35] FIG. 1 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] FIG. 1 is a block diagram illustrating one or more application programming interface (API) or API 110 functions 112, 114, 116, 118 provided by a driver and / or runtime 104 to be implemented as a result of calls by a software program 102, according to at least one embodiment.

[0006] In at least one embodiment, API 110 is a set of software instructions that, when executed by a processor, causes one or more processors to perform one or more computational operations. In at least one embodiment, one or more APIs 110 are distributed or otherwise provided as part of one or more software libraries 106, runtime 104, drivers 104, or any other grouping of software and / or executable code described further herein. In at least one embodiment, one or more APIs 110 provide functionality to a user-implemented software program 102. In at least one embodiment, software program 102 is a collection of software code, commands, instructions, or other sequences of text for instructing a computing device to perform one or more computational operations and / or invoke one or more other sets of instructions, such as API 110 or API 110 functions 112, 114, 116, 118, to be executed. In at least one embodiment, the functionality provided by the one or more APIs 110 includes software functions 112, 114, 116, 118, and / or one or more software functions 112, 114, 116, 118 for accelerating the user-implemented software program 102 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs).

[0007] In at least one embodiment, the API 110 is a hardware interface to one or more circuits for performing one or more computational operations. In at least one embodiment, one or more software APIs 110 described herein are implemented as one or more circuits for performing one or more techniques described below in conjunction with Figures 2A, 2B, and 3. In at least one embodiment, the one or more software programs 102 comprise instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described further below in conjunction with Figures 2A, 2B, and 3.

[0008] In at least one embodiment, the user-implemented software program 102 utilizes one or more APIs 110 for facilitating parallel computing, such as the Compute Unified Device Architecture (CUDA), oneAPI, or any other API 110 described further herein. In at least one embodiment, the one or more APIs for facilitating parallel computing provide a set of APIs 110, such as callable functions 112, 114, 116, 118, that individually perform one or more operations related to parallel computing. For example, in one embodiment, the one or more APIs for facilitating parallel computing 110 provide functions 112, 114, 116, 118 for scheduling one or more software instructions and / or operations to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs).

[0009] In at least one embodiment, one or more user-implemented software programs 102 interact with one or more APIs for facilitating parallel computing 110 to perform one or more computing operations using one or more PPUs, such as a GPU. In at least one embodiment, the one or more computing operations using one or more PPUs include at least one or more groups of computing operations to be accelerated, at least in part, by execution by the one or more PPUs. In at least one embodiment, the one or more user-implemented software programs interact with one or more APIs for facilitating parallel computing 110 using a remote interface or a local interface to the one or more APIs.

[0010] In at least one embodiment, the remote interface 108 is a set of one or more software instructions that, when executed, facilitate interaction between one or more user-implemented software programs 102 and one or more software libraries 106 that provide one or more APIs 110 over a communications medium such as a network. In at least one embodiment, the one or more software libraries 106 are sets of instructions that, when executed, provide one or more functions, such as APIs or API functions, to perform one or more computational operations. In at least one embodiment, the libraries comprise one or more function implementations 112, 114, 116, 118 to be provided as a result of one or more calls to the one or more APIs 110 through the interface 108. In at least one embodiment, the one or more function implementations 112, 114, 116, 118 are sets of software instructions that, when executed, implement one or more APIs or API functions, such as computational operations. In at least one embodiment, the remote interface 108 facilitates implementation of one or more APIs by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 106 with one or more APIs 110 are implemented by any other computing host and provide the one or more APIs 110 for facilitating computation by or with one or more user-implemented software programs 102.

[0011] In at least one embodiment, the local interface 108 comprises software instructions that, when executed, facilitate interaction between the software program 102 and one or more APIs 110 or API 110 functions 112, 114, 116, 118 without remote or network communication. In at least one embodiment, the local interface 108 facilitates access by the software program 102 to a library 106 or one or more APIs 110 of a library. In at least one embodiment, the local interface 108 is for use by a user-implemented software program 102, where the user-implemented software program 102 is compiled with one or more software libraries 106 that include one or more APIs 110. In at least one embodiment, the one or more user-implemented software programs 102 are statically compiled with pre-compiled software libraries 106 or uncompiled source code that implements the one or more APIs 110. In at least one embodiment, one or more user-implemented software programs 102 are dynamically compiled, and the one or more user-implemented software programs 102 are linked to one or more pre-compiled software libraries 106 comprising one or more APIs 110 and API 110 functions 112, 114, 116, 118 using a compiler or other linking tool, such as those described further herein.

[0012] In at least one embodiment, a driver or runtime 104 includes a local or remote interface 108 to a library 106 that implements or otherwise provides one or more APIs 110. In at least one embodiment, one or more user-implemented software programs 102 make one or more function calls, such as system calls and / or API function calls, to invoke or otherwise interact with one or more APIs 110 provided by the library 106 of one or more drivers or runtimes 104. In at least one embodiment, one or more user-implemented software programs 102 directly invoke one or more APIs 110 or API 110 functions 112, 114, 116, 118 provided by one or more libraries 106 in one or more drivers or runtimes 104 comprising the one or more APIs 110 by making one or more function calls to a system loader, which then interacts with the one or more drivers or runtimes 104 to invoke the one or more APIs 110, as described below in conjunction with Figures 2A and 2B.

[0013] In at least one embodiment, one or more user-implemented software programs 102 make one or more system calls to a system loader to obtain one or more APIs 110, one or more addresses of API 110 functions 112, 114, 116, 118, and / or implementations of API functions 112, 114, 116, 118 in one or more libraries 106 provided by one or more drivers or runtimes 104. In at least one embodiment, one or more user-implemented software programs 102 invoke one or more APIs 110 or API 110 functions 112, 114, 116, 118 based at least in part on one or more memory addresses or symbols provided by a system loader as a result of a call by the user-implemented software to the system loader to request the addresses of one or more APIs 110 or API 110 functions 112, 114, 116, 118, as described below in conjunction with Figures 2A and 2B. In at least one embodiment, one or more user-implemented software programs 102 directly invoke one or more APIs 110 or API 110 functions 112, 114, 116, 118 based at least in part on one or more memory addresses or symbols provided as a result of one or more function calls to a driver or runtime 104 that includes or otherwise provides a library 106 that implements the API 110 and / or API 110 functions 112, 114, 116, 118.

[0014] In at least one embodiment, one or more drivers or runtimes 104 comprising or otherwise providing an interface 108 to one or more libraries 106 include instructions that, when executed, perform one or more APIs 110, API 110 functions 112, 114, 116, 118, or other computing operations, such as functions to facilitate parallel computing or any other purpose described further herein. In at least one embodiment, one or more APIs 110, API 110 functions 112, 114, 116, 118 implemented or otherwise provided by one or more drivers or runtimes 104 comprising or facilitating interaction with one or more libraries 106 are updated to more recent versions to add functionality, fix software bugs, meet new requirements, or for any other software development purpose. In at least one embodiment, one or more user-developed software programs 102 invoke one or more APIs 110, API 110 functions 112, 114, 116, 118, either directly or by making one or more system calls to a system loader, as described below in conjunction with Figures 2A and 2B. In at least one embodiment, one or more user-developed software programs 102 invoke one or more APIs 110, API 110 functions 112, 114, 116, 118 by calling API 110 or API 110 functions 112, 114, 116, 118 at memory addresses received as a result of one or more API 110 calls to obtain the memory addresses.

[0015] In at least one embodiment, the one or more function pointers are data values ​​that include addresses of particular APIs 110, API 110 functions 112, 114, 116, 118, or other computing functionality implemented or otherwise provided by a driver or runtime 104 that implements one or more APIs 110. In at least one embodiment, one or more software programs 102 receive one or more function pointers corresponding to one or more APIs 110, API 110 functions 112, 114, 116, 118, or other computing functionality implemented or otherwise provided by a driver or runtime 104 as a result of one or more function calls to the interface 108 and / or API 110. In at least one embodiment, to provide one or more pointers to memory addresses corresponding to one or more APIs 110, API 110 functions 112, 114, 116, 118, or other computing functions, the driver and / or runtime 104 provides at least one computing function for retrieving one or more memory addresses corresponding to one or more APIs 110, API 110 functions 112, 114, 116, 118, or other computing functions provided by the driver and / or runtime 104.

[0016] FIG. 2A is a block diagram illustrating a system loader 206 exposing one or more application programming interfaces (APIs) or API functions, as described above in conjunction with FIG. 1 and further described herein, according to at least one embodiment. In at least one embodiment, the system loader 206 is a set of software instructions that, when executed, perform one or more computing operations to facilitate the execution of one or more software programs. In at least one embodiment, as described above in conjunction with FIG. 1 and further described herein, a user-implemented software program 202 is a data value that, when executed, is software instruction that performs some function in accordance with source code implementing the user-implemented software program 102. In at least one embodiment, the user-implemented software program 202 comprises instructions that, when executed, invoke or otherwise cause an API or API function call 204 to be performed. In at least one embodiment, an API or API function call 204 is one or more software instructions that, when executed, invoke one or more computing functions implemented or otherwise provided by one or more APIs, as described above in conjunction with FIG. 1 and further described herein.

[0017] In at least one embodiment, a user-implemented software program 202 implements API function calls 204 or APIs by interacting with a system loader 106. In at least one embodiment, the system loader 206 is a data value that, when executed, is software instructions that implement operating system functions, such as invoking one or more functions provided by a driver that implements one or more APIs to facilitate parallel computing. In at least one embodiment, the system loader 206 interacts with an API driver 210 to obtain 208 the addresses of the API function calls or APIs. In at least one embodiment, the API driver 210 is a data value that, when executed, is software instructions that implement one or more APIs or API functions as a result of one or more computing function calls and / or API calls to the API driver 110.

[0018] 1 and further described herein, system loader 206 receives 208 addresses of one or more APIs or API function calls as a result of making one or more computing function calls, such as getProcAddress, cuGetProcAddress, or any other function, to receive one or more memory addresses corresponding to one or more APIs and / or implementations of one or more function calls provided by one or more APIs. In at least one embodiment, as a result of user-implemented software program 202 making or otherwise invoking an API or API function call directly by making one or more system function calls to system loader 106, the system loader 206 determines one or more memory addresses associated with one or more implementations of APIs or called API functions 204 by the user-implemented software program 202 and begins executing instructions to implement the API or API function at the one or more memory addresses. In at least one embodiment, the user-implemented software program 202 makes one or more API or API function calls 204 regardless of which implementation of the one or more APIs or API functions is to be invoked in the API driver 210 by the system loader 106.

[0019] 2B is a block diagram illustrating a system loader 216 that does not expose APIs or API functions, according to at least one embodiment. In at least one embodiment, rather than using the system loader 216 to invoke APIs or API functions implemented by API driver 120, as described above in conjunction with FIG. 1 and further described herein, a user-implemented software program 212 makes one or more system function calls 214 to the system loader to obtain one or more memory addresses associated with one or more APIs or API function implementations provided by API driver 120, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, the system loader 216 responds to one or more system function calls requesting the one or more memory addresses of the one or more API function calls 214 by requesting 218 the one or more memory addresses of the one or more API function calls 214 from an API driver 220 that implements the one or more APIs or API function calls. In at least one embodiment, user-implemented software program 212 implements one or more API function calls by invoking one or more software instructions stored at one or more memory address locations determined as a result of one or more system function calls 214 to system loader 216, which determines the one or more memory address locations as a result of one or more function calls to API driver 120. In at least one embodiment, user-implemented software program 212 implements one or more APIs or API function calls by invoking one or more software instructions stored at one or more memory address locations determined as a result of one or more function calls directly to API driver 120.

[0020] 1 and further described herein, when requesting one or more memory addresses corresponding to the one or more APIs or API functions, the user-implemented software program 212 indicates to the API one or more versions of one or more software functions, such as other APIs or API functions, implemented or otherwise provided by API driver 220. In at least one embodiment, the user-implemented software program 212 receives one or more memory addresses corresponding to particular versions and / or implementations of one or more APIs or API functions implemented or otherwise provided by API driver 120 as a result of one or more calls to one or more APIs and / or one or more API function calls to a driver or runtime that implements or otherwise provides an API, such as an API to facilitate parallel computing.

[0021] In at least one embodiment, one or more APIs or API functions, such as functions provided by an API to facilitate parallel computing, or any other APIs and / or functions described further herein, are implemented or otherwise provided by a user-mode software driver and / or runtime software library, as described above in conjunction with FIG. 1 and as further described herein. In at least one embodiment, to facilitate determination of one or more memory addresses associated with or corresponding to one or more APIs or API functions, the user-mode software driver and / or runtime software library provides one or more additional functions and / or APIs for retrieving and / or indicating said one or more memory addresses. For example, in one embodiment, a driver implementing an API to facilitate parallel computing, such as CUDA, provides functions and / or APIs for obtaining one or more memory addresses corresponding to one or more implementations of one or more other APIs and / or API functions and / or functions, as follows:

number

[0022] In at least one embodiment, one or more parameters to a software function or API, such as getProcAddress or cuGetProcAddress, include a symbol. In at least one embodiment, a symbol is a data value, including a name, pointer, or other value, that can be used to identify a driver API function. In at least one embodiment, the name or other identifier provided by the symbol parameter is the base name of the driver API function. For example, in an API for facilitating parallel computing, such as CUDA, the symbol value may be "cuMemAlloc," which corresponds to an API or API function implemented by a driver named "cuMemAlloc" that has one or more implementation versions.

[0023] In at least one embodiment, one or more parameters to a software function, such as getProcAddress or cuGetProcAddress, include a function pointer "funcPtr." In at least one embodiment, a function pointer is a data value that includes or points to a memory address of a driver implementation of an API or API function in memory. In at least one embodiment, a software function, such as getProcAddress or cuGetProcAddress, when invoked obtains a function pointer value with a memory address corresponding to a driver-specific implementation of the requested API or API function at a "symbol" having a version corresponding to the particular driver version indicated by "cudaVersion."

[0024] In at least one embodiment, one or more parameters to a software and / or API function, such as getProcAddress or cuGetProcAddress, include a driver version. In at least one embodiment, the driver version is a data value indicating a numeric value for identifying a particular implementation or version of a driver that further implements or otherwise provides the API. In at least one embodiment, a driver version, such as "cudaVersion," corresponding to a particular version of CUDA as described herein, indicates a driver version that includes and / or provides an implementation of the API function indicated by "symbol." In at least one embodiment, an indication of a particular driver version causes getProcAddress or cuGetProcAddress to determine one or more addresses of one or more particular implementations or versions of the API or API function indicated by "symbol" and to set in the function pointer a memory address that is also passed as a parameter to getProcAddress or cuGetProcAddress. In at least one embodiment, the driver version provided as a parameter to getProcAddress or cuGetProcAddress causes a specific implementation of "symbol" to be searched for by the library providing getProcAddress or cuGetProcAddress. In one embodiment, if the driver version is less than or equal to the currently running driver version, getProcAddress or cuGetProcAddress will find the corresponding function or API indicated by "symbol."

[0025] In at least one embodiment, one or more parameters to a software function or API, such as getProcAddress or cuGetProcAddress, include one or more flags. In at least one embodiment, a flag is a data value that indicates one or more options available to the software function or API when retrieving a particular implementation of the API or API function provided by a driver or other software. In at least one embodiment, a parameter that does not include a particular flag causes the function or API, such as getProcAddress or cuGetProcAddress, to retrieve a default and / or nearest implementation of the API or API function indicated by the "symbol" parameter.

[0026] In at least one embodiment, one or more software functions or APIs, such as getProcAddress or cuGetProcAddress, return a value indicating a status corresponding to determining or locating one or more addresses of the API or API function indicated by the "symbol" parameter. In at least one embodiment, one or more software functions, such as getProcAddress or cuGetProcAddress, return a success value, such as CUDA_SUCCESS or any other data value to indicate success, to indicate that an API matching the "symbol" parameter was found and the respective memory address was returned or otherwise set in a function pointer, such as "funcPtr." In at least one embodiment, one or more software functions, such as getProcAddress or cuGetProcAddress, return a value indicating one or more invalid parameters, such as CUDA_ERROR_INVALID_VALUE, to indicate that one or more parameters provided to getProcAddress or cuGetProcAddress are null or otherwise invalid. In at least one embodiment, one or more software functions, such as getProcAddress or cuGetProcAddress, return a value indicating that a particular API function indicated by a "symbol" parameter could not be found or that a memory address corresponding to a particular API or API function indicated by the "symbol" parameter could not be located or calculated. In at least one embodiment, if the API or API function indicated by the "symbol" parameter could not be located, the function, such as getProcAddress or cuGetProcAddress, returns a value indicating that the API function could not be located, such as CUDA_ERROR_NOT_FOUND or any other value to indicate failure.

[0027] In at least one embodiment, a runtime library implementing an API or API function provides functionality for obtaining one or more memory addresses corresponding to one or more implementations or versions of one or more APIs or API functions, as described above in conjunction with FIG. 1 and further described herein, as follows:

number

[0028] In at least one embodiment, one or more parameters to an API, API function, or other software function, such as getDriverEntryPoint or cuGetDriverEntryPoint, include a symbol. In at least one embodiment, the symbol is a data value, such as a pointer, that includes the name of a driver-implemented API function for retrieving or determining one or more memory addresses corresponding to the symbol. In at least one embodiment, the name provided by the symbol parameter is the base name of the driver-implemented API function. For example, in an API for facilitating parallel computing, such as CUDA, the symbol value may be "cuMemAlloc," which corresponds to an API function implemented by a driver named "cuMemAlloc" that has one or more driver-version-specific implementations. In at least one embodiment, the API, API function, or software function, such as getDriverEntryPoint or cuGetDriverEntryPoint, determines a memory address or function pointer that corresponds to the most recent driver implementation of the API or API function indicated by the "symbol" parameter.

[0029] In at least one embodiment, one or more parameters to an API, API function, or software function, such as getDriverEntryPoint or cuGetDriverEntryPoint, include a function pointer "funcPtr." In at least one embodiment, the function pointer is a data value that includes a memory address that points to a current or most recent driver implementation of the API or API function, such as those described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, the API, API function, or software function, such as getDriverEntryPoint or cuGetDriverEntryPoint, sets the function pointer value with a memory address that corresponds to a current or most recent driver-specific implementation of the requested API or API function at a "symbol" having a version that corresponds to the current or most recent driver version.

[0030] In at least one embodiment, one or more parameters to an API, API function, or software function, such as getDriverEntryPoint or cuGetDriverEntryPoint, include one or more flags. In at least one embodiment, the flags passed as parameters to getDriverEntryPoint or cuGetDriverEntryPoint are data values ​​that indicate one or more options to consider when searching for a particular implementation of the API or API function in a driver that implements the API, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, a parameter that does not include a particular flag causes the API or API function, such as getDriverEntryPoint or cuGetDriverEntryPoint, to search for a default and / or nearest driver implementation of the API function indicated by the “symbol” parameter.

[0031] In at least one embodiment, one or more APIs, API functions, or software functions, such as getDriverEntryPoint or cuGetDriverEntryPoint, return a value indicating a status corresponding to determining or locating one or more addresses in the driver that correspond to the API or API function implementation indicated by the "symbol" parameter passed to getDriverEntryPoint or cuGetDriverEntryPoint, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, one or more APIs, API functions, or software functions, such as getDriverEntryPoint or cuGetDriverEntryPoint, return a success value, such as cudaSuccess, corresponding to cuGetDriverEntryPoint, to indicate that an API or API function implementation matching the "symbol" parameter was found and the respective memory address was returned or otherwise set in a function pointer, such as "funcPtr." In at least one embodiment, one or more APIs, API functions, or software functions, such as getDriverEntryPoint or cuGetDriverEntryPoint, return a value indicating one or more invalid parameters, such as cudaErrorInvalidValue corresponding to cuGetDriverEntryPoint, to indicate that one or more parameters provided to getDriverEntryPoint or cuGetDriverEntryPoint are null or otherwise invalid. In at least one embodiment, one or more software functions, such as getDriverEntryPoint or cuGetDriverEntryPoint, return a value indicating that a particular API or API function indicated by a "symbol" parameter could not be found or that a memory address corresponding to a particular driver-implemented API or API function indicated by the "symbol" parameter could not be located or calculated.In at least one embodiment, as described above in conjunction with FIG. 1 and further described herein, if the API or API function indicated by the “symbol” parameter could not be located or is invalid or otherwise unavailable in the current driver implementation of the API, the API or API function, such as getDriverEntryPoint or cuGetDriverEntryPoint, returns a value indicating that the API or API function could not be located, such as cudaErrorNotFound corresponding to cuGetDriverEntryPoint.

[0032] 1 and further described herein, to determine memory addresses corresponding to particular driver implementations of one or more versions of one or more APIs or API functions, a driver maintains a table of driver API or API function entries, where each entry consists of a set of driver functions including a default implementation of the driver function, a versioned implementation of the driver function, and specialized variants of the driver function. Each driver function, in one embodiment, has corresponding metadata, such as version information including a driver version indicating whether the particular API or API function was ever brought forward, removal information indicating the driver version when the particular API or API function was removed, and a pointer to one or more memory addresses corresponding to the particular implementation of the API or API function.

[0033] In at least one embodiment, when one or more calls are made to a driver API or API function, such as getProcAddress or cuGetProcAddress, the driver searches for the requested symbol in the proc table, as described above, and returns the address if a match is found. In at least one embodiment, the driver implements a hash table and pre-computes all hashes based at least in part on the symbol name, memory address, and / or other metadata associated with each API or API function corresponding to each symbol, as described above.

[0034] As described above, in at least one embodiment, a driver API or API function, such as getProcAddress or cuGetProcAddress, accepts a flag as a parameter or argument, which may indicate a particular variant of the driver-implemented API or API function. In at least one embodiment, an exemplary enumeration indicating one or more flags to be provided as a parameter or argument to getProcAddress or cuGetProcAddress is as follows:

number

[0035] In at least one embodiment, a flag value of GET_PROC_ADDRESS_DEFAULT or CU_GET_PROC_ADDRESS_DEFAULT indicates that the default driver implementation of a particular API or API function should be retrieved via getProcAddress or cuGetProcAddress, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, GET_PROC_ADDRESS_DEFAULT or CU_GET_PROC_ADDRESS_DEFAULT is equivalent to passing GET_PROC_ADDRESS_LEGACY_STREAM or CU_GET_PROC_ADDRESS_LEGACY_STREAM when API_PER_THREAD_DEFAULT_STREAM or CUDA_API_PER_THREAD_DEFAULT_STREAM is not set, and is equivalent to passing GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM or CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM when API_PER_THREAD_DEFAULT_STREAM or CUDA_API_PER_THREAD_DEFAULT_STREAM is set. In at least one embodiment, GET_PROC_ADDRESS_LEGACY_STREAM or CU_GET_PROC_ADDRESS_LEGACY_STREAM causes getProcAddress or cuGetProcAddress to search for all symbols that match the requested symbol passed in or otherwise provided as an argument.In at least one embodiment, GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM or CU_GET_PROC_ADDRESS_PER_THREAD_DEFAULT_STREAM causes getProcAddress or cuGetProcAddress to search for all symbols that match the symbol passed to or otherwise provided as an argument to getProcAddress or cuGetProcAddress containing all ptds versions that match the requested symbol.

[0036] In at least one embodiment, a driver may implement or otherwise provide one or more inline functions for modifying flag parameters or arguments to conform to a particular behavior for a given implementation of the driver. In at least one embodiment, a driver may implement or otherwise provide a list of publicly exposed type definitions or typedefs in various header files available to one or more user-implemented software programs for each available driver version or implementation version that corresponds to various APIs or API functions of an API for facilitating parallel computing, such as CUDA, or any other API described further herein.

[0037] As described above, in at least one embodiment, a runtime API or API function, such as driverGetEntryPoint or cudaDriverGetEntryPoint, accepts a flag as a parameter or argument, which may indicate a particular variation of the driver-implemented API or API function, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, one or more flags may be defined as follows:

number

[0038] In at least one embodiment, a flag value of enableDefault or cudaEnableDefault indicates that a default driver implementation for a particular API or API function should be retrieved by a runtime API or API function, such as driverGetEntryPoint or cudaDriverGetEntryPoint. In at least one embodiment, enableDefault or cudaEnableDefault is equivalent to passing enableLegacyStream or cudaEnableLegacyStream when API_PER_THREAD_DEFAULT_STREAM or CUDA_API_PER_THREAD_DEFAULT_STREAM is not set, and is equivalent to passing enablePerThreadDefaultStream or cudaEnablePerThreadDefaultStream when API_PER_THREAD_DEFAULT_STREAM or CUDA_API_PER_THREAD_DEFAULT_STREAM is set. In at least one embodiment, enableLegacyStream or cudaEnableLegacyStream causes runtime functions, such as driverGetEntryPoint or cudaDriverGetEntryPoint, to search for all symbols that match the requested symbols passed as parameters or arguments to driverGetEntryPoint or cudaDriverGetEntryPoint, excluding the corresponding ptds version. In at least one embodiment, enablePerThreadDefaultStream or cudaEnablePerThreadDefaultStream causes driverGetEntryPoint or cudaDriverGetEntryPoint to search for all symbols that match the requested symbols passed as parameters or other arguments, including one or more ptds versions.In at least one embodiment, if a function's ptds version is indicated by a symbolic parameter or argument to driverGetEntryPoint or cudaDriverGetEntryPoint, the default version of that function implemented by the current driver is returned or set in the function pointer parameter. In at least one embodiment, the runtime function driverGetEntryPoint or cudaDriverGetEntryPoint also returns the ptds version of a particular driver-implemented API or API function to support per-thread stream overloads.

[0039] In at least one embodiment, a runtime implementing an API or API function, such as driverGetEntryPoint or cudaDriverGetEntryPoint, dynamically loads all driver symbols it needs during initialization. In at least one embodiment, a runtime implementing an API or API function, such as driverGetEntryPoint or cudaDriverGetEntryPoint, utilizes one or more driver functions, such as getProcAddress or cuGetProcAddress, to determine one or more memory addresses corresponding to one or more driver symbols. In at least one embodiment, a runtime implementing an API or API function, such as driverGetEntryPoint or cudaDriverGetEntryPoint, utilizes one or more hash tables as described above in conjunction with a driver implementing one or more API functions, such as API functions to facilitate parallel computing, or any other API functions as part of any API described further herein.

[0040] In at least one embodiment, a driver or runtime that implements one or more functions for determining one or more addresses associated with one or more APIs or one or more implementations of API functions, such as functions provided by an API for facilitating parallel computing or any other API described further herein, may embed versioning information (e.g., "_v1," "_v2," etc.) in the symbol names themselves for compatible driver versions, rather than specifying a separate argument in the driver-specific implementation. In at least one embodiment, if a driver embeds versioning information, the driver does not need to maintain a map of driver functions and other metadata as described above. In contrast, in one embodiment, the driver can dynamically load each symbol and obtain its address.

[0041] In at least one embodiment, instead of symbols being passed as parameters to a runtime or driver as described above, an ordinal value may be provided as an argument. In at least one embodiment, the ordinal value is a data value that indicates a particular version or any other information about an API or API function to be searched by one or more drivers or runtime functions to determine a memory address. In at least one embodiment, when an ordinal value is specified, a direct lookup in a linear table may be performed by the runtime or driver instead of utilizing a hash table as described above.

[0042] In at least one embodiment, a runtime or driver that implements one or more APIs or API functions may accept one or more device identifiers as arguments or parameters, as described above in conjunction with FIG. 1 and further described herein. In at least one embodiment, the device identifiers are data values ​​that indicate one or more devices and identification values ​​or handles that correspond to the one or more devices. In at least one embodiment, the device identifiers enable retrieval of a particular driver that corresponds to a particular device that may implement one or more versions of one or more APIs or API functions that correspond to an API that facilitates parallel computing, or any other API described further herein.

[0043] FIG. 3 illustrates a process 300 for querying one or more libraries for one or more memory locations that store application programming interfaces (APIs) or API function implementations or instructions that, when executed, implement one or more versions of one or more APIs or API functions, according to at least one embodiment. In at least one embodiment, process 300 begins when a driver or runtime, as described above in conjunction with FIGS. 1, 2A, and 2B, receives at 304 one or more identifier data values ​​indicating one or more properties of the API or API function to be located, as described above in conjunction with FIGS. 2A and 2B. In at least one embodiment, the identifier includes a specific function name and / or version identifier. In at least one embodiment, the identifier includes information to indicate one or more APIs or API functions or instructions in one or more libraries that, when executed, implement the one or more APIs or API functions, as described above in conjunction with FIG. 1.

[0044] In at least one embodiment, once a driver or runtime receives the identifier at 304, as described above, the driver or runtime locates the API or API function in a library that comprises instructions that, when executed, implement the API or API function at 306. In at least one embodiment, the driver or runtime locates the API or API function in a library based at least in part on one or more data values ​​indicated to the driver or runtime to identify the API or API function, such as the data values ​​described above in conjunction with Figures 2A and 2B.

[0045] In at least one embodiment, if the driver or runtime locates an implementation of an API or API function, such as software instructions that, when executed, implement the API or API function, in 308, the driver or runtime returns a pointer to the implementation of the API or API function in 310. In at least one embodiment, the pointer is a data value that includes the address of a first software instruction in a set of software instructions that, when executed, implements the API or API function.

[0046] In at least one embodiment, if the driver or runtime, when executed at 308, does not locate an implementation of the API or API function, such as software instructions that implement the API or API function, the driver or runtime returns a null or nil value at 312. In at least one embodiment, a null or nil value is any data value that indicates that the driver or runtime failed to locate an implementation of the API or API function. In at least one embodiment, once the driver or runtime either returns a pointer at 310 or a null or nil value at 312, the process 300 for querying one or more libraries for one or more memory locations that store an API or API function implementation ends at 314.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0048] Data Center 4 illustrates an exemplary data center 400, according to at least one embodiment. In at least one embodiment, data center 400 includes, but is not limited to, a data center infrastructure layer 410, a framework layer 420, a software layer 430, and an application layer 440. In at least one embodiment, software layer 430 and / or application layer 440 comprise, at least in part, instructions for implementing the various components and / or operations described above in conjunction with FIGS. 1-3.

[0049] In at least one embodiment, as shown in FIG. 4, data center infrastructure layer 410 may include a resource orchestrator 412, grouped computing resources 414, and node computing resources (“node CR”) 416(1) through 416(N), where “N” represents any positive integer. In at least one embodiment, nodes CR 416(1)-416(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR 416(1)-416(N) may be a server having one or more of the computing resources described above.

[0050] In at least one embodiment, grouped computing resources 414 may include distinct groupings of node CRs housed within one or more racks (not shown), or many racks housed in a data center at various geographic locations (also not shown). The distinct groupings of node CRs within grouped computing resources 414 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0051] In at least one embodiment, resource orchestrator 412 may configure or otherwise control one or more nodes CR 416(1)-416(N) and / or grouped computing resources 414. In at least one embodiment, resource orchestrator 412 may include a software design infrastructure (“SDI”) management entity for data center 400. In at least one embodiment, resource orchestrator 412 may include hardware, software, or some combination thereof.

[0052] 4 , framework layer 420 includes, but is not limited to, job scheduler 432, configuration manager 434, resource manager 436, and distributed file system 438. In at least one embodiment, framework layer 420 may include a framework for supporting software 452 in software layer 430 and / or one or more applications 442 in application layer 440. In at least one embodiment, software 452 or application(s) 442 may include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 420 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which may utilize distributed file system 438 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 432 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 400. In at least one embodiment, configuration manager 434 may be capable of configuring different tiers, such as software tier 430 and framework tier 420, which includes Spark and distributed file system 438 to support large-scale data processing. In at least one embodiment, resource manager 436 may be capable of managing clustered or grouped computing resources mapped or allocated to support distributed file system 438 and job scheduler 432. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 414 in data center infrastructure tier 410.In at least one embodiment, resource manager 436 may manage these mapped or allocated computing resources in coordination with resource orchestrator 412.

[0053] In at least one embodiment, software 452 included in software layer 430 may include software used by nodes CR 416(1)-416(N), grouped computing resources 414, and / or at least a portion of distributed file system 438 of framework layer 420. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0054] In at least one embodiment, the application(s) 442 included in the application layer 440 may include one or more types of applications used by the nodes CR 416(1)-416(N), the grouped computing resources 414, and / or at least a portion of the distributed file system 438 of the framework layer 420. At least one or more types of applications may include, but are not limited to, CUDA applications.

[0055] In at least one embodiment, any of configuration manager 434, resource manager 436, and resource orchestrator 412 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve data center operators of data center 400 from determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0056] Computer-Based Systems The following diagram describes an exemplary computer-based system that may be used to implement at least one embodiment, but is not limited to the embodiment.

[0057] FIG. 5 illustrates a processing system 500 according to at least one embodiment. In at least one embodiment, the processing system 500 includes one or more processors 502 and one or more graphics processors 508 and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 502 or processor cores 507. In at least one embodiment, the processing system 500 is a processing platform integrated into a system-on-a-chip ("SoC") integrated circuit for use in a mobile, handheld, or embedded device. In at least one embodiment, the processing system 500 is adapted, at least in part, to implement the various components and / or operations described above in conjunction with FIGS. 1-3.

[0058] In at least one embodiment, processing system 500 may include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 500 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 500 may also include, be coupled to, or be incorporated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 500 is a television or set-top box device having one or more processors 502 and a graphical interface generated by one or more graphics processors 508.

[0059] In at least one embodiment, the one or more processors 502 each include one or more processor cores 507 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 507 is configured to process a particular instruction set 509. In at least one embodiment, the instruction set 509 may facilitate computing via Complex Instruction Set Computing ("CISC"), Reduced Instruction Set Computing ("RISC"), or Very Long Instruction Word ("VLIW"). In at least one embodiment, the processor cores 507 may each process a different instruction set 509, and the instruction set 509 may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 507 may also include other processing devices, such as a digital signal processor ("DSP").

[0060] In at least one embodiment, processor 502 includes cache memory (“cache”) 504. In at least one embodiment, processor 502 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 502. In at least one embodiment, processor 502 also uses an external cache (e.g., a level 3 (“L3”) cache or a last level cache (“LLC”)) (not shown), which may be shared among processor cores 507 using known cache coherency techniques. In at least one embodiment, processor 502 additionally includes a register file 506, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 506 may include general-purpose registers or other registers.

[0061] In at least one embodiment, one or more processors 502 are coupled to one or more interface buses 510 for transmitting communication signals, such as address, data, or control signals, between the processors 502 and other components in the processing system 500. In at least one embodiment, the interface bus 510 in one embodiment may be a processor bus, such as a version of a Direct Media Interface ("DMI") bus. In at least one embodiment, the interface bus 510 is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., Peripheral Component Interconnect, PCI Express ("PCIe")), a memory bus, or other types of interface buses. In at least one embodiment, the processor(s) 502 include an integrated memory controller 516 and a platform controller hub 530. In at least one embodiment, memory controller 516 facilitates communication between memory devices and other components of processing system 500, and platform controller hub (“PCH”) 530 provides connection to I / O devices via a local input / output (“I / O”) bus.

[0062] In at least one embodiment, memory device 520 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase-change memory device, or any other memory device having suitable performance to serve as processor memory. In at least one embodiment, memory device 520 may operate as system memory for processing system 500 to store data 522 and instructions 521 for use when one or more processors 502 execute applications or processes. In at least one embodiment, memory controller 516 also couples to an optional external graphics processor 512, which may communicate with one or more graphics processors 508 in processor 502 to perform graphics and media operations. In at least one embodiment, a display device 511 may be connected to processor(s) 502. In at least one embodiment, display device 511 may include one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 511 may include a head mounted display ("HMD"), such as a stereoscopic display device for use in virtual reality ("VR") or augmented reality ("AR") applications.

[0063] In at least one embodiment, platform controller hub 530 allows peripherals to connect to memory device 520 and processor 502 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 546, a network controller 534, a firmware interface 528, a wireless transceiver 526, a touch sensor 525, and a data storage device 524 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 524 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, touch sensor 525 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 526 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution ("LTE") transceiver. In at least one embodiment, firmware interface 528 enables communication with system firmware and may be, for example, a unified extensible firmware interface ("UEFI"). In at least one embodiment, network controller 534 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 510. In at least one embodiment, audio controller 546 is a multi-channel high-definition audio controller.In at least one embodiment, processing system 500 includes an optional legacy I / O controller 540 for coupling legacy (e.g., Personal System 2 (“PS / 2”)) devices to processing system 500. In at least one embodiment, platform controller hub 530 can also connect to one or more Universal Serial Bus (“USB”) controller 542-connected input devices, such as a keyboard and mouse 543 combination, a camera 544, or other USB input devices.

[0064] In at least one embodiment, instances of memory controller 516 and platform controller hub 530 may be embedded in a discreet external graphics processor, such as external graphics processor 512. In at least one embodiment, platform controller hub 530 and / or memory controller 516 may be external to one or more processors 502. For example, in at least one embodiment, processing system 500 may include external memory controller 516 and platform controller hub 530, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with processor(s) 502.

[0065] FIG. 6 illustrates a computer system 600 according to at least one embodiment. In at least one embodiment, computer system 600 may be a system, a SOC, or some combination with interconnected devices and components. In at least one embodiment, computer system 600 is formed with a processor 602, which may include an execution unit for executing instructions. In at least one embodiment, computer system 600 may include components, such as, but not limited to, processor 602, to employ an execution unit that includes logic for implementing algorithms for processing data. In at least one embodiment, computer system 600 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 600 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. In at least one embodiment, processing system 600 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0066] In at least one embodiment, computer system 600 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of performing one or more instructions.

[0067] In at least one embodiment, computer system 600 may include, but is not limited to, a processor 602, which may include one or more execution units 608 that may be configured to execute, but is not limited to, a Compute Unified Device Architecture ("CUDA") (CUDA® is developed by NVIDIA Corporation of Santa Clara, California) programs. In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 600 is a single-processor desktop or server system. In at least one embodiment, computer system 600 may be a multiprocessor system. In at least one embodiment, processor 602 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, processor 602 may be coupled to a processor bus 610 that may transmit data signals between processor 602 and other components in computer system 600.

[0068] In at least one embodiment, processor 602 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 604. In at least one embodiment, processor 602 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 602. In at least one embodiment, processor 602 may also include a combination of both internal and external cache. In at least one embodiment, register file 606 may store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0069] In at least one embodiment, an execution unit 608, including logic for performing integer and floating-point operations, may also be present in processor 602. Processor 602 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for some macroinstructions. In at least one embodiment, execution unit 608 may include logic for dealing with a packed instruction set 609. In at least one embodiment, by including packed instruction set 609, along with associated circuitry for executing the instructions, in the instruction set of general-purpose processor 602, operations used by many multimedia applications may be performed using packed data in general-purpose processor 602. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0070] In at least one embodiment, execution unit 608 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, computer system 600 may include, but is not limited to, memory 620. In at least one embodiment, memory 620 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. Memory 620 may store instruction(s) 619 and / or data 621 represented by data signals that may be executed by processor 602.

[0071] In at least one embodiment, a system logic chip may be coupled to processor bus 610 and memory 620. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 616, and processor 602 may communicate with MCH 616 via processor bus 610. In at least one embodiment, MCH 616 may provide a high-bandwidth memory path 618 to memory 620 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 616 may direct data signals between processor 602, memory 620, and other components in computer system 600, and may bridge data signals between processor bus 610, memory 620, and system I / O 622. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 616 may be coupled to memory 620 through a high-bandwidth memory path 618, and the graphics / video card 612 may be coupled to the MCH 616 via an Accelerated Graphics Port (“AGP”) interconnect 614.

[0072] In at least one embodiment, computer system 600 may use system I / O 622, a proprietary hub interface bus, to couple MCH 616 to I / O controller hub (“ICH”) 630. In at least one embodiment, ICH 630 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 620, a chipset, and processor 602. Examples may include, but are not limited to, an audio controller 629, a firmware hub (“flash BIOS”) 628, a wireless transceiver 626, data storage 624, a legacy I / O controller 623 including a user input interface 625 and a keyboard interface, a serial expansion port 627 such as USB, and a network controller 634. Data storage 624 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0073] In at least one embodiment, FIG. 6 illustrates a system including interconnected hardware devices or "chips." In at least one embodiment, FIG. 6 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 6 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 600 are interconnected using a Compute Express Link ("CXL") interconnect.

[0074] 7 illustrates a system 700, according to at least one embodiment. In at least one embodiment, system 700 is an electronic device utilizing processor 710. In at least one embodiment, system 700 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device. In at least one embodiment, system 700 comprises and / or is adapted to implement, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0075] In at least one embodiment, system 700 may include, without limitation, a processor 710 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 27 may be coupled using a bus or interface, such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, USB (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 7 illustrates a system including interconnected hardware devices or “chips.” In at least one embodiment, FIG. 7 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 7 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 7 are interconnected using a CXL interconnect.

[0076] In at least one embodiment, FIG. 7 includes a display 724, a touch screen 725, a touch pad 730, a Near Field Communication ("NFC") unit 745, a sensor hub 740, a thermal sensor 746, an Express Chipset ("EC") 735, a Trusted Platform Module ("TPM") 738, a BIOS / firmware / flash memory ("BIOS,FW flash") 722, a DSP 760, a Solid State Disk ("SSD") or Hard Disk Drive ("HDD") 720, a Wireless Local Area Network ("WLAN") unit 750, a Bluetooth unit 752, a Wireless Wide Area Network ("WWAN") unit 756, a Global Positioning System ("GPS") unit 758, a Bluetooth module 752, a Bluetooth 754 module 756, a Bluetooth module 754 ... The memory may include a USB 3.0 Camera ("USB 3.0 Camera") 754, a USB 3.0 Camera, or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 715, implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0077] In at least one embodiment, other components may be communicatively coupled to the processor 710 through the components described above. In at least one embodiment, an accelerometer 741, an ambient light sensor (“ALS”) 742, a compass 743, and a gyroscope 744 may be communicatively coupled to the sensor hub 740. In at least one embodiment, a thermal sensor 739, a fan 737, a keyboard 736, and a touchpad 730 may be communicatively coupled to the EC 735. In at least one embodiment, a speaker 763, headphones 764, and a microphone (“mic”) 765 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 762, which may be communicatively coupled to the DSP 760. In at least one embodiment, the audio unit 762 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 757 can be communicatively coupled to the WWAN unit 756. In at least one embodiment, components such as the WLAN unit 750 and Bluetooth unit 752, and the WWAN unit 756 can be implemented in a Next Generation Form Factor (“NGFF”).

[0078] 8 illustrates an exemplary integrated circuit 800, according to at least one embodiment. In at least one embodiment, the exemplary integrated circuit 800 is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 800 includes one or more application processors 805 (e.g., CPU, DPU), at least one graphics processor 810, and may additionally include an image processor 815 and / or a video processor 820, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 800 includes a USB controller 825, a UART controller 830, an SPI / SDIO controller 835, and an I / O controller 840.2 S / I 2 8. The integrated circuit 800 may include peripheral or bus logic including a C controller 840. In at least one embodiment, the integrated circuit 800 may include a display device 845 coupled to one or more of a high-definition multimedia interface ("HDMI") controller 850 and a mobile industry processor interface ("MIPI") display interface 855. In at least one embodiment, storage may be provided by a flash memory subsystem 860 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 865 for access to an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 870. In at least one embodiment, the example integrated circuit 800 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0079] FIG. 9 illustrates a computing system 900 according to at least one embodiment. In at least one embodiment, the computing system 900 includes a processing subsystem 901 having one or more processors 902 and system memory 904 that communicate via interconnect paths that may include a memory hub 905. In at least one embodiment, the memory hub 905 may be a separate component within a chipset component or may be incorporated within the one or more processors 902. In at least one embodiment, the memory hub 905 couples to an I / O subsystem 911 via a communication link 906. In at least one embodiment, the I / O subsystem 911 includes an I / O hub 907 that may enable the computing system 900 to receive input from one or more input devices 908. In at least one embodiment, the I / O hub 907 may enable a display controller, which may be included in one or more processors 902, to provide output to one or more display devices 910A. In at least one embodiment, one or more display devices 910A coupled with I / O hub 907 may include a local, internal, or embedded display device. In at least one embodiment, computing system 900 comprises and / or is adapted to implement, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0080] In at least one embodiment, the processing subsystem 901 includes one or more parallel processors 912 coupled to a memory hub 905 via a bus or other communication link 913. In at least one embodiment, the communication link 913 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or fabric. In at least one embodiment, the one or more parallel processors 912 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many-integrated-core processor. In at least one embodiment, the one or more parallel processors 912 form a graphics processing subsystem that can output pixels to one of one or more display devices 910A coupled via the I / O hub 907. In at least one embodiment, the one or more parallel processors 912 also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 910B.

[0081] In at least one embodiment, a system storage unit 914 may connect to an I / O hub 907 to provide a storage mechanism for the computing system 900. In at least one embodiment, an I / O switch 916 may be used to provide an interface mechanism to enable connections between the I / O hub 907 and other components, such as a network adapter 918 and / or a wireless network adapter 919, which may be embedded in the platform, as well as various other devices that may be added via one or more add-in devices 920. In at least one embodiment, the network adapter 918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 919 may include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more wireless radios.

[0082] In at least one embodiment, computing system 900 may include other components not expressly shown that may also be connected to I / O hub 907, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in FIG. 9 may be implemented using any suitable protocol, such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interface and / or protocol(s), or interconnection protocol, such as an NVLink high-speed interconnect.

[0083] In at least one embodiment, one or more parallel processors 912 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, to form a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processors 912 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 912, memory hub 905, processor(s) 902, and I / O hub 907 may be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system 900 may be integrated into a single package to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of the components of computing system 900 may be incorporated into a multi-chip module ("MCM"), which may be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 911 and display device 910B are omitted from computing system 900.

[0084] Processing System The following figures describe exemplary processing systems that may be used to implement, but are not limited to, at least one embodiment.

[0085] FIG. 10 illustrates an accelerated processing unit ("APU") 1000 according to at least one embodiment. In at least one embodiment, the APU 1000 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 1000 may be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1000 includes, but is not limited to, a core complex 1010, a graphics complex 1040, a fabric 1060, an I / O interface 1070, a memory controller 1080, a display controller 1092, and a multimedia engine 1094. In at least one embodiment, the APU 1000 may include, but is not limited to, any number of core complexes 1010, any number of graphics complexes 1050, any number of display controllers 1092, and any number of multimedia engines 1094 in any combination. For purposes of explanation, multiple instances of similar objects are indicated herein with a reference numeral identifying the object and, where necessary, a parenthetical number identifying the instance. In at least one embodiment, APU 1000 comprises and / or is adapted to implement, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0086] In at least one embodiment, core complex 1010 is a CPU, graphics complex 1040 is a GPU, and APU 1000 is a processing unit incorporating 1010 and 1040 on a single chip, without limitation. In at least one embodiment, some tasks may be assigned to core complex 1010 and other tasks may be assigned to graphics complex 1040. In at least one embodiment, core complex 1010 is configured to execute main control software associated with APU 1000, such as an operating system. In at least one embodiment, core complex 1010 is the master processor of APU 1000, controlling and coordinating the operation of the other processors. In at least one embodiment, core complex 1010 issues commands that control the operation of graphics complex 1040. In at least one embodiment, core complex 1010 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1040 may be configured to execute device executable code derived from CUDA source code.

[0087] In at least one embodiment, core complex 1010 includes, but is not limited to, cores 1020(1)-1020(4) and an L3 cache 1030. In at least one embodiment, core complex 1010 may include, but is not limited to, any number of cores 1020 and any number and type of caches, in any combination. In at least one embodiment, cores 1020 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1020 is a CPU core.

[0088] In at least one embodiment, each core 1020 includes, but is not limited to, a fetch / decode unit 1022, an integer execution engine 1024, a floating-point execution engine 1026, and an L2 cache 1028. In at least one embodiment, the fetch / decode unit 1022 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1024 and the floating-point execution engine 1026. In at least one embodiment, the fetch / decode unit 1022 can simultaneously dispatch one micro-instruction to the integer execution engine 1024 and another micro-instruction to the floating-point execution engine 1026. In at least one embodiment, the integer execution engine 1024 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1026 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1022 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1024 and the floating-point execution engine 1026 .

[0089] In at least one embodiment, each core 1020(i), where i is an integer representing a particular instance of core 1020, may access an L2 cache 1028(i) included in core 1020(i). In at least one embodiment, each core 1020 included in a core complex 1010(j), where j is an integer representing a particular instance of core complex 1010, is connected to the other cores 1020 included in core complex 1010(j) via an L3 cache 1030(j) included in core complex 1010(j). In at least one embodiment, a core 1020 included in a core complex 1010(j), where j is an integer representing a particular instance of core complex 1010, may access all of the L3 caches 1030(j) included in core complex 1010(j). In at least one embodiment, L3 cache 1030 may include, without limitation, any number of slices.

[0090] In at least one embodiment, the graphics complex 1040 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the graphics complex 1040 is configured to execute graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, the graphics complex 1040 is configured to execute non-graphics related operations. In at least one embodiment, the graphics complex 1040 is configured to execute both graphics related and non-graphics related operations.

[0091] In at least one embodiment, the graphics complex 1040 includes, but is not limited to, any number of compute units 1050 and an L2 cache 1042. In at least one embodiment, the compute units 1050 share the L2 cache 1042. In at least one embodiment, the L2 cache 1042 is partitioned. In at least one embodiment, the graphics complex 1040 includes, but is not limited to, any number of compute units 1050 and any number and type of cache (including zero). In at least one embodiment, the graphics complex 1040 includes, but is not limited to, any amount of dedicated graphics hardware.

[0092] In at least one embodiment, each compute unit 1050 includes, but is not limited to, any number of SIMD units 1052 and shared memory 1054. In at least one embodiment, each SIMD unit 1052 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1050 may execute any number of thread blocks, with each thread block executing on a single compute unit 1050. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1052 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 1054.

[0093] In at least one embodiment, fabric 1060 is a system interconnect that facilitates data and control transmission across core complex 1010, graphics complex 1040, I / O interface 1070, memory controller 1080, display controller 1092, and multimedia engine 1094. In at least one embodiment, APU 1000 may include any quantity and type of system interconnect in addition to or instead of fabric 1060, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to APU 1000. In at least one embodiment, I / O interface 1070 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1070. In at least one embodiment, peripheral devices coupled to I / O interface 1070 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0094] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display ("LCD") devices. In at least one embodiment, multimedia engine 1094 includes any quantity and type of circuitry related to multimedia, such as, but not limited to, a video decoder, a video encoder, and an image signal processor. In at least one embodiment, memory controller 1080 facilitates data transfer between APU 1000 and unified system memory 1090. In at least one embodiment, core complex 1010 and graphics complex 1040 share unified system memory 1090.

[0095] In at least one embodiment, the APU 1000 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1080 and memory devices (e.g., shared memory 1054) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 1000 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1128, L3 cache 1030, and L2 cache 1042), each of which may be private to any number of components (e.g., core 1020, core complex 1010, SIMD unit 1052, compute unit 1050, and graphics complex 1040) or shared among any number of components.

[0096] FIG. 11 illustrates a CPU 1100 according to at least one embodiment. In at least one embodiment, the CPU 1100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 1100 may be configured to execute application programs. In at least one embodiment, the CPU 1100 may be configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 1100 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1100 may be configured to execute host executable code derived from CUDA source code, and the external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1100 includes, but is not limited to, any number of core complexes 1110, a fabric 1160, an I / O interface 1170, and a memory controller 1180. In at least one embodiment, CPU 1100 comprises and / or is responsible, at least in part, for implementing the various components and / or operations described above in conjunction with FIGS. 1-3.

[0097] In at least one embodiment, core complex 1110 includes, but is not limited to, cores 1120(1)-1120(4) and an L3 cache 1130. In at least one embodiment, core complex 1110 may include, but is not limited to, any number of cores 1120 and any number and type of caches in any combination. In at least one embodiment, cores 1120 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1120 is a CPU core.

[0098] In at least one embodiment, each core 1120 includes, but is not limited to, a fetch / decode unit 1122, an integer execution engine 1124, a floating-point execution engine 1126, and an L2 cache 1128. In at least one embodiment, the fetch / decode unit 1122 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1124 and the floating-point execution engine 1126. In at least one embodiment, the fetch / decode unit 1122 can simultaneously dispatch one micro-instruction to the integer execution engine 1124 and another micro-instruction to the floating-point execution engine 1126. In at least one embodiment, the integer execution engine 1124 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1126 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1122 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1124 and the floating-point execution engine 1126 .

[0099] In at least one embodiment, each core 1120(i), where i is an integer representing a particular instance of core 1120, may access an L2 cache 1128(i) included in core 1120(i). In at least one embodiment, each core 1120 included in a core complex 1110(j), where j is an integer representing a particular instance of core complex 1110, is connected to the other cores 1120 in core complex 1110(j) via an L3 cache 1130(j) included in core complex 1110(j). In at least one embodiment, a core 1120 included in a core complex 1110(j), where j is an integer representing a particular instance of core complex 1110, may access all of the L3 caches 1130(j) included in core complex 1110(j). In at least one embodiment, L3 cache 1130 may include, without limitation, any number of slices.

[0100] In at least one embodiment, fabric 1160 is a system interconnect that facilitates data and control transmission across core complexes 1110(1) through 1110(N) (where N is an integer greater than 0), I / O interface 1170, and memory controller 1180. In at least one embodiment, CPU 1100 may include any quantity and type of system interconnect in addition to or instead of fabric 1160, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to CPU 1100. In at least one embodiment, I / O interface 1170 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1170. In at least one embodiment, peripheral devices coupled to I / O interface 1170 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0101] In at least one embodiment, memory controller 1180 facilitates data transfer between CPU 1100 and system memory 1190. In at least one embodiment, core complex 1110 and graphics complex 1140 share system memory 1190. In at least one embodiment, CPU 1100 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1180 and memory devices, which may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 1100 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1128 and L3 cache 1130), each of which may be private to any number of components (e.g., core 1120 and core complex 1110) or shared among any number of components.

[0102] FIG. 12 illustrates an exemplary accelerator integration slice 1290 according to at least one embodiment. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in a graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engine may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip. In at least one embodiment, the accelerator integration slice 1290 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0103] Application effective address space 1282 in system memory 1214 stores process element 1283. In one embodiment, process element 1283 is stored in response to GPU call 1281 from application 1280 executing on processor 1207. Process element 1283 contains the process state of the corresponding application 1280. Work descriptor (“WD”) 1284 contained in process element 1283 may be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1284 is a pointer to a job request queue in application effective address space 1282.

[0104] The graphics acceleration module 1246 and / or individual graphics processing engines may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and submitting WD1284 to the graphics acceleration module 1246 to start jobs in a virtualized environment.

[0105] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1246 or an individual graphics processing engine. Because the graphics acceleration module 1246 is owned by a single process, the hypervisor initializes the accelerator integration circuitry for the owning partition, and the operating system initializes the accelerator integration circuitry for the owning process when the graphics acceleration module 1246 is allocated.

[0106] In operation, WD fetch unit 1291 in accelerator integrated slice 1290 fetches the next WD 1284, which contains instructions for work to be performed by one or more graphics processing engines of graphics acceleration module 1246. As shown, data from WD 1284 is stored in register 1245 and may be used by memory management unit (“MMU”) 1239, interrupt management circuitry 1247, and / or context management circuitry 1248. For example, one embodiment of MMU 1239 includes segment / page walk circuitry for accessing segment / page table 1286 within OS virtual address space 1285. Interrupt management circuit 1247 may process interrupt events (“INT”) 1292 received from graphics acceleration module 1246. When performing graphics operations, effective addresses 1293 generated by the graphics processing engines are translated into real addresses by MMU 1239.

[0107] In one embodiment, the same set of registers 1245 may be replicated for each graphics processing engine and / or graphics acceleration module 1246 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 1290. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0108] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0109] In one embodiment, each WD 1284 is specific to a particular graphics acceleration module 1246 and / or a particular graphics processing engine. The WD 1284 may contain all the information needed by the graphics processing engine to perform work, or the WD 1284 may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0110] 13A-13B illustrate exemplary graphics processors, according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within an SoC.

[0111] FIG. 13A illustrates an exemplary graphics processor 1310 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 13B illustrates an additional exemplary graphics processor 1340 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1310 of FIG. 13A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1340 of FIG. 13B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1310, 1340 may be a variation of the graphics processor 810 of FIG. 8. In at least one embodiment, the graphics processor 1310 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0112] In at least one embodiment, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D-1315N-1, and 1315N). In at least one embodiment, the graphics processor 1310 can execute different shader programs through separate logic, whereby the vertex processor 1305 is optimized to perform operations for vertex shader programs, and one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processor(s) 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to create a frame buffer that is displayed on a display device. In at least one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0113] In at least one embodiment, graphics processor 1310 additionally includes one or more MMUs 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. In at least one embodiment, one or more MMUs 1320A-1320B provide virtual-to-physical address mapping for graphics processor 1310, including vertex processor 1305 and / or fragment processor(s) 1315A-1315N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In at least one embodiment, one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 805, image processor 815, and / or video processor 820 of Figure 8, thereby allowing each processor 805-820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0114] In at least one embodiment, graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of graphics processor 1310 of FIG. 13A. In at least one embodiment, the graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F-1355N-1, and 1355N), where the one or more shader cores 1355A-1355N provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N, and a tiling unit 1358 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are sub-partitioned in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0115] FIG. 14A illustrates a graphics core 1400 according to at least one embodiment. In at least one embodiment, graphics core 1400 may be included within graphics processor 810 of FIG. 8. In at least one embodiment, graphics core 1400 may be unified shader cores 1355A-1355N as in FIG. 13B. In at least one embodiment, graphics core 1400 includes a shared instruction cache 1402, a texture unit 1418, and a cache / shared memory 1420, which are common to execution resources within graphics core 1400. In at least one embodiment, graphics core 1400 may include multiple slices 1401A-1401N, or partitions for each core, and a graphics processor may include multiple instances of graphics core 1400. The slices 1401A-1401N may include support logic including local instruction caches 1404A-1404N, thread schedulers 1406A-1406N, thread dispatchers 1408A-1408N, and sets of registers 1410A-1410N. In at least one embodiment, slices 1401A-1401N may include a set of additional function units (“AFUs”) 1412A-1412N, floating-point units (“FPUs”) 1414A-1414N, integer arithmetic logic units (“ALUs”) 1416-1416N, address computational units (“ACUs”) 1413A-1413N, double-precision floating-point units (“DPFPUs”) 1415A-1415N, and matrix processing units (“MPUs”) 1417A-1417N.In at least one embodiment, graphics core 1400 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0116] In at least one embodiment, the FPUs 1414A-1414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1415A-1415N perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1416A-1416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPUs 1417A-1417N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 1417A-1417N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication ("GEMM"). In at least one embodiment, AFUs 1412A-1412N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0117] FIG. 14B illustrates a general-purpose graphics processing unit (“GPGPU”) 1430 according to at least one embodiment. In at least one embodiment, the GPGPU 1430 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1430 may be configured to allow highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 1430 may be directly linked to other instances of the GPGPU 1430 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1430 includes a host interface 1432 to enable connection with a host processor. In at least one embodiment, the host interface 1432 is a PCIe interface. In at least one embodiment, the host interface 1432 may be a vendor-specific communication interface or fabric. In at least one embodiment, the GPGPU 1430 receives commands from the host processor and distributes execution threads associated with those commands across a set of compute clusters 1436A-1436H using a global scheduler 1434. In at least one embodiment, the compute clusters 1436A-1436H share a cache memory 1438. In at least one embodiment, the cache memory 1438 can act as a higher-level cache for the cache memories within the compute clusters 1436A-1436H.

[0118] In at least one embodiment, GPGPU 1430 includes memory 1444A-1444B coupled to compute clusters 1436A-1436H via a set of memory controllers 1442A-1442B. In at least one embodiment, memory 1444A-1444B can include various types of memory devices, including DRAM or graphics random access memory such as synchronous graphics random access memory ("SGRAM"), including graphics double data rate ("GDDR") memory.

[0119] In at least one embodiment, compute clusters 1436A-1436H each include a set of graphics cores, such as graphics core 1400 of FIG. 14A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1436A-1436H may be configured to perform 16-bit or 32-bit floating-point operations, and a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0120] In at least one embodiment, multiple instances of GPGPU 1430 may be configured to operate as a compute cluster. The compute clusters 1436A-1436H may implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1430 communicate via host interface 1432. In at least one embodiment, GPGPU 1430 includes an I / O hub 1439 that couples GPGPU 1430 to a GPU link 1440 that enables direct connection to other instances of GPGPU 1430. In at least one embodiment, GPU link 1440 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1430. In at least one embodiment, GPU link 1440 couples to a high-speed interconnect for sending and receiving data to other GPGPUs 1430 or parallel processors. In at least one embodiment, multiple instances of GPGPU 1430 are located in separate data processing systems and communicate via a network device accessible via host interface 1432. In at least one embodiment, GPU link 1440 may be configured to allow connection to a host processor in addition to, or as an alternative to, host interface 1432. In at least one embodiment, GPGPU 1430 may be configured to execute CUDA programs.

[0121] 15A illustrates a parallel processor 1500, according to at least one embodiment. In at least one embodiment, various components of parallel processor 1500 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit ("ASIC"), or an FPGA. In at least one embodiment, parallel processor 1500 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0122] In at least one embodiment, parallel processor 1500 includes parallel processing units 1502. In at least one embodiment, parallel processing units 1502 include I / O units 1504 that enable communication with other devices, including other instances of parallel processing units 1502. In at least one embodiment, I / O units 1504 may be directly connected to other devices. In at least one embodiment, I / O units 1504 connect to other devices through the use of a hub or switch interface, such as memory hub 1505. In at least one embodiment, the connection between memory hub 1505 and I / O units 1504 forms a communication link. In at least one embodiment, I / O units 1504 connect to host interface 1506 and memory crossbar 1516, where host interface 1506 receives commands intended to perform processing operations and memory crossbar 1516 receives commands intended to perform memory operations.

[0123] In at least one embodiment, when host interface 1506 receives command buffers via I / O unit 1504, host interface 1506 can direct work operations to implement those commands to front end 1508. In at least one embodiment, front end 1508 is coupled to scheduler 1510, which is configured to distribute commands or other work items to processing array 1512. In at least one embodiment, scheduler 1510 ensures that processing array 1512 is properly configured and in a valid state before tasks are distributed to processing array 1512. In at least one embodiment, scheduler 1510 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1510 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, allowing rapid preemption and context switching of threads executing on the processing array 1512. In at least one embodiment, host software can present workloads for scheduling on the processing array 1512 via one of multiple graphics processing bells. In at least one embodiment, the workloads can then be automatically distributed across the processing array 1512 by scheduler 1510 logic within the microcontroller that includes the scheduler 1510.

[0124] In at least one embodiment, processing array 1512 may include up to “N” clusters (e.g., cluster 1514A, cluster 1514B through cluster 1514N). In at least one embodiment, each cluster 1514A-1514N of processing array 1512 may execute multiple concurrent threads. In at least one embodiment, scheduler 1510 may allocate work to clusters 1514A-1514N of processing array 1512 using various scheduling and / or work distribution algorithms, which may vary depending on the workload occurring for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1510 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing array 1512. In at least one embodiment, different clusters 1514A-1514N of processing array 1512 may be allocated to process different types of programs or perform different types of computations.

[0125] In at least one embodiment, processing array 1512 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 1512 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array 1512 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0126] In at least one embodiment, processing array 1512 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 1512 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 1512 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 1502 may transfer data from system memory via I / O unit 1504 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1522) during processing and then written back to system memory.

[0127] In at least one embodiment, when parallel processing unit 1502 is used to perform graphics processing, scheduler 1510 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 1514A-1514N of processing array 1512. In at least one embodiment, portions of processing array 1512 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data produced by one or more of clusters 1514A-1514N may be stored in a buffer to allow the intermediate data to be transmitted between clusters 1514A-1514N for further processing.

[0128] In at least one embodiment, the processing array 1512 may receive processing tasks to be performed via a scheduler 1510, which receives commands defining the processing tasks from the front end 1508. In at least one embodiment, the processing tasks may include an index of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, the scheduler 1510 may be configured to fetch the index corresponding to the task or may receive the index from the front end 1508. In at least one embodiment, the front end 1508 may be configured to ensure that the processing array 1512 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0129] In at least one embodiment, each of one or more instances of parallel processing unit 1502 can be coupled to parallel processor memory 1522. In at least one embodiment, parallel processor memory 1522 can be accessed via memory crossbar 1516, which can receive memory requests from processing array 1512 as well as I / O unit 1504. In at least one embodiment, memory crossbar 1516 can access parallel processor memory 1522 via memory interface 1518. In at least one embodiment, memory interface 1518 can include multiple partition units (e.g., partition unit 1520A, partition unit 1520B through partition unit 1520N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 1522. In at least one embodiment, the number of partition units 1520A-1520N is configured to be equal to the number of memory units, such that a first partition unit 1520A has a corresponding first memory unit 1524A, a second partition unit 1520B has a corresponding memory unit 1524B, and an Nth partition unit 1520N has a corresponding Nth memory unit 1524N. In at least one embodiment, the number of partition units 1520A-1520N may not be equal to the number of memory devices.

[0130] In at least one embodiment, the memory units 1524A-1524N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, the memory units 1524A-1524N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 1522, render targets, such as frame buffers or texture maps, may be stored across the memory units 1524A-1524N, allowing the partition units 1520A-1520N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 1522 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0131] In at least one embodiment, any one of the clusters 1514A-1514N of the processing array 1512 can process data that is to be written to any one of the memory units 1524A-1524N in the parallel processor memory 1522. In at least one embodiment, the memory crossbar 1516 can be configured to forward the output of each cluster 1514A-1514N to any partition unit 1520A-1520N that can perform additional processing operations on the output, or to another cluster 1514A-1514N. In at least one embodiment, each cluster 1514A-1514N can communicate with a memory interface 1518 through the memory crossbar 1516 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 1516 has a connection to a memory interface 1518 for communicating with the I / O units 1504, as well as a connection to a local instance of parallel processor memory 1522, which allows processing units in different clusters 1514A-1514N to communicate with system memory or other memory not local to the parallel processing units 1502. In at least one embodiment, the memory crossbar 1516 can use virtual channels to separate traffic streams between the clusters 1514A-1514N and the partition units 1520A-1520N.

[0132] In at least one embodiment, multiple instances of parallel processing unit 1502 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1502 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1502 may include higher precision floating-point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1502 or parallel processor 1500 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0133] FIG. 15B illustrates a processing cluster 1594, according to at least one embodiment. In at least one embodiment, the processing cluster 1594 is included within a parallel processing unit. In at least one embodiment, the processing cluster 1594 is one of the processing clusters 1514A-1514N of FIG. 15. In at least one embodiment, the processing cluster 1594 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single instruction, multiple data ("SIMD") instruction issue technique is used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, a single instruction, multiple thread ("SIMT") technique is used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 1594. In at least one embodiment, processing cluster 1594 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0134] In at least one embodiment, operation of the processing cluster 1594 may be controlled via a pipeline manager 1532 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1532 receives instructions from the scheduler 1510 of FIG. 15 and manages the execution of those instructions via the graphics multiprocessor 1534 and / or the texture unit 1536. In at least one embodiment, the graphics multiprocessor 1534 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 1594. In at least one embodiment, one or more instances of the graphics multiprocessor 1534 may be included within the processing cluster 1594. In at least one embodiment, the graphics multiprocessor 1534 may process data, and a data crossbar 1540 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1532 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed through the data crossbar 1540.

[0135] In at least one embodiment, each graphics multiprocessor 1534 in a processing cluster 1594 may include an identical set of function execution logic (e.g., arithmetic logic units, load / store units (“LSUs”), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, such that new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and computation of various algebraic functions. In at least one embodiment, the same function unit hardware may be utilized to perform different operations, and any combination of function units may be present.

[0136] In at least one embodiment, instructions sent to processing cluster 1594 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in graphics multiprocessor 1534. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 1534. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 1534. In at least one embodiment, when a thread group includes more threads than the number of processing engines in graphics multiprocessor 1534, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 1534.

[0137] In at least one embodiment, the graphics multiprocessor 1534 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1534 can forgo internal cache and use cache memory (e.g., L1 cache 1548) within the processing cluster 1594. In at least one embodiment, each graphics multiprocessor 1534 also has access to a level 2 (“L2”) cache within a partition unit (e.g., partition units 1520A-1520N in FIG. 15A ), and these L2 caches are shared among all processing clusters 1594 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1534 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing units 1502 can be used as global memory. In at least one embodiment, processing cluster 1594 includes multiple instances of graphics multiprocessor 1534, and the graphics multiprocessors 1534 can share common instructions and data, which can be stored in L1 cache 1548.

[0138] In at least one embodiment, each processing cluster 1594 may include an MMU 1545 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1545 may reside in memory interface 1518 of FIG. 15 . In at least one embodiment, MMU 1545 includes a set of page table entries (“PTEs”) used to map virtual addresses to physical addresses of tiles and, optionally, cache line indices. In at least one embodiment, MMU 1545 may include an address translation lookaside buffer (“TLB”) or cache, which may reside in graphics multiprocessor 1534, L1 cache 1548, or processing cluster 1594. In at least one embodiment, physical addresses are processed to distribute surface data access locality and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0139] In at least one embodiment, processing cluster 1594 may be configured such that each graphics multiprocessor 1534 is coupled to a texture unit 1536 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1534 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1534 outputs processed tasks to data crossbar 1540 to provide the processed tasks to another processing cluster 1594 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1516. In at least one embodiment, a pre-raster operation unit (“pre-ROP”) 1542 is configured to receive data from the graphics multiprocessor 1534 and direct the data to a ROP unit, which may be co-located with a partition unit as described herein (e.g., partition units 1520A-1520N of FIG. 15). In at least one embodiment, pre-ROP 1542 may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0140] FIG. 15C illustrates a graphics multiprocessor 1596, according to at least one embodiment. In at least one embodiment, graphics multiprocessor 1596 is graphics multiprocessor 1534 of FIG. 15B. In at least one embodiment, graphics multiprocessor 1596 couples to pipeline manager 1532 of processing cluster 1594. In at least one embodiment, graphics multiprocessor 1596 has an execution pipeline including, but not limited to, instruction cache 1552, instruction unit 1554, address mapping unit 1556, register file 1558, one or more GPGPU cores 1562, and one or more LSUs 1566. GPGPU cores 1562 and LSUs 1566 are coupled to cache memory 1572 and shared memory 1570 via memory and cache interconnect 1568. In at least one embodiment, the graphics multiprocessor 1596 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0141] In at least one embodiment, instruction cache 1552 receives a stream of instructions to execute from pipeline manager 1532. In at least one embodiment, instructions are cached in instruction cache 1552 and dispatched for execution by instruction unit 1554. In at least one embodiment, instruction unit 1554 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 1562. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying an address in the unified address space. In at least one embodiment, address mapping unit 1556 can be used to translate addresses in the unified address space into individual memory addresses that can be accessed by LSU 1566.

[0142] In at least one embodiment, register file 1558 provides a set of registers to the functional units of graphics multiprocessor 1596. In at least one embodiment, register file 1558 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU core 1562, LSU 1566) of graphics multiprocessor 1596. In at least one embodiment, register file 1558 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of register file 1558. In at least one embodiment, register file 1558 is divided among different thread groups being executed by graphics multiprocessor 1596.

[0143] In at least one embodiment, GPGPU cores 1562 may each include an FPU and / or integer ALU used to execute instructions for graphics multiprocessor 1596. GPGPU cores 1562 may be of similar or different architectures. In at least one embodiment, a first portion of GPGPU core 1562 includes a single-precision FPU and integer ALU, and a second portion of GPGPU core 1562 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, graphics multiprocessor 1596 may additionally include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 1562 may also include fixed or special-function logic. In at least one embodiment, GPGPU core 1562 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0144] In at least one embodiment, GPGPU core 1562 includes SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 1562 physically executes SIMD4, SIMD8, and SIMD16 instructions and logically executes SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU core 1562 may be generated at compile time by a shader compiler or automatically when executing a program written and compiled for a single program multiple data (“SPMD”) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0145] In at least one embodiment, memory and cache interconnect 1568 is an interconnect network connecting each functional unit of graphics multiprocessor 1596 to register file 1558 and shared memory 1570. In at least one embodiment, memory and cache interconnect 1568 is a crossbar interconnect that allows LSU 1566 to implement load and store operations between shared memory 1570 and register file 1558. In at least one embodiment, register file 1558 can operate at the same frequency as GPGPU cores 1562, and therefore data transfers between GPGPU cores 1562 and register file 1558 are very low latency. In at least one embodiment, shared memory 1570 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1596. In at least one embodiment, cache memory 1572 can be used as a data cache, for example, to cache texture data communicated between functional units and texture unit 1536. In at least one embodiment, shared memory 1570 can also be used as a managed program cache. In at least one embodiment, threads executing on GPGPU cores 1562 can programmatically store data in the shared memory in addition to the automatically cached data stored in cache memory 1572.

[0146] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated in the same package or chip as the cores and communicatively coupled to the cores via a processor bus / interconnect internal to the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0147] FIG. 16 illustrates a graphics processor 1600 according to at least one embodiment. In at least one embodiment, the graphics processor 1600 includes a ring interconnect 1602, a pipeline front end 1604, a media engine 1637, and graphics cores 1680A-1680N. In at least one embodiment, the ring interconnect 1602 couples the graphics processor 1600 to other graphics processors or other processing units, including one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1600 is one of many processors incorporated within a multi-core processing system. In at least one embodiment, the graphics processor 1600 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0148] In at least one embodiment, graphics processor 1600 receives batches of commands via ring interconnect 1602. In at least one embodiment, the incoming commands are interpreted by command streamer 1603 in pipeline front end 1604. In at least one embodiment, graphics processor 1600 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 1680A-1680N. In at least one embodiment, for 3D geometry processing commands, command streamer 1603 supplies the commands to geometry pipeline 1636. In at least one embodiment, for at least some media processing commands, command streamer 1603 supplies the commands to video front end 1634, which couples to media engine 1637. In at least one embodiment, media engine 1637 includes a video quality engine ("VQE") 1630 for video and image post-processing and a multi-format encode / decode ("MFX") engine 1633 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, geometry pipeline 1636 and media engine 1637 each spawn execution threads for thread execution resources provided by at least one graphics core 1680A.

[0149] In at least one embodiment, graphics processor 1600 includes scalable thread execution resources characterized by modular graphics cores 1680A-1680N (sometimes referred to as core slices), each having multiple sub-cores 1650A-1650N, 1660A-1660N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1600 can have any number of graphics cores 1680A-1680N. In at least one embodiment, graphics processor 1600 includes graphics core 1680A having at least a first sub-core 1650A and a second sub-core 1660A. In at least one embodiment, graphics processor 1600 is a low-power processor with a single sub-core (e.g., sub-core 1650A). In at least one embodiment, the graphics processor 1600 includes multiple graphics cores 1680A-1680N, each including a first set of sub-cores 1650A-1650N and a second set of sub-cores 1660A-1660N. In at least one embodiment, each sub-core in the first sub-cores 1650A-1650N includes at least a first set of execution units ("EUs") 1652A-1652N and media / texture samplers 1654A-1654N. In at least one embodiment, each sub-core in the second sub-cores 1660A-1660N includes at least a second set of execution units 1662A-1662N and samplers 1664A-1664N. In at least one embodiment, each sub-core 1650A-1650N, 1660A-1660N shares a set of shared resources 1670A-1670N. In at least one embodiment, the shared resources 1670 include shared cache memory and pixel operating logic.

[0150] FIG. 17 illustrates a processor 1700 according to at least one embodiment. In at least one embodiment, the processor 1700 may include logic circuitry for implementing instructions, including, but not limited to, x86 instructions, AMR instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 1700 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled with MMX™ technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with SIMD and streaming SIMD extension (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 1710 may execute instructions for accelerating CUDA programs. In at least one embodiment, processor 1700 comprises and / or is for implementing, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0151] In at least one embodiment, processor 1700 includes an in-order front end (“front end”) 1701 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, front end 1701 may include several units. In at least one embodiment, instruction prefetcher 1726 fetches instructions from memory and feeds the instructions to instruction decoder 1728, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 1728 decodes received instructions into one or more operations called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”) for execution. In at least one embodiment, instruction decoder 1728 parses instructions into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 1730 may assemble decoded uops into program-order sequences, or traces, for execution in uop queue 1734. In at least one embodiment, when trace cache 1730 encounters a complex instruction, microcode ROM 1732 provides the uops necessary to complete the operation.

[0152] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 1728 may access the microcode ROM 1732 to implement the instruction. In at least one embodiment, an instruction may be decoded into a fewer number of micro-ops for processing in the instruction decoder 1728. In at least one embodiment, an instruction may be stored in the microcode ROM 1732 if several micro-ops are required to accomplish the operation. In at least one embodiment, the trace cache 1730 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 1732. In at least one embodiment, after the microcode ROM 1732 finishes sequencing micro-ops for an instruction, the machine front end 1701 may resume fetching micro-ops from the trace cache 1730.

[0153] In at least one embodiment, an out-of-order execution engine (“out-of-order engine”) 1703 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth the flow of instructions and reorder them to optimize performance as they move down the pipeline and are scheduled for execution. The out-of-order execution engine 1703 includes, but is not limited to, an allocator / register renamer 1740, a memory uop queue 1742, an integer / floating point uop queue 1744, a memory scheduler 1746, a fast scheduler 1702, a slow / general purpose floating point scheduler (“slow / general purpose FP scheduler”) 1704, and a simple floating point scheduler (“simple FP scheduler”) 1706. In at least one embodiment, the fast scheduler 1702, the slow / general purpose floating point scheduler 1704, and the simple floating point scheduler 1706 are also collectively referred to herein as "uop schedulers 1702, 1704, 1706." The allocator / register renamer 1740 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, the allocator / register renamer 1740 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 1740 also allocates an entry for each uop in one of two uop queues: memory uop queue 1742 for memory operations and integer / floating point uop queue 1744 for non-memory operations, before memory scheduler 1746 and uop schedulers 1702, 1704, 1706. In at least one embodiment, uop schedulers 1702, 1704, 1706 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 1702 of at least one embodiment may schedule every half of a main clock cycle, and the slow / general purpose floating point scheduler 1704 and simple floating point scheduler 1706 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 1702, 1704, 1706 arbitrate for dispatch ports to schedule uops for execution.

[0154] In at least one embodiment, execution block 1711 includes, but is not limited to, integer register file / bypass network 1708, floating point register file / bypass network (“FP register file / bypass network”) 1710, address generation units (“AGUs”) 1712 and 1714, fast ALUs 1716 and 1718, slow ALU 1720, floating point ALU (“FP”) 1722, and floating point move unit (“FP move”) 1724. In at least one embodiment, integer register file / bypass network 1708 and floating point register file / bypass network 1710 are also referred to herein as “register files 1708, 1710.” In at least one embodiment, AGUs 1712 and 1714, fast ALUs 1716 and 1718, slow ALU 1720, floating-point ALU 1722, and floating-point move unit 1724 are also referred to herein as "execution units 1712, 1714, 1716, 1718, 1720, 1722, and 1724." In at least one embodiment, an execution block may include any number and type (including, but not limited to, zero) of register files, bypass networks, address generation units, and execution units in any combination.

[0155] In at least one embodiment, register files 1708, 1710 may be located between uop schedulers 1702, 1704, 1706 and execution units 1712, 1714, 1716, 1718, 1720, 1722, and 1724. In at least one embodiment, integer register file / bypass network 1708 performs integer operations. In at least one embodiment, floating point register file / bypass network 1710 performs floating point operations. In at least one embodiment, each of register files 1708, 1710 may include, but is not limited to, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 1708, 1710 may communicate data with each other. In at least one embodiment, integer register file / bypass network 1708 may include, but is not limited to, two separate register files: one register file for lower 32-bit data and a second register file for higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 1710 may include, but is not limited to, 128-bit wide entries.

[0156] In at least one embodiment, execution units 1712, 1714, 1716, 1718, 1720, 1722, and 1724 may execute instructions. In at least one embodiment, register files 1708 and 1710 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 1700 may include, but is not limited to, any number and combination of execution units 1712, 1714, 1716, 1718, 1720, 1722, and 1724. In at least one embodiment, floating-point ALU 1722 and floating-point move unit 1724 may perform floating-point, MMX, SIMD, AVX, and SSE, or other operations. In at least one embodiment, the floating-point ALU 1722 may include a 64-bit floating-point divider for performing, but not limited to, division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the fast ALUs 1716, 1718. In at least one embodiment, the fast ALUs 1716, 1718 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the slow ALU 1720 may include integer execution hardware for long-latency type operations such as, but not limited to, multipliers, shifts, flag logic, and branching, so that most complex integer operations proceed to the slow ALU 1720. In at least one embodiment, memory load / store operations may be performed by the AGUs 1712, 1714. In at least one embodiment, fast ALU 1716, fast ALU 1718, and slow ALU 1720 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 1716, fast ALU 1718, and slow ALU 1720 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 1722 and floating-point move unit 1724 may be implemented to support various operands having various bit widths.In at least one embodiment, floating-point ALU 1722 and floating-point move unit 1724 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0157] In at least one embodiment, the uop schedulers 1702, 1704, 1706 dispatch dependent operations before the parent load finishes executing. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 1700, the processor 1700 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0158] In at least one embodiment, the term “register” may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0159] FIG. 18 illustrates a processor 1800 according to at least one embodiment. In at least one embodiment, the processor 1800 includes, but is not limited to, one or more processor cores (“cores”) 1802A-1802N, an integrated memory controller 1814, and an integrated graphics processor 1808. In at least one embodiment, the processor 1800 may include additional cores, up to an additional processor core 1802N, represented by a dashed box. In at least one embodiment, each of the processor cores 1802A-1802N includes one or more internal cache units 1804A-1804N. In at least one embodiment, each processor core also has access to one or more shared cache units 1806. In at least one embodiment, the processor 1800 comprises and / or is adapted to perform, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0160] In at least one embodiment, the internal cache units 1804A-1804N and the shared cache unit 1806 represent a cache memory hierarchy within the processor 1800. In at least one embodiment, the cache memory units 1804A-1804N may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as L2, L3, level 4 (“L4”), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 1806 and 1804A-1804N.

[0161] In at least one embodiment, processor 1800 may also include a set of one or more bus controller units 1816 and a system agent core 1810. In at least one embodiment, one or more bus controller units 1816 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 1810 provides management functionality for various processor components. In at least one embodiment, system agent core 1810 includes one or more integrated memory controllers 1814 for managing access to various external memory devices (not shown).

[0162] In at least one embodiment, one or more of the processor cores 1802A-1802N include support for simultaneous multithreading. In at least one embodiment, the system agent core 1810 includes components for coordinating and operating the processor cores 1802A-1802N during multithreaded processing. In at least one embodiment, the system agent core 1810 may additionally include a power control unit (“PCU”), which includes logic and components for adjusting the power state of one or more of the processor cores 1802A-1802N and the graphics processor 1808.

[0163] In at least one embodiment, processor 1800 additionally includes a graphics processor 1808 for performing graphics processing operations. In at least one embodiment, graphics processor 1808 couples to a system agent core 1810 that includes a shared cache unit 1806 and one or more integrated memory controllers 1814. In at least one embodiment, system agent core 1810 also includes a display controller 1811 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 1811 may also be a separate module coupled to graphics processor 1808 via at least one interconnect or may be incorporated within graphics processor 1808.

[0164] In at least one embodiment, a ring-based interconnect unit 1812 is used to couple the internal components of processor 1800. In at least one embodiment, alternative interconnect units such as point-to-point interconnects, switched interconnects, or other techniques may be used. In at least one embodiment, graphics processor 1808 couples to ring interconnect 1812 via I / O link 1813.

[0165] In at least one embodiment, I / O link 1813 represents at least one of several types of I / O interconnect, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1818, such as an eDRAM module. In at least one embodiment, each of processor cores 1802A-1802N and graphics processor 1808 use embedded memory module 1818 as a shared LLC.

[0166] In at least one embodiment, processor cores 1802A-1802N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 1802A-1802N are heterogeneous in terms of ISA, where one or more of processor cores 1802A-1802N execute a common instruction set and one or more other of processor cores 1802A-1802N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 1802A-1802N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are combined with one or more cores with lower power consumption. In at least one embodiment, processor 1800 may be implemented on one or more chips or as an SoC integrated circuit.

[0167] FIG. 19 illustrates a graphics processor core 1900 according to at least one described embodiment. In at least one embodiment, graphics processor core 1900 is included within a graphics core array. In at least one embodiment, graphics processor core 1900, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 1900 is illustrative of one graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 1900 may include a fixed function block 1930 coupled with multiple sub-cores 1901A-1901F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed-function logic. In at least one embodiment, graphics processor core 1900 comprises and / or is adapted to implement, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0168] In at least one embodiment, fixed function block 1930 includes a geometry / fixed function pipeline 1936 that may be shared by all sub-cores in graphics processor 1900, e.g., in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 1936 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0169] In at least one embodiment, fixed function block 1930 also includes graphics SoC interface 1937, graphics microcontroller 1938, and media pipeline 1939. Graphics SoC interface 1937 provides an interface between graphics core 1900 and other processor cores within the SoC integrated circuit. In at least one embodiment, graphics microcontroller 1938 is a programmable sub-processor that is configurable to manage various functions of graphics processor 1900, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 1939 includes logic for facilitating decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 1939 implements media operations via requests to compute logic or sampling logic within sub-cores 1901-1901F.

[0170] In at least one embodiment, SoC interface 1937 enables graphics core 1900 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 1937 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable and / or implement global memory atomics that may be shared between graphics core 1900 and a CPU within the SoC. In at least one embodiment, SoC interface 1937 can also implement power management controls for graphics core 1900 and enable an interface between the clock domain of graphics core 1900 and other clock domains within the SoC. In at least one embodiment, SoC interface 1937 enables receiving command buffers from a command streamer and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, the commands and instructions may be dispatched to a media pipeline 1939 when a media operation is to be performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 1936, geometry and fixed function pipeline 1914) when a graphics processing operation is to be performed.

[0171] In at least one embodiment, graphics microcontroller 1938 can be configured to perform various scheduling and management tasks for graphics core 1900. In at least one embodiment, graphics microcontroller 1938 can perform graphics and / or compute workload scheduling for various graphics parallel engines in execution unit (EU) arrays 1902A-1902F, 1904A-1904F within sub-cores 1901A-1901F. In at least one embodiment, host software running on a CPU core of an SoC including graphics core 1900 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is complete. In at least one embodiment, graphics microcontroller 1938 can also facilitate low power or idle states for graphics core 1900, providing graphics core 1900 with the ability to save and restore registers within graphics core 1900 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0172] In at least one embodiment, graphics core 1900 may have up to N modular sub-cores, more or fewer than the illustrated sub-cores 1901A-1901F. For each set of N sub-cores, in at least one embodiment, graphics core 1900 may also include shared function logic 1910, shared and / or cache memory 1912, geometry / fixed function pipeline 1914, and additional fixed function logic 1916 for accelerating various graphics and compute processing operations. In at least one embodiment, shared function logic 1910 may include logic units (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics core 1900. Shared and / or cache memory 1912 may be an LLC for the N sub-cores 1901A-1901F in graphics core 1900 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 1914 may be included in place of geometry / fixed function pipeline 1936 in fixed function block 1930 and may include the same or similar logical units.

[0173] In at least one embodiment, graphics core 1900 includes additional fixed-function logic 1916, which can include various fixed-function acceleration logic for use by graphics core 1900. In at least one embodiment, additional fixed-function logic 1916 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines: a full geometry pipeline in geometry / fixed-function pipeline 1916, 1936, and a cull pipeline, where the cull pipeline is an additional geometry pipeline that can be included in additional fixed-function logic 1916. In at least one embodiment, the cull pipeline is a scaled-down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can run different instances of an application, each instance having a separate context. In at least one embodiment, position-only shading can hide long cull runs of truncated triangles, which allows shading to complete faster in some instances. For example, in at least one embodiment, the cull pipeline fetches and shades vertex position attributes without rasterizing and rendering pixels to the frame buffer, allowing the cull pipeline logic in the additional fixed-function logic 1916 to execute position shaders in parallel with the main application and produce critical results faster than the full pipeline. In at least one embodiment, the cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which may be referred to in this instance as the replay pipeline) can consume the visibility information and shade only visible triangles, skipping over culled triangles, which are ultimately passed to the rasterization phase.

[0174] In at least one embodiment, the additional fixed function logic 1916 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, to accelerate CUDA programs.

[0175] In at least one embodiment, each graphics sub-core 1901A-1901F includes a set of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 1901A-1901F include a plurality of EU arrays 1902A-1902F, 1904A-1904F, thread dispatch and inter-thread communication (“TD / IC”) logic 1903A-1903F, 3D (e.g., texture) samplers 1905A-1905F, media samplers 1906A-1906F, shader processors 1907A-1907F, and shared local memory (“SLM”) 1908A-1908F. EU arrays 1902A-1902F, 1904A-1904F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer / fixed-point logic operations in service of graphics, media, or compute operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 1903A-1903F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitates communication between threads executing on the execution units of a sub-core. In at least one embodiment, 3D samplers 1905A-1905F can read textures or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and texture format associated with a given texture. In at least one embodiment, media samplers 1906A-1906F can perform similar read operations based on the type and format associated with the media data.In at least one embodiment, each graphics sub-core 1901A-1901F can alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of the sub-cores 1901A-1901F can utilize shared local memory 1908A-1908F within each sub-core to allow threads executing within a thread group to execute using a common pool of on-chip memory.

[0176] FIG. 20 illustrates a parallel processing unit (“PPU”) 2000 according to at least one embodiment. In at least one embodiment, the PPU 2000 comprises machine-readable code that, when executed by the PPU 2000, causes the PPU 2000 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2000 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizing multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by the PPU 2000. In at least one embodiment, the PPU 2000 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2000 is utilized to perform computations such as linear algebra operations and machine learning operations. Figure 20 depicts an exemplary parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment. In at least one embodiment, PPU 2000 comprises and / or performs, at least in part, the various components and / or operations described above in conjunction with Figures 1-3.

[0177] In at least one embodiment, the one or more PPUs 2000 are configured to accelerate high performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, the one or more PPUs 2000 are configured to accelerate CUDA programs. In at least one embodiment, the PPUs 2000 include, but are not limited to, an I / O unit 2006, a front end unit 2010, a scheduler unit 2012, a work distribution unit 2014, a hub 2016, a crossbar ("Xbar") 2020, one or more general processing clusters ("GPC") 2018, and one or more partition units ("memory partition units") 2022. In at least one embodiment, the PPU 2000 is connected to a host processor or other PPUs 2000 via one or more high-speed GPU interconnects (“GPU interconnects”) 2008. In at least one embodiment, the PPU 2000 is connected to a host processor or other peripheral devices via a system bus or interconnect 2002. In at least one embodiment, the PPU 2000 is connected to local memory comprising one or more memory devices (“memory”) 2004. In at least one embodiment, the memory devices 2004 include, but are not limited to, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high bandwidth memory (“HBM”) subsystem with multiple DRAM dies stacked within each device.

[0178] In at least one embodiment, the high-speed GPU interconnect 2008 may refer to a wire-based, multi-lane communication link used by the system to scale and include one or more PPUs 2000 in combination with one or more CPUs, supporting cache coherence between the PPUs 2000 and the CPUs and CPU mastering. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2008 through the hub 2016 to and from other units of the PPU 2000, such as one or more copy engines, a video encoder, a video decoder, a power management unit, and other components that may not be explicitly shown in FIG. 20 .

[0179] In at least one embodiment, I / O unit 2006 is configured to receive and send communications (e.g., commands, data) from a host processor (not shown in FIG. 20 ) via system bus 2002. In at least one embodiment, I / O unit 2006 communicates with the host processor directly via system bus 2002 or through one or more intermediate devices, such as a memory bridge. In at least one embodiment, I / O unit 2006 may communicate with one or more other processors, such as one or more of PPUs 2000, via system bus 2002. In at least one embodiment, I / O unit 2006 implements a PCIe interface for communication over the PCIe bus. In at least one embodiment, I / O unit 2006 implements an interface for communicating with external devices.

[0180] In at least one embodiment, the I / O unit 2006 decodes packets received via the system bus 2002. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2000 to perform various operations. In at least one embodiment, the I / O unit 2006 transmits the decoded commands to various other units of the PPU 2000 specified by the commands. In at least one embodiment, the commands are transmitted to the front end unit 2010 and / or to the hub 2016 or other units of the PPU 2000, such as one or more copy engines, video encoders, video decoders, or power management units (not explicitly shown in FIG. 20 ). In at least one embodiment, the I / O unit 2006 is configured to route communications to and between various logical units of the PPU 2000.

[0181] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2000 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory accessible (e.g., readable / writable) by both the host processor and the PPU 2000, and the host interface unit may be configured to access the buffer in system memory connected to the system bus 2002 via memory requests sent by the I / O unit 2006 over the system bus 2002. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2000, whereby the front end unit 2010 receives the pointer to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to various units of the PPU 2000.

[0182] In at least one embodiment, the front end unit 2010 is coupled to a scheduler unit 2012 that configures the various GPCs 2018 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2012 is configured to track state information related to the various tasks managed by the scheduler unit 2012, where the state information may indicate which of the GPCs 2018 the task is assigned to, whether the task is active or inactive, the priority level associated with the task, etc. In at least one embodiment, the scheduler unit 2012 manages the execution of multiple tasks on one or more of the GPCs 2018.

[0183] In at least one embodiment, the scheduler unit 2012 is coupled to a work distribution unit 2014 configured to dispatch tasks for execution on the GPCs 2018. In at least one embodiment, the work distribution unit 2014 tracks the number of scheduled tasks received from the scheduler unit 2012, and the work distribution unit 2014 manages a pending task pool and an active task pool for each of the GPCs 2018. In at least one embodiment, the pending task pool may comprise a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2018, and the active task pool may comprise a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 2018, such that when one of the GPCs 2018 completes execution of a task, the task is removed from the active task pool for the GPC 2018 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2018. In at least one embodiment, when an active task is idle on the GPC2018, such as while waiting for a data dependency to be resolved, the active task is evicted from the GPC2018 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC2018.

[0184] In at least one embodiment, work distribution unit 2014 communicates with one or more GPCs 2018 via X-bar 2020. In at least one embodiment, X-bar 2020 is an interconnection network coupling many units of PPU 2000 to other units of PPU 2000 and may be configured to couple work distribution unit 2014 to a particular GPC 2018. In at least one embodiment, one or more other units of PPU 2000 may also be connected to X-bar 2020 via hub 2016.

[0185] In at least one embodiment, tasks are managed by the scheduler unit 2012 and dispatched by the work distribution unit 2014 to one of the GPCs 2018. The GPC 2018 is configured to process the task and produce a result. In at least one embodiment, the result may be consumed by other tasks within the GPC 2018, routed to a different GPC 2018 via the Xbar 2020, or stored in memory 2004. In at least one embodiment, the result may be written to memory 2004 via the partition unit 2022, which implements a memory interface for reading and writing data to and from memory 2004. In at least one embodiment, the result may be sent to another PPU 2004 or a CPU via the high-speed GPU interconnect 2008. In at least one embodiment, the PPU 2000 includes U partition units 2022 equal to, but not limited to, the number of distinct individual memory devices 2004 coupled to the PPU 2000 .

[0186] In at least one embodiment, the host processor executes a driver kernel, which implements an application programming interface ("API") that allows one or more applications running on the host processor to schedule operations for execution on the PPU 2000. In at least one embodiment, multiple compute applications are executed concurrently by the PPU 2000, which provides isolation, quality of service ("QoS"), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2000, and the driver kernel outputs the tasks to one or more streams that are processed by the PPU 2000. In at least one embodiment, each task comprises one or more groups of participating threads, which may be referred to as a warp. In at least one embodiment, a warp comprises multiple participating threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, cooperating threads can refer to multiple threads that contain instructions to perform a task and exchange data through a shared memory.

[0187] 21 illustrates a GPC 2100, according to at least one embodiment. In at least one embodiment, the GPC 2100 is the GPC 2018 of FIG. 20. In at least one embodiment, each GPC 2100 includes several hardware units for processing tasks, including, but not limited to, a pipeline manager 2102, a pre-raster operation unit ("PROP") 2104, a raster engine 2108, a work distribution crossbar ("WDX") 2116, an MMU 2118, one or more data processing clusters ("DPC") 2106, and any suitable combination of parts.

[0188] In at least one embodiment, operation of the GPC 2100 is controlled by a pipeline manager 2102. In at least one embodiment, the pipeline manager 2102 manages the configuration of one or more DPCs 2106 to process tasks allocated to the GPC 2100. In at least one embodiment, the pipeline manager 2102 configures at least one of the one or more DPCs 2106 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2106 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2114. In at least one embodiment, the pipeline manager 2102 is configured to route packets received from the work distribution unit to the appropriate logical unit within the GPC 2100; in at least one embodiment, some packets may be routed to a fixed-function hardware unit in the PROP 2104 and / or the raster engine 2108, while other packets may be routed to the DPC 2106 for processing by the primitive engine 2112 or the SM 2114. In at least one embodiment, the pipeline manager 2102 configures at least one of the DPCs 2106 to implement a computing pipeline. In at least one embodiment, the pipeline manager 2102 configures at least one of the DPCs 2106 to execute at least a portion of a CUDA program. In at least one embodiment, the GPC 2100 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0189] In at least one embodiment, the PROP unit 2104 is configured to route data generated by the raster engine 2108 and the DPC 2106 to a raster operation ("ROP") unit in a partition unit, such as the memory partition unit 2022 described in more detail above in conjunction with FIG. 20. In at least one embodiment, the PROP unit 2104 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2108 includes several fixed-function hardware units configured to perform various raster operations, including, but not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices. The plane equations are sent to a coarse raster engine to generate coverage information for the primitives (e.g., x, y coverage masks for tiles). The output of the coarse raster engine is sent to a culling engine to cull fragments associated with primitives that fail a z-test and to a clipping engine to clip fragments that are outside the view frustum. In at least one embodiment, fragments that pass clipping and culling are passed to a fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2108 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within the DPC 2106.

[0190] In at least one embodiment, each DPC 2106 included in the GPC 2100 includes, but is not limited to, an M-Pipe Controller (“MPC”) 2110, a Primitive Engine 2112, one or more SMs 2114, and any suitable combination thereof. In at least one embodiment, the MPC 2110 controls the operation of the DPC 2106 and routes packets received from the Pipeline Manager 2102 to the appropriate units in the DPC 2106. In at least one embodiment, packets related to vertices are routed to the Primitive Engine 2112, which is configured to fetch vertex attributes related to the vertices from memory; in contrast, packets related to shader programs may be sent to the SM 2114.

[0191] In at least one embodiment, SM2114 includes a programmable streaming processor configured to process tasks represented by, but not limited to, several threads. In at least one embodiment, SM2114 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular group of threads and implements a SIMD architecture, where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instructions. In at least one embodiment, SM2114 implements a SIMT architecture, where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp to enable concurrent processing between warps and serial execution within a warp when threads within a warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to allow equal concurrency among all threads, within and between warps. In at least one embodiment, execution state is maintained for each individual thread, so that threads executing the same instructions can converge and execute in parallel for better efficiency. At least one embodiment of SM2114 is described in further detail in conjunction with FIG. 22.

[0192] In at least one embodiment, MMU 2118 provides an interface between GPC 2100 and a memory partition unit (e.g., partition unit 2022 of FIG. 20), and MMU 2118 provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 2118 provides one or more translation lookaside buffers (TLBs) for performing translations from virtual addresses to physical addresses in memory.

[0193] Figure 22 illustrates a streaming multiprocessor ("SM") 2200, according to at least one embodiment. In at least one embodiment, the SM 2200 is the SM 2114 of Figure 21. In at least one embodiment, the SM 2200 includes, without limitation, an instruction cache 2202, one or more scheduler units 2204, a register file 2208, one or more processing cores ("cores") 2210, one or more special function units ("SFUs") 2212, one or more LSUs 2214, an interconnect network 2216, a shared memory / L1 cache 2218, and any suitable combination thereof. In at least one embodiment, the work distribution unit dispatches tasks for execution on the GPCs of the parallel processing unit (PPU), with each task being assigned to a particular data processing cluster (DPC) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2200. In at least one embodiment, the scheduler unit 2204 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SMs 2200. In at least one embodiment, the scheduler unit 2204 schedules the thread blocks for execution as warps of parallel threads, with each thread block being assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, scheduler unit 2204 manages multiple different thread blocks, allocates warps to the different thread blocks, and then dispatches instructions from multiple different interlocking groups to various functional units (e.g., processing cores 2210, SFUs 2212, and LSUs 2214) during each clock cycle. In at least one embodiment, SM 2200 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0194] In at least one embodiment, a "coordination group" may refer to a programming model for organizing groups of communicating threads, where the programming model allows developers to express the granularity at which threads are communicating, enabling richer and more efficient expression of parallel decompositions. In at least one embodiment, a coordination invocation API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, traditional programming model APIs provide a single simple construct for synchronizing coordinated threads, i.e., a barrier across all threads in a thread block (e.g., the syncthreads() function). However, in at least one embodiment, a programmer may define groups of threads at a granularity finer than a thread block and synchronize within the defined group, enabling higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, coordination groups allow programmers to explicitly define groups of threads at sub-block and multi-block granularity and perform collective operations, such as synchronization, on threads in the coordination group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local context without having to make assumptions about convergence. In at least one embodiment, the interlocking group primitive enables new patterns of interlocking parallelism, including, but not limited to, producer-consumer parallelism, opportunistic parallelism, and global synchronization across a grid of thread blocks.

[0195] In at least one embodiment, dispatch unit 2206 is configured to send instructions to one or more of the functional units, and scheduler unit 2204 includes, without limitation, two dispatch units 2206, allowing two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2204 includes a single dispatch unit 2206 or additional dispatch units 2206.

[0196] In at least one embodiment, each SM2200 includes, in at least one embodiment, a register file 2208 that provides a set of registers to the functional units of the SM2200, including, but not limited to, a register file 2208. In at least one embodiment, the register file 2208 is divided among each of the functional units, such that each functional unit is allocated a dedicated portion of the register file 2208. In at least one embodiment, the register file 2208 is divided among different warps being executed by the SM2200, and the register file 2208 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2200 includes, but is not limited to, a plurality of L processing cores 2210. In at least one embodiment, the SM2200 includes, but is not limited to, a large number (e.g., 128 or more) of individual processing cores 2210. In at least one embodiment, each processing core 2210 includes, but is not limited to, fully pipelined, single-precision, double-precision, and / or mixed-precision processing units, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2210 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0197] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2210. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0198] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and sum matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor cores operate on 16-bit floating-point input data with a 32-bit floating-point sum. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations, resulting in a full-precision product, which is then added using 32-bit floating-point addition with other intermediate products for a 4x4x4 matrix multiplication. In at least one embodiment, the tensor cores are used to perform much larger two-dimensional or even higher-dimensional matrix operations that build up from these smaller elements. In at least one embodiment, an API such as the CUDA-C++ API exposes specialized matrix load, matrix multiply-and-add, and matrix store operations to efficiently use the tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp-level interface assumes a matrix of size 16x16 that spans all 32 threads of a warp.

[0199] In at least one embodiment, each SM2200 includes M SFUs2212 that perform special functions (e.g., but not limited to, attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs2212 include, but are not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs2212 include, but are not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., 2D arrays of texels) from memory and sample texture maps to produce sampled texture values ​​for use in shader programs executed by the SM2200. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2218. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2200 includes, but is not limited to, two texture units.

[0200] In at least one embodiment, each SM 2200 includes, but is not limited to, N LSUs 2214 that implement load and store operations between shared memory / L1 cache 2218 and register file 2208. In at least one embodiment, each SM 2200 includes, but is not limited to, an interconnection network 2216 that connects each of the functional units to register file 2208 and connects LSUs 2214 to register file 2208 and shared memory / L1 cache 2218. In at least one embodiment, interconnection network 2216 is a crossbar that can be configured to connect any of the functional units to any of the registers in register file 2208 and connect LSUs 2214 to memory locations in register file 2208 and shared memory / L1 cache 2218.

[0201] In at least one embodiment, shared memory / L1 cache 2218 is an array of on-chip memory that enables data storage and communication between SM2200 and the primitive engines and between threads in SM2200. In at least one embodiment, shared memory / L1 cache 2218 has, but is not limited to, 128 KB of storage capacity and is in the path from SM2200 to the partition unit. In at least one embodiment, shared memory / L1 cache 2218 is used to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 2218, L2 cache, and memory are backing stores.

[0202] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used as a cache or available for use by programs that do not use shared memory, such as when the shared memory is configured to use half the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, the integration within the shared memory / L1 cache 2218 allows the shared memory / L1 cache 2218 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth, low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computation, a simpler configuration may be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a much simpler programming model. In at least one embodiment, and in the general-purpose parallel computation configuration, the work distribution unit directly assigns and distributes blocks of threads to the DPCs. In at least one embodiment, blocked threads execute the same program using unique thread IDs in computations to ensure each thread produces unique results, use SM2200 to execute the program and perform computations, use shared memory / L1 cache 2218 to communicate between threads, and use LSU2214 to read and write global memory through shared memory / L1 cache 2218 and memory partition unit 2214. In at least one embodiment, when configured for general-purpose parallel computation, SM2200 writes commands that scheduler unit 2204 can use to launch new work on DPCs.

[0203] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in an SoC with one or more other devices, such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.

[0204] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in the chipset of the motherboard.

[0205] Software Constructs for General-Purpose Computing The following diagram describes an exemplary software construct for implementing at least one embodiment, but is not limited to this embodiment.

[0206] FIG. 23 illustrates a software stack for a programming platform, according to at least one embodiment. In at least one embodiment, the programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. In at least one embodiment, the programming platform may be accessible to software developers through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by the Khronos group), SYCL, or the Intel One API. In at least one embodiment, software stack 2300 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0207] In at least one embodiment, programming platform software stack 2300 provides an execution environment for application 2301. In at least one embodiment, application 2301 may include any computer software capable of being run on software stack 2300. In at least one embodiment, application 2301 may include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0208] In at least one embodiment, application 2301 and software stack 2300 run on hardware 2307. In at least one embodiment, hardware 2307 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices supporting a programming platform. In at least one embodiment, such as in the case of CUDA, software stack 2300 may be vendor-specific and compatible only with devices from a particular vendor(s). In at least one embodiment, such as in the case of OpenCL, software stack 2300 may be used with devices from different vendors. In at least one embodiment, hardware 2307 includes a host connected to another device that may be accessed to perform computational tasks via application programming interface (“API”) calls. In at least one embodiment, in contrast to a host in hardware 2307, which may include, but is not limited to, a CPU (but may also include a compute device) and its memory, a device in hardware 2307 may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory.

[0209] In at least one embodiment, the programming platform's software stack 2300 includes, but is not limited to, several libraries 2303, a runtime 2305, and a device kernel driver 2306. In at least one embodiment, each of the libraries 2303 may include data and programming code used by a computer program and utilized during software development. In at least one embodiment, the libraries 2303 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2303 include functionality optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2303 may include, but are not limited to, functionality for performing mathematics, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 2303 are associated with corresponding APIs 2302, which may include one or more APIs that expose the functionality implemented in the libraries 2303.

[0210] In at least one embodiment, application 2301 is written as source code that is compiled into executable code, as described in more detail below in conjunction with FIGS. 28-30. In at least one embodiment, the executable code of application 2301 may run, at least in part, on an execution environment provided by software stack 2300. In at least one embodiment, during execution of application 2301, code that needs to run on the device, as opposed to the host, may be reached. In at least one embodiment, in such cases, runtime 2305 may be called to load and launch the requisite code on the device. In at least one embodiment, runtime 2305 may include any technically feasible runtime system capable of supporting execution of application S01.

[0211] In at least one embodiment, runtime 2305 is implemented as one or more runtime libraries associated with corresponding API(s), shown as API(s) 2304. In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functionality for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functionality may include, but is not limited to, functionality for allocating, deallocating, and copying device memory, as well as transferring data between host and device memory. In at least one embodiment, execution control functionality may include, but is not limited to, functionality for launching functions on the device (sometimes referred to as "kernels" when the functions are global functions callable from the host) and setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0212] In at least one embodiment, the runtime library and corresponding API(s) 2304 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functionality for fine-grained control of the device, while another (or any number of) APIs may expose a higher-level set of such functionality. In at least one embodiment, a high-level runtime API may be built on top of the low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of a language-agnostic runtime API.

[0213] In at least one embodiment, device kernel driver 2306 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 2306 may provide low-level functionality upon which APIs, such as API(s) 2304 and / or other software rely. In at least one embodiment, device kernel driver 2306 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, in the case of CUDA, device kernel driver 2306 may compile non-hardware-specific Parallel Thread Execution (“PTX”) IR code into binary code for a particular target device at runtime (with caching of the compiled binary code), which may be referred to as “finalizing” the code. In at least one embodiment, doing so may allow the finalized code to run on the target device, which may not have been present when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline without requiring the device kernel driver 2306 to compile the IR code at run time.

[0214] FIG. 24 illustrates a CUDA implementation of the software stack 2300 of FIG. 23 , according to at least one embodiment. In at least one embodiment, the CUDA software stack 2400, upon which an application 2401 may be launched, includes a CUDA library 2403, a CUDA runtime 2405, a CUDA driver 2407, and a device kernel driver 2408. In at least one embodiment, the CUDA software stack 2400 executes on hardware 2409, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, California. In at least one embodiment, the CUDA software stack 2400 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0215] In at least one embodiment, application 2401, CUDA runtime 2405, and device kernel driver 2408 may perform functionality similar to application 2301, runtime 2305, and device kernel driver 2306, respectively, described above in conjunction with FIG. 23. In at least one embodiment, CUDA driver 2407 includes a library (libcuda.so) that implements CUDA driver API 2406. In at least one embodiment, similar to CUDA runtime API 2404 implemented by the CUDA runtime library (cudart), CUDA driver API 2406 may expose functionality for, among other things, but not limited to, memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2406 differs from the CUDA runtime API 2404 in that the CUDA runtime API 2404 simplifies device code management by providing implicit initialization, context management (similar to processes), and module management (similar to dynamically loaded libraries). In at least one embodiment, in contrast to the high-level CUDA runtime API 2404, the CUDA driver API 2406 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2406 may expose functionality for context management not exposed by the CUDA runtime API 2404. In at least one embodiment, the CUDA driver API 2406 is also language-independent, e.g., supports OpenCL in addition to the CUDA runtime API 2404. Additionally, in at least one embodiment, the development libraries including the CUDA runtime 2405 may be considered separate from the driver components including the user-mode CUDA driver 2407 and the kernel-mode device driver 2408 (sometimes referred to as the "display" driver).

[0216] In at least one embodiment, CUDA libraries 2403 may include, but are not limited to, math libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that may be utilized by parallel computing applications, such as application 2401. In at least one embodiment, CUDA libraries 2403 may include, among other things, math libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, the cuFFT library for computing fast Fourier transforms (“FFTs”), and the cuRAND library for generating random numbers. In at least one embodiment, CUDA libraries 2403 may include, among other deep learning libraries, such as the cuDNN library of primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0217] FIG. 25 illustrates a ROCm implementation of software stack 2300 of FIG. 23 , according to at least one embodiment. In at least one embodiment, ROCm software stack 2500, upon which application 2501 may be launched, includes language runtime 2503, system runtime 2505, thunk 2507, and ROCm kernel driver 2508. In at least one embodiment, ROCm software stack 2500 executes on hardware 2509, which may include a GPU that supports ROCm and is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, ROCm software stack 2500 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0218] In at least one embodiment, application 2501 may perform functionality similar to application 2301 described above in conjunction with FIG. 23. Additionally, in at least one embodiment, language runtime 2503 and system runtime 2505 may perform functionality similar to runtime 2305 described above in conjunction with FIG. 23. In at least one embodiment, language runtime 2503 and system runtime 2505 differ in that system runtime 2505 is a language-independent runtime that implements ROCr system runtime API 2504 and utilizes the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes an interface for accessing and interacting with an AMD GPU, including functions for, among other things, memory management, execution control via kernel architected dispatch, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, the language runtime 2503, as opposed to the system runtime 2505, is an implementation of a language-specific runtime API 2502 layered on top of the ROCr system runtime API 2504. In at least one embodiment, the language runtime API may include, but is not limited to, the Heterogeneous Compute Interface for Portability (“HIP”) language runtime API, the Heterogeneous Compute Compiler (“HCC”) language runtime API, or the OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA facilities, and in at least one embodiment, the HIP language runtime API includes functionality similar to the functionality of the CUDA runtime API 2404 described above in conjunction with FIG. 24, such as functionality for memory management, execution control, device management, error handling, and synchronization, among others.

[0219] In at least one embodiment, thunk (ROCt) 2507 is an interface 2506 that can be used to interact with an underlying ROCm driver 2508. In at least one embodiment, ROCm driver 2508 is a ROCk driver that is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that implements functionality similar to device kernel driver 2306 described above in conjunction with FIG. 23. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more effectively share system resources through hardware features.

[0220] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2500 above the language runtime 2503 and may provide functionality similar to the CUDA library 2403 described above in conjunction with Figure 24. In at least one embodiment, the various libraries may include, but are not limited to, mathematics, deep learning, and / or other libraries, such as, among others, a hipBLAS library that implements functionality similar to that of CUDA cuBLAS, a rocFFT library for computing FFTs that are similar to CUDA cuFFT, and the like.

[0221] FIG. 26 illustrates an OpenCL implementation of software stack 2300 of FIG. 23 , according to at least one embodiment. In at least one embodiment, OpenCL software stack 2600, upon which application 2601 may be launched, includes OpenCL framework 2610, OpenCL runtime 2606, and driver 2607. In at least one embodiment, OpenCL software stack 2600 executes on non-vendor-specific hardware 2409. In at least one embodiment, OpenCL is supported by devices developed by different vendors, and therefore, specific OpenCL drivers may be required to interoperate with hardware from such vendors. In at least one embodiment, OpenCL software stack 2600 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0222] In at least one embodiment, application 2601, OpenCL runtime 2606, device kernel driver 2607, and hardware 2608 may perform functionality similar to application 2301, runtime 2305, device kernel driver 2306, and hardware 2307, respectively, described above in conjunction with Figure 23. In at least one embodiment, application 2601 further includes an OpenCL kernel 2602 having code to be executed on the device.

[0223] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 2603 and runtime API 2605. In at least one embodiment, the runtime API 2605 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, and the runtime API 2605 may use each context to manage command queues, program objects, and kernel objects for that device, among other things, and share memory objects. In at least one embodiment, the platform API 2603 exposes functions that allow device contexts to be used to, among other things, select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In at least one embodiment, the OpenCL framework also provides various built-in functions (not shown), including, among other things, mathematical functions, relational functions, and image processing functions.

[0224] In at least one embodiment, a compiler 2604 is also included in OpenCL framework 2610. In at least one embodiment, source code may be compiled offline prior to executing the application or online while the application is running. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler 2604, which is included to represent any number of compilers that may be used to compile source code and / or IR code into binary code, such as Standard Portable Intermediate Representation ("SPIR-V") code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline prior to executing such applications.

[0225] FIG. 27 illustrates software supported by a programming platform, according to at least one embodiment. In at least one embodiment, programming platform 2704 is configured to support various programming models 2703, middleware and / or libraries 2702, and frameworks 2701 upon which applications 2700 may rely. In at least one embodiment, applications 2700 may be AI / ML applications implemented using deep learning frameworks such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, the NVIDIA Collective Communication Library (“NCCL”), and / or the NVIDA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computing on the underlying hardware. In at least one embodiment, programming platform 2704 comprises and / or implements, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0226] In at least one embodiment, programming platform 2704 may be one of the CUDA, ROCm, or OpenCL platforms described above in conjunction with FIGS. 24, 25, and 26, respectively. In at least one embodiment, programming platform 2704 supports multiple programming models 2703, which are abstractions of the underlying computing system that allow expression of algorithms and data structures. In at least one embodiment, programming model 2703 may expose features of the underlying hardware to improve performance. In at least one embodiment, programming model 2703 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multi-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and / or Vulcan Compute.

[0227] In at least one embodiment, libraries and / or middleware 2702 provide implementations of the abstractions in programming model 2704. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications beyond software available from programming platform 2704. In at least one embodiment, libraries and / or middleware 2702 may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middleware 2702 may include NCCL and ROCm Communication Collectives Library ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or Eigen libraries for linear algebra, matrix and vector operations, geometric transforms, numerical solvers, and related algorithms.

[0228] In at least one embodiment, application frameworks 2701 depend on libraries and / or middleware 2702. In at least one embodiment, each of application frameworks 2701 is a software framework used to implement a standard structure of application software. Returning to the AI / ML example described above, in at least one embodiment, the AI / ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0229] Figure 28 illustrates compiling code for execution on one of the programming platforms of Figures 23-26, according to at least one embodiment. In at least one embodiment, compiler 2801 receives source code 2800, which includes both host code and device code. In at least one embodiment, compiler 2801 is configured to convert source code 2800 into host executable code 2802 for execution on the host and device executable code 2803 for execution on the device. In at least one embodiment, source code 2800 may be compiled either offline prior to execution of the application or online while the application is running.

[0230] In at least one embodiment, source code 2800 may include code in any programming language supported by compiler 2801, such as C++, C, Fortran, etc. In at least one embodiment, source code 2800 may be included in a single source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single source file may be a .cu file containing CUDA code or a .hip.cpp file containing HIP code. Alternatively, in at least one embodiment, source code 2800 may include multiple source code files rather than a single source file in which the host code and device code are separated.

[0231] In at least one embodiment, compiler 2801 is configured to compile source code 2800 into host executable code 2802 for execution on a host and device executable code 2803 for execution on a device. In at least one embodiment, compiler 2801 performs operations including parsing source code 2800 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code 2800 comprises a single source file, compiler 2801 may separate the device code from the host code in such a single source file, compile the device code and host code into device executable code 2803 and host executable code 2802, respectively, and link device executable code 2803 and host executable code 2802 together in the single file, as described in more detail below with respect to FIG. 29 .

[0232] In at least one embodiment, host executable code 2802 and device executable code 2803 may be in any suitable format, such as binary code and / or IR code. In at least one embodiment, in the case of CUDA, host executable code 2802 may include native object code and device executable code 2803 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 2802 and device executable code 2803 may include target binary code.

[0233] FIG. 29 is a more detailed diagram of compiling code for execution on one of the programming platforms of FIGS. 23-26 , according to at least one embodiment. In at least one embodiment, compiler 2901 is configured to receive source code 2900, compile source code 2900, and output executable file 2910. In at least one embodiment, source code 2900 is a single source file, such as a .cu file, a .hip.cpp file, or another format file, that contains both host code and device code. In at least one embodiment, compiler 2901 may be, but is not limited to, the NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in a .cu file or the HIP compiler for compiling HIP code in a .hip.cpp file.

[0234] In at least one embodiment, compiler 2901 includes compiler front end 2902, host compiler 2905, device compiler 2906, and linker 2909. In at least one embodiment, compiler front end 2902 is configured to separate device code 2904 from host code 2903 in source code 2900. In at least one embodiment, device code 2904 is compiled by device compiler 2906 into device executable code 2908, which may include binary code or IR code, as described. In at least one embodiment, separately, host code 2903 is compiled by host compiler 2905 into host executable code 2907. In at least one embodiment, for NVCC, host compiler 2905 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 2906 may be, but is not limited to, a Low Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 2905 and device compiler 2906 may be, but are not limited to, LLVM-based compilers that output target binary code.

[0235] In at least one embodiment, after compiling source code 2900 into host executable code 2907 and device executable code 2908, linker 2909 links host executable code 2907 and device executable code 2908 together in executable file 2910. In at least one embodiment, the native object code for the host and the PTX or binary code for the device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code.

[0236] 30 illustrates translating source code prior to compiling the source code, according to at least one embodiment. In at least one embodiment, source code 3000 is passed through a translation tool 3001, which translates the source code 3000 into translated source code 3002. In at least one embodiment, a compiler 3003 is used to compile the translated source code 3002 into host executable code 3004 and device executable code 3005, in a process similar to the compilation of source code 2800 by compiler 2801 into host executable code 2802 and device executable code 2803, as described above in conjunction with FIG. 28.

[0237] In at least one embodiment, the translation performed by translation tool 3001 is used to port source code 3000 for execution in an environment different from the environment in which it was originally intended to run. In at least one embodiment, translation tool 3001 may include, but is not limited to, a HIP translator used to "hipify" CUDA code targeted for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the translation of source code 3000 may include parsing source code 3000 and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as described in more detail below in conjunction with FIGS. 31A-32. Returning to the example of hipfifying CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries may be converted to corresponding HIP API calls. In at least one embodiment, the automatic translation performed by translation tool 3001 may sometimes be incomplete and require additional manual effort to fully port source code 3000.

[0238] Configuring GPUs for general-purpose computing The following diagram describes an exemplary architecture for compiling and executing compute source code according to, but not limited to, at least one embodiment.

[0239] 31A illustrates a system 31A00 configured to compile and execute CUDA source code 3110 using different types of processing units, according to at least one embodiment. In at least one embodiment, system 31A00 includes, but is not limited to, CUDA source code 3110, CUDA compiler 3150, host executable code 3170(1), host executable code 3170(2), CUDA device executable code 3184, CPU 3190, CUDA-enabled GPU 3194, GPU 3192, CUDA to HIP translation tool 3120, HIP source code 3130, HIP compiler driver 3140, HCC 3160, and HCC device executable code 3182.

[0240] In at least one embodiment, the CUDA source code 3110 is a set of human-readable code in the CUDA programming language. In at least one embodiment, the CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language, including, but not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, the device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU3190, GPU31192, or another GPGPU. In at least one embodiment, the host code is source code that is executable on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU3190.

[0241] In at least one embodiment, CUDA source code 3110 includes, but is not limited to, any number (including zero) of global functions 3112, any number (including zero) of device functions 3114, any number (including zero) of host functions 3116, and any number (including zero) of host / device functions 3118. In at least one embodiment, global functions 3112, device functions 3114, host functions 3116, and host / device functions 3118 may be intermixed in CUDA source code 3110. In at least one embodiment, each of global functions 3112 is executable on a device and callable from a host. In at least one embodiment, one or more of global functions 3112 may therefore serve as entry points to a device. In at least one embodiment, each of global functions 3112 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3112 define a kernel, which is executable on a device and callable from such a device. In at least one embodiment, the kernel is executed N times in parallel by N different threads on the device during execution, where N is any positive integer.

[0242] In at least one embodiment, each of the device functions 3114 executes on a device and is callable only from such device. In at least one embodiment, each of the host functions 3116 executes on a host and is callable only from such host. In at least one embodiment, each of the host / device functions 3116 defines both a host version of the function that executes on a host and is callable only from such host, and a device version of the function that executes on a device and is callable only from such device.

[0243] In at least one embodiment, CUDA source code 3110 may include, but is not limited to, any number of calls to any number of functions defined via CUDA runtime API 3102. In at least one embodiment, CUDA runtime API 3102 may include, but is not limited to, any number of functions that execute on the host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code 3110 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, a CUDA API includes, but is not limited to, CUDA runtime API 3102, a CUDA driver API, an API for any number of CUDA libraries, etc. In at least one embodiment, and relative to the CUDA Runtime API 3102, the CUDA Driver API is a lower level API, but provides finer grained control of the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0244] In at least one embodiment, CUDA compiler 3150 compiles input CUDA code (e.g., CUDA source code 3110) to generate host executable code 3170(1) and CUDA device executable code 3184. In at least one embodiment, CUDA compiler 3150 is NVCC. In at least one embodiment, host executable code 3170(1) is a compiled version of host code contained in the input source code that is executable on CPU 3190. In at least one embodiment, CPU 3190 can be any processor optimized for sequential instruction processing.

[0245] In at least one embodiment, the CUDA device executable code 3184 is a compiled version of device code included in the input source code that is executable on a CUDA-enabled GPU 3194. In at least one embodiment, the CUDA device executable code 3184 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3184 includes IR code, such as, but not limited to, PTX code, which is further compiled at runtime by a device driver into binary code for a particular target device (e.g., a CUDA-enabled GPU 3194). In at least one embodiment, the CUDA-enabled GPU 3194 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3194 is developed by NVIDIA Corporation of Santa Clara, California.

[0246] In at least one embodiment, the CUDA to HIP translation tool 3120 is configured to translate the CUDA source code 3110 into functionally similar HIP source code 3130. In at least one embodiment, the HIP source code 3130 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension to the C++ programming language that includes, but is not limited to, a functionally similar version of CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, mechanisms for defining global functions 3112, but such HIP programming languages ​​may lack support for dynamic parallelism, and therefore global functions 3112 defined in the HIP code may only be callable from the host.

[0247] In at least one embodiment, HIP source code 3130 includes, but is not limited to, any number of global functions 3112 (including zero), any number of device functions 3114 (including zero), any number of host functions 3116 (including zero), and any number of host / device functions 3118 (including zero). In at least one embodiment, HIP source code 3130 may also include any number of calls to any number of functions specified in HIP runtime API 3132. In at least one embodiment, HIP runtime API 3132 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3102. In at least one embodiment, HIP source code 3130 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP APIs include, but are not limited to, a HIP runtime API 3132, a HIP driver API, an API for any number of HIP libraries, an API for any number of ROCm libraries, and the like.

[0248] In at least one embodiment, the CUDA to HIP translation tool 3120 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, the CUDA calls are calls to functions specified in the CUDA API and the HIP calls are calls to functions specified in the HIP API. In at least one embodiment, the CUDA to HIP translation tool 3120 converts any number of calls to functions specified in the CUDA runtime API 3102 into any number of calls to functions specified in the HIP runtime API 3132.

[0249] In at least one embodiment, the CUDA to HIP translation tool 3120 is a tool known as hipify-perl, which performs a text-based translation process. In at least one embodiment, the CUDA to HIP translation tool 3120 is a tool known as hipify-clang, which performs a more complex and robust translation process for hipify-perl that involves parsing the CUDA code using clang (a compiler front end) and then translating the resulting symbols. In at least one embodiment, properly converting the CUDA code to HIP code may require modifications (e.g., manual edits) in addition to the modifications performed by the CUDA to HIP translation tool 3120.

[0250] In at least one embodiment, HIP compiler driver 3140 is a front end that determines a target device 3146 and then configures a compiler compatible with target device 3146 to compile HIP source code 3130. In at least one embodiment, target device 3146 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3140 may determine target device 3146 in any technically feasible manner.

[0251] In at least one embodiment, if target device 3146 is compatible with CUDA (e.g., CUDA-enabled GPU 3194), HIP compiler driver 3140 generates HIP / NVCC compile commands 3142. In at least one embodiment, and as described in more detail in conjunction with FIG. 31B, HIP / NVCC compile commands 3142 configure CUDA compiler 3150 to compile HIP source code 3130 using, without limitation, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile commands 3142, CUDA compiler 3150 generates host executable code 3170(1) and CUDA device executable code 3184.

[0252] In at least one embodiment, if target device 3146 is not CUDA compatible, HIP compiler driver 3140 generates HIP / HCC compile commands 3144. In at least one embodiment, and as described in more detail in conjunction with FIG. 31C , HIP / HCC compile commands 3144 configure HCC 3160 to compile HIP source code 3130 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile commands 3144, HCC 3160 generates host executable code 3170(2) and HCC device executable code 3182. In at least one embodiment, HCC device executable code 3182 is a compiled version of device code included in HIP source code 3130 that is executable on GPU 3192. In at least one embodiment, the GPU3192 may be any processor that is optimized for parallel instruction processing, is not CUDA compatible, and is HCC compatible. In at least one embodiment, the GPU3192 is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, the GPU3192 is a non-CUDA GPU3192.

[0253] For illustrative purposes only, three different flows that may be implemented in at least one embodiment for compiling CUDA source code 3110 for execution on CPU 3190 and different devices are illustrated in Figure 31A. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3110 for execution on CPU 3190 and CUDA-enabled GPU 3194 without translating CUDA source code 3110 into HIP source code 3130. In at least one embodiment, an indirect CUDA flow translates CUDA source code 3110 into HIP source code 3130 and then compiles HIP source code 3130 for execution on CPU 3190 and CUDA-enabled GPU 3194. In at least one embodiment, the CUDA / HCC flow translates CUDA source code 3110 into HIP source code 3130 and then compiles the HIP source code 3130 for execution on the CPU 3190 and GPU 3192.

[0254] A direct CUDA flow that may be implemented in at least one embodiment is illustrated via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment, and as illustrated by the bubble annotated A1, a CUDA compiler 3150 receives CUDA source code 3110 and a CUDA compile command 3148 that configures the CUDA compiler 3150 to compile the CUDA source code 3110. In at least one embodiment, the CUDA source code 3110 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3148, the CUDA compiler 3150 generates host executable code 3170(1) and CUDA device executable code 3184 (illustrated by the bubble annotated A2). In at least one embodiment, and as illustrated by the bubble annotated A3, host executable code 3170(1) and CUDA device executable code 3184 may execute on CPU 3190 and CUDA-enabled GPU 3194, respectively. In at least one embodiment, CUDA device executable code 3184 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3184 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0255] An indirect CUDA flow that may be implemented in at least one embodiment is illustrated via a dotted line and a series of bubbles annotated B1-B6. In at least one embodiment, and as illustrated by the bubble annotated B1, a CUDA to HIP translation tool 3120 receives CUDA source code 3110. In at least one embodiment, and as illustrated by the bubble annotated B2, the CUDA to HIP translation tool 3120 translates the CUDA source code 3110 into HIP source code 3130. In at least one embodiment, and as illustrated by the bubble annotated B3, a HIP compiler driver 3140 receives the HIP source code 3130 and determines that the target device 3146 is CUDA-capable.

[0256] In at least one embodiment, and as illustrated by the bubble annotated B4, HIP compiler driver 3140 generates HIP / NVCC compile command 3142 and sends both HIP / NVCC compile command 3142 and HIP source code 3130 to CUDA compiler 3150. In at least one embodiment, and as described in more detail in conjunction with FIG. 31B, HIP / NVCC compile command 3142 configures CUDA compiler 3150 to compile HIP source code 3130 using, but not limited to, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile command 3142, CUDA compiler 3150 generates host executable code 3170(1) and CUDA device executable code 3184 (illustrated by the bubble annotated B5). In at least one embodiment, and as illustrated by the bubble annotated B6, host executable code 3170(1) and CUDA device executable code 3184 may execute on CPU 3190 and CUDA-enabled GPU 3194, respectively. In at least one embodiment, CUDA device executable code 3184 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3184 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0257] A CUDA / HCC flow that may be implemented in at least one embodiment is illustrated via a solid line and a series of bubbles annotated C1-C6. In at least one embodiment, and as illustrated by the bubble annotated C1, a CUDA to HIP translation tool 3120 receives CUDA source code 3110. In at least one embodiment, and as illustrated by the bubble annotated C2, the CUDA to HIP translation tool 3120 translates the CUDA source code 3110 into HIP source code 3130. In at least one embodiment, and as illustrated by the bubble annotated C3, a HIP compiler driver 3140 receives the HIP source code 3130 and determines that the target device 3146 is not CUDA-capable.

[0258] In at least one embodiment, HIP compiler driver 3140 generates HIP / HCC compile command 3144 and sends both HIP / HCC compile command 3144 and HIP source code 3130 to HCC 3160 (illustrated by the bubble annotated C4). In at least one embodiment, and as described in more detail in conjunction with FIG. 31C, HIP / HCC compile command 3144 configures HCC 3160 to compile HIP source code 3130 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile command 3144, HCC 3160 generates host executable code 3170(2) and HCC device executable code 3182 (illustrated by the bubble annotated C5). In at least one embodiment, and as illustrated by the bubble annotated C6, host executable code 3170(2) and HCC device executable code 3182 may execute on CPU 3190 and GPU 3192, respectively.

[0259] In at least one embodiment, after CUDA source code 3110 is translated into HIP source code 3130, HIP compiler driver 3140 can then be used to generate executable code for either CUDA-enabled GPU 3194 or GPU 3192 without re-running CUDA to HIP translation tool 3120. In at least one embodiment, CUDA to HIP translation tool 3120 translates CUDA source code 3110 into HIP source code 3130, which is then stored in memory. In at least one embodiment, HIP compiler driver 3140 then configures HCC 3160 to generate host executable code 3170(2) and HCC device executable code 3182 based on HIP source code 3130. In at least one embodiment, the HIP compiler driver 3140 then configures the CUDA compiler 3150 to generate host executable code 3170(1) and CUDA device executable code 3184 based on the stored HIP source code 3130.

[0260] Figure 31B illustrates a system 3104 configured to compile and execute the CUDA source code 3110 of Figure 31A using a CPU 3190 and a CUDA-enabled GPU 3194, according to at least one embodiment. In at least one embodiment, system 3104 includes, but is not limited to, CUDA source code 3110, a CUDA-to-HIP translation tool 3120, HIP source code 3130, a HIP compiler driver 3140, a CUDA compiler 3150, host executable code 3170(1), CUDA device executable code 3184, a CPU 3190, and a CUDA-enabled GPU 3194. In at least one embodiment, system 3104 comprises and / or performs, at least in part, the various components and / or operations described above in conjunction with Figures 1-3.

[0261] 31A , CUDA source code 3110 includes, but is not limited to, any number of global functions 3112 (including zero), any number of device functions 3114 (including zero), any number of host functions 3116 (including zero), and any number of host / device functions 3118. In at least one embodiment, CUDA source code 3110 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0262] In at least one embodiment, CUDA to HIP translation tool 3120 translates CUDA source code 3110 into HIP source code 3130. In at least one embodiment, CUDA to HIP translation tool 3120 converts each kernel call in CUDA source code 3110 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in CUDA source code 3110 into any number of other functionally similar HIP calls.

[0263] In at least one embodiment, HIP compiler driver 3140 determines that target device 3146 is CUDA-enabled and generates HIP / NVCC compile commands 3142. In at least one embodiment, HIP compiler driver 3140 then configures CUDA compiler 3150 via HIP / NVCC compile commands 3142 to compile HIP source code 3130. In at least one embodiment, HIP compiler driver 3140, as part of configuring CUDA compiler 3150, provides access to a HIP-to-CUDA translation header 3152. In at least one embodiment, HIP-to-CUDA translation header 3152 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3150 uses HIP to CUDA translation header 3152 in conjunction with CUDA runtime library 3154 corresponding to CUDA runtime API 3102 to generate host executable code 3170(1) and CUDA device executable code 3184. In at least one embodiment, host executable code 3170(1) and CUDA device executable code 3184 may then be executed on CPU 3190 and CUDA-enabled GPU 3194, respectively. In at least one embodiment, CUDA device executable code 3184 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3184 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

[0264] Figure 31C illustrates a system 3106 configured to compile and execute the CUDA source code 3110 of Figure 31A using a CPU 3190 and a non-CUDA GPU 3192, according to at least one embodiment. In at least one embodiment, system 3106 includes, but is not limited to, CUDA source code 3110, a CUDA to HIP translation tool 3120, HIP source code 3130, a HIP compiler driver 3140, an HCC 3160, host executable code 3170(2), an HCC device executable code 3182, a CPU 3190, and a GPU 3192. In at least one embodiment, system 3106 comprises and / or performs, at least in part, the various components and / or operations described above in conjunction with Figures 1-3.

[0265] 31A , CUDA source code 3110 includes, but is not limited to, any number of global functions 3112 (including zero), any number of device functions 3114 (including zero), any number of host functions 3116 (including zero), and any number of host / device functions 3118. In at least one embodiment, CUDA source code 3110 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0266] In at least one embodiment, CUDA to HIP translation tool 3120 translates CUDA source code 3110 into HIP source code 3130. In at least one embodiment, CUDA to HIP translation tool 3120 converts each kernel call in CUDA source code 3110 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3110 into any number of other functionally similar HIP calls.

[0267] In at least one embodiment, HIP compiler driver 3140 then determines that target device 3146 is not CUDA-enabled and generates HIP / HCC compile commands 3144. In at least one embodiment, HIP compiler driver 3140 then configures HCC 3160 to execute HIP / HCC compile commands 3144 to compile HIP source code 3130. In at least one embodiment, HIP / HCC compile commands 3144 configure HCC 3160 to use, without limitation, HIP / HCC runtime library 3158 and HCC headers 3156 to generate host executable code 3170(2) and HCC device executable code 3182. In at least one embodiment, HIP / HCC runtime library 3158 corresponds to HIP runtime API 3132. In at least one embodiment, HCC header 3156 includes, without limitation, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3170(2) and HCC device executable code 3182 may execute on CPU 3190 and GPU 3192, respectively.

[0268] FIG. 32 illustrates an exemplary kernel translated by the CUDA to HIP translation tool 3120 of FIG. 31C , according to at least one embodiment. In at least one embodiment, the CUDA source code 3110 partitions the overall problem that a given kernel is designed to solve into relatively coarse-grained subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each subproblem is partitioned into relatively finer pieces that can be solved in parallel and in concert by threads within the thread block. In at least one embodiment, threads within a thread block can coordinate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.

[0269] In at least one embodiment, the CUDA source code 3110 organizes the thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks, where in at least one embodiment each thread block includes, but is not limited to, any number of threads and the grid includes, but is not limited to, any number of thread blocks.

[0270] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the dimensions of the grid in which the kernel will execute for a given kernel call and associated stream are specified using CUDA kernel invocation syntax 3210. In at least one embodiment, CUDA kernel invocation syntax 3210 includes the following syntax: "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<<...>>>" construct inserted between the kernel name ("KernelName") and the parenthesized list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel launch syntax 3210 includes, but is not limited to, CUDA launch function syntax instead of execution configuration syntax.

[0271] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure including, but not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., "threadIdx").

[0272] In at least one embodiment, and with respect to CUDA kernel invocation syntax 3210, "SharedMemorySize" is an optional argument that specifies the number of bytes in shared memory that will be dynamically allocated per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3210, SharedMemorySize defaults to 0. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3210, "Stream" is an optional argument that specifies the associated stream and defaults to 0 to specify the default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0273] In at least one embodiment, CUDA source code 3110 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd." In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines a threadsPerBlock variable as 16×16 and a numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then defines the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);." In at least one embodiment, and in accordance with CUDA kernel invocation syntax 3210, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16 x N / 16, where each thread block has dimensions 16 x 16. In at least one embodiment, each thread block includes 256 threads, and the grid is created with enough blocks to have one thread per matrix element, and each thread in such grid executes the kernel MatAdd to perform one pairwise addition.

[0274] In at least one embodiment, while translating CUDA source code 3110 into HIP source code 3130, CUDA to HIP translation tool 3120 translates each kernel call in CUDA source code 3110 from CUDA kernel launch syntax 3210 to HIP kernel launch syntax 3220 and converts any number of other CUDA calls in source code 3110 into any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3220 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments have the same meaning in HIP kernel invocation syntax 3220 as in CUDA kernel invocation syntax 3210 (described earlier in this specification). In at least one embodiment, the arguments SharedMemorySize and Stream are required in HIP kernel invocation syntax 3220 and optional in CUDA kernel invocation syntax 3210.

[0275] In at least one embodiment, the portion of HIP source code 3130 illustrated in FIG. 32 is identical to the portion of CUDA source code 3110 illustrated in FIG. 32, except for the kernel call that causes kernel MatAdd to execute on the device. In at least one embodiment, kernel MatAdd is defined in HIP source code 3130 with the same "__global__" declaration specifier that kernel MatAdd is defined in CUDA source code 3110. In at least one embodiment, the kernel call in HIP source code 3130 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in CUDA source code 3110 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);".

[0276] FIG. 33 illustrates the non-CUDA GPU 3192 of FIG. 31C in more detail, according to at least one embodiment. In at least one embodiment, the GPU 3192 is developed by AMD Corporation of Santa Clara. In at least one embodiment, the GPU 3192 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the GPU 3192 is configured to execute graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3192 is configured to execute non-graphics related operations. In at least one embodiment, the GPU 3192 is configured to execute both graphics related and non-graphics related operations. In at least one embodiment, the GPU 3192 may be configured to execute device code included in the HIP source code 3130.

[0277] In at least one embodiment, GPU 3192 includes, but is not limited to, a number of programmable processing units 3320, a command processor 3310, an L2 cache 3322, a memory controller 3370, a DMA engine 3380(1), a system memory controller 3382, a DMA engine 3380(2), and a GPU controller 3384. In at least one embodiment, each programmable processing unit 3320 includes, but is not limited to, a workload manager 3330 and a number of compute units 3340. In at least one embodiment, command processor 3310 reads commands from one or more command queues (not shown) and distributes the commands to workload manager 3330. In at least one embodiment, for each programmable processing unit 3320, the associated workload manager 3330 distributes work to the compute units 3340 included in the programmable processing unit 3320. In at least one embodiment, each compute unit 3340 may execute any number of thread blocks, but each thread block executes on a single compute unit 3340. In at least one embodiment, a workgroup is a thread block.

[0278] In at least one embodiment, each compute unit 3340 includes, but is not limited to, any number of SIMD units 3350 and shared memory 3360. In at least one embodiment, each SIMD unit 3350 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3350 includes, but is not limited to, a vector ALU 3352 and a vector register file 3354. In at least one embodiment, each SIMD unit 3350 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 3360.

[0279] In at least one embodiment, the programmable processing units 3320 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3320 includes any amount of dedicated graphics hardware in addition to, but not limited to, compute units 3340. In at least one embodiment, each programmable processing unit 3320 includes, but is not limited to, any number of geometry processors (including zero), any number of rasterizers (including zero), any number of render back ends (including zero), a workload manager 3330, and any number of compute units 3340.

[0280] In at least one embodiment, the compute units 3340 share an L2 cache 3322. In at least one embodiment, the L2 cache 3322 is partitioned. In at least one embodiment, the GPU memory 3390 is accessible by all of the compute units 3340 in the GPU 3192. In at least one embodiment, the memory controller 3370 and the system memory controller 3382 facilitate data transfers between the GPU 3192 and a host, and the DMA engine 3380(1) enables asynchronous memory transfers between the GPU 3192 and such a host. In at least one embodiment, the memory controller 3370 and the GPU controller 3384 facilitate data transfers between the GPU 3192 and other GPUs 3192, and the DMA engine 3380(2) enables asynchronous memory transfers between the GPU 3192 and other GPUs 3192.

[0281] In at least one embodiment, GPU 3192 includes any quantity and type of system interconnects facilitating data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to GPU 3192, without limitation. In at least one embodiment, GPU 3192 includes any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices, without limitation. In at least one embodiment, GPU 3192 may include any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3192 implements a memory subsystem, including any quantity and type of memory controllers (e.g., memory controller 3370 and system memory controller 3382) and memory devices (e.g., shared memory 3360), which may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU 3192 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 3322), each of which may be private to or shared among any number of components (e.g., SIMD unit 3350, compute unit 3340, and programmable processing unit 3320).

[0282] FIG. 34 illustrates how threads of an exemplary CUDA grid 3420 are mapped to the different compute units 3340 of FIG. 33, according to at least one embodiment. In at least one embodiment, and for illustrative purposes only, the grid 3420 has a GridSize of BX×BY×1 and a BlockSize of TX×TY×1. In at least one embodiment, the grid 3420 therefore includes, but is not limited to, (BX*BY) thread blocks 3430, and each thread block 3430 includes, but is not limited to, (TX*TY) threads 3440. The threads 3440 are illustrated in FIG. 34 as squiggly arrows.

[0283] In at least one embodiment, grid 3420 is mapped to programmable processing unit 3320(1), which includes, but is not limited to, compute units 3340(1) through 3340(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 3430 are mapped to compute unit 3340(1), and the remaining thread blocks 3430 are mapped to compute unit 3340(2). In at least one embodiment, each thread block 3430 may include, but is not limited to, any number of warps, with each warp mapped to a different SIMD unit 3350 in FIG. 33.

[0284] In at least one embodiment, warps in a given thread block 3430 may synchronize with each other and communicate through shared memory 3360 included in the associated compute unit 3340. For example, and in at least one embodiment, warps in thread block 3430(BJ,1) may synchronize with each other and communicate through shared memory 3360(1). For example, and in at least one embodiment, warps in thread block 3430(BJ+1,1) may synchronize with each other and communicate through shared memory 3360(2).

[0285] FIG. 35 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture, proprietary languages, allowing developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and to implement custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs that conform to ISO C++, with which developers may be familiar. DPC++ incorporates the SYCL standard from the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the underlying concepts, portability, and efficiency of OpenCL, allowing code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL can enable single-source development, where C++ template functions contain both host and device code, allowing developers to build complex algorithms using OpenCL acceleration and then reuse them across their source code for different types of data.

[0286] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across a variety of hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across a variety of hardware targets, and DPC++ compatibility tools can be used to migrate CUDA applications to DPC++ multi-platform programs. In at least one embodiment, a DPC++ base toolkit includes a DPC++ compiler for deploying applications across a variety of hardware targets, a DPC++ library for increasing productivity and performance across CPUs, GPUs, and FPGAs, a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications, or any suitable combination thereof.

[0287] In at least one embodiment, the DPC++ programming model is utilized solely for one or more aspects related to programming the CPU and accelerator by using modern C++ features to express parallelism using a programming language called Data Parallel C++. The DPC++ programming language is utilized for code reuse for the host (e.g., CPU) and accelerator (e.g., GPU or FPGA), using a single source language, and execution and memory dependencies can be clearly communicated. Mapping within the DPC++ code can be used to migrate applications to run on the hardware or set of hardware devices that best accelerate the workload. Even on platforms that do not have available accelerators, a host may be available to simplify development and debugging of device code.

[0288] In at least one embodiment, CUDA source code 3500 is provided as input to a DPC++ compatibility tool 3502 to generate a human-readable DPC++ 3504. In at least one embodiment, the human-readable DPC++ 3504 includes inline comments generated by the DPC++ compatibility tool 3502 that guide a developer as to how and / or where to modify the DPC++ code to complete the coding and tune for desired performance 3506, thereby generating DPC++ source code 3508. In at least one embodiment, the DPC++ 3504 comprises and / or implements, at least in part, various components and / or operations described above in conjunction with FIGS.

[0289] In at least one embodiment, CUDA source code 3500 is or includes a set of human-readable source code in the CUDA programming language. In at least one embodiment, CUDA source code 3500 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA) and may run on one or more processor cores of the device or may include a more parallelizable workflow. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, some or all of the host code and device code may execute in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 3500 described with respect to FIG. 35 may follow CUDA source code described elsewhere herein.

[0290] In at least one embodiment, DPC++ compatibility tool 3502 refers to an executable tool, program, application, or any other suitable type of tool used to facilitate the migration of CUDA source code 3500 to DPC++ source code 3508. In at least one embodiment, DPC++ compatibility tool 3502 is a command-line based code migration tool available as part of the DPC++ tool kit used to port existing CUDA source to DPC++. In at least one embodiment, DPC++ compatibility tool 3502 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, called a human-readable DPC++ 3504. In at least one embodiment, the human-readable DPC++ 3504 includes comments generated by DPC++ compatibility tool 3502 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when CUDA source code 3500 calls a CUDA API that does not have a similar DPC++ API; other instances where user intervention is required are described in more detail below.

[0291] In at least one embodiment, a workflow for migrating CUDA source code 3500 (e.g., an application or portions thereof) includes creating one or more compilation database files, migrating CUDA to DPC++ using a DPC++ compatibility tool 3502, completing and validating the migration, thereby generating DPC++ source code 3508, and compiling the DPC++ source code 3508 with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used when a Makefile executes and stores them in a compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile commands into DPC-compatible commands.

[0292] In at least one embodiment, intercept-build is a utility script that intercepts the build process, captures compilation options, macro definitions, and include paths, and writes this data to a compilation database file. In at least one embodiment, the compilation database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3502 parses the compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files, where the commands may include required compilation flags, the directories may include paths to header files, and the files may include paths to CUDA files.

[0293] In at least one embodiment, the DPC++ compatibility tool 3502 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, the DPC++ compatibility tool 3502 is available as part of a tool kit. In at least one embodiment, the DPC++ tool kit includes an intercept-build tool. In at least one embodiment, the intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the intercept-built tool is used by the DPC++ compatibility tool 3502 to migrate the CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ compatibility tool 3502 generates a human-readable DPC++ 3504, which may be DPC++ code that, when generated by the DPC++ compatibility tool 3502, may not compile with the DPC++ compiler and may require additional plumbing to identify portions of the code that were not correctly migrated, which may involve manual intervention, such as by a developer. In at least one embodiment, the DPC++ compatibility tool 3502 provides hints or tools embedded in the code to help the developer manually migrate additional code that may not be automatically migrated. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0294] In at least one embodiment, the DPC++ compatibility tool 35002 may successfully migrate all portions of CUDA code to DPC++, with only an optional step to manually review and tune the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3502 directly generates DPC++ source code 3508 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3502. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that may be optionally tuned by a developer for performance, readability, maintainability, various other considerations, or any combination thereof.

[0295] In at least one embodiment, one or more CUDA source files are at least partially migrated to DPC++ source files using DPC++ compatibility tool 3502. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files include<cuda.h> Header files can be used to print text<stdio.h> In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as follows or related to the following:

number

number

[0296] In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 3502 parses the CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID; correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0297] In at least one embodiment, and with respect to the CUDA source file presented above, there are two vectors A and B that are initialized, and the vector addition result is placed into vector C as part of VectorAddKernel(). In at least one embodiment, DPC++ compatibility tool 3502 converts CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via local IDs as part of migrating CUDA code to DPC++ code. In at least one embodiment, the DPC++ code generated by DPC++ compatibility tool 3502 can be optimized, for example, by reducing the dimensionality of nd_item, thereby increasing memory and / or processor utilization.

[0298] In at least one embodiment, and with respect to the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device(), to which a device and context are passed, relying on SYCL concepts such as platform, device, context, and queue. In at least one embodiment, a SYCL platform can have multiple devices (e.g., host and GPU devices), a device can have multiple queues to which jobs can be submitted, each device can have a context, and a context can have multiple devices and manage shared memory objects.

[0299] In at least one embodiment, and with respect to the CUDA source file presented above, the main() function invokes or calls VectorAddKernel() to add two vectors A and B together and store the result in vector C. In at least one embodiment, the CUDA code to invoke VectorAddKernel() is replaced by DPC++ code to submit the kernel to a command queue for execution. In at least one embodiment, the command group handler cgh passes the data, synchronization, and computation to be submitted to the queue, and parallel_for is called for the number of global elements and the number of work items in the work group for which VectorAddKernel() is called.

[0300] In at least one embodiment, and with respect to the CUDA source files presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as is without modification by DPC++ compatibility tool 3502. In at least one embodiment, DPC++ compatibility tool 3502 modifies CUDA APIs for memory setup and / or host calls to execute the kernel on the acceleration device. In at least one embodiment, and with respect to the CUDA source files presented above, a corresponding human-readable DPC++ 3504 (which may be compiled, for example) is written as follows or relates to the following:

number

number

number

[0301] In at least one embodiment, human-readable DPC++ 3504 refers to the output generated by DPC++ compatibility tool 3502 and may be optimized in one way or another. In at least one embodiment, human-readable DPC++ 3504 generated by DPC++ compatibility tool 3502 may be manually edited by a developer after migration to make it more maintainable, for performance, or other considerations. In at least one embodiment, DPC++ code generated by DPC++ compatibility tool 3502, such as the disclosed DPC++, may be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which may be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer may manually edit the DPC++ code generated by DPC++ compatibility tool 3502 and replace the use of uniform shared memory with accessors. In at least one embodiment, DPC++ compatibility tool 3502 has options to change how it migrates CUDA code to DPC++ code. In at least one embodiment, DPC++ compatibility tool 3502 is verbose because it uses a generic template to migrate CUDA code to DPC++ code that works for many cases.

[0302] In at least one embodiment, the CUDA to DPC++ migration workflow includes steps for preparing for migration using an intercept-build script, steps for performing the migration of the CUDA project to DPC++ using DPC++ compatibility tools 3502, steps for manually reviewing and editing the migrated source files for completion and correctness, and steps for compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including, but not limited to, the migrated APIs not returning error codes (CUDA code can return error codes that can then be consumed by the application, but SYCL uses exceptions to report errors and therefore does not use error codes to surface errors), CUDA compute-capability dependent logic is not supported by DPC++, and statements may not be removed. In at least one embodiment, scenarios where DPC++ code requires manual intervention may include, but are not limited to, error code logic being replaced with (*,0) code or commented out, equivalent DPC++ API not being available, CUDA compute power dependent logic, hardware dependent API (clock()), missing features, unsupported APIs, execution time measurement logic, addressing built-in vector type conflicts, cuBLAS API migration, etc.

[0303] In at least one embodiment, one or more techniques described herein utilize a oneAPI programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, the oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language for data-parallel programming productivity. In at least one embodiment, the DPC++ programming language is based at least in part on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is a programming model such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, the oneAPI and / or oneAPI programming model comprise and / or implement, at least in part, the various components and / or operations described above in conjunction with FIGS. 1-3.

[0304] In at least one embodiment, oneAPI and / or the oneAPI programming model are utilized to interact with various accelerator architectures, GPU architectures, processor architectures, and / or variations thereof. In at least one embodiment, oneAPI includes a set of libraries that implement various functionality. In at least one embodiment, oneAPI includes at least a oneAPI DPC++ library, a oneAPI math kernel library, a oneAPI data analysis library, a oneAPI deep neural network library, a oneAPI collective communication library, a oneAPI threading building blocks library, a oneAPI video processing library, and / or variations thereof.

[0305] In at least one embodiment, the oneAPI DPC++ library, also referred to as oneDPL, is a library that implements algorithms and functions for accelerating DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions, such as parallel algorithms, iterators, function object classes, range-based APIs, and / or variations thereof. In at least one embodiment, oneDPL implements one or more classes and / or functions of the C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions.

[0306] In at least one embodiment, the oneAPI Math Kernel Library, also referred to as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more Basic Linear Algebra Subprograms (BLAS) and / or linear algebra package (LAPACK) dense linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more fast Fourier transform (FFT) functions.

[0307] In at least one embodiment, the oneAPI Data Analysis Library, also referred to as oneDAL, is a library that implements various data analysis applications and distributed computation. In at least one embodiment, oneDAL implements various algorithms for pre-processing, transformation, analysis, modeling, validation, and decision-making for data analysis in batch, online, and distributed computational modes. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements DPC++ API extensions to the traditional C++ interface to enable GPU usage for various algorithms.

[0308] In at least one embodiment, the oneAPI Deep Neural Network Library, also referred to as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural network, machine learning, and deep learning functions, algorithms, and / or variations thereof.

[0309] In at least one embodiment, the oneAPI Collective Communication Library, also referred to as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL builds on lower-level communication middleware, such as the message passing interface (MPI) and libfabric. In at least one embodiment, oneCCL enables a set of deep learning-specific optimizations, such as prioritization, persistent behavior, out-of-order execution, and / or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU capabilities.

[0310] In at least one embodiment, the oneAPI Threading Building Blocks library, also referred to as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is utilized for task-based shared parallel programming on a host. In at least one embodiment, oneTBB implements general parallel algorithms. In at least one embodiment, oneTBB implements concurrent containers. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler independent and usable on various processors, such as GPUs, PPUs, CPUs, and / or variations thereof.

[0311] In at least one embodiment, the oneAPI Video Processing Library, also referred to as oneVPL, is a library utilized to accelerate video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media-centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing.

[0312] In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language is a programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the DPC++ programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are implemented using the oneAPI programming model using the DPC++ programming language.

[0313] It should be noted that while the exemplary embodiments described herein may relate to the CUDA programming model, the techniques described herein may be utilized with any suitable programming model, such as HIP, oneAPI (e.g., using oneAPI-based programming to perform or implement the methods disclosed herein), and / or variations thereof.

[0314] In at least one embodiment, one or more components of the systems and / or processors disclosed above can be in communication with one or more CPUs, ASICs, GPUs, FPGAs, or other hardware, circuit elements, or integrated circuit components, including, for example, an upscaler or upsampler for upscaling an image, an image blender or image blender component for blending, mixing, or adding images together, a sampler for sampling an image (e.g., as part of a DSP), a neural network circuit configured to implement an upscaler for upscaling an image (e.g., from a low-resolution image to a high-resolution image), or other hardware for modifying or generating an image, frame, or video to adjust its resolution, size, or pixels, and one or more components of the systems and / or processors disclosed above can use the components described in this disclosure to implement the methods, operations, or instructions for generating or modifying images.

[0315] At least one embodiment of the present disclosure may be described in view of the following provisions. 1. One or more circuits for implementing an application programming interface (API) to identify one or more versions of one or more portions of one or more libraries to be used with the API. A processor comprising: 2. The processor of clause 1, wherein the API is for identifying one or more versions of one or more portions of one or more libraries by indicating the location in memory of one or more instructions for the function based at least in part on the version of the function indicated in the API. 3. The processor of clause 1 or 2, wherein the API is for receiving one or more data values ​​indicating the one or more versions. 4. A processor as described in any one of clauses 1 to 3, wherein the API is for receiving one or more first data values ​​to indicate a base name and one or more second data values ​​to indicate one or more versions. 5. A processor according to any one of clauses 1 to 4, wherein the one or more libraries are runtime libraries to be implemented by one or more circuits. 6. A processor according to any one of clauses 1 to 5, wherein the one or more libraries are drivers to be implemented by one or more circuits. 7. One or more processors for implementing an application programming interface (API) to identify one or more versions of one or more portions of one or more libraries to be used with the API. A system comprising: 8. The system described in clause 7, wherein the API is for identifying one or more versions of one or more portions of one or more libraries by indicating one or more memory locations of one or more instructions for implementing one or more versions of the one or more portions of the one or more libraries based at least in part on one or more data values ​​indicated in the API. 9. The system of clause 7 or 8, further comprising one or more data values ​​indicating a base name and version number to be used by the API to identify one or more versions. 10. A system described in any one of clauses 7 to 9, wherein the API is for receiving one or more parameters including data indicating at least a name value and a numerical value, the name value and the numerical value being for use by the API to identify one or more versions of one or more parts of one or more libraries. 11. The system of any one of clauses 7 to 10, wherein the one or more libraries are drivers to be executed by one or more processors. 12. A system according to any one of clauses 7 to 11, wherein the one or more libraries are runtime libraries to be executed by one or more processors. 13. When at least partially implemented by one or more processors, causing the one or more processors to at least: Identifying one or more versions of one or more portions of one or more libraries to be used with one or more application programming interfaces (APIs) A machine-readable medium storing one or more APIs that cause the 14. The machine-readable medium of clause 13, further comprising one or more instructions that, when executed by one or more processors, cause the one or more processors to identify one or more versions of one or more portions of one or more libraries based at least in part on one or more data values ​​indicated in one or more APIs, the data values ​​including information to indicate names that can be used to identify the one or more versions. 15. The machine-readable medium of clause 13 or 14, further comprising one or more instructions that, when executed by one or more processors, cause the one or more processors to identify one or more versions of one or more portions of one or more libraries based at least in part on one or more data values ​​indicated in one or more APIs, the data values ​​including information to indicate a numeric value usable to identify the one or more versions. 16. The machine-readable medium of any one of clauses 13 to 15, wherein the one or more APIs are for identifying the one or more versions based at least in part on one or more parameters indicated in the one or more APIs. 17. The machine-readable medium of any one of clauses 13 to 16, wherein the one or more APIs are for causing the one or more processors to identify one or more versions of one or more portions of one or more libraries by at least indicating the location in memory of one or more instructions. 18. The machine-readable medium of any one of clauses 13 to 17, wherein the one or more libraries are drivers to be executed by one or more processors. 19. In response to an application programming interface (API), identifying one or more versions of one or more portions of one or more libraries to be used with the API. A method comprising: 20. The method of clause 19, wherein the one or more versions are to be identified based at least in part on one or more parameters to the API, the one or more parameters including data indicating at least a string usable to identify the one or more versions. 21. The method of clause 19 or 20, wherein the one or more versions are identified based at least in part on one or more parameters to the API, the one or more parameters including data indicating at least a numerical value that can be used to identify the one or more versions. 22. The method of any one of clauses 19 to 21, further comprising identifying one or more versions by indicating the location in memory of one or more instructions for one or more versions of one or more parts of one or more libraries based at least in part on one or more data values ​​indicated in the API. 23. The method of any one of clauses 19 to 22, wherein one or more parts comprise one or more sets of instructions to be performed by one or more software programs together with the API. 24. The method of any one of clauses 19 to 23, wherein the one or more libraries are runtime libraries comprising instructions that, when executed, implement the API. 25. The method of any one of clauses 19 to 24, wherein the one or more libraries are drivers, the drivers comprising one or more instructions for implementing the API.

[0316] Other variations are within the scope of the present disclosure. Thus, while the disclosed techniques are susceptible to various modifications and alternative constructions, several illustrative examples thereof have been shown in the drawings and described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the particular disclosed form or forms, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure as defined in the appended claims.

[0317] The use of the terms "a," "an," and "the," and similar referents in the context of describing the disclosed embodiments (particularly in the context of the claims that follow) should be construed to cover both the singular and the plural and not as defining terms, unless otherwise stated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" should be construed as open-ended terms (meaning "including, but not limited to"), unless otherwise indicated. The term "connected," when unmodified and referring to a physical connection, should be construed as partially or fully contained within, attached to, or joined to one another, even if there are intervening elements. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of individually referring to each separate value falling within the range, unless otherwise stated herein and unless each separate value is incorporated into the specification as if it were individually recited herein. Use of the term "set" (e.g., "set of items") or "subset" should be construed as a non-empty collection having one or more members, unless otherwise stated or constrained by context. Furthermore, unless otherwise stated or constrained by context, the term "subset" of a corresponding set does not necessarily refer to a strict subset of the corresponding set; a subset and a corresponding set may be equivalent.

[0318] Connective language, such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C," is understood in the context in which it is generally used to indicate that an item, term, etc. may be either A or B or C, or any non-empty subset of the set A, B, and C, unless specifically stated otherwise or clearly contradicted by context. For example, in the illustrative example of a set having three members, the connective phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such connective language does not generally imply that some embodiments require that at least one of A, at least one of B, and at least one of C each be present. Further, unless stated otherwise or negated by context, the term "plurality" refers to a plurality (e.g., "a plurality of items" refers to multiple items). A plurality of items is at least two but may be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, the phrase "based on" means "based at least in part on," and not "based only on."

[0319] The operations of processes described herein may be performed in any suitable order unless otherwise stated herein or otherwise clearly contradicted by context. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems comprised of executable instructions and implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that collectively execute on one or more processors, by hardware, or by a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, e.g., in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions), but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media that store executable instructions (or have other memory for storing executable instructions) that, when executed by (e.g., as a result of) one or more processors of a computer system, cause the computer system to perform the operations described herein. The set of non-transitory computer-readable storage media, in at least one embodiment, comprises a plurality of non-transitory computer-readable storage media, wherein one or more individual non-transitory storage media of the plurality of non-transitory computer-readable storage media do not contain all of the code, but the plurality of non-transitory computer-readable storage media collectively store all of the code.In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors, e.g., a non-transitory computer-readable storage medium stores the instructions, a main central processing unit ("CPU") executes some of the instructions, and a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of a computer system have separate processors, with different processors executing different subsets of the instructions.

[0320] Thus, in at least one embodiment, a computer system is configured to implement one or more services that, singly or collectively, perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that enables the performance of the operations. Further, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment, is a distributed computer system comprising multiple devices that operate in different ways, such that a distributed computer system performs the operations described herein, and such that no single device performs all of the operations.

[0321] The use of any illustrative or exemplary language (e.g., "such as") provided herein is intended only to further clarify embodiments of the disclosure and does not limit the scope of the disclosure unless otherwise stated. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0322] All references cited herein, including publications, patent applications, and patents, are hereby incorporated by reference to...

Claims

1. One or more circuits implementing an application programming interface (API) that identify one or more versions of one or more portions of one or more libraries to be used with the API. Equipped with A processor, wherein the one or more libraries are drivers to be implemented by the one or more circuits.

2. 2. The processor of claim 1, wherein the API identifies the one or more versions of the one or more portions of the one or more libraries by at least indicating a location in memory of one or more instructions for the function based at least in part on a version of the function indicated in the API.

3. The processor of claim 1 , wherein the API receives one or more data values ​​to indicate the one or more versions.

4. 2. The processor of claim 1, wherein the API receives one or more first data values ​​to indicate a base name and one or more second data values ​​to indicate the one or more versions.

5. 2. The processor of claim 1, wherein the one or more libraries are runtime libraries to be implemented by the one or more circuits.

6. One or more processors implementing an application programming interface (API) that identify one or more versions of one or more portions of one or more libraries to be used with the API. Equipped with The system, wherein the one or more libraries are drivers to be executed by the one or more processors.

7. 7. The system of claim 6, wherein the API identifies the one or more versions of the one or more portions of the one or more libraries by at least indicating one or more memory locations of one or more instructions for implementing the one or more versions of the one or more portions of the one or more libraries based at least in part on one or more data values ​​indicated to the API.

8. The system of claim 6 , further comprising one or more data values ​​indicating a base name and a version number to be used by the API to identify the one or more versions.

9. 7. The system of claim 6, wherein the API receives one or more parameters including data indicating at least a name value and a numerical value, the name value and the numerical value being used by the API to identify the one or more versions of the one or more portions of the one or more libraries.

10. 7. The system of claim 6, wherein the one or more libraries are runtime libraries to be executed by the one or more processors.

11. A machine-readable medium having stored thereon one or more application programming interfaces (APIs), comprising: if the one or more APIs are at least partially implemented by one or more processors, causing the one or more processors to at least identify one or more versions of one or more portions of one or more libraries to be used with the one or more APIs; A machine-readable medium, wherein the one or more libraries are drivers to be executed by the one or more processors.

12. 12. The machine-readable medium of claim 11, further comprising one or more instructions that, when executed by the one or more processors, cause the one or more processors to identify the one or more versions of the one or more portions of the one or more libraries based at least in part on one or more data values ​​indicated in the one or more APIs, the data values ​​including information to indicate names that can be used to identify the one or more versions.

13. 12. The machine-readable medium of claim 11, further comprising one or more instructions that, when executed by the one or more processors, cause the one or more processors to identify the one or more versions of the one or more portions of the one or more libraries based at least in part on one or more data values ​​indicated in the one or more APIs, the data values ​​including information to indicate a numeric value usable to identify the one or more versions.

14. 12. The machine-readable medium of claim 11, wherein the one or more APIs identify the one or more versions based at least in part on one or more parameters indicated in the one or more APIs.

15. 12. The machine-readable medium of claim 11, wherein the one or more APIs cause the one or more processors to identify the one or more versions of the one or more portions of the one or more libraries by at least indicating a location in memory of one or more instructions.

16. In response to an application programming interface (API), identifying one or more versions of one or more portions of one or more libraries to be used with said API. Including, The method, wherein the one or more libraries are drivers, the drivers including one or more instructions for implementing the API.

17. 17. The method of claim 16, wherein the one or more versions are identified based at least in part on one or more parameters to the API, the one or more parameters including data for indicating at least one string usable to identify the one or more versions.

18. 17. The method of claim 16, wherein the one or more versions are identified based at least in part on one or more parameters to the API, the one or more parameters including data indicating at least one numerical value usable to identify the one or more versions.

19. 17. The method of claim 16, further comprising identifying the one or more versions by indicating locations in memory of one or more instructions of the one or more versions of one or more portions of one or more libraries based at least in part on one or more data values ​​indicated in the API.

20. 17. The method of claim 16, wherein the one or more portions include one or more sets of instructions to be performed by one or more software programs in conjunction with the API.

21. 17. The method of claim 16, wherein the one or more libraries are runtime libraries that contain instructions that, when executed, implement the API.

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