Signal classification system, signal classification method, and data signal classification system

Abstract

The signal classification system includes an input that receives input waveform data, a memory, and one or more processors configured to execute a program that causes the one or more processors to perform the following operations: generate a ramp sweep signal from the input waveform data, locate data bursts within the input waveform data using a burst detector, receive a signal from the burst detector, and store in the memory cyclic loop image data having the input waveform data as Y-axis data and the ramp sweep signal as X-axis data, and utilize a machine learning system to receive and classify the cyclic loop image data. The signal classification method includes the following operations: generate a ramp sweep signal from the input waveform data, locate data bursts within the input waveform data, store cyclic loop image data for data bursts having the input waveform data as Y-axis data and the ramp sweep signal as X-axis data, and utilize the machine learning system to receive and classify the cyclic loop image data.

Description

[Technical Field]

[0001] This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 038,040, filed June 11, 2020, entitled "PAM4 Circular Eye Image Display for Waveform Data," U.S. Provisional Patent Application No. 63 / 039,360, filed June 15, 2020, entitled "Read / Write Burst Separation and Measurement Using Novel Circular Eye Plots and Machine Learning," U.S. Provisional Patent Application No. 63 / 041,041, filed June 18, 2020, entitled "Circular Eye Image Display for Waveform Data," and U.S. Provisional Patent Application No. 63 / 177,930, filed April 21, 2021, entitled "Circular Eye for Measuring or Tuning Optical Transmitters Using Machine Learning," each of which is incorporated herein by reference in its entirety.

[0002] This disclosure is related to the following patent applications: U.S. Patent Application No. 17 / 345,342 (Atty-Dkt No. 12222-US1), filed June 11, 2021, entitled "System and Method for Signal Separation and Classification Using Recursive Loop Images," U.S. Patent Application No. 17 / 345,283 (Atty-Dkt No. 12223-US1), filed June 11, 2021, entitled "Recursive Loop Image Display of Waveform Data," and U.S. Patent Application No. 17 / 345,312 (Atty-Dkt No. 12224-US2), filed June 11, 2021, entitled "System and Method for Recursive Loop Image Display of Multi-Level Signals for Measurement and Machine Learning."

[0003] The present disclosure relates to identifying data on a bidirectional bus, and more particularly to identifying and classifying data direction. [Background technology]

[0004] In some situations, it is useful to identify bursts of data on an acquired bidirectional bus and classify which direction the data signal is traveling. If test and measurement equipment, such as an oscilloscope, had unlimited channels, it would be possible to acquire the necessary command bus lines and separate the read and write bursts on such a bidirectional bus. However, this is a challenge when only one or two probes are available.

[0005] An example of such signals is found in DDR5 memory, the Double Data Rate Memory Version 5 standard. This represents the next major shift in increasing computing memory speed and density while maintaining similar DIMM (dual in-line memory module) dimensions. System channel characteristics, as seen at the probe point, are significantly different between read and write operations. Read signals must be processed and measured separately from write signals, and therefore must be separated.

[0006] Users often use eye diagrams (so-called because the opening between two waveforms resembles an eye) to analyze signals. However, as memory speeds increase on the same printed circuit board (PCB) material, the waveform diagram of write data bursts becomes a "closed" eye when they arrive at the memory. DDR5 DRAM supports data rates from 3200MT / s to 6400MT / s. This data rate increase is achieved without changing the signaling scheme of the data pins; that is, the DQ bus remains single-ended, the same as DDR3 / 4. However, because DDR5 channels have many impedance mismatch points, increased inter-symbol interference (ISI) due to reflections is expected. At data rates of 4800MT / s and above, the data eye at the DRAM probe points (e.g., solder balls) is expected to close. The receiver of DDR5 DRAM implements a 4-tap DFE that equalizes the DQ signals to mitigate this problem.

[0007] While the PCB DIMMs and board size on which the memory is mounted remain the same, the size of these memories has doubled. Additionally, oscilloscopes typically only have four channels, limiting the number of parallel data, clock, and command / address lines that can be acquired for analysis and testing.

[0008] Typically, the DQS clock strobe signal and the DQ data signals are the most important for analysis. Therefore, two probes are required. The DQS signal has a preamble before each data burst, which can be used to identify the start of a read or write data burst. Previous DDR DRAM protocols, such as DDR3 / DDR4, had a phase difference between read and write bursts. DQS and DQ were center-aligned in write bursts and edge-aligned in read bursts. The command bus also had separate WE (Write Enable), RAS (Row Access Select), and CAS (Column Address Select) signals, which were used to identify read or write bursts. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Patent Publication No. 2003 / 0235103 [Patent Document 2] European Patent Application Publication No. 3624113 [Patent Document 3] US Patent Application Publication No. 2017 / 0285986 Summary of the Invention [Problem to be solved by the invention]

[0010] However, in DDR5, the WE / CAS / RAS signals are replaced with a compact 14-pin Command / Address (CA) bus, which requires decoding to understand the read / write command. This typically means accessing all 14 CA pins, which is not practical. Also, there is no longer a clear phase difference between the DQS and DQ signals like in DDR4 / DDR3. In DDR5, the DQS and DQ signals on the write path can have a fixed offset of up to three UIs (unit intervals), which is programmed during the boot-up process.

[0011] Therefore, what is needed is a method that uses only the data lines to identify whether a burst signal is a read or a write.Embodiments of the disclosed apparatus and method address shortcomings in the prior art. [Means for solving the problem]

[0012] The disclosed embodiments address the problem of identifying bursts of data acquired on a bidirectional bus and classifying the direction the data is propagating. For DDR5 memory, oscilloscopes typically lack the number of channels, or devices under test (DUTs) lack sufficient space, to connect enough probes to acquire the command bus lines necessary to distinguish between read and write data bursts. However, system channel characteristics, as seen at the probe points, are significantly different for read and write operations. Read signals must be processed and measured separately from write signals. The present embodiments address the need to perform this separation using only one or two probes. One key feature of these embodiments is the use of a unique circular loop image, which is sparser than a traditional eye diagram. The circular loop image emphasizes the edges of the signal, which contain most of the information characterizing the system response.

[0013] These embodiments utilize an apparatus and method for creating a circular loop image as an XY plot of an incoming signal. The circular loop image of the embodiments facilitates multiple measurements and provides a simplified image suitable for use as input to an existing pre-trained neural network or other machine learning system, for example, for classifying reads versus writes in a particular data burst. Embodiments may also have applications for other binary-coded signals, such as non-return-to-zero (NRZ), or multi-level signals, such as pulse amplitude modulated signals (e.g., PAM4). The present embodiments also address the use of circular loop images in conjunction with machine learning to perform read and write separation for memory systems. Figure 1 illustrates an example of a circular loop diagram 10.

[0014] The embodiment uses a simple yet robust algorithm to create an XY plot of the input signal. The vertical Y axis consists of the signal itself. For DDR5 applications, this signal is typically either the DQ data burst signal or the DQS data strobe clock signal. The horizontal X axis consists of a sweep signal created by processing the DQ or DQS signal. This processing creates a unique linear or semi-linear ramp sweep signal only at the edge transitions of the data pattern. During periods of constant signal level (such as long highs or long lows), no ramp sweep signal occurs. This is a unique approach that differs from standard Lissajous figures. The embodiment automatically arranges these ramp sweep signals so that the path of the XY signal forms a closed loop, with all rising edges contained within the upper part of the loop and all falling edges contained within the lower part of the loop.

[0015] Because the edges of a system contain most of the information that defines the system's transfer function, this simple image produces a cyclic display that captures every cycle of the waveform in a single image, yet eliminates many of the redundant, cluttered data points found in a typical eye diagram. The resulting plot may be similar in appearance to a magnetic hysteresis BH plot, depending on the waveform characteristics. However, there are significant differences in the creation of horizontal ramp signals, how they are generated, and how they are applied to PRBS (pseudo-random binary sequence) data patterns.

[0016] The primary advantages are its simplicity of implementation and its robustness. The overall approach describes several methods for creating an X-axis ramp-like signal. The specific embodiment described below with respect to FIG. 8 addresses the simplicity of the process in terms of complexity and processing speed. This approach may result in distortion of the edge shape. For machine learning recognition purposes, this method improves computational speed while also enabling classification by machine learning algorithms. For example, a machine learning system can classify read and write operations in a memory system by examining only the DQS or DQ signals.

[0017] It should be noted that while the following description addresses memory signal classifications, embodiments are not limited to this application. No such limitation should be inferred. Embodiments may also be used for other bidirectional systems in which system characteristics may differ depending on the direction of signal propagation. Furthermore, signals may consist of any two-level binary-encoded signal, such as a read or write data burst signal or a non-return-to-zero (NRZ) signal, or a pulse amplitude modulated signal with more than two levels, such as PAM4.

[0018] The circular loop image is a simplified plot that specifically illustrates signal attributes such as system response, nonlinearity of rising edges compared to falling edges, SNR, amplitude, reflection delay, and reflection coefficient. The resulting XY image reduces unnecessary waveform display and displays only the key attributes necessary to classify the differences between system response during write and read operations. The small image size and simplified closed-loop path representing the system serve as ideal input for existing pre-trained image processing neural networks or other machine learning networks or systems. The circular loop image can also be used to perform multiple measurements such as those described above.

[0019] Once the DQS and DQ bursts are classified and separated into separate waveforms, these waveforms can be further processed by operations such as creating a virtual test point filter to move the view of the actual probe points, which is amplitude versus time. This removes steps due to memory load reflections that are not aligned with the transmission line. This does not actually remove reflections, but rather removes the delay due to reflections, which results in no steps on the rising and falling edges. However, the amplitude is usually increased by reflections. In the case of DDR5, a DFE equalizer is applied to the separated write bursts, as well as other possible applications. Finally, the processed waveforms are processed and further analyzed by DDR compliance or jitter analysis application software.

[0020] Thus, there is a need, and the present embodiments address, for a method to identify whether a burst signal is a read or a write using only the DQS or DQ data lines. These embodiments also utilize a unique method for creating a circular loop image instead of a standard eye diagram, facilitating multiple measurements. The circular loop provides a simplified image suitable for input into existing pre-trained neural networks for classifying read and write signal bursts. [Brief explanation of the drawings]

[0021] [Figure 1] Figure 1 shows a representation of a circular loop image. [Figure 2] Figure 2 shows an example of a data burst signal in a DDR5 memory. [Figure 3] Figure 3 shows an example of a data burst signal of a DDR5 memory with reflections from a mismatched load. [Figure 4] Figure 4 shows an example of a DDR5 memory data burst signal with reflections from a mismatched load and inter-symbol interference (ISI) losses on the trace. [Figure 5] FIG. 5 shows the trace between the test probe and the mismatched load for a write operation. [Figure 6] FIG. 6 shows the trace between the test probe and the mismatched load for lead operation. [Figure 7] Figure 7 shows a graph comparing the trace loss modeled with the exponential equation with two actual measured traces. [Figure 8] FIG. 8 illustrates an embodiment of a system for creating and analyzing recursive loop images. [Figure 9] Figure 9 shows an example of an oscilloscope screen of the waveform used to create the circulation loop diagram. [Figure 10] FIG. 10 shows an example of a circular loop image. [Figure 11] Figure 11 shows an example of a DQ random data signal with no reflections or ISI and the resulting circular loop image. [Figure 12] FIG. 12 shows an example of a measurement based on a standard YT trace display. [Figure 13] FIG. 13 shows an example of measuring the reflection delay. [Figure 14] FIG. 14 shows an example of measuring the coefficients. [Figure 15] FIG. 15 shows an example of measuring the reflection coefficient using a circular loop diagram. DETAILED DESCRIPTION OF THE INVENTION

[0022] Figures 2-4 show examples of DQS burst signals. Figure 2 shows an example of an ideal DQS burst signal 12 in a DDR5 memory system. Figure 3 shows an example of a DDR5 memory DQS burst signal 14 including reflections from a mismatched load. Figure 4 shows an example of a DDR5 DQS signal 16 with reflections from a mismatched load and trace inter-symbol interference (ISI) loss.

[0023] The system transfer function is typically different between read and write data bursts, allowing the distinction between read and write data bursts. System hardware has different characteristics during read and write operations. The load at the end of the transmission line may be different. The voltage swing of the memory transmitter may be different from the voltage swing of the SOC (System on Chip) transmitter. The reflection delay time may be different.

[0024] Furthermore, the probe is often physically connected to the interposer board, far away from the SOC, in close proximity to the memory chip. Figure 5 shows a trace 20 on a device under test between a probe 22 from a test and measurement instrument 26 and a mismatched memory load 24. The trace 20 is short, and its signal is observed at the probe 22 point with a large reflection. This results in a high reflection coefficient and a small delay. This causes the pulse amplitude at the probe point to be larger than the incident pulse amplitude from the SOC 28. However, a long trace 30 from the SOC to the probe 22 point will have losses that will cause a loss of signal amplitude from the SOC. Thus, the ISI losses in the trace tend to reduce the pulse amplitude at the probe point, and the memory's reflection coefficient tends to increase the amplitude at this point. This occurs because the impedance of the memory load is larger than the impedance of the transmission line. This is the situation in a typical DDR5 system being probed with an interposer 32 during a write operation.

[0025] Figure 6 illustrates a read operation. In this case, the memory 24 is the transmitter. The probe 22 is typically connected through an interposer 32 and is only separated from the memory 24 by a short, low-loss trace 34. This causes the incident pulse at the probe 22 to be similar in amplitude to the one transmitted by the memory. The signal then propagates down a long trace 36 to the SOC 28, which has a large impedance mismatch that reflects some signal back to the probe 22. The long trace 36 is lossy, reducing the amplitude of the reflected signal. This reflected signal returns to the probe 22, but typically sees an increased amplitude at the probe because the impedance of the SOC 28's load is greater than the characteristic impedance of the transmission line. In this case, the delay time is much longer, and the loading of the SOC may be different from that of the memory when it was a receiver.

[0026] The reflection delay time and reflection coefficient value can be calculated by making several cursor measurements on the waveform acquired by the probe 22 and test and measurement equipment 26, such as an oscilloscope. Then, if the SOC load is known, the impedance of the trace can be calculated for a given reflection coefficient and the above SOC load value. Alternatively, if the trace impedance, i.e., characteristic impedance, is known, the SOC impedance can be calculated using the following standard transmission line theory equation:

number

[0027] Generally speaking, in the example DDR5 model, the main system characteristics that affect pulse shape are 1) long trace losses, which can be represented by a single parameter, α; 2) reflection delay, τ; 3) reflection coefficient, Γ; and 4) transmitter output voltage gain constant, K. Looking at several industry examples, this model appears to work fairly well in defining system equations that can simulate the types of waveforms observed in these systems. These parameters can be configured into a frequency domain expression, shown in Equation 6. This model approximates the response of the system shown in Figures 5 and 6.

[0028] The first step in creating the modeled transfer function H is to model the long trace length between the SOC and the probe point, as shown in (2).

number

[0029] The value of α is a constant that determines the loss characteristics of different PCB trace lengths. The exponential term defines only the magnitude response. To assign the appropriate phase response, the minimum phase response can be obtained from Equation 4. [Formula 4] h=rceps(ifft(H)) where rceps is a Matlab function that returns the minimum phase impulse response of Y. [Formula 5] H=fft(h) where H is the modeled minimum phase frequency response of the PCB trace from the SOC to the probe point.

number

[0030] The preceding discussion has explained the system modeling and measurement issues required for read / write separation in DDR5 memory, providing a basis for understanding why embodiments of the present disclosure are needed.

[0031] When configuring a machine learning application, a commonly used first step is data reduction. For example, the more parameters and data inputs to a machine learning algorithm, the more difficult it becomes to arrive at a unique, correct answer. Furthermore, the more input data, the more training time and runtime processing is required. Therefore, the first step is to examine all input parameters and data and determine which parameters and which data have the least impact on the outcome. These items are to be removed as inputs to the system.

[0032] The above discussion presented a set of four most basic elements necessary to understand the shapes commonly found in DDR waveforms. These four parameters were α (representing the ISI of the long trace in the model), τ (representing the reflection delay time), Γ (representing the reflection coefficient), and K (representing the constant amplitude difference between the SOC transmission amplitude during a write operation and the memory transmission amplitude from the memory during a read operation). These three parameters, except for K, can affect ISI, or inter-symbol interference. The value of α represents the ISI due to trace loss, while the values ​​of the reflection coefficient and delay represent the ISI due to reflections caused by mismatched load impedances.

[0033] Figure 8 shows an embodiment of a system used to classify data burst signals. The system's pulse response can be derived from a variety of different perspectives. For example, a waveform plot of amplitude as a function of time is one approach. However, providing this perspective to a machine learning system has its drawbacks due to the variety of bit rates, data patterns, and how they are incorporated. Similarly, signals can be viewed from frequency and cepstrum domains. However, using these perspectives as inputs to a machine learning system presents challenges because signal patterns interfere with the perspective on the system's response. This requires deconvolution. There are many issues and details that make implementing these perspectives difficult to set up and handle.

[0034] For example, complex clock recovery techniques may be required, and complex gating and interpolation may be required as part of the deconvolution process. Other issues include the short reflection delay of the interposer, which causes resolution problems in cepstrum and spectral displays. Large ISI makes it more difficult to extract key features.

[0035] The present embodiments address the problems associated with these other methods by generating a circular loop image that captures all edge transitions in a single closed-loop XY plot. This circular loop image simply cycles along the same path throughout the entire length of the input data record. The input data may be a clock signal during a burst interval, such as in a DDR5 memory system. The input signal may also be a random data pattern, such as a DQ burst interval in a DDR5 memory system. Although not shown here, the input signal may be interpolated or decimated to increase or decrease the number of samples to fill the resulting image or to reduce the amount of data used in artificial intelligence (AI) / machine learning systems. Data reduction (commonly referred to as dimensionality reduction) allows machine learning systems to function more efficiently and accurately. The system may also subtract the mean of the input signal from the input signal to remove DC offset from the input signal.

[0036] As mentioned above, the input signal can be any kind of waveform with high and low levels (the positions of which are determined by the system clock) with edge transitions. The X-axis signal can be thought of as a linear sweep ramp or ramp-like signal derived from the input signal. It can be thought of in terms of a standard oscilloscope horizontal sweep ramp signal. This ramp is directly synchronous with the input signal because it depends on it for generation.

[0037] The related patent applications referenced above detail various approaches to generating circular loop images and their associated data. Regarding one specific embodiment of circular loop image creation, a horizontal sweep ramp is generated by first passing the input signal through a circuit (referred to herein as clipper circuits 42 and 43) that creates a rectangular pulse representation of the input signal. In one embodiment, this circuit multiplies the signal by a large value, e.g., 500, and then assigns the signal to an ideal high-value constant that is the same as the nominal high level of the input voltage if the signal is greater than zero. If the signal is less than or equal to zero, it assigns the signal to a low-level constant value. In the embodiment of FIG. 8, the input signal DQ passes through clipping circuit 43, and the DQS signal passes through clipper circuit 42.

[0038] After the clipping circuit, the signal passes through short-term integrators 40 and 45. In this embodiment, the integrators take the form of boxcar filters. The width of the boxcar filters is set equal to the width of one UI of the input signal. Because there are an integer number of coefficients, the number of coefficients at a given sample rate can be equal to the UI interval or an amount of sample intervals less than one UI width. This creates a positive-going ramp-like signal during the positive edge of the input signal and a negative-going ramp-like signal during the falling edge of the input signal. For long intervals of several UIs where there is no edge, there is no ramp, which is a unique feature of this approach. As a result, only positive and negative edge locations appear in the closed-loop path of the recursive image.

[0039] All data for multiple UI intervals without edges is present in the image, but only at two locations on the screen, so only the edges characteristic of the system model are fully displayed in a very simple loop path within the image. When ISI is high, the variation in the path traced around the loop spreads out. This causes the center of the circular loop to become more closed. For clock signals that change every UI, the entire waveform data set repeatedly traces the same closed-loop path on the XY circular loop display. This is also a novel aspect, as all edges are traced along the loop path. This results in a circular loop image without the significant overlay of positive and negative edges that obscure much of the signal detail seen in traditional eye diagrams.

[0040] The burst detector 44 detects bursts of read and write data. Each burst of data must be detected and processed so that it can be classified as a read or write operation. For DDR5, burst detection is achieved by examining the DQS clock signal, which remains zero until the burst begins. There is a preamble consisting of a multi-UI period, which has two or more consecutive lows. This preamble occurs in the DQS signal, which is the basis for detecting the start of the burst. After that, the DQS signal within the burst alternates between high and low for each UI. The DQ signal has random high and low periods within each UI.

[0041] Burst gates 46 and 48 control the data used to generate the circular loop image based on the signal from the burst detector. In the embodiment of Figure 8, the burst gates have a multiplier between the input signal and a 1 or 0 input from the burst detector. The main system controller 76 sequences the entire system, processing and classifying only one burst at a time.

[0042] The system generates one or two plots, such as 50 and 52. One plot, 52, has the acquired DQS on the vertical axis and a swept ramp output signal from the clipper and boxcar filter applied to the DQS signal on the horizontal x-axis. The second plot, 50, has the DQ signal on the y-axis and applies a swept ramp signal created from the cyclic loop algorithm to the DQ signal. These two plots represent two relatively low-resolution cyclic loop images that can be used as inputs to a deep learning neural network for classification training. These two plots can also be rendered on a display screen to allow a user to analyze and measure various characteristics of the input waveforms, DQ and DQS. In some embodiments, the system may store the cyclic loop image data in memory (not shown) and does not necessarily render the cyclic loop images on a display.

[0043] The system may perform multiple measurements using the measurement unit 54, which may be performed by observing the circular loop image or the data used to form the circular loop image. These measurements may optionally be used as parameter inputs for some machine learning. Some measurements may be used to identify whether the system model is configured for reads or writes. The measurement unit 54 may be comprised of one or more hardware circuits, software measurement routines, or any combination of hardware and software implementations.

[0044] Examples of measurements include reflection delay, reflection coefficient, ISI, signal-to-noise ratio (SNR), and nonlinearity. The system obtains the angle between two radial lines from the center of the loop to the correct point on the closed loop to obtain the reflection delay. This angle is converted to the time delay of the reflection. As rising and falling edges appear on the XY display, the ratio of the incident signal to the reflected signal can be measured and the reflection coefficient can be calculated. This is most accurate and easy to do when the trace ISI is small. Large trace ISI can obscure where to start measuring and reduce accuracy. The relative value of ISI can be obtained by examining the overall outer diameter of the loop and the inner diameter of the loop. This is due to noise, to some extent. However, in a noise-free system, the ISI does not translate to a single, thin line of the loop path. In contrast, high ISI closes the loop and increases the thickness of the loop path.

[0045] Furthermore, from these other measurements, the system can calculate the signal-to-noise ratio. Transmitter nonlinearity causes the edge shape or slope of the falling and rising edges to be different, but this nonlinearity is easily manifested in the symmetry of the circulation loop. The measurement can express this linearity as a single number, which can serve as an input for machine learning.

[0046] Another aspect of the embodiment is the combination of measurements with the displayed image. The various measurements described above serve as input parameters for machine learning. One way to input them into an existing trained neural net that processes the image is to incorporate them into the image as bar graphs or other forms of digitally encoded data. In this way, the extracted parameters work in conjunction with the actual waveform image to aid in the classification process.

[0047] The machine learning system 56 receives the circular loop image as input. The primary purpose of the system or network 56 is to examine the circular loop image along with any digitally encoded extraction parameters placed on the image and then classify the waveform depicted in the image as either a light burst or a light burst. There may be a training phase 57 in which multiple examples of read and write circular loop images are provided to the network to train the network on how to classify them. After the training period, the input image is analyzed by the trained network and classified as either a read or a light.

[0048] The machine learning system 56 may have the following inputs: a circular loop XY plot image showing the circular closed-loop path, with all edges overlaid on this path; extracted measurement parameters, if any, may be provided as a separate image in some other form, or inserted into the circular loop image as a vector of numbers, or other forms may be devised. If inserted into the image, they may take the form of a simple bar graph, multiple bar graphs, a pi chart-shaped object, etc. The user input menu 72 allows a user, as part of the training process 57, to, for example, look at the circular loop image of the acquired bursts and tell the machine which ones are leads and which ones are writes. Once the machine understands which ones are, it can then classify them in the runtime process 58.

[0049] This is useful for systems where there is little difference between reads and writes, or where the key model assumptions above are not the same, such as placing the probe near the mid bus where there is no interposer and the delay of the read reflection is the same as the write reflection. The system also has a user input menu 74 that allows input of various system parameters such as memory load, trace impedance, and interposer use and location.

[0050] The machine learning system 56 outputs the classified data burst signals as either read or write. Blocks 66 and 62 create a multi-burst waveform. In one embodiment, this may involve concatenating each detected burst into a single waveform containing only read or write bursts. After the multi-burst waveform is created, de-embedding filters 64 and 68 may be calculated for each waveform. Because the system transfer functions for reads and writes are different, there are different filters for each waveform. These filters also move the probe test points on the interposer to virtual probe test points on the memory or SOC. In most cases, a DFE equalizer 70 may be applied to the DQ signals. The machine learning system 56 may also provide the results of measurement 60.

[0051] The system controller 76 may consist of a general-purpose processor that controls and sequences the entire system, or a processor on the test and measurement instrument, or a processor distributed among them. The system controller may also be distributed across multiple processors, cloud computing, etc. These processors may be configured to execute code (programs) that cause the processors to provide all processing functions related to measurements and neural networks or other types of machine learning that may be employed. Of course, any part of this system may be implemented with other types of processors, such as ASICs, GPUs, FPGAs, etc.

[0052] Figure 9 shows an example of the waveforms used to create the circular loop image on an oscilloscope screen. In this display, the waveform that appears somewhat sinusoidal is the DQS clock signal 80. The output signal of the clipper is shown as a square wave 82. The ramp signal is the output signal of the boxcar filter 84.

[0053] Figure 10 shows an example of a circular loop image. On the left is a DQS write signal with high ISI. In the center is a DQS read signal with visible reflections. On the right is an overlay of both the read and write DQS. Figure 11 shows an example of a DQ random pulse level signal 90 and its associated ramp sweep signal 92 (the ramps occur only during edge transitions of the DQ signal), as well as a circular loop image 94 consisting of the DQ signal 90 and the ramp sweep signal 92.

[0054] The reflection delay between the probe and the memory load can be measured from a standard YT trace display, as shown in Figure 12. The trace delay is calculated from Equation 7 as follows: [Formula 7] Delay = T / 2

[0055] Figure 13 shows how to measure trace delay using circular loop imaging, where delay is expressed as θ in degrees. In both cases, the waveforms are shown without trace ISI loss for ease of display, showing the point at which to measure the phase angle θ for calculating reflection delay time.

[0056] The delay time may be calculated using Equation 8. One full pass through the loop is 360 degrees, which is one cycle. One cycle is two UIs or two bits for NRZ type signals. [Formula 8] Delay = θ / (360*bit rate) where θ is in degrees, delay is in seconds, and the data rate of the signal is the bit rate for NRZ type signals.

[0057] The reflection coefficient of a short trace between the probe and the memory can be measured on a standard YT-type waveform display, as shown in Figure 14. The reflection coefficient is then calculated as follows: [Formula 9] Γ=(v2-v1) / v1

[0058] Once the reflection coefficient is known, the impedance Z of the load or the characteristic impedance Z can be calculated if either of these is known. [Formula 10] Z=Z0*(1+Γ) / (1-Γ)

[0059] The reflection coefficient can be measured using circular loop imaging, as shown in FIG.

[0060] In this way, the system can create and utilize new circular loop images, optionally including bar graphs with encoded measurements. These images can then be used in a deep learning environment to characterize and classify signals by separating and classifying them for analysis or other uses.

[0061] Aspects of the disclosed technology may operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The terms "controller" or "processor" herein contemplate microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology may be implemented as computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. Computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, etc. Those skilled in the art will appreciate that the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed technology, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein.

[0062] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0063] "Computer storage media" means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) and other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage and other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable medium implemented in any technology. "Computer storage media" excludes signals themselves and transitory forms of signal transmission.

[0064] A communication medium means any medium usable for communicating computer-readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0065] Additionally, the description of this application refers to specific features. It should be understood that the disclosure herein includes all possible combinations of these specific features. For example, if a specific feature is disclosed in connection with a particular embodiment, that feature can also be used in connection with other embodiments, to the extent possible.

[0066] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the circumstances preclude this possibility. Example

[0067] The following examples are provided to aid in understanding the technology disclosed in this application. Embodiments of the technology may include one or more of the examples described below, and any combination thereof.

[0068] Example 1 is a system for classifying signals, comprising an input unit for receiving input waveform data, a memory, and one or more processors, wherein the one or more processors are configured to execute a program that causes the one or more processors to perform the following processes: generating a ramp sweep signal from the input waveform data; identifying positions of data bursts in the input waveform data using a burst detection unit; receiving a signal from the burst detection unit and storing circulating loop image data in the memory, with the input waveform data as Y-axis data and the ramp sweep signal as X-axis data; and receiving the circulating loop image data and classifying the data bursts using a machine learning system.

[0069] A second embodiment is the system of the first embodiment, further comprising a test and measurement instrument that acquires the input waveform data from a device under test.

[0070] Example 3 is the system of either Example 1 or 2, wherein the program that causes the one or more processors to perform the process of generating the ramp sweep signal from the input waveform data further includes a program that causes the one or more processors to perform the process of generating a rectangular pulse signal from the input waveform data using a clipper, and the process of generating a ramp signal using an integrating circuit based on the rectangular pulse signal and sending the ramp signal to the burst gate.

[0071] Example 4 is the system of example 3, wherein the integrator circuit comprises a boxcar filter.

[0072] Example 5 is the system of any one of Examples 1 to 4, further comprising a measurement unit that performs measurement using the circulating loop image data.

[0073] Example 6 is the system of example 5, wherein the measurements include one or more of reflection delay, reflection coefficient, inter-symbol interference, signal-to-noise ratio, and nonlinearity.

[0074] Example 7 is the system of example 5, wherein the measurement unit transmits the measurements to the machine learning system.

[0075] Example 8 is the system of any of Examples 1 to 7, further comprising a concatenation unit for creating a multi-burst waveform from the classified data bursts from the machine learning system.

[0076] Example 9 is the system of example 8, further comprising a filter applied to the multiburst waveform.

[0077] Example 10 is the system of any of Examples 1 to 9, further comprising a system controller that coordinates operation of the system.

[0078] Example 11 is a method for classifying a signal, the method comprising: generating a ramp sweep signal from input waveform data; locating a data burst within the input waveform data; storing cyclic loop image data for the data burst, with the input waveform data as Y-axis data and the ramp sweep signal as X-axis data; and receiving the cyclic loop image data and classifying the data burst using a machine learning system.

[0079] Example 12 is the method of example 11, further comprising receiving system parameters from a user.

[0080] A thirteenth embodiment is the method of either the eleventh or twelfth embodiment, wherein the process of generating the ramp sweep signal includes a process of generating a rectangular pulse signal from the input waveform data, and a process of integrating the rectangular pulse signal to generate the ramp sweep signal.

[0081] Example 14 is the method of example 13, wherein the process of integrating the rectangular pulse signal is performed by a boxcar filter.

[0082] Example 15 is the method of any of Examples 11 to 14, further comprising performing measurements using the cyclic loop image data.

[0083] Example 16 is the method of example 15, wherein the measuring comprises measuring one or more of a reflection delay, a reflection coefficient, an inter-symbol interference, a signal-to-noise ratio, and a nonlinearity.

[0084] Example 17 is the method of Example 15, further comprising sending the measurement values ​​to the machine learning system, wherein the machine learning system classifies the data burst using the circulating loop image data and the measurement values.

[0085] Example 18 is the method of any of Examples 11 to 17, further comprising creating a multi-burst waveform from the classified data bursts from the machine learning system.

[0086] Example 19 is a method of any of Examples 11 to 18, further comprising a process for training the machine learning system, the training process including a process for supplying a plurality of cyclical loop images, a process for receiving user input for classifying each of the cyclical loop images, a process for testing the machine learning system by having the machine learning system provide a classification and verifying the classification against the user input, and a process for repeating the testing process until the machine learning system correctly classifies the cyclical loop images.

[0087] Example 20 is a system for classifying data signals, comprising: a ramp generation unit that generates a ramp sweep signal from input waveform data; a burst detection unit that identifies the position of a data burst within the input waveform data; a burst gate that receives a signal from the burst detection unit and stores circulating loop image data in a memory, the circulating loop image data having the input waveform data as Y-axis data and the ramp sweep signal as X-axis data; and a machine learning system that receives the circulating loop image data and classifies the data burst.

[0088] Example 21 is the system of Example 20, wherein the input waveform data is captured from a memory device under test, and the machine learning system classifies the data bursts resulting from either a write operation or a read operation on the memory device under test.

[0089] All features disclosed in the specification, abstract, claims and drawings, and all steps in any disclosed method or process, may be combined in any combination, except where at least some of such features or steps are mutually exclusive combinations. Each feature disclosed in the specification, abstract, claims and drawings may be replaced by an alternative feature serving the same, equivalent, or similar purpose, unless expressly stated otherwise.

[0090] While specific embodiments of the disclosed technology have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims.

Claims

1. 1. A system for classifying a signal, comprising: an input for receiving input waveform data; Memory and one or more processors wherein the one or more processors: generating a ramp sweep signal from the input waveform data; using a burst detector to locate data bursts within the input waveform data; a process of receiving a signal from the burst detection unit and storing in the memory circulating loop image data in a form in which the input waveform data is used as Y-axis data and the ramp sweep signal is used as X-axis data; utilizing a machine learning system to receive said cyclical loop image data and classify said data bursts; a signal classification system configured to execute a program that causes the one or more processors to perform the steps of:

2. The signal classification system of claim 1 , further comprising a measurement unit that performs measurements using the circulating loop image data and transmits the measurements to the machine learning system.

3. 1. A method for classifying a signal, comprising: generating a ramp sweep signal from the input waveform data; locating data bursts within the input waveform data; storing cyclic loop image data for said data burst, with said input waveform data as Y-axis data and said ramp sweep signal as X-axis data; utilizing a machine learning system to receive said cyclical loop image data and classify said data bursts; A signal classification method comprising:

4. The method further comprises performing measurements using the circulating loop image data and transmitting the measurements to the machine learning system; 4. The method of claim 3, wherein the machine learning system classifies the data bursts using the recursive loop image data and the measurements.

5. training the machine learning system; The training process comprises: providing a plurality of circulating loop image data; receiving user input to classify each of the circulating loop image data; testing the machine learning system by having the machine learning system provide classifications and verifying the classifications against the user input; repeating the testing process until the machine learning system correctly classifies the cyclic loop image data; 4. The method of claim 3, comprising:

6. 1. A system for classifying a data signal, comprising: a ramp generator for generating a ramp sweep signal from input waveform data; a burst detector for locating data bursts within the input waveform data; a burst gate that receives a signal from the burst detection unit and stores in a memory circulating loop image data in a format in which the input waveform data is used as Y-axis data and the ramp sweep signal is used as X-axis data; a machine learning system that receives the cyclical loop image data and classifies the data bursts; A data signal classification system comprising:

7. 7. The data signal classification system of claim 6, wherein the input waveform data is acquired from a memory device under test, and the machine learning system classifies the data bursts resulting from either a write operation or a read operation on the memory device under test.

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