Preemptive staging for full-stride destaging

Abstract

A method for improving destage performance to a RAID array is disclosed. Such a method periodically scans a cache for a first stride that is ready to be destaged to the RAID array. While scanning the cache, the method identifies a second stride that is not currently ready to be destaged to the RAID array but that will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of missing data for the second stride from the RAID array to the cache in preparation for the subsequent scan. When the subsequent scan occurs, the method destages the second stride from the cache to the RAID array. Corresponding systems and computer program products are also disclosed.

Description

[Technical Field]

[0001] The present invention relates to a system and method for improving destage performance to a RAID array. [Background technology]

[0002] RAID (Redundant Array of Independent Disks) is a storage technology that improves storage capacity and reliability through redundancy. RAID is created by combining multiple storage drive components (e.g., disk drives, solid-state drives, or both) into a logical unit. Data is then distributed across the drives using various techniques called "RAID levels." Standard RAID levels, currently including RAID levels 1 through 6, are a basic set of RAID configurations that employ striping, mirroring, or parity to provide data redundancy, or a combination of these. Each configuration strikes a balance between two primary goals: (1) improving data reliability and (2) improving I / O performance.

[0003] Disks configured in a RAID array can provide accelerated read performance because data can be accessed from multiple drives simultaneously. However, performing writes to RAID arrays, such as RAID-5 or RAID-6 arrays, can incur increased overhead. This is primarily due to parity calculations. For example, to write a subset of a stride (i.e., a strip) of data in a RAID-5 array, other strips of the stride may need to be staged from the RAID-5 array and the parity value associated with the stride recalculated. Once the parity value is recalculated, the entire stride may be destaged to the RAID-5 array. Thus, a write of less than a full stride to a RAID-5 array can require significant overhead to stage the data from the RAID array, recalculate the parity value, and destage the data and recalculated parity value to the RAID array. On the other hand, a write that comprises a full stride of data can be destaged to the RAID-5 array along with the calculated parity value using a single operation. This is because neither missing data nor parity values ​​need to be loaded from the disk drives before writing a stride to the RAID array. Summary of the Invention

[0004] The present invention was developed in response to the current state of the art, and more particularly in response to problems and needs in the art not yet completely solved by currently available systems and methods. Accordingly, the present invention was developed to improve destage performance to RAID arrays. The features and advantages of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.

[0005] Consistent with the foregoing, a method for improving destage performance to a RAID array is disclosed. In one embodiment, such a method periodically scans a cache for first strides that are ready to be destaged to the RAID array. While scanning the cache, the method identifies second strides that are not currently ready to be destaged to the RAID array but that will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of missing data for the second stride from the RAID array to the cache in preparation for the subsequent scan. When the subsequent scan occurs, the method destages the second stride from the cache to the RAID array.

[0006] Corresponding computer program products and systems are also disclosed and claimed herein.

[0007] In order that the advantages of the present invention may be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments which are illustrated in the accompanying drawings, in which the invention will be described and explained with additional specificity and detail, bearing in mind that these drawings illustrate only typical embodiments of the invention and therefore should not be considered as limiting its scope. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a high-level block diagram illustrating an example of a network environment in which systems and methods consistent with the present invention may be implemented; [Figure 2] 2 is a high-level block diagram illustrating an example of a storage system for use in the network environment of FIG. 1. [Figure 3A] FIG. 1 is a high-level block diagram illustrating strides of a RAID array. [Figure 3B] 3B is a table showing the parity values ​​calculated for each stride of the RAID array of FIG. 3A. [Figure 4] FIG. 2 is a high-level block diagram illustrating read and write caches within a cache. [Figure 5] FIG. 1 is a high-level block diagram illustrating a cache destage module for destaging data from the cache to the RAID array. [Figure 6] 1 is a flow diagram illustrating one embodiment of a method for scanning a cache for strides to destage to a RAID array. [Figure 7] 1 is a flow diagram illustrating one embodiment of a method for adjusting the number of strides preemptively staged in a cache. DETAILED DESCRIPTION OF THE INVENTION

[0009] It will be readily understood that the components of the present invention, as generally described and illustrated herein, could be arranged and designed in a wide variety of different configurations. Thus, the following more detailed description of the embodiments of the present invention, as illustrated in the figures, is not intended to limit the scope of the invention as claimed, but is merely representative of specific examples of embodiments presently contemplated in accordance with the present invention. The embodiments described herein can best be understood by referring to the drawings, in which like parts are designated with like numerals throughout.

[0010] The present invention may be embodied as a system, method, or computer program product, or any combination thereof. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0011] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction-execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), Memory Stick®, floppy disk, mechanically encoded devices such as punch cards or grooved ridge structures having instructions recorded thereon, and any suitable combination thereof. Computer-readable storage medium, as used herein, should not be construed as a transitory signal per se, such as, for example, radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0012] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, fiber optic transmission cables, wireless transmission cables, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0013] The computer readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0014] The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may be personalized by executing the computer-readable program instructions using state information from the computer-readable program instructions to perform aspects of the present invention.

[0015] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0016] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when the instructions are executed by the processor of the computer or other programmable data processing apparatus, means are generated for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored constitutes an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0017] Furthermore, computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device and caused to perform a series of operational steps on the computer, other programmable apparatus, or other device to generate a computer-implemented process that, when executed on the computer, other programmable apparatus, or other device, implements the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0018] Referring to Figure 1, an example of a network environment 100 is shown. Network environment 100 is provided to illustrate an example of an environment in which embodiments of the present invention may operate. Network environment 100 is provided by way of example only and not limitation. Indeed, the systems and methods disclosed herein may be applicable to a wide variety of different network environments in addition to the illustrated network environment 100.

[0019] As shown, network environment 100 includes one or more computers 102, 106 interconnected by a network 104. Network 104 may include, for example, a local area network (LAN) 104, a wide area network (WAN) 104, the Internet 104, an intranet 104, etc. In particular embodiments, computers 102, 106 may include both client computers 102 and server computers 106 (also referred to herein as "hosts" 106 or "host systems" 106). Generally, client computers 102 initiate communication sessions, and server computers 106 await and respond to requests from client computers 102. In particular embodiments, computers 102 and / or servers 106 may be connected to one or more internal or external direct-attached storage systems 112 (e.g., arrays of hard disk drives, solid-state drives, tape drives, etc.). These computers 102, 106 and the directly attached storage system 112 may communicate using protocols such as ATA, SATA, SCSI, SAS, and Fibre Channel.

[0020] The network environment 100, in certain embodiments, may include a storage network 108, such as a storage-area network (SAN) 108 or a LAN 108 (e.g., when using network-attached storage), behind the server 106. This network 108 may connect the server 106 to one or more storage systems 110, such as an array of hard disk drives or solid-state drives 110a, a tape library 110b, individual hard disk drives or solid-state drives 110c, a tape drive 110d, a CD-ROM library, etc. To access the storage system 110, the host system 106 may communicate through a physical connection from one or more ports on the host 106 to one or more ports on the storage system 110. The connection may be via a switch, a fabric, a direct connection, etc. In certain embodiments, the server 106 and the storage system 110 may communicate using a network standard such as Fibre Channel (FC) or iSCSI.

[0021] Referring to FIG. 2, one embodiment of a storage system 110a is shown that includes an array of storage drives 204 (e.g., hard disk drives and / or solid-state drives). As shown, storage system 110a includes a storage controller 200, one or more switches 202, and one or more storage drives 204, such as hard disk drives and / or solid-state drives (e.g., flash memory-based drives). Storage controller 200 may enable one or more hosts 106 (e.g., open systems and / or mainframe servers 106) to access data in one or more storage drives 204. In certain embodiments, storage drives 204 may be configured in RAID arrays with various RAID levels to provide desired levels of I / O performance and / or data redundancy.

[0022] In selected embodiments, storage controller 200 includes one or more servers 206. Storage controller 200 may also include host adapters 208 and device adapters 210 for connecting storage controller 200 to host devices 106 and storage drives 204, respectively. During normal operation (when both servers 206 are operational), servers 206 may manage I / O to different logical subsystems (LSSs) within enterprise storage system 110a. For example, in a particular configuration, a first server 206a may handle I / O to even-numbered LSSs, and a second server 206b may handle I / O to odd-numbered LSSs. These servers 206a, 206b may provide redundancy to ensure data is always available to connected hosts 106. Thus, if one server 206a fails, the other server 206b may take over the I / O load of the failed server 206a, allowing I / O to continue between the host 106 and the storage drive 204. This process may be referred to as a "failover."

[0023] In selected embodiments, each server 206 includes one or more processors 212 and memory 214. Memory 214 may include volatile memory (e.g., RAM) as well as non-volatile memory (e.g., ROM, EPROM, EEPROM, flash memory, local disk drives, local solid state drives, etc.). The volatile and non-volatile memory, in particular embodiments, may store software modules that run on processor(s) 212 and are used to access data in storage drive 204. These software modules may manage all read and write requests to logical volumes 302 in storage drive 204.

[0024] In select embodiments, the memory 214 includes a cache 218, such as a DRAM cache 218. Whenever a host 106 (e.g., an open system or mainframe server 106) performs a read operation, the server 206 performing the read may fetch the data from the storage drive 204 and store it in its cache 218 if it is needed again. If the data is requested again by the host 106, the server 206 may fetch it from the cache 218 instead of fetching it from the storage drive 204, saving both time and resources. Similarly, when a host 106 performs a write, the server 106 receiving the write request may store the write in its cache 218 and later destage the write to the storage drive 204. If the write is stored in the cache 218, the write may also be stored in the non-volatile storage (NVS) 220 of the opposite server 206, so that the write can be recovered by the opposite server 206 if the first server 206 fails.

[0025] One example of a storage system 110a having an architecture similar to that shown in FIG. 2 is the IBM DS8000® enterprise storage system. The DS8000® is a high-performance, high-capacity storage controller that provides disk and solid-state storage designed to support continuous operations. However, the systems and methods disclosed herein are not limited to the IBM DS8000® enterprise storage system and may be implemented with any equivalent or similar storage system or group of storage systems, regardless of the manufacturer, product name, or component or component names associated with the system. Any storage system that can benefit from one or more embodiments of the present invention is considered to be within the scope of the present invention. As such, the IBM DS8000® is presented by way of example only and is not intended to be limiting.

[0026] Referring to FIG. 3A, in selected embodiments, the disk drives 204 of storage system 110a may be configured in a RAID array 302 (i.e., a redundant array of inexpensive disks). For example, in a "RAID 5" array 302, logically sequential data may be divided among multiple disk drives 204a-d. For example, if disk drives 204a-d include four disks, logically sequential data "A" may be divided into segments "A1," "A2," and "A3" (collectively referred to as "Stride A") and stored on three separate disks 204a-c. In selected embodiments, each segment includes one or more tracks 300, although other divisions are possible. Parity data "A" is generated by performing an XOR operation on A1, A2, and A3. p " may be calculated. This parity data may be stored on a fourth disk 204d. Exemplary data and parity values ​​are shown in Figure 3B (parity values ​​are shaded). If one of disks 204a-c fails, the remaining data and parity values ​​may be used to reconstruct the data on the failed disk. For example, if disk 204b containing A2 is lost, the values ​​A1, A3, and A4 may be reconstructed. p A2 can be reconstructed using

[0027] Disks configured in a RAID array 302 can provide accelerated read performance because data can be accessed from multiple drives 204a-c simultaneously. However, there is typically increased overhead when performing writes to the array, primarily due to parity calculations. For example, to write to A1, values ​​A2, A3, and A4 must be written. p may need to be loaded (i.e., staged) from disk drive 204, value A1 may need to be changed on the disk drive, and parity value A pmust be recalculated (using values ​​A1, A2, and A3) and destaged to disk drive 204. These operations require a total of four disk operations. Meanwhile, a full stride of data (i.e., A1, A2, and A3) can be destaged to the parity value A using one disk operation. p The full-stride destage is preferred when destaging data from cache 218 to storage drive 204. This is because when writing strides, neither the data value nor the parity value needs to be loaded from disk drive 204. For this reason, full-stride destage is preferred when destaging data from cache 218 to storage drive 204.

[0028] 4, in particular embodiments, cache 218 may be divided into a read cache 218a and a write cache 218b. Read cache 218a may store unchanged data (e.g., unchanged tracks 400). Write cache 218b may store changed data (e.g., changed tracks 400). This changed data may eventually be destaged to backend storage drive 204.

[0029] In particular embodiments, an ordered list (e.g., a b-tree) of modified data elements (e.g., tracks) may be maintained for each rank (i.e., RAID array 302) in storage system 110a. This ordered list may be used to determine which modified data elements should be destaged from write cache 218b to RAID array 302, as well as the order in which to perform the destages. In particular embodiments, the ordered list is sorted based on the physical location of each data element within RAID array 302.

[0030] As shown in FIG. 4, in certain embodiments, one or more clock bits 402 may be maintained per modified data element 400 in the write cache 218b. For example, in certain embodiments, four clock bits 402 may be maintained per data element 400, allowing values ​​from 0 to 15. As described in more detail in connection with FIG. 6, these clock bits 402 may store a count used to determine when to destage a data element. Each time the ordered list is scanned, the count of the data element may be decremented. Each time a data element 400 is written, the count associated with the data element 400 may be incremented. The count may ensure that frequently written data elements 400 are not prematurely destaged from the cache 218 to the storage drive 204.

[0031] Referring to FIG. 5 , in particular embodiments, a cache destage module 500 may be provided for destaging data elements 400 from write cache 218b to storage drive 204. This cache destage module 500 may include various sub-modules for providing various features and functionality. Cache destage module 500 and associated sub-modules may be implemented in hardware, software, firmware, or a combination thereof. Cache destage module 500 and associated sub-modules are presented by way of example and not limitation. In different embodiments, more or fewer sub-modules may be provided. For example, the functionality of some sub-modules may be combined into a single or fewer sub-modules, or the functionality of a single sub-module may be distributed across several sub-modules.

[0032] As shown, the cache destage module 500 includes one or more of a cache scan module 502, a count decrement module 504, a count identification module 506, a threshold module 508, a stage module 510, a destage module 512, a preemptive stage module 514, and a limit module 516. The cache scan module 502 may be configured to periodically scan the ordered list to identify which data elements 400 are ready to be destaged from the write cache 218b to the RAID array 302. Each time a data element 400 in the ordered list is scanned, the count decrement module 504 may decrement the count of the clock bits 402 associated with the data element 400.

[0033] Upon scanning the data elements 400 in the ordered list, the count identification module 506 may identify the count associated with the data element 400 by reading the clock bits 402. Upon this identification, the threshold module 508 may determine whether all counts associated with data elements 400 from the same stride are less than or equal to a first threshold (e.g., zero). If the counts are less than or equal to the first threshold, the data element 400 may be considered "ready" to be destaged from the cache 218 to the RAID array 302. If necessary, the stage module 510 may stage the missing data elements 400 from the RAID array 302 to the cache 218 so that the data elements 400 in the cache 218 constitute a full stride. The destage module 512 may then recalculate the parity values ​​associated with the stride, if necessary, and destage the stride from the cache 218 to the RAID array 302.

[0034] If the count of the data elements 400 associated with the stride is not less than or equal to the first threshold, the threshold module 508 may determine whether the count is less than or equal to a second threshold (e.g., 3). If so, the data elements 400 associated with the stride may not currently be ready for destage to the RAID array 302 (because their count is not less than or equal to the first threshold), but will likely be ready during a subsequent scan of the cache 218 (because their count is decremented and therefore likely to fall below the first threshold during the subsequent scan, absent an event such as a write that increases the count above the first threshold). In such a case, the preemptive stage module 514 may preemptively stage the missing data elements 400 from the RAID array 302 to the cache 218 so that a full stride is present in the cache 218 during the next pass of the cache scan module 502. During the next scan of the cache 218, if all counts associated with the data elements 400 of the stride fall below the first threshold, the data elements 400 associated with the stride are considered "ready" to be destaged. Preemptively staging missing data elements 400 in this manner may eliminate or reduce the need to stage missing data elements 400 from the RAID array 302 to the cache 218 at destage time, thereby improving efficiency.

[0035] The limiting module 516 may be configured to limit the number of strides being preemptively staged from the RAID array 302. In particular embodiments, the limiting module 516 may limit the number of strides to a selected threshold (e.g., 50). If the number of preemptively staged strides is equal to or greater than this amount, the limiting module 516 may queue further requests for preemptive staging. If the number of preemptively staged strides falls below the threshold (or an even lower threshold), the limiting module 516 may resume processing requests to preemptively stage strides, starting with the requests in the queue, in the order they were queued. One embodiment of a method 700 that may be used by the limiting module 516 is discussed in connection with FIG. 7.

[0036] 6, one embodiment of a method 600 for scanning the cache 218 is shown. Such method 600 may be performed by the cache destage module 500 described above. As shown, the method 600 first determines at 602 whether it is time to scan the cache 218. In particular embodiments, the scan may occur when a previous scan is completed or at specified intervals. The time required to perform the scan may, in particular embodiments, correspond to the time required to proceed through the ordered list described above.

[0037] As shown, when a new scan begins, method 600 examines 604 the data elements 400 in cache 218 associated with the first stride in the ordered list. In step 606, if the counts (i.e., clock bits 402) of all data elements 400 associated with the stride are less than or equal to a first threshold (e.g., zero), the stride is ready to be destaged to RAID array 302. In step 608, if data is missing to perform a full-stride destage (assuming a full-stride destage is necessary and / or is the most efficient way to destage the data), method 600 stages 610 the missing data elements 400 from RAID array 302 so that a full stride is present in cache 218. Using the full stride of data, method 600 recalculates 612 the parity values ​​and destages 612 the stride to RAID array 302. On the other hand, if no data is missing from the stride at step 608, then method 600 simply recalculates the parity value at 612 and destages the stride at 612. No staging of the missing data element 400 from the RAID array 302 is required. Method 600 then determines at 614 whether the ordered list still contains the stride, and if so, checks at 604 the next stride in the ordered list.

[0038] If the counts (i.e., clock bits 402) of all data elements 400 associated with the stride are not less than or equal to the first threshold in step 606, then method 600 determines whether the counts of all data elements 400 associated with the stride are less than or equal to a second threshold (e.g., 3) in 616. If not, method 600 determines whether the ordered list still contains the stride in 614, and if so, examines the next stride in the ordered list in 604. If all data elements 400 associated with the stride are less than or equal to the second threshold, then the stride may not currently be ready for destage to the RAID array 302, but will likely be ready for destage during a subsequent scan of the cache 218 (assuming no further writes to the data elements 400 occur). If, at step 616, all data elements 400 associated with the stride are less than or equal to the second threshold, method 600 determines at 618 whether missing data is needed to complete the stride, assuming that destaging the full stride is necessary and / or most efficient. If data is missing, method 600 preemptively stages at 620 the missing data from RAID array 302 to cache 218 so that the full stride is present in cache 218 during the next scan. On the other hand, if, at step 618, no data is missing from the stride, preemptive staging is not needed. Method 600 then determines at 614 whether the ordered list still contains strides, and if so, examines at 604 the next stride in the ordered list.

[0039] Once all strides in the ordered list have been examined at 604, the method 600 ends and waits at 602 for the next scan to begin. In certain embodiments, the next scan begins immediately. In other embodiments, the next scan begins after a fixed time has elapsed since the previous scan ended. In still other embodiments, scans occur at fixed intervals, and the next scan begins at the start of the next fixed interval.

[0040] 7, one embodiment of a method 700 for adjusting the number of strides being preemptively staged from the RAID array 302 is shown. As shown, the method 700 determines, at 702, whether a stride in the cache 218 requires preemptive staging. If so, the method 700 determines, at 704, whether the number of preemptively staged strides is above a high threshold (e.g., 50). If so, the method 700 queues the stride, at 706. If, at step 704, the number of preemptively staged strides is below the high threshold, the method 700 increments, at 708, the number of strides currently being preemptively staged and begins, at 708, preemptive staging of that stride.

[0041] If preemptive staging of the stride is completed at step 710, method 700 decrements the number of strides currently preemptively staged at 712. Method 700 then determines whether the number of strides currently preemptively staged is below a low threshold (e.g., 40) at 714. If so, method 700 determines whether there are any strides currently in the queue at 716. If so, method 700 increments the number of strides currently preemptively staged at 708 and begins preemptive staging of the next stride in the queue at 708. If there are no strides in the queue, method 700 returns to the top to determine whether another stride needs to be preemptively staged at 702 or whether preemptive staging of the stride is completed at 710.

[0042] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer-usable media according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of code, including one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order shown. For example, depending on the functionality involved, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may possibly be executed in the reverse order. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions.

Claims

1. 1. A method for improving destage performance to a RAID array, comprising: storing a plurality of strides in a RAID array, each stride comprising a set of data elements distributed across a plurality of storage drives of the RAID array; maintaining a count for each data element of each stride, wherein maintaining the counts includes each count being incremented each time a corresponding data element is written and decremented each time a corresponding data element is scanned; periodically scanning a cache to identify a first stride ready to be destaged to the RAID array, wherein identifying the first stride includes identifying a stride whose data elements have a count less than or equal to a first specified threshold; identifying, while scanning the cache, second strides that are not currently ready to be destaged to the RAID array but that will likely be ready to be destaged during a subsequent scan of the cache, wherein identifying the second strides includes identifying strides whose data elements have a count less than or equal to a second specified threshold that is greater than the first specified threshold; initiating preemptive staging of missing data of the second stride necessary to calculate a parity value for the second stride from the RAID array to the cache; destaging the second stride from the cache to the RAID array when the subsequent scan occurs; A method comprising:

2. The method of claim 1 , wherein the first specified threshold is zero.

3. The method of claim 1 , wherein each count comprises four bits.

4. The method of claim 1 , wherein the data elements are tracks.

5. 2. The method of claim 1, wherein initiating preemptive staging includes initiating preemptive staging for a number of second strides up to a specified threshold.

6. 1. A computer program product for improving destage performance to a RAID array, the computer program product comprising: a non-transitory computer-readable storage medium having computer usable program code embodied thereon, the computer usable program code, when executed by at least one processor, storing a plurality of strides in a RAID array, each stride comprising a set of data elements distributed across a plurality of storage drives of the RAID array; maintaining a count for each data element of each stride, wherein maintaining the counts includes each count being incremented each time a corresponding data element is written and decremented each time a corresponding data element is scanned; periodically scanning a cache to identify a first stride ready to be destaged to the RAID array, wherein identifying the first stride includes identifying a stride whose data elements have a count less than or equal to a first specified threshold; identifying, while scanning the cache, second strides that are not currently ready to be destaged to the RAID array but that will likely be ready to be destaged during a subsequent scan of the cache, wherein identifying the second strides includes identifying strides whose data elements have a count less than or equal to a second specified threshold that is greater than the first specified threshold; initiating preemptive staging of missing data of the second stride necessary to calculate a parity value for the second stride from the RAID array to the cache; destaging the second stride from the cache to the RAID array when the subsequent scan occurs; 1. A computer program product configured to:

7. 7. The computer program product of claim 6, wherein the first specified threshold is zero.

8. 7. The computer program product of claim 6, wherein each count comprises four bits.

9. 7. The computer program product of claim 6, wherein the data element is a track.

10. 7. The computer program product of claim 6, wherein initiating preemptive staging comprises initiating preemptive staging for a number of second strides up to a specified threshold.

11. 1. A system for improving destage performance to a RAID array, comprising: at least one processor; at least one memory device operatively coupled to said at least one processor, said memory device storing instructions for execution on said at least one processor; wherein the instructions cause the at least one processor to: storing a plurality of strides in a RAID array, each stride comprising a set of data elements distributed across a plurality of storage drives of the RAID array; maintaining a count for each data element of each stride, wherein maintaining the counts includes each count being incremented each time a corresponding data element is written and decremented each time a corresponding data element is scanned; periodically scanning a cache to identify a first stride ready to be destaged to the RAID array, wherein identifying the first stride includes identifying a stride whose data elements have a count less than or equal to a first specified threshold; identifying, while scanning the cache, second strides that are not currently ready to be destaged to the RAID array but that will likely be ready to be destaged during a subsequent scan of the cache, wherein identifying the second strides includes identifying strides whose data elements have a count less than or equal to a second specified threshold that is greater than the first specified threshold; initiating preemptive staging of missing data of the second stride necessary to calculate a parity value for the second stride from the RAID array to the cache; destaging the second stride from the cache to the RAID array when the subsequent scan occurs; A system that allows the following to be performed.

12. The system of claim 11 , wherein the first specified threshold is zero.

13. The system of claim 11 , wherein the data element is a track.

14. 12. The system of claim 11, wherein initiating preemptive staging includes initiating preemptive staging for a number of second strides up to a specified threshold.

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