Dynamic balancing of inbound traffic in a multi-network interface processing system

Abstract

Examples described herein provide a computer-implemented method that includes registering at least one of a plurality of virtual internet protocol addresses (VIPAs) with each of a plurality of network adapters, the method further including, by each of the plurality of network adapters, distributing inbound data among the plurality of network adapters using an address resolution protocol.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate generally to processing systems, and more particularly to dynamic balancing of inbound traffic in a multi-network interface enabled processing system.

[0002] A processing system (e.g., a laptop computing system, a desktop computing system, a server computing system, a tablet computing system, etc.) may include one or more network interface cards (NICs) that enable the processing system to communicate with other processing systems. In some cases, the one or more NICs enable the processing system to connect to a network (e.g., the Internet, a local area network, a wide area network, etc.). Summary of the Invention

[0003] SUMMARY OF THE INVENTION Embodiments of the present invention are directed to dynamic balancing of inbound traffic in a multi-network interface enabled processing system.

[0004] A non-limiting example of a computer-implemented method includes registering at least one of a plurality of virtual internet protocol addresses (VIPAs) with each of a plurality of network adapters, and distributing, by each of the plurality of network adapters, inbound data among each of the plurality of network adapters using an address resolution protocol.

[0005] Other embodiments of the present invention embody features of the above-described methods in computer systems and computer program products.

[0006] Additional technical features and advantages are realized through the techniques of the present invention.Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter.

[0007] To easily identify the discussion of any particular element or operation, the most significant digit(s) of a reference number refers to the figure number in which that element is first introduced. [Brief explanation of the drawings]

[0008] [Figure 1] 1 illustrates a block diagram of a processing system according to one or more embodiments described herein. [Figure 2] 1 illustrates a method for performing inbound load balancing according to one embodiment. [Figure 3] 1 illustrates a block diagram of a processing system having multiple open system adapters, each having a virtual Internet Protocol address assigned thereto by a round-robin technique, in accordance with one or more embodiments described herein. [Figure 4] 1 illustrates a block diagram of a processing system having multiple open system adapters, the open system adapters having virtual Internet Protocol addresses that are assigned by a round-robin technique, in accordance with one or more embodiments described herein. [Figure 5] FIG. 4 illustrates a block diagram of a processing system in which an open system adapter has a virtual Internet Protocol address that is reassigned by a load balancing technique according to one or more embodiments described herein. [Figure 6] 1 shows a block diagram of a processing system for performing the methods described herein, according to one or more embodiments described herein.

[0009] The diagrams shown herein are illustrative. Various modifications may be made to the diagrams or operations described without departing from the scope of the present invention. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" and variations thereof indicate having a communication path between two elements, but do not imply a direct connection between the elements without an intervening element / connection between them. All such variations are considered part of this specification. DETAILED DESCRIPTION OF THE INVENTION

[0010] One or more embodiments of the present invention provide dynamic balancing of inbound traffic in a multi-network interface-enabled processing system. In some environments, the processing system is configured with multiple network interface cards (NICs), also referred to as network adapters, on virtual local area networks (VLANs) for redundancy. Network adapters, as described herein, may utilize Address Resolution Protocol (ARP) offload support. As one example, IBM's z / OS® network environment utilizes Open System Adapters (OSAs) as network adapters. In some environments, multiple Virtual Internet Protocol Addresses (VIPAs) represent multiple applications and prevent loss of connectivity in the event of a network adapter (i.e., network adapter) failure.

[0011] 1 illustrates a block diagram of a processing system 102 according to an embodiment of the present disclosure. The processing system 102 in this example includes a processing device 104 and a memory 106. According to an embodiment of the present disclosure, the techniques described herein may be implemented with a combination of hardware and programming. The programming may be processor-executable instructions stored in a tangible memory, and the hardware may include the processing device 104 for executing those instructions. Thus, a system memory (e.g., the memory 106) may store program instructions that, when executed by the processing device 104, implement the techniques described herein.

[0012] Processing system 102 may also include one or more network adapters (e.g., network adapter 616 of FIG. 6 ). In the example of FIG. 1 , processing system 102 includes two network adapters, referred to as open system adapters, such as network adapter 108 and network adapter 110. Each of network adapter 108 and network adapter 110 is communicatively coupled to network device 116 via network 112, as indicated by the arrows in FIG. 1 , which may represent wired or wireless links, or both. It should be understood that other numbers and / or types of network adapters may be used, and additional OSAs may be used, including, for example, three OSAs, four OSAs, five OSAs, six OSAs, etc. For example, it may be convenient to utilize more than one network adapter for redundancy purposes to provide load balancing, resilience, etc. In the case of load balancing, network traffic can be divided among multiple interfaces, and in the case of resiliency, the failure of a network adapter does not cut off the processing system's network access because other network adapters can support network communications.

[0013] Network 112 may represent any one or combination of different types of suitable communications networks, such as, for example, a cable network, a public network (e.g., the Internet), a private network, a wireless network, a cellular network, or other suitable private or public networks or both. Furthermore, network 112 may have any suitable communications coverage associated with it, including, for example, a global network (e.g., the Internet), a metropolitan area network (MAN), a wide area network (WAN), a local area network (LAN), or a personal area network (PAN). Additionally, network 112 may include any type of medium over which network traffic may be carried, including, but not limited to, coaxial cable, twisted pair cable, optical fiber, hybrid fiber coaxial (HFC) media, microwave terrestrial transceiver, radio frequency communications media, satellite communications media, or any combination thereof. In one example, network 112 includes a switch fabric 114 that switches network traffic / data between devices, such as between processing system 102 and network device 116.

[0014] In the example of FIG. 1 , processing system 102 configured and arranged as shown utilizes network adapter 108 and network adapter 110 on the same subnet. Such a configuration is useful for static routing (i.e., when dynamic routing is not used), allowing for the use of a flat Layer 2 network. Processing system 102 can utilize a multihomed host approach, where each interface (i.e., network adapter 108, network adapter 110) is presented to the stacks running on processing system 102 and to network 112 as a separate Internet Protocol (IP) interface. In such an example, the network layer of each stack sees multiple IP interfaces that can be accessed and controlled separately. Network 112 similarly sees multiple IP interfaces that can be routed separately. Each IP interface uses its own IP address. In another example, processing system 102 utilizes network adapter 108 and network adapter 110 on different subnets. This approach is useful in situations where dynamic routing is used.

[0015] In IBM's z / OS® network environment, it may be preferable to configure multiple network adapters (e.g., network adapter 108, network adapter 110) on a single virtual local area network (VLAN) for redundancy. It may also be preferable to use multiple virtual internet protocol addresses (VIPAs) to represent multiple applications and prevent loss of connectivity in the event of a network adapter failure. This works because each VIPA on the stack can be reached from any network adapter (e.g., either network adapter 108 or network adapter 110). When a VIPA is defined as network adapter 108 or network adapter 110 on the same subnet, one of network adapter 108 or network adapter 110 is responsible for responding to Address Resolution Protocol (ARP) requests and sending gratuitous ARPs for the VIPA. This network adapter (e.g., network adapter 108, one of network adapters 110) is referred to as the "VIPA owner" because it is the VIPA owner, and its (virtual or real) MAC address is recognized by the rest of network 112 as the MAC address for each of the VIPAs registered with it.

[0016] Because a single network adapter acts as the VIPA owner, all inbound packets destined for any VIPA will pass through the one network adapter acting as the VIPA owner rather than any other OSAs on the same subnet that would otherwise be available for inbound traffic. This can overload a single network adapter, resulting in packet loss, performance issues, and imbalances in network adapter usage.

[0017] One conventional approach utilizes link aggregation. However, link aggregation is not a supported feature in IBM's z / OS®. Another conventional approach uses a Layer 3 dynamic routing protocol, such as Open Shortest Path First (OSPF), to advertise the VIPA addresses through each of the OSAs. However, the processing and management burden imposed on z / OS® by implementing dynamic routing makes this solution undesirable for small, uncomplex networks.

[0018] Therefore, the present technology addresses these and other shortcomings of conventional approaches by providing a technique for balancing inbound traffic across OSAs in a z / OS® environment. More specifically, the VIPA owner function is implemented by registering each VIPA (using Transmission Control Protocol / Internet Protocol (TCP / IP)) with a single eligible network adapter that resides in the same subnet as the VIPA. According to one or more embodiments described herein, inbound traffic is spread among available network adapters by registering applicable VIPAs among the eligible network adapters. For example, applicable VIPAs may be registered evenly among eligible network adapters (e.g., for 100 VIPAs and four OSA adapters in the same subnet, 25 VIPAs would be registered / assigned to each network adapter). In one example, inbound packet or data counts for each VIPA are monitored, such as at a configured time interval. Individual VIPAs may be re-registered with different OSAs to improve the balancing of packet / data counts among network adapters. In some cases, balancing may be based on number of bytes, classification of services, security classification of different interfaces, etc.

[0019] FIG. 2 illustrates a method 200 for performing inbound load balancing according to one embodiment. Method 200 may be performed by any suitable processing system (e.g., processing system 102, processing system 600, etc.), or any suitable processing device (e.g., processing device 104, processing device 602, etc.), or a combination thereof. Method 200 is described with reference to, but not limited to, FIGS. 1, 3, 4, and 5. In particular, FIGS. 3, 4, and 5 illustrate various embodiments of four network adapters having seven VIPAs registered therebetween. With reference to these three figures, the most significant digits of the element numbers differ with respect to the figure numbers, but otherwise the three figures illustrate and reference the same network adapters / VIPAs. For example, VIPA310, VIPA410, and VIPA510 are the same VIPA in different embodiments. Similarly, network adapter 302, network adapter 402, and network adapter 502 are the same OSA in different embodiments.

[0020] At block 202, method 200 includes processing system 102 registering at least one of a plurality of virtual internet protocol addresses (VIPAs) with each of a plurality of open system adapters (OSAs). Registration means that the OSA interface of the network adapter sends a gratuitous ARP packet and responds to ARP requests for the registered VIPA address. At block 204, method 200 includes, by each of the plurality of network adapters, distributing inbound data among each of the plurality of network adapters using an address resolution protocol (gratuitous and response). This feature and the functionality of blocks 202 and 204 will now be described with reference to FIGS. 3, 4, and 5.

[0021] 3, as an example, a block diagram of a processing system 300 having four open system adapters (i.e., network adapter 302, network adapter 304, network adapter 306, and network adapter 308) is shown. Processing system 300 also includes seven virtual IP addresses (i.e., VIPA 310, VIPA 312, VIPA 314, VIPA 316, VIPA 318, VIPA 320, and VIPA 322) registered to network adapter 302, network adapter 304, network adapter 306, and network adapter 308, as shown. In this example, the VIPAs are registered based on a round-robin registration in accordance with one or more embodiments described herein. That is, VIPA 310 is assigned to network adapter 302, then VIPA 312 is registered to network adapter 304, VIPA 314 is registered to network adapter 306, and VIPA 316 is registered to network adapter 308. Once each of the network adapters has a VIPA registered to it, the round-robin registration repeats for the additional VIPAs, with VIPA 318 being registered with network adapter 302, VIPA 320 being registered with network adapter 304, and VIPA 322 being registered with network adapter 306.

[0022] According to another embodiment, byte registration is performed. Byte registration begins with round-robin registration (see FIG. 3), and then the inbound byte count is measured over a configured time interval. After the configured time interval, the inbound byte counts per OSA are compared. If the difference in the totals exceeds, for example, a threshold, rebalancing is initiated. During rebalancing, one or more VIPAs move their registrations to different network adapters so that the inbound byte counts for the VIPAs are more evenly distributed among the network adapters. In one example, the inbound byte count can take into account non-VIPA packets. In one example, moving a VIPA causes the moved network adapter to perform a gratuitous ARP so that inbound traffic for the VIPA is directed to the VIPA rather than the previous owner.

[0023] 4 and 5 both illustrate a block diagram of a processing system 400 having four open system adapters (i.e., network adapter 402 / network adapter 502, network adapter 404 / network adapter 504, network adapter 406 / network adapter 506, and network adapter 408 / network adapter 508). Similar to the example of FIG. 3, the network adapters in FIG. 4 are initially registered using the round-robin registration technique described herein. However, in this example, during a set time interval (e.g., 20 seconds, 45 seconds, 1 minute, 2 minutes, 5 minutes, etc.), inbound data is monitored for each of VIPA 410, VIPA 412, VIPA 414, VIPA 416, VIPA 418, VIPA 420, and VIPA 422.

[0024] That is, as shown in block 204 of FIG. 2, method 200 includes processing system 102 distributing inbound data among each of a plurality of OSAs (i.e., network adapter 402 / network adapter 502, network adapter 404 / network adapter 504, network adapter 406 / network adapter 506, and network adapter 408 / network adapter 508). As the inbound data is distributed among each of the plurality of OSAs, processing system 102 monitors how much inbound data is received at each VIPA (e.g., VIPA 410, VIPA 412, VIPA 414, VIPA 416, VIPA 418, VIPA 420, and VIPA 422). The amount of inbound data (i.e., the number of inbound bytes) is determined and shown for each VIPA in FIGS. 4 and 5. After a set time interval (which may be adjustable), the VIPAs may be re-registered with other network adapters to provide a balanced load for each network adapter. For example, as shown in FIG. 4, network adapter 406 has two registered VIPAs: VIPA 414 (with 600 MB of inbound data) and VIPA 422 (with 300 MB of inbound data). As can be observed, these represent the two VIPAs with the largest inbound byte counts. As a result, network adapter 406 is overloaded compared to network adapter 402, network adapter 404, and network adapter 408. Therefore, the VIPAs in FIG. 4 may be re-registered based on their respective inbound byte counts to balance the inbound data as shown in FIG. 5. In some instances, re-registration may occur based on the total amount of inbound data received (e.g., every 1 GB), based on time, based on network conditions, detected failure conditions, and other triggers.

[0025] According to one or more embodiments described herein, each of the plurality of network adapters resides on a common Internet Protocol stack. Further, in some examples, each of the plurality of network adapters is configured on a common subnet or virtual local area network, as shown in Figures 3, 4, and 5.

[0026] It should be understood that one or more embodiments described herein can be implemented with any other type of computing environment, whether known or later developed. For example, FIG. 6 illustrates a block diagram of a processing system 600 for implementing the techniques described herein. By way of example, the processing system 600 has a processing device 602, which may include one or more central processing units (CPUs) 604, 606, 608, etc. (collectively or generally referred to as processors or processing devices, or a combination thereof). In an aspect of the present disclosure, the processing device 602 may include a reduced instruction set computer (RISC) microprocessor. In some examples, the processing device 602 and / or the CPUs 604, 606, or 608, or a combination thereof, may include multiple processing cores that execute instructions simultaneously / concurrently. The processing device 602 is coupled to system memory (e.g., random access memory RAM 612) and various other components via a system bus 620. Read-only memory ROM 610 is coupled to system bus 620 and may include a basic input / output system (BIOS) that controls certain basic functions of processing system 600 .

[0027] Also shown are an input / output I / O adapter 614 and a network adapter 616 coupled to the system bus 620. The I / O adapter 614 may be a small computer system interface (SCSI) that communicates with a hard disk 636 and / or storage device 638, or any other similar component. The I / O adapter 614, hard disk 636 and / or storage device 638, or any combination thereof, are collectively referred to herein as mass storage 640. An operating system 642 for executing on the processing system 600 may be stored within the mass storage 640. The network adapter 616 interconnects the system bus 620 with an external network 618, enabling the processing system 600 to communicate with other such systems.

[0028] A display 632 (e.g., a display monitor) is connected to the system bus 620 via a display adapter 630, which may include a graphics adapter that improves performance for graphics-intensive applications and a video controller. In one embodiment of the present disclosure, the I / O adapter 614, network adapter 616, and / or display adapter 630 may be connected to one or more I / O buses that are connected to the system bus through an intermediate bus bridge (not shown). Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Additional input / output devices are shown connected to the system bus 620 via a user interface adapter 622 and a display adapter 630. The keyboard 624, mouse 626, and speakers 628 may be interconnected with the system bus 620 via a user interface adapter 622, which may include, for example, a super I / O chip that combines multiple device adapters into a single integrated circuit.

[0029] In one aspect of the present disclosure, processing system 600 includes a graphics processing unit 634. Graphics processing unit 634 is a specialized electronic circuit designed to manipulate and modify memory and accelerate the generation of images in a frame buffer for output to a display. Graphics processing unit 634 is generally very efficient at handling computer graphics and image processing, and has a highly parallel architecture that makes it more efficient than a general-purpose CPU for algorithms in which large blocks of processing are performed in parallel.

[0030] Thus, as configured herein, processing system 600 includes processing functionality in the form of processing device 602, storage functionality including system memory (e.g., RAM 612) and mass storage 640, input means such as keyboard 624 and mouse 626, and output functionality including speakers 628 and display 632. In one aspect of the present disclosure, a portion of the system memory (e.g., RAM 612) and mass storage 640 collectively store IBM's AIX® operating system 642, which coordinates the functionality of the various components illustrated in processing system 600.

[0031] Embodiments of the invention have been described with reference to the drawings associated with this specification. Variations of the embodiments of the invention may be devised without departing from the scope of the present invention. Various connection and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and in the drawings. These connection and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, coupling of entities may refer to either direct coupling or indirect coupling, and positional relationships between entities may be direct or indirect. Furthermore, various tasks and processing steps described herein may be combined into a more comprehensive procedure or process having additional steps or functions not specifically described herein.

[0032] The following definitions and abbreviations will be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or that are inherent in such composition, mixture, process, method, article, or device.

[0033] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "a plurality" may be understood to include any integer greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connection" may include both a direct and an indirect connection.

[0034] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with the measurement of a particular quantity based on equipment available at the time of filing. For example, "about" can include a range of ±8% or 5%, or ±2% of a given value.

[0035] For the sake of brevity, prior art related to making or using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing various technical features described herein are well known. Thus, for the sake of brevity, many conventional implementation details are only briefly mentioned herein or omitted entirely without providing detailed descriptions of known systems and / or processes.

[0036] The present invention may be a system, method, or computer program product, or combination thereof, at any level of integrated technical detail. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon that cause a processor to perform aspects of the present invention.

[0037] The computer-readable storage medium may be any tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or raised structures in grooves having instructions recorded thereon, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as being a transitory signal itself, such as an electric wave or other freely propagating electromagnetic wave, or an electromagnetic wave propagating in a waveguide or other transmission body (e.g., a light pulse traveling in a fiber optic cable), or an electrical signal transmitted through an electrical wire.

[0038] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each corresponding computing / processing device, or can be downloaded to an external computer or external storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. This network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions to a computer-readable storage medium in each corresponding computing / processing device for storage.

[0039] Computer-readable program instructions for carrying out the operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or configuration data for an integrated circuit, or may be source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the "C" programming language or the like. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or remote server. In the last scenario above, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to carry out aspects of the present invention.

[0040] Aspects of the present invention are described herein with reference to flowchart and / or block diagram illustrations of methods, apparatus (systems) and computer program products according to embodiments of the invention, it being understood that each block of those flowchart and / or block diagram illustrations, and combinations of blocks in those flowchart and / or block diagram illustrations, can be implemented by computer-readable program instructions.

[0041] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce means for performing the functions / acts specified in the blocks of the flowchart and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for performing aspects of the functions / acts specified in the blocks of the flowchart and / or block diagrams, and may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0042] These computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to produce a computer-implemented process such that the instructions, when executed on the computer, other programmable apparatus, or other device, perform the functions / acts specified in the blocks of the flowchart and / or block diagrams.

[0043] The flowcharts and block diagrams in the accompanying figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions that implement the specified logical function(s). In some alternative implementations, the functions shown in the blocks may be performed in an order different from that shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or implements a combination of dedicated hardware and computer instructions.

[0044] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications that do not depart from the scope of the described embodiments will be apparent to those skilled in the art. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. 1. A method for performing inbound load balancing, comprising: registering at least two of a plurality of virtual internet protocol addresses (VIPA) with one of a plurality of network adapters based at least in part on the data usage registration; and Distributing inbound data among each of the plurality of network adapters using an address resolution protocol for a VIPA registered by each of the plurality of network adapters. Including, said data usage registration including monitoring said inbound data to determine a number of inbound bytes for each of said plurality of VIPAs, said monitoring being performed at set time intervals; method.

2. 2. The method of claim 1, wherein registering the at least two of the plurality of VIPAs with each of the plurality of network adapters is based at least in part on round-robin registration.

3. registering said at least two of said plurality of VIPAs with each of said plurality of network adapters based at least in part on said number of inbound bytes for each of said plurality of VIPAs; The method of claim 1 , comprising:

4. re-registering said at least two of said plurality of VIPAs with each of said plurality of network adapters based at least in part on said inbound byte count for each of said plurality of VIPAs. The method of claim 1 further comprising:

5. 2. The method of claim 1, wherein each of the plurality of network adapters resides on a common Internet Protocol stack, and each of the plurality of network adapters is configured on a common subnet or virtual local area network.

6. 2. The method of claim 1, wherein the plurality of network adapters includes at least one open system adapter.

7. a memory containing computer readable instructions; and a processing device for executing the computer readable instructions, the computer readable instructions controlling the processing device to: registering at least two of a plurality of virtual internet protocol addresses (VIPA) with one of a plurality of network adapters based at least in part on the data usage registration; and Distributing inbound data among each of the plurality of network adapters using an address resolution protocol for a VIPA registered by each of the plurality of network adapters. Including, said data usage registration including monitoring said inbound data to determine a number of inbound bytes for each of said plurality of VIPAs, said monitoring being performed at set time intervals; The system that performs the operation.

8. 8. The system of claim 7, wherein registering the at least two of the plurality of VIPA's with each of the plurality of network adapters is based at least in part on round-robin registration.

9. registering said at least two of said plurality of VIPAs with each of said plurality of network adapters based at least in part on said number of inbound bytes for each of said plurality of VIPAs; The system of claim 7, comprising:

10. re-registering said at least two of said plurality of VIPAs with each of said plurality of network adapters based at least in part on said inbound byte count for each of said plurality of VIPAs. The system of claim 7 further comprising:

11. 8. The system of claim 7, wherein each of the plurality of network adapters resides on a common Internet Protocol stack, and each of the plurality of network adapters is configured on a common subnet or virtual local area network.

12. 8. The system of claim 7, wherein the plurality of network adapters includes at least one open system adapter.

13. A computer program executed by a computer, the computer comprising: registering at least two of a plurality of virtual internet protocol addresses (VIPA) with one of a plurality of network adapters based at least in part on the data usage registration; and Distributing inbound data across the plurality of network adapters using an address resolution protocol for the VIPA registered by each of the plurality of network adapters. Including, said data usage registration including monitoring said inbound data to determine an inbound byte count for each of said plurality of VIPAs, said monitoring being performed at set time intervals; A computer program that causes an operation to be performed.

14. 14. The computer program product of claim 13, wherein registering the at least two of the plurality of VIPA's with each of the plurality of network adapters is based at least in part on round-robin registration.

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