Three-dimensional array device

Abstract

This three-dimensional array device include a plurality of layers in a height direction, the device comprising a first two-dimensional array circuit that is positioned in a first layer, and a second two-dimensional array circuit that is positioned in a second layer adjacent to the first layer and that overlaps the first two-dimensional array circuit in plan view. The first two-dimensional array circuit and the second two-dimensional array circuit each include a first wiring group, an input part that inputs a signal to the first wiring group, a second wiring group that crosses the first wiring group, and a output part that outputs a signal from the second wiring group. The output part of the first two-dimensional array circuit overlaps the input part of the second two-dimensional array circuit in plan view and is connected so as to be capable of sending and receiving signals.

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a three-dimensional array device, and more particularly to a three-dimensional array device in which memory cell array circuits are stacked. [Background technology]

[0002] In recent years, with the dramatic improvement in computer performance and the development of deep learning, research on deep neural networks, which are multi-layered neural networks, has progressed. Figure 30 shows the configuration of a general neural network. In Figure 30, a neuron receives N inputs X i (collectively referred to as x) and weight W i (collectively referred to as w) and the sum of products Σ(X i *W i ) with activation function f (k) (k=1, 2, ..., collectively referred to as f) nonlinear calculations are performed. In a deep neural network, input x is converted into intermediate output 1 by a multiply-and-accumulate operation by neurons in the input layer. Intermediate output 1 is converted into intermediate output 2 by a multiply-and-accumulate operation by neurons in the hidden layer. After a similar repetition, it is converted into the final output y by neurons in the output layer.

[0003] As described above, deep neural networks learn by repeatedly performing a large number of product-sum operations, evaluating errors, and updating weights. Therefore, using semiconductor chips with a conventional von Neumann architecture poses the problem of high power consumption due to communication between the memory and the CPU or GPU. Therefore, non-volatile memory chips employing a non-von Neumann architecture, known as neuromorphic computing or in-memory computing, have attracted attention. In a two-dimensional array circuit with a crossbar configuration in which non-volatile memory elements are arranged at the intersections of word lines and bit lines, the results of product-sum operations in the bit line direction for data stored in each non-volatile memory can be read as output. This type of in-memory computing technique has been adopted in analog circuit implementations of neural networks since the 1980s (Non-Patent Document 1). For example, neural networks using non-volatile memory chips based on ReRAM (Resistive Random Access Memory) have been widely studied from the device level to the system level. ReRAM functions as an element called a memristor, which stores the amount of charge flowing through the element and changes its resistance, allowing the weights W of a neural network to be calculated. i It is also possible to control it with an analog value instead of a binary value of 0 or 1.

[0004] Deep neural networks are expected to be incorporated into various devices as a core technology supporting AI (Artificial Intelligence) applications. Therefore, binary neural networks, which are easy to implement in digital hardware, have been proposed. Nonvolatile memory such as ReRAM, MRAM, or PCRAM can be used. In particular, ReRAM-based binary neural networks have the advantages of being able to use analog weights as mentioned above, as well as good stability, a wide noise margin, and ease of testing. XNOR operations for weighted sum calculations in binary neural networks can be easily implemented as in-memory computing using ReRAM cells.

[0005] Binary neural networks have the disadvantage of low expressive power because they binarize weights and activation values. Therefore, it is common to increase the computational accuracy of binary neural networks by increasing the network size. However, when performing large-scale parallel input / output, two-dimensional binary neural networks have the problem of increasing the footprint. Therefore, research is currently being conducted on three-dimensional neural networks, which are stacked two-dimensional neural networks. For example, a 3D stacked structure element has been proposed in which synaptic core layers and interconnect layers are alternately stacked and connected between layers by through-silicon vias (TSVs) (Patent Document 1). In this way, implementing a neural network using a 3D stacked structure element improves area efficiency and enables in-memory computing, thereby reducing power consumption. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2019 / 0318230 [Non-patent literature]

[0007] [Non-Patent Document 1] Takashi Morie, "Neuromorphic Systems and Physical Devices," Applied Physics, Japan Society of Applied Physics, 2019, Vol. 88, No. 7, pp. 481-485 Summary of the Invention [Problem to be solved by the invention]

[0008] In conventional 3D neural networks, the layers constituting a 2D neural network must be electrically connected using techniques such as TSV or wire bonding via an interconnect layer, making vertical integration difficult. Furthermore, when stacking nonvolatile memory chips for in-memory computing in a 3D manner, the interconnect layer or wire bonding wiring connecting the output terminals of the lower-layer neural network to the input terminals of the upper-layer neural network becomes longer, resulting in increased signal delays and power consumption.

[0009] One of the objects of the present invention is to provide a three-dimensional array device that realizes a neural network with low latency and low energy loss. [Means for solving the problem]

[0010] A three-dimensional array device in one embodiment of the present invention is a three-dimensional array device having multiple layers in the vertical direction, and comprises a first two-dimensional array circuit located on a first layer, and a second two-dimensional array circuit located on a second layer adjacent to the first layer and overlapping the first two-dimensional array circuit in a planar view, wherein the first two-dimensional array circuit and the second two-dimensional array circuit each have a first wiring group, an input section that inputs signals to the first wiring group, a second wiring group that intersects with the first wiring group, and an output section that outputs signals from the second wiring group, and the output section in the first two-dimensional array circuit overlaps with the input section in the second two-dimensional array circuit in a planar view and is connected to enable signal transfer.

[0011] a first wiring group, an input section for inputting signals to the first wiring group, a second wiring group intersecting the first wiring group, and an output section for outputting signals from the second wiring group; a first wiring group in which the first wiring group is connected to the input section of the second two-dimensional array circuit; a second wiring group in which the second wiring group is connected to the input section of the second two-dimensional array circuit; a first wiring group in which the second wiring group is connected to the input section of the second two-dimensional array circuit; a second wiring group in which the first wiring group is connected to the input section of the second two-dimensional array circuit; a first wiring group in which the second wiring group is connected to the input section of the second two-dimensional array circuit;

[0012] The input section of the first two-dimensional array circuit may not overlap the output section of the second two-dimensional array circuit in a plan view.

[0013] The output section of the first two-dimensional array circuit may be electrically connected to the input section of the second two-dimensional array circuit through a via.

[0014] The first two-dimensional array circuit and the second two-dimensional array circuit may be memory cell array circuits. In this case, the first wiring group may be a wiring group formed of word lines. The second wiring group may be a wiring group formed of bit lines.

[0015] The memory cell array circuit may include at least one resistance change memory and at least one select transistor in each memory cell. In this case, the resistance change memory may have a dielectric layer containing hafnium oxide. The select transistor may have a channel made of an oxide semiconductor containing IGZO. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing a configuration of a three-dimensional array device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the configuration of a two-dimensional array circuit according to the first embodiment. [Figure 3] FIG. 10 is a schematic diagram showing changes in the positions of input and output sections in a two-dimensional array circuit. [Figure 4] FIG. 2 is a cross-sectional view showing the configuration of a memory cell in the three-dimensional array device of the first embodiment. [Figure 5] FIG. 2 is an enlarged cross-sectional view showing the configuration of the three-dimensional array device of the first embodiment. [Figure 6] 4 is a photograph in place of a drawing showing the layout of memory cells in the two-dimensional array circuit shown in FIG. [Figure 7] FIG. 7 is a plan view schematically showing the layout of the memory cell shown in FIG. 6. [Figure 8] 7 is a photograph, substituted for a drawing, showing a cross-sectional structure in the vicinity of the channel of FET1 shown in FIG. 6. [Figure 9] 7 is a photograph in place of a drawing showing a cross-sectional structure of the ReRAM 1 shown in FIG. 6. [Figure 10]4 is a photograph in place of a drawing showing the layout of memory cells in the two-dimensional array circuit shown in FIG. 3(B). [Figure 11] 4 is a photograph in place of a drawing showing the layout of memory cells in the two-dimensional array circuit shown in FIG. [Figure 12] FIG. 4 is a diagram showing the Id-Vg characteristics of a selection transistor in the three-dimensional array device of the first embodiment. [Figure 13] FIG. 4 is a diagram showing the Id-Vd characteristics of a selection transistor in the three-dimensional array device of the first embodiment. [Figure 14] This is a graph comparing the IV characteristics of a "1T1R" cell, which is a memory cell composed of a select transistor and ReRAM, with the IV characteristics of a "1R" cell, which is a memory cell composed of only ReRAM. [Figure 15] FIG. 15 is a diagram showing the cumulative probability of the set / reset voltages of the “1T1R” cell and the “1R” cell measured from the IV characteristics shown in FIG. [Figure 16] This is a diagram showing the IV characteristics of the "1T1R" cell extracted from the IV characteristics shown in FIG. [Figure 17] FIG. 17 is a diagram showing the cumulative probability of the resistance values ​​in the low resistance state and the high resistance state of the “1T1R” cell measured from the IV characteristics shown in FIG. [Figure 18] FIG. 10 is a diagram showing the IV characteristics of a "1T1R" cell in a two-dimensional array circuit. [Figure 19] FIG. 19 is a diagram showing the cumulative probability of resistance values ​​in a low resistance state and a high resistance state measured from the IV characteristics of the two-dimensional array circuit shown in FIG. 18. [Figure 20] FIG. 10 is a diagram showing the rewrite endurance characteristics of each ReRAM in a two-dimensional array circuit at room temperature. [Figure 21] FIG. 10 is a diagram showing the retention characteristics of each ReRAM in a two-dimensional array circuit at room temperature. [Figure 22] This is a circuit diagram showing the configuration of an XNOR circuit using two "1T1R" cells. [Figure 23] 1 is a photograph showing the configuration of a memory cell array prototyped using memory cells according to the first embodiment. [Figure 24] 10 is a photograph showing the configuration of an external peripheral circuit used to measure the prototype XNOR circuit. [Figure 25] FIG. 10 is a diagram showing measurement results of a prototype XNOR circuit. [Figure 26] FIG. 10 is an enlarged cross-sectional view showing the configuration of a three-dimensional array device in a modified example of the first embodiment. [Figure 27] FIG. 1 is a circuit diagram showing the configuration of a memory cell array circuit that executes arithmetic processing digitally. [Figure 28] FIG. 1 is a circuit diagram showing the configuration of a memory cell array circuit that executes arithmetic processing in an analog manner. [Figure 29] FIG. 10 is a diagram showing the configuration of a three-dimensional array device according to a third embodiment of the present invention. [Figure 30] FIG. 1 is a diagram illustrating a configuration of a general neural network. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below. To clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described with reference to the previous drawings may be assigned the same reference numerals, and redundant explanations may be omitted.

[0018] In this specification, multiple elements formed by processing a single thin film, such as etching, may each have a different function or role. These multiple elements are composed of thin films of the same layer structure and the same material. In this specification and claims, multiple elements formed of thin films of the same layer structure and the same material are referred to as "elements of the same layer." In this specification, "two two-dimensional array circuits overlap in a plan view" means that in the two-dimensional array circuit, a quadrangle formed by the wires at both ends of a first wiring group and the wires at both ends of a second wiring group overlaps in a plan view. The overlapping area is preferably 50% or more, more preferably 75% or more, and most preferably 95% or more, based on the area of ​​either quadrangle.

[0019] In this specification, "the input section and the output section overlap in a planar view" means that a rectangle with the smallest area that includes all input terminals included in the input section and a rectangle with the smallest area that includes all output terminals included in the output section overlap in a planar view. The overlapping area is preferably 50% or more, more preferably 75% or more, and most preferably 95% or more, based on the area of ​​either rectangle. When the input terminals and the output terminals are connected vertically, for example, in the case of via connection using a through-silicon electrode, 100% overlap in a planar view.

[0020] In this specification, when describing elements shown in the drawings, the reference numerals attached to those elements are used. In this case, multiple elements having similar functions may be distinguished by adding a symbol such as an alphabet (e.g., "a," "b," etc.) to the same reference numeral. However, when it is not necessary to distinguish between elements, the elements may be described using only the reference numerals indicating those elements.

[0021] In each of the embodiments described below, the temperature condition for measurements or simulations is room temperature.

[0022] (First embodiment) [Structure of three-dimensional array device] FIG. 1 is a diagram showing the configuration of a three-dimensional array device 10 according to a first embodiment of the present invention. As shown in FIG. 1, the three-dimensional array device 10 includes, from bottom to top, a control circuit 100 and two-dimensional array circuits 200a-200e. The control circuit 100 controls the operations (e.g., signal input / output) of the two-dimensional array circuits 200a-200e. While FIG. 1 shows an example in which five two-dimensional array circuits are stacked vertically, the present invention is not limited to this example and a layer structure of two or more layers may be used. Here, the "vertical direction" refers to a direction perpendicular to the plane constituting the two-dimensional array circuit. Because the three-dimensional array device 10 is a structure in which multiple two-dimensional array circuits 200a-200e are sequentially stacked, the "vertical direction" can also be referred to as the "height direction" or the "up-down direction." In the following description, when it is not necessary to distinguish between the two-dimensional array circuits 200a-200e, they will be collectively referred to as the two-dimensional array circuit 200.

[0023] Each two-dimensional array circuit 200 is a memory cell array circuit based on ReRAM (Resistive Random Access Memory). Specifically, the two-dimensional array circuit 200 has a plurality of memory cells arranged in an array, and each memory cell includes a ReRAM. However, the memory arranged in the memory cell is not limited to ReRAM, and may be other non-volatile memories such as MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and PCRAM (Phase Change Random Access Memory). Furthermore, the two-dimensional array circuit 200 is not limited to a memory cell array circuit, and may be other array-type circuits such as a CMOS sensor array circuit.

[0024] In this embodiment, in-memory computing is realized using three-dimensional array device 10. Specifically, a binary neural network (quantized neural network) is configured using each two-dimensional array circuit 200, and a deep neural network is configured by stacking multiple binary neural networks. For example, three-dimensional array device 10 may configure a deep neural network in which two-dimensional array circuit 200a, two-dimensional array circuits 200b to 200d, and two-dimensional array circuit 200e serve as an input layer, hidden layer, and output layer, respectively.

[0025] As shown in FIG. 1 , each two-dimensional array circuit 200 includes a first wiring group 210, an input unit 215 that inputs signals to the first wiring group 210, a second wiring group 220 that intersects with the first wiring group 210, and an output unit 225 that outputs signals from the second wiring group 220. In this embodiment, the first wiring group 210 is composed of a plurality of word lines. The second wiring group 220 is composed of a plurality of bit lines. Memory cells are provided at the intersections of the word lines and the bit lines. That is, although not shown, at the intersections of the first wiring group 210 and the second wiring group 220, at least one resistive random access memory (ReRAM) and at least one select transistor are disposed as memory cells. The first wiring group 210 is preferably a wiring group consisting of parallel wirings. The second wiring group 220 is preferably a wiring group consisting of parallel wirings, and is preferably a wiring group that intersects with the first wiring group 210 at right angles.

[0026] The input unit 215 is a part that inputs information transmitted from an external circuit (including other two-dimensional array circuits 200) to the two-dimensional array circuit 200. Specifically, the information input from the input unit 215 drives each word line constituting the first wiring group 210. In this embodiment, the input unit 215 is a collection of input terminals electrically connected to each word line. The output unit 225 is a part that outputs information from the two-dimensional array circuit 200 to an external circuit (including other two-dimensional array circuits 200). Specifically, information transmitted via the second wiring group 220 is output via the output unit 225. In this embodiment, the output unit 225 is a collection of output terminals electrically connected to each bit line.

[0027] FIG. 2 is a diagram showing the configuration of a two-dimensional array circuit 200 according to the first embodiment. As shown in FIG. 2, memory cells 230 are arranged at the intersections of a plurality of word lines WL and a plurality of bit lines BL. In this embodiment, each memory cell 230 is composed of a selection transistor 232 and a resistance-change memory 234. The resistance-change memory 234 is provided between the bit line BL and the selection transistor 232. The selection transistor 232 is provided between the resistance-change memory 234 and a source line SL. The word line WL is connected to the gate of the selection transistor 232. However, the configuration of the memory cell 230 is not limited to this example. For example, the resistance-change memory 234 may be provided between the selection transistor 232 and the source line SL.

[0028] Although not shown in FIG. 2, the two-dimensional array circuit 200 includes peripheral circuits for reading and writing information stored in each memory cell 230. The peripheral circuits may include a peripheral circuit for driving the word lines WL and a peripheral circuit for driving the bit lines BL. That is, the input unit 215 shown in FIG. 1 may include a peripheral circuit for driving the word lines WL. The output unit 225 may also include a peripheral circuit for driving the bit lines BL. These peripheral circuits may include at least one circuit selected from a latch circuit, a buffer circuit, a write circuit, a precharge circuit, and an amplifier circuit. The peripheral circuits may be formed, for example, by a circuit consisting only of n-type IGZO or a CMOS circuit consisting of n-type IGZO and p-type SnO. The peripheral circuits may also be formed on the control circuit 100 using Si-CMOS.

[0029] The resistance change memory 234 can store one bit of information by changing the resistance of a CER layer (hereinafter also referred to as a "resistance change layer") that exhibits electric field-induced giant resistance change. For example, the information when the resistance is in a low resistance state (LRS) where the resistance is relatively low is "0," and the information when the resistance is in a high resistance state (HRS) where the resistance is relatively high is "1." However, the correspondence between the resistance value and the information "0" or "1" may be reversed.

[0030] Each memory cell 230 is individually selected by controlling the on / off of the selection transistor 232. The selected memory cell 230 performs an information write operation or read operation according to the voltages applied to the bit line BL and the source line SL. In this embodiment, the word line WL is driven based on a signal input to the input unit 215 of the two-dimensional array circuit 200, and the signal output from the output unit 225 is determined based on a signal read from the memory cell 230 via the bit line BL.

[0031] Returning to FIG. 1 , the two-dimensional array circuit 200a has a first wiring group 210a connected to the input section 215a and a second wiring group 220a connected to the output section 225a. The two-dimensional array circuit 200b has a first wiring group 210b connected to the input section 215b and a second wiring group 220b connected to the output section 225b. The two-dimensional array circuit 200c has a first wiring group 210c connected to the input section 215c and a second wiring group 220c connected to the output section 225c. The two-dimensional array circuit 200d has a first wiring group 210d connected to the input section 215d and a second wiring group 220d connected to the output section 225d. The two-dimensional array circuit 200e has a first wiring group 210e connected to the input section 215e and a second wiring group 220e connected to the output section 225e.

[0032] The three-dimensional array device 10 of this embodiment has a structure in which two-dimensional array circuits 200a-200e are stacked while being rotated by 90 degrees from the lower layer to the upper layer. Specifically, in the three-dimensional array device 10, the positions of the input units 215 and output units 225 change counterclockwise by 90 degrees in planar views. Therefore, in the three-dimensional array device 10 of this embodiment, the input units 215 of the two-dimensional array circuit 200 on the upper layer side and the output units 225 of the two-dimensional array circuit 200 on the lower layer side overlap in planar views.

[0033] 3 is a schematic diagram showing changes in the positions of the input section 215 and the output section 225 in the two-dimensional array circuit 200. Specifically, FIGS. 3(A), 3(B), and 3(C) are plan views showing the configurations of the two-dimensional array circuit 200a, the two-dimensional array circuit 200b, and the two-dimensional array circuit 200c, respectively.

[0034] As shown in FIGS. 1, 3A, and 3B, the two-dimensional array circuit 200b is located at a position obtained by rotating the two-dimensional array circuit 200a 90 degrees counterclockwise in a planar view. In this case, the output section 225a of the two-dimensional array circuit 200a overlaps with the input section 215b of the two-dimensional array circuit 200b. Also, as shown in FIGS. 1, 3B, and 3C, the two-dimensional array circuit 200c is located at a position obtained by rotating the two-dimensional array circuit 200b 90 degrees counterclockwise in a planar view. In this case, the output section 225b of the two-dimensional array circuit 200b overlaps with the input section 215c of the two-dimensional array circuit 200c. Although not shown, the relationship between the two-dimensional array circuit 200c and the two-dimensional array circuit 200d and the relationship between the two-dimensional array circuit 200d and the two-dimensional array circuit 200e are similar.

[0035] As described above, in the three-dimensional array device 10 of this embodiment, the positions of the input units 215 and output units 225 change spirally from the lower layer to the upper layer. Specifically, the three-dimensional array device 10 has a structure in which, from the lower layer to the upper layer, the two-dimensional array circuit on the upper layer is arranged at a position rotated 90 degrees counterclockwise from the two-dimensional array circuit on the lower layer. In this case, signals input to the three-dimensional array device 10 are calculated as they progress from the lower layer to the upper layer. However, the structure of the three-dimensional array device 10 is not limited to this example. For example, the three-dimensional array device 10 may have a structure in which, from the upper layer to the lower layer, the two-dimensional array circuit on the lower layer is arranged at a position rotated 90 degrees clockwise from the two-dimensional array circuit on the upper layer. In other words, the output unit 225 of the two-dimensional array circuit 200 on the upper layer is electrically connected to the input unit 215 of the two-dimensional array circuit 200 on the lower layer. In this case, signals input to the three-dimensional array device 10 are calculated as they progress from the upper layer to the lower layer.

[0036] 1, the output of the lower two-dimensional array circuit 200 becomes the input of the upper two-dimensional array circuit 200. That is, the output section 225 of the lower two-dimensional array circuit 200 is electrically connected to the input section 215 of the upper two-dimensional array circuit 200. In this case, any method may be used for the electrical connection between the input section 215 of the upper two-dimensional array circuit 200 and the output section 225 of the lower two-dimensional array circuit 200. For example, the electrical connection may be a connection using a via that connects wiring layers in a previous process or a connection using a TSV. Furthermore, the electrical connection between the input section 215 and the output section 225 includes an electrical connection between a peripheral circuit included in the input section 215 (such as a peripheral circuit for driving the word line WL) and a peripheral circuit included in the output section 225 (such as a peripheral circuit for driving the bit line BL). Here, the output section 225 of the lower-layer two-dimensional array circuit 200 and the input section 215 of the upper-layer two-dimensional array circuit 200 are electrically connected by vias between wiring layers in a previous process or by TSVs, but the present invention is not limited to these examples. For example, by providing a surface-emitting laser in the output section 225 of the lower-layer two-dimensional array circuit 200 and providing a light-receiving element in the input section 215 of the upper-layer two-dimensional array circuit 200, the output section 225 and the input section 215 can be optically connected by through-silicon optical interconnection (TSFV). Alternatively, a method using radio wave connection by electric field or magnetic field coupling by providing inductors in the lower and upper layers is also possible.

[0037] In this embodiment, the output section 225 of the two-dimensional array circuit 200 on the lower layer and the input section 215 of the two-dimensional array circuit 200 on the upper layer are overlapped in the vertical direction, thereby minimizing the wiring length between the output section 225 and the input section 215. In other words, this structure makes it possible to suppress signal delays and increases in power consumption caused by wiring length compared to conventional techniques, and provides a three-dimensional array device 10 that realizes a neural network with low latency and low energy loss.

[0038] [Memory cell configuration] 4 is a cross-sectional view showing the configuration of a memory cell 230 in the three-dimensional array device 10 of the first embodiment. As described above, in this embodiment, the memory cell 230 includes a selection transistor 232 and a resistance change memory 234. However, the configuration shown in FIG. 4 is an example and is not limited to this example.

[0039] 4, the substrate 21 functions as a base supporting the select transistor 232 and the resistance change type memory 234. In this embodiment, a silicon substrate is used as the substrate 21, but other substrates such as a glass substrate, a resin substrate, a metal substrate, or a ceramic substrate may also be used. Furthermore, when the substrate 21 is a silicon substrate, an integrated circuit using silicon CMOS may be formed thereon. The insulating layer 22 functions as a base layer. In this embodiment, a silicon oxide layer is used as the insulating layer 22, but the present invention is not limited to this example.

[0040] A gate electrode 23 is provided on the insulating layer 22. The gate electrode 23 functions as the bottom gate of the select transistor 232 and also functions as the word line WL shown in FIG. 2. The gate electrode 23 has a laminated structure of a first metal layer 23-1 made of titanium (Ti) and a second metal layer 23-2 made of titanium nitride (TiN). In this embodiment, the first metal layer 23-1 has a thickness of 5 nm, and the second metal layer 23-2 has a thickness of 20 nm, but this is not limited to this example. The gate electrode 23 may have a single-layer structure or may be formed using other metal layers. For example, the gate electrode 23 may be made of a metal material containing tungsten, tantalum, molybdenum, aluminum, copper, or the like, or a compound material containing these metal materials. The gate electrode 23 may be formed by, for example, a sputtering method.

[0041] The gate insulating layer 24 uses hafnium oxide. However, it is not limited to this, and as the gate insulating layer 24, a dielectric layer containing an oxide or nitride such as silicon or aluminum may be used. The gate insulating layer 24 can be formed, for example, using the ALD (Atomic Layer Deposition) method at a temperature of 250°C. In this embodiment, the film thickness of the gate insulating layer 24 is 8 nm, but it is not limited to this example.

[0042] The channel layer 25 functions as the channel of the selection transistor 232. In this embodiment, as the material constituting the channel layer 25, a metal oxide called IGZO is used. IGZO is a metal oxide exhibiting semiconductor characteristics and is a compound material composed of indium, gallium, zinc, and oxygen. Specifically, IGZO is an oxide containing In, Ga, and Zn, or a mixture of such oxides. The composition of IGZO is preferably In 2-x Ga x O3(ZnO) m (0 < x < 2, m is a natural number of 0 or less than 6), more preferably InGaO3(ZnO) m (m is a natural number of 0 or less than 6), most preferably InGaO3(ZnO). In this embodiment, as the channel layer 25, an IGZO film with a film thickness of 8 nm is used. The IGZO film can be formed by a sputtering method at room temperature. Instead of IGZO, other oxide semiconductors, such as an oxide containing In, an oxide containing Zn, an oxide containing Sn, an oxide containing In and Zn, an oxide containing In and Sn, an oxide containing Sn and Zn, an oxide containing In, Sn, and Zn, or an oxide composed of other elements, can also be used as the material constituting the channel layer .

[0043] In this embodiment, the gate insulating layer 24 is made of a dielectric layer, and the channel layer 25 is made of an IGZO film. This prevents the formation of an interfacial layer with a low dielectric constant at the interface between the gate insulating layer 24 and the channel layer 25, thereby preventing deterioration of the transistor characteristics. Such an interfacial layer with a low dielectric constant may be formed between the gate insulating layer 24 and the channel layer 25 when the channel layer is made of silicon.

[0044] The source electrode 26 and the drain electrode 27 each function as a connection terminal for achieving electrical connection with the channel layer 25. In this embodiment, a titanium nitride layer with a thickness of 20 nm is used as the source electrode 26 and the drain electrode 27. The titanium nitride layer can be formed by, for example, a sputtering method. However, this example is not limiting, and the source electrode 26 and the drain electrode 27 may be made of other metal materials. Note that the functions of the source electrode 26 and the drain electrode 27 may be reversed depending on the voltage applied thereto. That is, the source electrode 26 may function as a drain electrode, and the drain electrode 27 may function as a source electrode. Note that the drain electrode 27 functions as a lower electrode of the resistance change memory 234, as will be described later.

[0045] The select transistors 232 are covered with an insulating layer 28. In this embodiment, the insulating layer 28 is a silicon oxide layer with a thickness of 200 nm. The insulating layer 28 can be formed by, for example, plasma CVD or sputtering. As will be described later, the three-dimensional array device 10 of this embodiment has a structure in which multiple memory cell array circuits are stacked. Therefore, the insulating layer 28 has the function of insulating and isolating the memory cell array circuits on the lower layer from the memory cell array circuits on the upper layer. The insulating layer 28 also functions as a passivation layer that protects the channel layer 25 of the select transistor 232 from moisture and the like. Furthermore, the insulating layer 28 also functions as a planarization layer that planarizes undulations caused by the select transistors 232. However, the material constituting the insulating layer 28 is not limited to silicon oxide, and other insulating materials (e.g., inorganic materials such as silicon nitride, or resin materials such as polyimide and acrylic) can also be used.

[0046] The insulating layer 28 has an opening 29. The opening 29 is provided on the drain electrode 27 and exposes the surface of the drain electrode 27. The opening 29 can be formed by, for example, photolithography. In this embodiment, the diameter of the opening 29 is 3 μm, but is not limited to this example.

[0047] A resistance change layer 30 is provided on the sidewalls and bottom of the opening 29. The resistance change layer 30 is made of a dielectric layer containing hafnium oxide, and functions as a CER layer of the resistance change memory 234. In this embodiment, the dielectric layer is used as the resistance change layer 30 without being patterned, but it may be processed into a pattern that covers the opening 29.

[0048] An upper electrode 31 is provided on the resistance change layer 30 so as to cover the opening 29. The upper electrode 31 functions as an electrode of the resistance change memory 234 and also functions as the bit line BL shown in FIG. 2. In this embodiment, the upper electrode 31 is made of the same metal layer as the gate electrode 23 of the select transistor 232 in the memory cell array circuit on the upper layer side. That is, the upper electrode 31 has a stacked structure of a first metal layer 31-1 made of titanium (Ti) and a second metal layer 31-2 made of titanium nitride (TiN). In this case, as with the gate electrode 23, it can be formed by, for example, a sputtering method.

[0049] As described above, inside the opening 29 provided in the insulating layer 28, a resistance change memory 234 composed of the lower electrode (part of the drain electrode 27), the resistance change layer 30, and the upper electrode 31 is formed. The resistance change memory 234 is connected to the select transistor 232 via the drain electrode 27. As shown in FIG. 2, the memory cell 230 described above includes the select transistor 232 whose gate is the word line WL, and the resistance change memory 234 arranged between the select transistor 232 and the bit line BL.

[0050] The three-dimensional array device 10 of this embodiment is configured by stacking memory cell array circuits (two-dimensional array circuits 200) in which the above-mentioned memory cells 230 are arranged in an array. Specifically, the three-dimensional array device 10 has a device structure in which the memory cells 230 shown in FIG. 4 are stacked in the vertical direction.

[0051] 5 is an enlarged cross-sectional view showing the configuration of three-dimensional array device 10 of the first embodiment. Specifically, it shows the state in which two-dimensional array circuits 200a-200c have been formed on substrate 21. As shown in FIG. 5, two-dimensional array circuits 200a-200c are stacked on substrate 21 using a thin-film formation process. At this time, select transistors 232a-232c of each of two-dimensional array circuits 200a-200c are separated by insulating layers 28a-28c, respectively.

[0052] 5, the upper electrode 31a in the resistance change memory 234a in the two-dimensional array circuit 200a is configured in the same metal layer as the gate electrode 23b in the select transistor 232b in the two-dimensional array circuit 200b. That is, the upper electrode 31a and the gate electrode 23b are configured in a metal layer having the same structure and material. Similarly, the upper electrode 31b in the resistance change memory 234b in the two-dimensional array circuit 200b is configured in the same metal layer as the gate electrode 23c in the select transistor 232c in the two-dimensional array circuit 200c. In other words, in this embodiment, the bit lines BL (second wiring group 220) of the lower two-dimensional array circuit 200 and the word lines WL (first wiring group 210) of the upper two-dimensional array circuit 200 are configured in the same metal layer.

[0053] Fig. 6 is a photograph substituting for a drawing showing the layout of memory cell 230a of two-dimensional array circuit 200a shown in Fig. 3(A). Fig. 7 is a plan view schematically showing the layout of memory cell 230a shown in Fig. 6.

[0054] 6 and 7, word line WL1 corresponds to gate electrode 23a in FIG. 5, and bit line BL1 corresponds to upper electrode 31a in FIG. 5. Memory cell 230a has FET1 and ReRAM1 at the intersection of word line WL1 and bit line BL1. As described with reference to FIG. 5, ReRAM1 is located inside opening 29a provided in insulating layer 28a. In FIG. 6, the circular portion indicated by the arrow corresponds to opening 29a. However, this is not limiting, and the shape of opening 29a may be polygonal.

[0055] The source line SL1 extends in parallel to the word line WL1. As shown in FIG. 7, the source line SL1 is formed integrally with the source electrode 26a of the FET1 (the select transistor 232a in FIG. 5). The lower electrode of the ReRAM1 (the resistance change memory 234a in FIG. 5) is formed integrally with the drain electrode 27a of the FET1 (the select transistor 232a in FIG. 5). The word line WL2 is a wiring formed in the same layer as the bit line BL1, and corresponds to the gate electrode 23b of the select transistor 232b in FIG. 5.

[0056] Fig. 8 is a photograph showing a cross-sectional structure near the channel of FET1 shown in Fig. 6. Specifically, Fig. 8 shows a cross-sectional structure near the channel of select transistor 232a shown in Fig. 5. As shown in Fig. 8, from the bottom up, a titanium nitride layer constituting gate electrode 23a, a dielectric layer containing hafnium oxide constituting gate insulating layer 24a, an IGZO layer constituting channel layer 25a, and a silicon oxide layer constituting insulating layer 28a are uniformly formed.

[0057] 9 is a photograph showing the cross-sectional structure of the ReRAM1 shown in FIG. 6. Specifically, FIG. 9 shows the cross-sectional structure of the resistance change memory 234a shown in FIG. 5. As shown in FIG. 9, from the bottom up, a titanium nitride layer constituting the drain electrode 27a, a dielectric layer containing hafnium oxide constituting the resistance change layer 30a, and a titanium layer and a titanium nitride layer constituting the upper electrode 31a are uniformly formed. As will be described later, in this embodiment, a structure in which the titanium layer and the dielectric layer containing hafnium oxide are in contact with each other forms a filament of oxygen vacancies inside the dielectric layer.

[0058] FIG. 10 is a photograph, substituted for a drawing, showing the layout of memory cell 230b of two-dimensional array circuit 200b shown in FIG. 3(B). FIG. 11 is a photograph, substituted for a drawing, showing the layout of memory cell 230c of two-dimensional array circuit 200c shown in FIG. 3(C). Below memory cell 230b shown in FIG. 10, memory cell 230a shown in FIG. 6 is arranged. Below memory cell 230c shown in FIG. 11, memory cell 230a shown in FIG. 6 and memory cell 230b shown in FIG. 10 are arranged, from bottom to top, below memory cell 230c. The layouts shown in FIGS. 6, 10, and 11 correspond to FIGS. 3(A), 3(B), and 3(C), respectively, and are rotated counterclockwise by 90 degrees in plan view.

[0059] As described above, the three-dimensional array device 10 of this embodiment is constructed by stacking multiple two-dimensional array circuits 200 (multiple memory cell circuits) using a typical thin-film formation process. In this embodiment, an IGZO layer that can be formed at room temperature is used as the channel layer 25 of the select transistor 232, so the three-dimensional array device 10 can be formed using a low-temperature process at 400 degrees or less. Furthermore, the select transistor 232 using the IGZO layer as the channel layer 25 has sufficient mobility to drive the memory cell 230. Therefore, this embodiment can provide a three-dimensional array device 10 that realizes in-memory computing in AI applications using deep neural networks.

[0060] [Characteristics of three-dimensional array devices] The characteristics of the selection transistor 232 or the resistance change memory 234 constituting the three-dimensional array device 10 of this embodiment will be described below.

[0061] FIG. 12 is a diagram showing the Id-Vg characteristics of the select transistors 232a to 232c in the three-dimensional array device 10 of the first embodiment. "1st" indicates the characteristics of the select transistor 232a in the first two-dimensional array circuit 200a shown in FIG. 6. "2nd" indicates the characteristics of the select transistor 232b in the second two-dimensional array circuit 200b shown in FIG. 10. "3rd" indicates the characteristics of the select transistor 232c in the third two-dimensional array circuit 200c shown in FIG. 11. The source-drain voltage (Vd) was set to 50 mV or 2 V. The channel width and channel length were set to 100 μm and 10 μm, respectively. FIG. 12 also shows the subthreshold coefficient (SS) calculated from the Id-Vg characteristics.

[0062] 13 is a diagram showing the Id-Vd characteristics of the select transistors 232a to 232c in the three-dimensional array device 10 of the first embodiment. The meanings of "1st," "2nd," and "3rd" are the same as in FIG. 12. The channel width and channel length were set to 100 μm and 10 μm, respectively. The gate voltage (Vg) was set to 0.5 V, 1 V, 1.5 V, or 2 V.

[0063] 12 and 13, the select transistors 232a to 232c all exhibit substantially the same transfer characteristics and output characteristics, and no degradation due to the three-dimensional integration process is observed. A drive current of 200 μA or more was obtained for each of the select transistors 232a to 232c. Thus, in this embodiment, by using transistors with a small off-current, a large on-off ratio, and a sufficiently large current drive force (specifically, transistors with an IGZO layer as a channel layer) as the select transistors 232a to 232c, a memory cell with excellent switching characteristics can be configured.

[0064] Figure 14 compares the IV characteristics of a memory cell composed of a select transistor 232 and a ReRAM 234 (hereinafter referred to as a "1T1R" cell) with those of a memory cell composed only of a ReRAM 234 (hereinafter referred to as a "1R" cell). The IV characteristics of both the "1T1R" cell and the "1R" cell are plotted by overlaying multiple measurements, showing the variation between measurement cycles. Voltage was applied to the upper electrode 31 with the source electrode 26 grounded. The set / reset voltage sweep range for the 1R cell was 1V / -1.5V, while the set / reset voltage sweep range for the 1T1R cell was 1.5V / -1.8V. In Figure 14, the size of the ReRAM 234 was 3 μm × 3 μm for both memory cells. The gate voltages of the select transistor 232 of the 1T1R cell during set / reset operations were 2.5V / 1.5V.

[0065] 14, the on-current of the "1T1R" cell is smaller than that of the "1R" cell. In the "1T1R" cell, the select transistor 232 connected to the ReRAM 234 acts as a series resistor. Therefore, the reason why the on-current of the "1T1R" cell is measured to be relatively small is thought to be the effect of the series resistance caused by the select transistor 232.

[0066] Figure 15 shows the cumulative probability of the set / reset voltages of the "1T1R" and "1R" cells measured from the IV characteristics shown in Figure 14. Figure 15 shows the variation in the set / reset voltages of the "1T1R" and "1R" cells between measurement cycles. As shown in Figure 15, there was almost no difference in the set voltage between the "1T1R" and "1R" cells. However, the "1T1R" cell exhibited a larger absolute value of reset voltage than the "1R" cell. This is because, during set, the ReRAM 234 is in a high-resistance state, so the voltage drop due to the select transistor 232 can be ignored. However, during reset, the ReRAM 234 is in a low-resistance state, so the series resistance due to the select transistor 232 cannot be ignored relative to the resistance of the ReRAM 234. Therefore, to achieve low-voltage operation and a small area for the "1T1R" cell, it is desirable to increase the mobility of the select transistor 232 and reduce the series resistance.

[0067] FIG. 16 is a diagram showing the IV characteristics of the "1T1R" cell extracted from the IV characteristics shown in FIG. 14. As shown in FIG. 16, the "1T1R" cell is in a low resistance state in the region indicated by "LRS" and in a high resistance state in the region indicated by "HRS." FIG. 17 is a diagram showing the cumulative probability of the resistance values ​​of the "1T1R" cell in the low resistance state and the high resistance state measured from the IV characteristics shown in FIG. 16. FIG. 17 shows the variation in the resistance value of the "1T1R" cell between measurement cycles. The read voltage was set to 0.1 V.

[0068] As is clear from Figures 16 and 17, the IV characteristics of the "1T1R" cell show some variation between measurement cycles in the high resistance state. In contrast, the resistance values ​​in the low resistance state show a nearly uniform distribution. This phenomenon is thought to be due to variations in the dissociation of the filament in the high resistance state.

[0069] FIG. 18 is a diagram showing the IV characteristics of "1T1R" cells in the two-dimensional array circuits 200a to 200c. In FIG. 18, "1st layer," "2nd layer," and "3rd layer" refer to the two-dimensional array circuits 200a to 200c, respectively. Each IV characteristic shown in FIG. 18 is a graph in which the average value of the results of multiple measurements per device is plotted for 11 devices. In other words, the variation in the IV characteristics shown in FIG. 18 indicates the variation between devices. In FIG. 18, the gate voltages during the set / reset operations were set to 2.5 / 1.5V. As shown in FIG. 18, no significant differences in the IV characteristics were observed among the two-dimensional array circuits 200a to 200c.

[0070] FIG. 19 is a diagram showing the cumulative probability of resistance values ​​in the low resistance state and the high resistance state measured from the IV characteristics of the two-dimensional array circuits 200a to 200c shown in FIG. 18. FIG. 19 shows the device-to-device variation in the resistance values ​​of the "1T1R" cells in each layer. The read voltage was set to 0.1 V. The results shown in FIG. 19 show that the two-dimensional array circuits 200a to 200c show almost the same distribution in the range where the ratio of the resistance in the LRS state to the resistance in the HRS state is greater than 10. This indicates that no degradation of memory characteristics is observed due to the three-dimensional stacking process.

[0071] 20 is a diagram showing the rewrite endurance characteristics of the ReRAMs of the two-dimensional array circuits 200a to 200c at room temperature. The endurance characteristics shown in FIG. 20 were measured in a cycle test with a pulse width of 1 μs and a Set / Reset voltage of 1 V / −1.5 V. As shown in FIG. 20, the ReRAMs of each layer showed a 10 5No degradation was observed after 100 Set / Reset cycles. Furthermore, no difference in rewrite endurance characteristics was observed among the three layers. FIG. 21 shows the retention characteristics of the ReRAMs in the two-dimensional array circuits 200a-200c at room temperature, and no degradation was observed after 12 hours in the ReRAMs in each layer. Furthermore, no difference in retention characteristics was observed among the three layers. As shown in FIGS. 20 and 21, no significant differences were observed among the two-dimensional array circuits 200a-200c, and no decrease in reliability due to three-dimensional integration was observed.

[0072] The present inventors actually fabricated an XNOR circuit using a memory cell 230 (a "1T1R" cell) having the structure shown in FIG.

[0073] FIG. 22 is a circuit diagram showing the configuration of an XNOR circuit using two "1T1R" cells. FIG. 23 is a photograph showing the configuration of a memory cell array prototyped using the memory cell 230 of the first embodiment. FIG. 24 is a photograph showing the configuration of an external peripheral circuit used to measure the prototype XNOR circuit. FIG. 25 is a diagram showing the measurement results of the prototype XNOR circuit. Specifically, FIG. 25(A) shows the results when (R, R')=(High, Low) in the circuit diagram shown in FIG. 22, and FIG. 25(B) shows the results when (R, R')=(Low, High) in the circuit diagram shown in FIG. 22. During the measurement, a precharge voltage (V PC )=0.3V, reference voltage (V REF )=0.1V, word line voltage (V WL ) = 1.5V. The power supply voltage for the external peripheral circuits was set to 3.3V.

[0074] In the XNOR circuit shown in FIG. 22, weight bits (W) are written to two ReRAMs in a complementary manner. Input bits (x) are applied to two word lines (WL) in a complementary manner. Also, the capacitors (V BL) is precharged via the precharge switch (PC). The precharged capacitor is discharged slowly or quickly depending on the weight bit (W) and input bit (x). After a certain time, the voltage on the bit line (BL) is compared to the reference voltage (V REF ) and binarized to obtain the final output bit (y).

[0075] In this way, the XNOR circuit outputs binary data by utilizing the difference in the capacitor discharge speed depending on the combination of the difference between the two complementary resistance values ​​(R, R') written into the two "1T1R" cells and the word line voltage. For example, when W = 0, R is set to the low resistance state (LRS) and R' is reset to the high resistance state (HRS). In this case, when x = 0, the ReRAM reset to the high resistance state is selected, so the capacitor discharge speed is slow. Conversely, when x = 1, the ReRAM set to the low resistance state is selected, so the capacitor discharge speed is fast. Therefore, by appropriately setting the discharge time and reference voltage, the voltage of the bit line (BL) can be detected and the result of comparison with the reference voltage can be output from the comparator.

[0076] As shown in FIG. 25, when the input bit (x) and the weight bit (W) are the same (when x=W=0 or when x=W=1), the discharge speed slows down, and the voltage of the bit line (BL) after a certain time has passed since the start of discharge becomes equal to the reference voltage (V REF ) remains higher than the reference voltage (V REF ) becomes lower. As a result, the comparator outputs "0." This operation performs the XNOR operation shown in the truth table in Figure 22.

[0077] As described above, normal XNOR operation was confirmed in the XNOR circuit prototyped using the memory cell 230 of this embodiment.

[0078] (Modification of the first embodiment) 4 and 5 show an example in which a bottom-gate transistor is used as the select transistor 232, but this is not limiting and a top-gate transistor may also be used. Also, while Fig. 5 shows an example in which the upper electrode 31 of the resistance change memory 234 in the lower layer is an element in the same layer as the gate electrode 23 of the select transistor 232 in the upper layer adjacent to the lower layer, these may be elements formed from different layers and separated by an insulating layer.

[0079] FIG. 26 is an enlarged cross-sectional view showing the configuration of a three-dimensional array device 10 according to a modification of the first embodiment. Specifically, the diagram shows a state in which two-dimensional array circuits 200a-200c, each having a top-gate select transistor 232, are formed on a substrate 41. As shown in FIG. 26, the two-dimensional array circuits 200a-200c are stacked on the substrate 41 using a thin-film formation process. At this time, the two-dimensional array circuits 200a-200c are separated by insulating layers 43 and 44, respectively. In this modification, silicon oxide is used as the material constituting the insulating layers 43 and 44; however, the present invention is not limited to this example, and other insulating materials (for example, inorganic materials such as silicon nitride, or resin materials such as polyimide and acrylic) can also be used.

[0080] In FIG. 26, the substrate 41 is a silicon substrate, and the insulating layer 42 is a silicon oxide layer. The substrate 41 and the insulating layer 42 can be made of the same materials as the substrate 21 and the insulating layer 22 shown in FIG. 4. When the substrate 41 is a silicon substrate, an integrated circuit using silicon CMOS may be formed. For ease of explanation, FIG. 26 shows an example in which two-dimensional array circuits 200a-200c are stacked on the substrate 41 and the insulating layer 42, but in reality, two-dimensional array circuits 200d and 200e are stacked on the two-dimensional array circuit 200c. Since the two-dimensional array circuits 200a-200c have the same structure, the specific structure of the two-dimensional array circuit 200a will be described below.

[0081] As shown in FIG. 26, a channel layer 51a, a gate insulating layer 52a, a gate electrode 53a, and sidewalls 54a are provided on the insulating layer 42. In this modification, IGZO, hafnium oxide, tantalum, and silicon oxide are used as materials for the channel layer 51a, the gate insulating layer 52a, the gate electrode 53a, and the sidewalls 54a, respectively. However, this is not limiting, and the materials for the channel layer 51a, the gate insulating layer 52a, and the gate electrode 53a can be the same as the channel layer 25, the gate insulating layer 24, and the gate electrode 23 shown in FIG. 4. Furthermore, an insulating layer other than silicon oxide may be used as a material for the sidewalls 54a. The gate electrode 53a functions as the top gate of the select transistor 232 and also functions as the word line WL.

[0082] A source electrode 56a is provided on an insulating layer 55a that covers the channel layer 51a, the gate insulating layer 52a, the gate electrode 53a, and the sidewalls 54a. The source electrode 56a is connected to the channel layer 51a via a contact hole formed in the insulating layer 55a. In this modification, silicon oxide and tantalum nitride are used as materials for the insulating layer 55a and the source electrode 56a, respectively, but the materials are not limited to this example. Although not shown in the drawings, the source electrode 56a is connected to a source line SL. It is preferable that the gate electrode and the source / drain electrodes are self-aligned.

[0083] An insulating layer 57a is provided on the source electrode 56a. A via hole is formed through the insulating layers 55a and 57a, and a via 58a is provided inside the via hole. In this modification, tantalum nitride is used as the material for the via 58a, but the material is not limited to this example. The upper surfaces of the insulating layer 57a and the via 58a are planarized using, for example, CMP (Chemical Mechanical Polishing).

[0084] A resistance change memory 234a is provided on the insulating layer 57a. In this modification, the resistance change memory 234a is composed of a lower electrode 59a, a resistance change layer 60a, a first metal layer 61-1a, and a second metal layer 61-2a. A stacked electrode composed of the first metal layer 61-1a and the second metal layer 61-2a functions as an upper electrode 61a of the resistance change memory 234a. In this modification, the materials constituting the lower electrode 59a, the resistance change layer 60a, the first metal layer 61-1a, and the second metal layer 61-2a are titanium nitride, hafnium oxide, titanium, and titanium nitride, respectively. However, this is not a limitation, and the lower electrode 59a and the upper electrode 61a may be composed of other metal materials, and the resistance change layer 60a may be composed of other insulating materials.

[0085] In this modification, the resistance change memory 234a has a structure called a pillar type. Such a pillar type resistance change memory 234a can be formed, for example, by stacking a titanium nitride layer, a hafnium oxide layer, a titanium layer, and a titanium nitride layer in this order from the bottom up, and then etching them all at once.

[0086] Furthermore, in this modification, the side surfaces of the resistance change memory 234a are covered with the insulating layer 62a. Such a structure can be achieved by covering the resistance change memory 234a formed by the above-described method with the insulating layer 62a, and then reducing the film thickness of the insulating layer 62a by CMP or the like until the top surface of the second metal layer 61-2a is exposed. However, the present invention is not limited to this example, and the resistance change memory 234a may be formed by any method.

[0087] A wiring 63a is provided on the insulating layer 62a. The wiring 63a functions as a bit line BL. In this modification, tungsten is used as the material for the wiring 63a, but the material is not limited to this example. The wiring 63a may be made of the same material as the gate electrode 53a.

[0088] A two-dimensional array circuit 200b is provided on the two-dimensional array circuit 200a having the structure described above, with an insulating layer 43 interposed therebetween. The structure of the two-dimensional array circuit 200b is similar to that of the two-dimensional array circuit 200a, and elements denoted with the same numbers have the same functions. As described with reference to FIG. 3, the two-dimensional array circuit 200a and the two-dimensional array circuit 200b are positioned at 90-degree angles relative to each other. Therefore, as shown in FIG. 26, the word lines WL (gate electrodes 53a) of the two-dimensional array circuit 200a are substantially perpendicular to the word lines WL (gate electrodes 53b) of the two-dimensional array circuit 200b. Similarly, the bit lines BL (wirings 63a) of the two-dimensional array circuit 200a are substantially perpendicular to the bit lines BL (wirings 3b) of the two-dimensional array circuit 200b.

[0089] The relationship between the two-dimensional array circuit 200a and the two-dimensional array circuit 200b described above is similar to that between the two-dimensional array circuit 200b and the two-dimensional array circuit 200a, so a detailed description thereof will be omitted.

[0090] As described above, the insulating layers 43 and 44 are interposed between the two-dimensional array circuits 200a to 200c. Therefore, for example, the output section of the two-dimensional array circuit 200a is electrically connected to the input section of the two-dimensional array circuit 200b through a via (not shown) provided in the insulating layer 43. Similarly, the output section of the two-dimensional array circuit 200b is electrically connected to the input section of the two-dimensional array circuit 200c through a via (not shown) provided in the insulating layer 44. In this manner, in this modification, the output section of the lower-layer two-dimensional array circuit and the input section of the upper-layer two-dimensional array circuit are electrically connected through a via provided in the insulating layer between them. Therefore, the wiring distance between the output section of the lower-layer two-dimensional array circuit and the input section of the upper-layer two-dimensional array circuit can be shortened, thereby suppressing the effects of wiring delay and energy loss.

[0091] (Second embodiment) In the first embodiment, it is assumed that a binary neural network is configured using two-dimensional array circuits 200. Therefore, the input and output of each two-dimensional array circuit 200 are processed digitally using digital signals (binary data).

[0092] 27 is a circuit diagram showing the configuration of a memory cell array circuit that executes arithmetic processing in a digital manner. In the memory cell array circuit shown in FIG. 27, a comparator 240 is arranged at the output end of the bit line BL. The comparator 240 compares the output data of the bit line BL with the reference data (V REF 27, the comparator 240 outputs a 1-bit digital signal in accordance with the output data of the bit line BL input to the comparator 240.

[0093] On the other hand, the two-dimensional array circuit 200 is not limited to a digital system, and can also perform input and output using analog signals and execute arithmetic processing in an analog system.

[0094] FIG. 28 is a circuit diagram showing the configuration of a memory cell array circuit that performs arithmetic processing in an analog manner. Specifically, the example shown in FIG. 28 shows a configuration that performs a product-sum operation in an analog manner. In the memory cell array circuit shown in FIG. 28, an analog amplifier circuit 250 is arranged at the output end of the bit line BL. The analog amplifier circuit 250 outputs the output signal of the bit line BL as an analog signal, thereby outputting the result of the product-sum operation. Note that in the analog amplifier circuit 250, the impedance connected between the input terminal and the output terminal may be a resistor (R) or a capacitor (C).

[0095] When a three-dimensional array device 10 is configured using a two-dimensional array circuit 200 that implements the analog arithmetic circuit shown in Figure 28, the analog signal output from the output unit 225 is input to the input unit 215 of the upper two-dimensional array circuit 200. The input unit 215 can input the input analog signal directly to the word line WL, or it can A / D convert the input analog signal to a pulse-width modulated modulated signal and input it to the word line WL. In this way, a signal can be output to the bit line depending on the input pulse time of the analog input signal or modulated signal input to the word line WL and the resistance value of the memory cell 230, and a product-sum operation can be performed in an analog manner.

[0096] As described above, the three-dimensional array device 10 described in the first embodiment can perform arithmetic processing by either a digital method or an analog method.

[0097] (Third embodiment) In the third embodiment, a three-dimensional array device 10a having a different structure from that of the first embodiment will be described. In the description using the drawings, the parts common to the first embodiment will be denoted by the same reference numerals as in the first embodiment, and detailed description thereof may be omitted.

[0098] FIG. 29 is a diagram showing the configuration of a three-dimensional array device 10a according to a third embodiment of the present invention. As shown in FIG. 29, the three-dimensional array device 10a includes, from bottom to top, a control circuit 100 and two-dimensional array circuits 300a-300e. The control circuit 100 controls the operation of each of the two-dimensional array circuits 300a-300e. While FIG. 29 shows an example in which five layers of two-dimensional array circuits are stacked, this is not limiting and a layer structure of two or more layers can also be used. In the following description, when there is no need to distinguish between the two-dimensional array circuits 300a-300e, they will be collectively referred to as two-dimensional array circuits 300.

[0099] Each two-dimensional array circuit 300 is a memory cell array circuit based on ReRAM, as in the first embodiment. Each two-dimensional array circuit 300 has a first wiring group 310, an input unit 315 that inputs signals to the first wiring group 310, a second wiring group 320 that intersects with the first wiring group 310, and an output unit 325 that outputs signals from the second wiring group 320. In this embodiment, the first wiring group 310 is composed of a plurality of word lines. The second wiring group 320 is composed of a plurality of bit lines. Memory cells are provided at the intersections where the word lines and bit lines intersect. That is, although not shown, at the intersections where the first wiring group 310 and the second wiring group 320 intersect, at least one resistive random access memory (ReRAM) and at least one select transistor are arranged as memory cells.

[0100] The functions of the input unit 315 and the output unit 325 are similar to those of the input unit 215 and the output unit 225 in the first embodiment. That is, the input unit 315 may include a peripheral circuit for driving the word line WL, and the output unit 325 may include a peripheral circuit for driving the bit line BL. Furthermore, the electrical connection between the input unit 315 and the output unit 325 includes the electrical connection between the peripheral circuit included in the input unit 315 (the peripheral circuit for driving the word line WL) and the peripheral circuit included in the output unit 325 (the peripheral circuit for driving the bit line BL).

[0101] Three-dimensional array device 10a of this embodiment has a structure in which two-dimensional array circuits 300a-300e are stacked from the bottom layer to the top layer so that the positions of input sections 315 and output sections 325 are interchanged. Specifically, in three-dimensional array device 10a, input sections 315 and output sections 325 are arranged alternately in the vertical direction in a planar view. Therefore, in three-dimensional array device 10a of this embodiment, input sections 315 of two-dimensional array circuit 300 on the upper layer side and output sections 325 of two-dimensional array circuit 300 on the lower layer side overlap in a planar view.

[0102] 29, the output of the lower-layer two-dimensional array circuit 300 becomes the input of the upper-layer two-dimensional array circuit 300. That is, the output section 325 of the lower-layer two-dimensional array circuit 300 is electrically connected to the input section 315 of the upper-layer two-dimensional array circuit 300. In this case, any method may be used for the electrical connection between the input section 315 of the upper-layer two-dimensional array circuit 300 and the output section 325 of the lower-layer two-dimensional array circuit 300.

[0103] In this embodiment, the output section 325 of the two-dimensional array circuit 300 on the lower layer and the input section 315 of the two-dimensional array circuit 300 on the upper layer are overlapped in the vertical direction, thereby minimizing the wiring length between the output section 325 and the input section 315. In other words, this structure makes it possible to suppress signal delays and increases in power consumption caused by wiring length compared to conventional techniques, and it is possible to provide a three-dimensional array device 10a that realizes a neural network with low latency and low energy loss.

[0104] (Fourth embodiment) In the above-described embodiment, an example was shown in which each layer constituting the three-dimensional array device includes one two-dimensional array circuit, but this is not limited to this example. For example, the three-dimensional array device may have a structure in which m layers (m is a natural number) of circuit groups are stacked in the three-dimensional direction, and each layer may have n (n is a natural number) two-dimensional array circuits. In other words, the three-dimensional array device of this embodiment may have a configuration in which m × n two-dimensional array circuits are electrically connected.

[0105] The n two-dimensional array circuits provided on each layer are electrically connected between the output of the preceding two-dimensional array circuit and the input of the following two-dimensional array circuit. The output of the final two-dimensional array circuit on the lower layer overlaps and is electrically connected to the input of the first two-dimensional array circuit on the adjacent upper layer in plan view. The values ​​of m and n can be appropriately designed, taking into consideration the increased footprint and the increased cost due to the multi-layer structure.

[0106] The above-described embodiments of the present invention can be implemented in any suitable combination as long as they are not mutually contradictory. A nonvolatile memory element or a nonvolatile memory device according to any of the embodiments may be appropriately combined, deleted, or modified by a person skilled in the art, or a process may be added, omitted, or conditions may be changed. As long as the gist of the present invention is maintained, such a combination is also included in the scope of the present invention.

[0107] Furthermore, even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0108] 10, 10a... three-dimensional array device, 21... substrate, 22... insulating layer, 23... gate electrode, 23-1... first metal layer, 23-2... second metal layer, 24... gate insulating layer, 25... channel layer, 26... source electrode, 27... drain electrode, 28... insulating layer, 29... opening, 30... resistance change layer, 31... upper electrode, 31-1... first metal layer, 31-2... second metal layer, 100... control circuit, 200... two-dimensional array circuit, 210... first wiring group, 215... input section, 220... second wiring group, 225... output section, 230... memory cell, 232... selection transistor, 234... resistance change memory, 240... comparator, 250... analog amplifier circuit, 300...two-dimensional array circuit, 310...first wiring group, 315...input section, 320...second wiring group, 325...output section, 41...substrate, 42-44...insulating layer, 51a-51c...channel layer, 52a-52c...gate insulating layer, 53a-53c...gate electrodes, 54a-54c...sidewall, 55a-55c...insulating layer, 56a-56c...source electrode, 57a-57c...insulating layer, 58a-58c...via, 59a-59c...lower electrode, 60a-60c...resistance change layer, 61-1a-61-1c...first metal layer, 61-2a-61-2c...second metal layer, 61a-61c...upper electrode, 62a-62c...insulating layer, 63a-63c...wiring

Claims

1. A three-dimensional array device having multiple layers in a height direction, a first two-dimensional array circuit located on a first layer; a second two-dimensional array circuit located on a second layer adjacent to the first layer and overlapping the first two-dimensional array circuit in a plan view; Equipped with the first two-dimensional array circuit and the second two-dimensional array circuit are memory cell array circuits each having a first wiring group, an input section consisting of a collection of input terminals that input signals to the first wiring group, a second wiring group that intersects with the first wiring group, and an output section consisting of a collection of output terminals that output signals from the second wiring group; A three-dimensional array device, wherein the output section of the first two-dimensional array circuit overlaps with the input section of the second two-dimensional array circuit in a plan view and is connected to enable signal transfer.

2. 2. The three-dimensional array device of claim 1, wherein the first two-dimensional array circuit and the second two-dimensional array circuit are stacked from the lower layer to the upper layer so that the positions of the input section and the output section change spirally, or so that the positions of the input section and the output section are interchanged.

3. A three-dimensional array device having multiple layers in a height direction, a first two-dimensional array circuit located on a first layer; a second two-dimensional array circuit located on a second layer adjacent to the first layer and overlapping the first two-dimensional array circuit in a plan view; Equipped with the first two-dimensional array circuit and the second two-dimensional array circuit are memory cell array circuits each having a first wiring group, an input unit that inputs signals to the first wiring group, a second wiring group that intersects with the first wiring group, and an output unit that outputs signals from the second wiring group; the output unit of the first two-dimensional array circuit is located closer to the input unit of the second two-dimensional array circuit than the output unit of the second two-dimensional array circuit, and is connected to the input unit of the second two-dimensional array circuit so as to be able to exchange signals; a direction in which the second wiring group in the first two-dimensional array circuit extends is substantially parallel to a direction in which the first wiring group in the second two-dimensional array circuit extends;

4. 4. The three-dimensional array device according to claim 1, wherein the input section of the first two-dimensional array circuit does not overlap the output section of the second two-dimensional array circuit in a plan view.

5. 5. The three-dimensional array device according to claim 1, wherein the output section of the first two-dimensional array circuit is electrically connected to the input section of the second two-dimensional array circuit through a via.

6. the first wiring group is a wiring group configured of word lines, 6. The three-dimensional array device according to claim 1, wherein said second wiring group is a wiring group made up of bit lines.

7. 7. The three-dimensional array device according to claim 1, wherein said memory cell array circuit includes at least one resistance change type memory and at least one selection transistor for each memory cell.

8. The three-dimensional array device of claim 7 , wherein the resistance change memory has a dielectric layer containing hafnium oxide.

9. The three-dimensional array device according to claim 7 , wherein the select transistor has a channel made of an oxide semiconductor containing IGZO.

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