Power Conversion Device

Abstract

To provide a power conversion device that is capable of suppressing an excess current flowing through a bypass element and protecting the bypass element in the event of an abnormality occurring in a converter cell composed of two half-bridge circuits connected in series.SOLUTION: Each of multiple converter cells included in the power conversion device includes a cell control unit, a first switching circuit and a second switching circuit connected in series, and a bypass element. The first switching circuit includes a first semiconductor device, a second semiconductor device, and a first energy storage element. The second switching circuit includes a third semiconductor device, a fourth semiconductor device, and a second energy storage element. When a short-circuit current flowing through the first semiconductor device or a short-circuit current flowing through the fourth semiconductor device is detected, the cell control unit controls the first semiconductor device and the fourth semiconductor device to an off state.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] In recent years, modular multilevel converters (MMCs) have become known as high-voltage, large-capacity power conversion devices applied to high-voltage systems such as electric power grids. MMCs are composed of arms in which converter cells are cascaded. Each converter cell includes multiple semiconductor switches and capacitors, and outputs either a voltage across the capacitor or zero voltage by turning the semiconductor switches on and off. Power conversion devices are also known that, if an abnormality occurs in a converter cell, short-circuit the converter cell using a bypass element, thereby enabling continued operation.

[0003] For example, the power conversion device disclosed in Japanese Patent Publication No. 5889498 (Patent Document 1) is configured such that, when an abnormality in a converter cell is detected, a semiconductor element selected from among a plurality of semiconductor elements is turned on so as to continuously form a current path that does not include a bypass element for a period until a closed circuit of the bypass element is established. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5889498 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, when an abnormality occurs in a converter cell, a method for preventing damage to the bypass element by suppressing an overcurrent that flows through the bypass element as the bypass element closes is studied. The converter cell in Patent Document 1 is configured as a half-bridge circuit or a full-bridge circuit.

[0006] On the other hand, in a converter cell having a configuration in which two half-bridge circuits are connected in series, the voltage applied to the entire converter cell can be divided by the two half-bridge circuits, thereby reducing the voltage applied to each half-bridge circuit.Even in a converter cell having this configuration, it is necessary to protect the bypass elements from damage by suppressing overcurrent flowing through them. However, Patent Document 1 does not teach or suggest a solution for achieving this protection.

[0007] An object of one aspect of the present disclosure is to provide a power conversion device that can protect a bypass element by suppressing an overcurrent flowing through the bypass element when an abnormality occurs in a converter cell composed of two half-bridge circuits connected in series. [Means for solving the problem]

[0008] According to one embodiment, a power conversion device is provided that includes a plurality of converter cells connected in series. Each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, a first input / output terminal and a second input / output terminal, and a bypass element connected between the first input / output terminal and the second input / output terminal. The first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series body including the first semiconductor element and the second semiconductor element. The first input / output terminal is connected to a connection point between the negative terminal of the first semiconductor element and the positive terminal of the second semiconductor element. The second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to the series body including the third semiconductor element and the fourth semiconductor element. The second input / output terminal is connected to a connection point between the negative terminal of the third semiconductor element and the positive terminal of the fourth semiconductor element. When an abnormality is detected in either the first switching circuit or the second switching circuit, the cell control unit executes control to close the bypass element, and executes control to turn each of the first semiconductor element and the fourth semiconductor element to an off state and control to turn each of the second semiconductor element and the third semiconductor element to an on state during a period before the bypass element is closed in accordance with the control.

[0009] According to another embodiment, there is provided a power conversion device including a plurality of converter cells connected in series. Each of the plurality of converter cells includes a cell control unit, a first switching circuit and a second switching circuit connected in series, a first input / output terminal and a second input / output terminal, and a bypass element connected between the first input / output terminal and the second input / output terminal. The first switching circuit includes a first semiconductor element, a second semiconductor element, and a first energy storage element connected in parallel to a series body including the first semiconductor element and the second semiconductor element. The first input / output terminal is connected to a connection point between the negative terminal of the first semiconductor element and the positive terminal of the second semiconductor element. The second switching circuit includes a third semiconductor element, a fourth semiconductor element, and a second energy storage element connected in parallel to the series body including the third semiconductor element and the fourth semiconductor element. The second input / output terminal is connected to a connection point between the negative terminal of the third semiconductor element and the positive terminal of the fourth semiconductor element. When a short-circuit current flowing through the first semiconductor element or a short-circuit current flowing through the fourth semiconductor element is detected, the cell control unit controls the first semiconductor element and the fourth semiconductor element to an off state. [Effects of the Invention]

[0010] According to the present disclosure, when an abnormality occurs in a converter cell composed of two half-bridge circuits connected in series, it is possible to protect the bypass element by suppressing the overcurrent flowing through the bypass element. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic configuration diagram of a power conversion device. [Figure 2] FIG. 2 is a diagram illustrating a configuration example of a converter cell. [Figure 3] FIG. 10 is a diagram showing an example of a path of a short-circuit current that can occur when a bypass element is closed. [Figure 4] FIG. 10 is a diagram showing another example of a path of a short-circuit current that can occur when the bypass element is closed. [Figure 5] 10 is a diagram illustrating an example of a path of a short-circuit current when on / off control is executed. [Figure 6]FIG. 10 shows a current path for bypassing a converter cell. [Figure 7] FIG. 10 is a diagram illustrating another example of a path of a short-circuit current when on / off control is executed. [Figure 8] 10 is a flowchart showing an example of a processing procedure of a cell control unit according to the first embodiment. [Figure 9] FIG. 10 is a diagram for explaining an example of a method for detecting a short-circuit current. [Figure 10] FIG. 10 is a diagram for explaining another example of a method for detecting a short-circuit current. [Figure 11] FIG. 10 is a diagram for explaining yet another example of a method for detecting a short-circuit current. [Figure 12] 10 is a flowchart showing an example of a processing procedure of a cell control unit according to the second embodiment. [Figure 13] 1A and 1B are diagrams for explaining an example in which a semiconductor element is destroyed on a large scale; [Figure 14] FIG. 10 is a diagram for explaining a control method for a semiconductor device according to a third embodiment. [Figure 15] FIG. 10 is a diagram illustrating a semiconductor element group according to a fourth embodiment. [Figure 16] 13 is a diagram for explaining a control method for a semiconductor element group according to a fourth embodiment. FIG. [Figure 17] FIG. 10 is a diagram showing a modified example of a converter cell. [Figure 18] FIG. 2 is a diagram illustrating an example of the configuration of a cell control unit. [Figure 19] FIG. 10 is a diagram for explaining another example configuration of the cell control unit. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, the present embodiment will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. The names and functions of these components are also the same. Therefore, detailed description thereof will not be repeated.

[0013] Embodiment 1 <Configuration of power conversion device> FIG. 1 is a schematic diagram of a power conversion device. Referring to FIG. 1, the power conversion device 100 includes a power converter 110 including a plurality of converter cells 10 connected in series with each other, and a control device 120 for controlling the power converter 110. A "converter cell" is also called a "sub-module" or a "unit converter." The power converter 110 is configured by a modular multilevel converter. Typically, the power converter 110 performs power conversion between a DC circuit 130 and an AC circuit 150.

[0014] The power converter 110 includes a plurality of leg circuits 40u, 40v, 40w (hereinafter also collectively referred to as "leg circuits 40") connected in parallel with each other between a positive DC terminal (i.e., a high potential side DC terminal) Np and a negative DC terminal (i.e., a low potential side DC terminal) Nn.

[0015] A leg circuit 40 is provided for each of the multiple phases constituting the AC. The leg circuit 40 is connected between the DC circuit 130 and the AC circuit 150 and performs power conversion between the two circuits. FIG. 1 shows a case where the AC circuit 150 is a three-phase AC system, and three leg circuits 40u, 40v, and 40w are provided corresponding to the U phase, V phase, and W phase, respectively. AC terminals Nu, Nv, and Nw provided in the leg circuits 40u, 40v, and 40w, respectively, are connected to the AC circuit 150 via a transformer 140. The AC circuit 150 is, for example, an AC power system including an AC power source or the like.

[0016] The positive DC terminal Np and the negative DC terminal Nn, which are commonly connected to each leg circuit 40, are connected to a DC circuit 130. The DC circuit 130 is, for example, a DC terminal of a DC power system including a DC transmission network or other power conversion device.

[0017] The leg circuit 40u includes a positive arm extending from the positive DC terminal Np to the AC terminal Nu, and a negative arm extending from the negative DC terminal Nn to the AC terminal Nu. The AC terminal Nu, which is the connection point between the positive arm and the negative arm, is connected to the transformer 140. The leg circuits 40v and 40w have a similar configuration.

[0018] The positive arm includes a plurality of cascaded converter cells 10 and a reactor 14P. The plurality of converter cells 10 and the reactor 14P are connected in series to each other. The negative arm includes a plurality of cascaded converter cells 10 and a reactor 14N. The plurality of converter cells 10 and the reactor 14N are connected in series to each other.

[0019] The reactor 14P may be inserted at any position on the positive arm, and the reactor 14N may be inserted at any position on the negative arm. There may be a plurality of reactors 14P and 14N. The reactor 14P and the reactor 14N may be magnetically coupled to form a single reactor. Only the reactor 14P or only the reactor 14N may be provided. Note that instead of providing a reactor, a configuration may be adopted in which a parasitic inductance such as wiring inductance serves as a substitute for the reactor.

[0020] The control device 120 controls the power converter 110 based on detection signals detected by various electric quantity detectors (not shown) (for example, an AC voltage detector, an AC current detector, a DC voltage detector, an arm current detector, etc.). The control device 120 may be configured by a dedicated circuit, or part or all of it may be configured by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a microprocessor, etc.

[0021] <Converter cell configuration> 2 is a diagram showing a configuration example of a converter cell 10. Referring to Fig. 2, converter cell 10 includes a cell control unit 15, a switching circuit 21 and a switching circuit 22 connected in series, a bypass element 25, a high-potential side input / output terminal Po, and a low-potential side input / output terminal No.

[0022] The switching circuits 21 and 22 are configured as half-bridge circuits. Specifically, the switching circuit 21 includes a semiconductor element 31, a semiconductor element 32, and a capacitor EP as an energy storage element.

[0023] The semiconductor element 31 includes a switching element 31s and a diode 31d. The diode 31d is connected in anti-parallel to the switching element 31s (i.e., in parallel and in a reverse bias direction). The semiconductor element 32 includes a switching element 32s and a diode 32d. The diode 32d is connected in anti-parallel to the switching element 32s. The switching element 31s may be configured to include the diode 31d.

[0024] The switching circuit 22 includes a semiconductor element 33, a semiconductor element 34, and a capacitor EN as an energy storage element. The semiconductor element 33 includes a switching element 33s and a diode 33d. The diode 33d is connected in anti-parallel to the switching element 33s. The semiconductor element 34 includes a switching element 34s and a diode 34d. The diode 34d is connected in anti-parallel to the switching element 34s.

[0025] The switching elements 31s, 32s, 33s, and 34s are configured by switching elements such as an IGBT (Insulated Gate Bipolar Transistor), a GCT (Gate Commutated Turn-off Thyristor), or a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

[0026] Capacitor EP is connected in parallel to a series circuit including semiconductor element 31 and semiconductor element 32, and holds a DC voltage. An input / output terminal Po is connected to the connection point between the negative terminal of semiconductor element 31 and the positive terminal of semiconductor element 32. The positive terminal of capacitor EP is connected to the positive terminal of semiconductor element 31, and the negative terminal of capacitor EP is connected to the negative terminal of semiconductor element 32.

[0027] Capacitor EN is connected in parallel to a series circuit including semiconductor element 33 and semiconductor element 34. Input / output terminal No is connected to the connection point between the negative terminal of semiconductor element 33 and the positive terminal of semiconductor element 34. The positive terminal of capacitor EN is connected to the positive terminal of semiconductor element 33, and the negative terminal of capacitor EN is connected to the negative terminal of semiconductor element 34.

[0028] The bypass element 25 is connected between the input / output terminal Po and the input / output terminal No. When the bypass element 25 is closed (i.e., turned on), the converter cell 10 is bypassed. For example, when an element (e.g., semiconductor elements 31 to 34, etc.) of the converter cell 10 fails, the bypass element 25 is used to bypass the converter cell 10. As a result, even if any one of the multiple converter cells 10 fails, the other converter cells 10 can be used to continue operating the power converter 110.

[0029] The cell control unit 15 controls the operation of the switching circuits 21 and 22. During steady-state operation (for example, power conversion operation when no abnormality occurs in the switching circuits 21 and 22), the cell control unit 15 controls the switching elements 31s to 34s to an on or off state, and outputs zero voltage or a positive voltage between the input / output terminals Po and No. The operation of the cell control unit 15 when an abnormality occurs in the switching circuits 21 and 22 will be described later. The cell control unit 15 is configured, for example, by an ASIC, an FPGA, or a combination of these.

[0030] 2, the two switching circuits 21 and 22 are connected in series, which reduces the voltage applied to each of the switching circuits 21 and 22. Therefore, such a configuration of the converter cell 10 is particularly useful when the voltage applied to the converter cell 10 becomes high due to the miniaturization and high density of MMCs.

[0031] <Operation when switching circuit is abnormal> If an abnormality (e.g., a failure of a semiconductor element, an abnormality in the control power supply used in the gate drive unit of the semiconductor element, etc.) is detected in any of the converter cells 10, the bypass element 25 of the converter cell 10 in which the abnormality is detected is closed, and the converter cell 10 is bypassed.

[0032] If the number of converter cells 10 is designed to be redundant so that an operation equivalent to a steady-state operation can be performed, even if one of the converter cells 10 becomes abnormal, the power converter 110 can continue to perform power conversion operation by bypassing the abnormal converter cell 10. However, the following problems can occur.

[0033] 3 is a diagram showing an example of a path of a short-circuit current that can occur when the bypass element is closed. Referring to FIG. 3, assume that semiconductor element 31, which constitutes the upper arm of switching circuit 21, is short-circuited. In this case, an abnormality (i.e., a short-circuit fault) in semiconductor element 31 is detected and bypass element 25 is closed. However, this causes the energy charge stored in capacitor EP to be discharged, and a short-circuit current (i.e., an overcurrent) flows through path R1 of capacitor EP, semiconductor element 31, bypass element 25, and semiconductor element 33.

[0034] 4 is a diagram showing another example of a path of a short-circuit current that can occur when the bypass element is closed. Referring to FIG. 4, assume that the semiconductor element 34 that constitutes the lower arm of the switching circuit 22 is short-circuited. In this case, an abnormality (i.e., a short-circuit fault) in the semiconductor element 34 is detected, and the bypass element 25 is closed. However, this causes the energy charge stored in the capacitor EN to be discharged, and a short-circuit current flows through the path R2 of the capacitor EN, the semiconductor element 32, the bypass element 25, and the semiconductor element 34.

[0035] The bypass element 25 is designed based on the value of the current that flows through the converter cell 10 during normal power conversion operation, and the current value is usually several kA or less. On the other hand, the short-circuit current shown in Figures 3 and 4 is several tens to several hundreds of kA, and therefore the bypass element 25 may be damaged by this short-circuit current. If the bypass element 25 is damaged, the power conversion device 100 cannot continue the power conversion operation.

[0036] Therefore, when cell control unit 15 according to this embodiment detects an abnormality in either switching circuit 21 or switching circuit 22, it executes control to close bypass element 25 (hereinafter also referred to as "closing control"), executes control to turn off each of semiconductor element 31 (specifically, switching element 31s) and semiconductor element 34 (specifically, switching element 34s), and executes control to turn on each of semiconductor element 32 (specifically, switching element 32s) and semiconductor element 33 (specifically, switching element 33s). The reason for executing the above-mentioned on / off control will be explained below.

[0037] (When an abnormality occurs in the semiconductor element 31) Assume that the cell control unit 15 detects an abnormality related to a short-circuit fault in the semiconductor element 31 (hereinafter also referred to as a "short-circuit related abnormality"). One example of a short-circuit related abnormality is an abnormality in the control power supply. The control power supply is a power supply supplied to a gate driver for turning the semiconductor element on and off, a power supply supplied to a control board that determines the on / off logic, etc. Typically, the gate driver and the control board are included in the cell control unit 15. The cell control unit 15 detects the voltage of the control power supply and determines whether the voltage is within the normal operating range. If the voltage is outside the normal operating range, the cell control unit 15 detects a short-circuit related abnormality in the semiconductor element 31. The same applies to the abnormality detection method for the other semiconductor elements 32 to 34.

[0038] In this case, the cell control unit 15 executes a closing control of the bypass element 25, and executes the above-described on / off control in the period before the closed circuit of the bypass element 25 is established in response to the closing control (i.e., before the bypass element 25 is completely closed). Specifically, the cell control unit 15 outputs a control signal (hereinafter also referred to as an "off signal") to the semiconductor elements 31 and 34 to turn them off, and outputs a control signal (hereinafter also referred to as an "on signal") to the semiconductor elements 32 and 33 to turn them on. As a result, the semiconductor elements 32 and 33 are turned on, and the semiconductor element 34 is turned off. However, since the semiconductor element 31 is in a short-circuit state, it does not turn off. As a result, a short-circuit current path is formed as shown in FIG. 5.

[0039] 5 shows an example of a path of a short-circuit current when on / off control is being executed. Referring to FIG. 5, before bypass element 25 is closed, semiconductor element 32 is turned on, which places semiconductor elements 31 and 32 in a conductive state, causing a short-circuit current to flow through path R3 of capacitor EP, semiconductor element 31, and semiconductor element 32. This consumes the energy stored in capacitor EP (i.e., the charge is discharged), so that by the time bypass element 25 is actually closed, the energy stored in capacitor EP has been sufficiently consumed. Therefore, the short-circuit current flowing through path R1 in FIG. 3 after bypass element 25 is closed is suppressed, and damage to bypass element 25 can be prevented.

[0040] Here, we will explain the output timing of the close signal to the bypass element 25 and the on / off signals to the semiconductor elements 31 to 34. Since the bypass element 25 is usually configured with a mechanical switch, the time from when the close signal is given to the bypass element 25 until the bypass element 25 is actually closed is about several ms. On the other hand, the time from when the on / off signal is given to the semiconductor element until the semiconductor element is actually turned on or off is about several μs.

[0041] Therefore, even if the cell control unit 15 simultaneously outputs a close signal to the bypass element 25 and an on / off signal to the semiconductor elements 31 to 34, the on / off states of the semiconductor elements 31 to 34 are established before the bypass element 25 is closed, and the current path R3 shown in Figure 5 is formed. Note that, when using a bypass element 25 other than the above-mentioned mechanical switch, it is also possible to use one that closes in a value of several tens of microseconds or more after the close signal is applied. Note that the output timing of the on / off signal to the semiconductor elements 31 to 34 may be before the output timing of the close signal to the bypass element 25.

[0042] Here, the reason why semiconductor element 34 is turned off when a short-circuit-related abnormality occurs in semiconductor element 31 will be explained. As described above, when semiconductor elements 31 and 32 are conductive, the charge in capacitor EP is discharged through path R3, and when bypass element 25 is closed, current flows through path R1. If semiconductor element 34 were to be turned on in this state, current would flow through path R2 in FIG. 4. In this case, charge would be discharged from capacitor EN, which has sufficient stored energy, so the current flowing through path R2 would become an overcurrent, which could damage bypass element 25. Therefore, semiconductor element 34 is turned off to prevent discharge from capacitor EN.

[0043] Furthermore, it is necessary to form a current path for bypassing the converter cell 10 during the period from when the semiconductor device 31 has short-circuited to when the bypass element 25 is actually closed.

[0044] Fig. 6 is a diagram showing a current path for bypassing the converter cell 10. Referring to Fig. 6, by controlling the semiconductor elements 32 and 33 to be in the on state, a current can be made to flow through path R4. This bypasses the converter cell 10. Therefore, the semiconductor element 33 needs to be in the on state.

[0045] As described above, when a short-circuit related abnormality occurs in semiconductor element 31, semiconductor element 32 is turned on to cause current to flow through path R3 (see Figure 5) to consume the energy of capacitor EP, semiconductor element 34 is turned off to prevent overcurrent from capacitor EN from flowing to bypass element 25 through path R2 (see Figure 4), and semiconductor element 33 is turned on to cause current to flow through path R4 (see Figure 6) to bypass converter cell 10.

[0046] (When an abnormality occurs in the semiconductor element 34) Assume that the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 34. In this case, the cell control unit 15 also outputs a close signal to the bypass element 25, outputs an OFF signal to the semiconductor elements 31 and 34, and outputs an ON signal to the semiconductor elements 32 and 33. However, since the semiconductor element 34 is in a short-circuit state, it does not enter an OFF state. As a result, a short-circuit current path is formed as shown in FIG. 7.

[0047] 7 is a diagram showing another example of a path of a short-circuit current when on / off control is being executed. Referring to FIG. 7, before bypass element 25 is closed, semiconductor element 33 is turned on, which places semiconductor elements 33 and 34 in a conductive state, causing a short-circuit current to flow through path R5 of capacitor EN, semiconductor element 33, and semiconductor element 34. This consumes the energy stored in capacitor EN, and by the time bypass element 25 is actually closed, the energy stored in capacitor EN has been sufficiently consumed. Therefore, the short-circuit current flowing through path R2 in FIG. 4 after bypass element 25 is closed is suppressed, preventing damage to bypass element 25.

[0048] The reason why semiconductor element 31 is turned off when an abnormality related to a short circuit in semiconductor element 34 occurs will be explained below. Specifically, when semiconductor elements 33 and 34 are conductive, the charge in capacitor EN is discharged via path R5 in FIG. 7, and when bypass element 25 is closed, current flows via path R2 in FIG. 4. If semiconductor element 31 were to be turned on in this state, an overcurrent would flow via path R1 in FIG. 3, which could damage bypass element 25. Therefore, semiconductor element 31 is turned off to prevent discharge from capacitor EP.

[0049] In addition, from the time when semiconductor element 34 short-circuits until bypass element 25 is actually closed, semiconductor element 32 is controlled to be in the on state to form a current path (i.e., path R4 in Figure 6) for bypassing converter cell 10.

[0050] As described above, when a short-circuit related abnormality occurs in semiconductor element 34, semiconductor element 33 is turned on to cause current to flow through path R5 (see Figure 7) to consume the energy of capacitor EN, semiconductor element 31 is turned off to prevent overcurrent from capacitor EP from flowing to bypass element 25 through path R1 (see Figure 3), and semiconductor element 32 is turned on to cause current to flow through path R4 (see Figure 6) to bypass converter cell 10.

[0051] (When an abnormality occurs in semiconductor elements 32 and 33) Assume that the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 32 or the semiconductor element 33. In this case, the cell control unit 15 also outputs a close signal to the bypass element 25, outputs an OFF signal to the semiconductor elements 31 and 34, and outputs an ON signal to the semiconductor elements 32 and 33.

[0052] If a short-circuit-related abnormality is detected in semiconductor element 32 or semiconductor element 33, and if semiconductor element 31 is turned on while bypass element 25 is closed, an overcurrent will flow through path R1 in FIG. 3. Therefore, semiconductor element 31 is controlled to the off state. This prevents discharge from capacitor EP. If semiconductor element 34 is turned on while bypass element 25 is closed, an overcurrent will flow through path R2 in FIG. 4. Therefore, semiconductor element 34 is controlled to the off state. This prevents discharge from capacitor EN.

[0053] When a short-circuit related abnormality occurs in the semiconductor element 32, the semiconductor element 33 is controlled to be in the ON state, and when a short-circuit related abnormality occurs in the semiconductor element 33, the semiconductor element 32 is controlled to be in the ON state. As a result, the converter cell 10 is bypassed.

[0054] (summary) As described above, when an abnormality occurs in either switching circuit 21 or switching circuit 22 (i.e., any of semiconductor elements 31 to 34), semiconductor elements 31 and 34 are controlled to the off state and semiconductor elements 32 and 33 are controlled to the on state during the period before bypass element 25 is closed. This suppresses overcurrent to bypass element 25 and prevents damage to bypass element 25.

[0055] <Flowchart> 8 is a flowchart showing an example of a processing procedure of cell control unit 15 according to the first embodiment. Referring to Fig. 8, cell control unit 15 determines whether or not an abnormality has been detected in either switching circuit 21 or 22 (step S10). If the abnormality has not been detected (NO in step S10), cell control unit 15 repeats step S10.

[0056] If the abnormality is detected (YES in step S10), the cell control unit 15 outputs a close signal to the bypass element 25 (step S12), outputs an off signal to the semiconductor elements 31 and 34 (step S14), and outputs an on signal to the semiconductor elements 32 and 33 (step S16). Note that the processing of steps S12, S14, and S16 may be performed in any order or simultaneously. However, it is assumed that the close circuit of the bypass element 25 is established after the on / off states of the semiconductor elements 31 to 34 are established.

[0057] <Advantages> According to the first embodiment, even if a short-circuit-related abnormality occurs in any of the semiconductor elements 31 to 34, the bypass element 25 can be appropriately protected by suppressing the overcurrent flowing through the bypass element 25. Therefore, even if an abnormality occurs in any of the converter cells 10, the operation of the power conversion device 100 can be continued. Furthermore, a small, lightweight, and inexpensive bypass element can be adopted.

[0058] Embodiment 2 In the above-described first embodiment, a configuration has been described that prevents damage to the bypass element 25 when a short-circuit-related abnormality occurs in the semiconductor elements 31 to 34. In the second embodiment, a configuration will be described that prevents damage to the bypass element 25 when the semiconductor elements 31 to 34 are in a normal state but the bypass element 25 is erroneously closed.

[0059] 3, if bypass element 25 malfunctions (i.e., closes) due to noise or other factors while semiconductor element 31 is controlled to the on state, capacitor EP is short-circuited and a short-circuit current flows through path R1. If semiconductor element 31 does not fail, this short-circuit current is limited to a saturation current value (e.g., several kA). However, the semiconductor element will fail within several μs to several tens of μs and enter a completely short-circuited state. In this case, the current flowing through bypass element 25 will instantaneously rise to several tens of kA to several hundreds of kA.

[0060] To prevent this, the cell control unit 15 has an arm short-circuit protection function for protecting the semiconductor element 31. The arm short-circuit protection function is a function for protecting the semiconductor element 31 from a short-circuit current that flows when the capacitor EP is short-circuited via the semiconductor element 31.

[0061] The cell control unit 15 directly or indirectly detects that a short-circuit current has flowed through the semiconductor element 31, and cuts off (for example, turns off) the semiconductor element 31. The cell control unit 15 achieves this cutoff within several μs to several tens of μs before the semiconductor element 31 fails, thereby eliminating the short-circuit current.

[0062] Semiconductor elements generally have tolerance characteristics (i.e., characteristics that do not break) for short-circuit currents within 2 μs to 10 μs. Therefore, the semiconductor element 31 can be protected by shutting it off within 2 μs to 10 μs after a short-circuit current occurs. This prevents the semiconductor element 31 from breaking down, and prevents a current of tens to hundreds of kA from flowing through the bypass element 25. Therefore, damage to the bypass element 25 can be prevented.

[0063] The cell control unit 15 may shut off the semiconductor element 31 using a "soft shutdown" operation, which shuts down the semiconductor element 31 using a slower switching operation than the switching operation used in normal control. This is done to suppress the surge voltage that occurs across the semiconductor element when it is shut off, because the saturation current of the semiconductor element is larger than the current that is normally controlled.

[0064] Next, a configuration for preventing damage to the bypass element 25 when the bypass element 25 malfunctions (i.e., closes) while the semiconductor element 34 is in the on state will be described. Referring to Fig. 4, if the bypass element 25 malfunctions while the semiconductor element 34 is controlled to be in the on state, the capacitor EN is short-circuited and a short-circuit current flows through the path R2. As described above, the semiconductor element 34 becomes completely short-circuited in several microseconds to several tens of microseconds.

[0065] Therefore, the cell control unit 15 has an arm short-circuit protection function that protects the semiconductor element 34 from a short-circuit current that flows when the capacitor EN is short-circuited via the semiconductor element 34. The cell control unit 15 detects that a short-circuit current has flowed through the semiconductor element 34, and then cuts off the semiconductor element 34 to remove the short-circuit current before the semiconductor element 34 fails. The cell control unit 15 may also output an ON signal to the semiconductor elements 32 and 33.

[0066] 9 is a diagram illustrating an example of a method for detecting a short-circuit current. Referring to FIG. 9, current sensors 51 to 55 are provided in converter cell 10. Current sensor 51 is provided between capacitor EP and semiconductor element 31, current sensor 52 is provided between the connection point of semiconductor elements 31, 32 and bypass element 25, and current sensor 53 is provided between the connection point of semiconductor elements 33, 34 and bypass element 25. Current sensor 54 is provided between capacitor EN and semiconductor element 34, and current sensor 55 is provided between the connection point of capacitor EP and capacitor EN and the connection point of semiconductor elements 32, 33.

[0067] When cell control unit 15 detects a short-circuit current based on a detection signal from at least one of current sensors 51-55 (i.e., when it detects a short-circuit current flowing through semiconductor element 31 or a short-circuit current flowing through semiconductor element 34), it shuts off (i.e., controls to an OFF state) semiconductor element 31 and semiconductor element 34. Note that it is sufficient that at least one of current sensors 51-55 is provided.

[0068] 10 is a diagram for explaining another example of a short-circuit current detection method. Referring to Fig. 10, cell control unit 15 has, for a target semiconductor element 61 (e.g., semiconductor element 31), a gate drive circuit 60, a detection unit 62 that detects a short-circuit current, and a cutoff unit 63 that performs a cutoff operation when a short-circuit current is detected.

[0069] When an ON signal is input to the semiconductor element 31, the detection unit 62 determines whether the collector potential is equal to or higher than a specified potential. When a short-circuit current is flowing, the voltage of the capacitor EP is applied to both ends of the semiconductor element 31, causing the ON-state voltage to rise. On the other hand, when no short-circuit current is flowing, the voltage drop across the semiconductor element 31 is several volts. The detection unit 62 determines whether a short-circuit current is flowing by comparing the detected collector potential using a comparator.

[0070] The cutoff unit 63 receives a signal from the detection unit 62 and performs a cutoff operation on the semiconductor element 31. The cutoff unit 63 may employ a "soft cutoff" that cuts off via a resistance greater than that used during normal operation.

[0071] 11 is a diagram for explaining yet another example of a method for detecting a short-circuit current. Referring to FIG. 11, the cell control unit 15 detects a short-circuit current by utilizing parasitic inductances 71 and 72 of the wiring of the converter cell 10.

[0072] Assume that a short-circuit current occurs along path R1 (see FIG. 3) in semiconductor element 31. In this case, a self-induced electromotive force occurs along path R1 based on the change in the short-circuit current over time, causing a voltage to be generated in parasitic inductance 71 on the emitter side of semiconductor element 31. Therefore, cell control unit 15 detects the short-circuit current flowing through semiconductor element 31 based on the voltage of parasitic inductance 71. For example, cell control unit 15 determines that a short-circuit current has occurred when the voltage of parasitic inductance 71 is equal to or greater than a threshold value.

[0073] When detecting a short-circuit current flowing through bypass element 25 using the detection method using the collector potential described in Fig. 10, the rise of the collector potential is slow, so it may be difficult to detect the short-circuit current itself, or it may take a long time to detect it. In this respect, the detection method in Fig. 11 is more useful than the detection method in Fig. 10.

[0074] Furthermore, the cell control unit 15 detects the short-circuit current of path R2 (see FIG. 4) by monitoring the voltage of parasitic inductance 72 on the emitter side of semiconductor element 34. Note that the short-circuit path passing through semiconductor element 33 (i.e., path R1) includes semiconductor element 31, and the short-circuit path passing through semiconductor element 32 (i.e., path R2) includes semiconductor element 34. Therefore, the cell control unit 15 only needs to monitor the voltages of parasitic inductances 71 and 72 on the emitter sides of semiconductor elements 31 and 34.

[0075] 12 is a flowchart showing an example of a processing procedure of cell control unit 15 according to the second embodiment. Referring to Fig. 12, cell control unit 15 determines whether or not a short-circuit current flowing through semiconductor element 31 or semiconductor element 34 has been detected (step S50). If a short-circuit current has not been detected (NO in step S50), cell control unit 15 repeats step S50.

[0076] If a short-circuit current is detected (YES in step S50), an OFF signal is output to semiconductor element 31 (step S52), and an OFF signal is output to semiconductor element 34 (step S54). This removes the short-circuit current. Note that the processing of steps S52 and S54 may be performed in any order or simultaneously. Furthermore, cell control unit 15 may output ON signals to semiconductor elements 32 and 33.

[0077] According to the second embodiment, even if the bypass element 25 is erroneously closed, the bypass element 25 can be appropriately protected.

[0078] Embodiment 3 In the above-described first embodiment, a configuration has been described in which semiconductor element 32 is turned on to consume the energy stored in capacitor EP when a short-circuit related abnormality occurs in semiconductor element 31. However, in this case, an overcurrent flows in a state in which a high voltage is applied to semiconductor elements 31 and 32, and therefore, if energy exceeding the short-circuit withstand capacity of semiconductor elements 31 and 32 is applied, the scale of destruction of semiconductor elements 31 and 32 may become large (for example, destruction accompanied by an explosion).

[0079] To prevent the deformation of converter cells due to the above-mentioned events, semiconductor elements or converter cells are designed with explosion-proofing in mind. However, there is variation in the short-circuit resistance of semiconductor elements, and it is difficult to accurately grasp the state of an explosion. Therefore, even with an explosion-proof design, unexpected converter cell failure may occur. Furthermore, if this damages the bypass element or the bypass element's control board, it may become difficult for the bypass element to bypass the converter cell, and the entire power converter may be forced to shut down.

[0080] Therefore, in the third embodiment, a configuration will be described in which, when a short-circuit related abnormality occurs in semiconductor element 31, large-scale destruction of semiconductor elements 31 and 32 is avoided while capacitor EP is discharged and bypass element 25 is closed.

[0081] 13 is a diagram illustrating an example in which a semiconductor element is destroyed on a large scale. Referring to FIG. 13, when a short-circuit-related abnormality occurs in semiconductor element 31, the resistance value between the collector and emitter of semiconductor element 31 decreases. Subsequently, when cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 31, it outputs an ON signal to semiconductor element 32. When semiconductor element 32 enters the ON state, the resistance value between the collector and emitter of semiconductor element 32 decreases. Accordingly, energy in capacitor EP begins to be consumed, and the energy applied to semiconductor elements 31 and 32 increases.

[0082] Then, several microseconds to several tens of microseconds after semiconductor element 32 is turned on, the energy applied to semiconductor elements 31 and 32 exceeds the short-circuit resistance, causing semiconductor elements 31 and 32 to be destroyed. This occurs because the applied energy causes a rapid rise in temperature of semiconductor elements 31 and 32. The example in FIG. 13 shows how all of the energy from capacitor EP is consumed by semiconductor elements 31 and 32. Because all of the energy from capacitor EP is applied to semiconductor elements 31 and 32 in a time period of several microseconds to several tens of microseconds, the scale of destruction of semiconductor elements 31 and 32 is large. Below, we will explain a control method for semiconductor element 32 that prevents such large-scale destruction of semiconductor elements 31 and 32.

[0083] FIG. 14 is a diagram illustrating a control method for semiconductor elements according to the third embodiment. Referring to FIG. 14, when a short-circuit-related abnormality occurs in semiconductor element 31, the resistance value between the collector and emitter of semiconductor element 31 decreases. When cell control unit 15 detects a short-circuit-related abnormality in semiconductor element 31, it starts control to intermittently turn semiconductor element 32 on and off. That is, when a short-circuit-related abnormality in semiconductor element 31 is detected, cell control unit 15 alternately switches semiconductor element 32 between the on state and the off state during the period before bypass element 25 is closed. Note that semiconductor elements 33 and 34 are controlled in the same manner as in the first embodiment. Specifically, cell control unit 15 maintains semiconductor element 33 in the on state and semiconductor element 34 in the off state.

[0084] With the above control, the energy applied to semiconductor elements 31 and 32 is high when semiconductor element 32 is in the on state, but is low when semiconductor element 32 is in the off state. Therefore, the energy of capacitor EP is gradually consumed, which makes it possible to suppress a sudden rise in temperature of semiconductor elements 31 and 32. As a result, it is possible to prevent damage to semiconductor elements 31 and 32. Alternatively, since semiconductor elements 31 and 32 reach damage with the energy of capacitor EP sufficiently reduced, the scale of damage to semiconductor elements 31 and 32 can be reduced.

[0085] For example, even if the semiconductor element 32 is turned on for several μs before the bypass element 25 is closed (for example, several ms after the output of the on signal), and then an off period of several tens to several hundreds of μs is provided to wait for the temperature to drop, the semiconductor element 32 can be turned on and off several times.

[0086] The above describes a configuration in which semiconductor element 32 is alternately switched between the on state and the off state when a short-circuit related abnormality occurs in semiconductor element 31, but a similar phenomenon can occur when a short-circuit related abnormality occurs in semiconductor element 34. That is, when a short-circuit related abnormality occurs in semiconductor element 34, if semiconductor element 33 is turned on, the energy of capacitor EN may increase the scale of damage to semiconductor elements 33 and 34.

[0087] Therefore, when the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 34, it controls the semiconductor element 33 to be intermittently turned on and off. That is, when a short-circuit-related abnormality in the semiconductor element 34 is detected, the cell control unit 15 alternately switches the semiconductor element 33 between the on state and the off state during the period before the bypass element 25 is closed. Note that the same control as in the first embodiment is performed on the semiconductor elements 31 and 32. Specifically, the cell control unit 15 maintains the semiconductor element 31 in the off state and the semiconductor element 32 in the on state. This can prevent the semiconductor elements 33 and 34 from being destroyed by the energy of the capacitor EN, or can reduce the scale of such destruction.

[0088] Other methods may be employed to gradually consume the energy of capacitors EP and EN. Specifically, when the cell control unit 15 controls the semiconductor element 32 to be on when a short-circuit-related abnormality occurs in semiconductor element 31, the cell control unit 15 reduces the gate voltage of the semiconductor element 32 when it is on compared to the gate voltage during normal switching. This limits the current flowing from capacitor EP to semiconductor element 32, thereby suppressing a rapid temperature rise in the semiconductor elements 31 and 32. As a result, damage to the semiconductor elements 31 and 32 can be prevented or the extent of damage to the semiconductor elements 31 and 32 can be reduced. Similarly, when the cell control unit 15 controls the semiconductor element 33 to be on when a short-circuit-related abnormality occurs in semiconductor element 34, the cell control unit 15 may reduce the gate voltage of the semiconductor element 33 when it is on compared to the gate voltage during normal switching.

[0089] According to the third embodiment, it is possible to prevent the semiconductor elements from being destroyed by the energy of the capacitors EP and EN, or to reduce the scale of the destruction.

[0090] Embodiment 4 The third embodiment described above describes a configuration that prevents damage to semiconductor elements 31 and 32 (or reduces the scale of damage) by alternately switching the on and off states of one semiconductor element 32. The fourth embodiment describes a configuration that prevents damage to semiconductor elements 31 and 32 by connecting one or more semiconductor elements in parallel to semiconductor element 32 and controlling these semiconductor elements to be sequentially turned on.

[0091] 15 is a diagram illustrating a semiconductor element group according to the fourth embodiment. Referring to FIG. 15, semiconductor element group 320 includes semiconductor elements 32, 32A, 32B, and 32C, a high-potential side terminal Xp, and a low-potential side terminal Xn. Terminal Xp is connected to the negative terminal of semiconductor element 31. Terminal Xn is connected to the positive terminal of semiconductor element 33. Semiconductor elements 32, 32A, 32B, and 32C are connected in parallel with each other.

[0092] 16 is a diagram illustrating a control method for a semiconductor element group according to the fourth embodiment. Referring to FIG. 16, when a short-circuit related abnormality occurs in semiconductor element 31, the resistance value between the collector and the emitter of semiconductor element 31 decreases. When cell control unit 15 detects a short-circuit related abnormality in semiconductor element 31, it starts control to alternately turn on semiconductor elements 32 to 32C included in semiconductor element group 320.

[0093] Specifically, the cell control unit 15 turns on the semiconductor element 32, and then turns it off a certain time later. Next, the cell control unit 15 turns on the semiconductor element 32A, and then turns it off a certain time later. Thereafter, the cell control unit 15 performs similar control on the semiconductor elements 32B and 32C. That is, when a short-circuit-related abnormality is detected in the semiconductor element 31, the cell control unit 15 controls the on and off states of each of the multiple semiconductor elements 32 to 32C during the period before the bypass element 25 is closed, so that the on time of each of the multiple semiconductor elements 32 to 32C does not overlap with the on time of the other semiconductor elements.

[0094] By such control, the energy applied to the semiconductor elements 31, 32 to 32C is dispersed, so that it is possible to prevent the semiconductor elements 31, 32 to 32C from being damaged by the energy of the capacitor EP, or to reduce the scale of such damage.

[0095] The cell control unit 15 may control the on / off of the semiconductor elements 32 to 32C using a gate driver that drives a plurality of semiconductor elements collectively, or may control the on / off of the semiconductor elements 32 to 32C using individual gate drivers.

[0096] Furthermore, another semiconductor element (also referred to as "semiconductor element G" for convenience) may be connected in parallel to the semiconductor element 33, and these semiconductor elements may be controlled to be turned on sequentially to prevent damage to the semiconductor elements 33 and 34. Specifically, when the cell control unit 15 detects a short-circuit-related abnormality in the semiconductor element 34, it starts control to alternately turn on the semiconductor element 33 and the semiconductor element G. That is, when a short-circuit-related abnormality in the semiconductor element 34 is detected, the cell control unit 15 controls the on and off states of the semiconductor element 33 and the semiconductor element G so that the on time of the semiconductor element 33 does not overlap with the on time of the semiconductor element G during the period before the bypass element 25 is closed. Note that, as in the example of FIG. 15, a configuration in which multiple semiconductor elements G are provided may also be used.

[0097] According to the fourth embodiment, it is possible to prevent the semiconductor elements from being destroyed by the energy of the capacitors EP and EN, or to reduce the scale of the destruction.

[0098] Other embodiments. (1) In the above-described first embodiment, if the semiconductor elements 31 and 32 both experience an open circuit failure due to the energy of the capacitor EP being consumed in the semiconductor elements 31 and 32 before the bypass element 25 is closed, the converter cell 10 is in an open state and has a high impedance until the bypass element 25 is closed. The same applies to the case where the semiconductor elements 33 and 34 both experience an open circuit failure due to the energy of the capacitor EN being consumed in the semiconductor elements 33 and 34 before the bypass element 25 is closed.

[0099] In this case, a voltage higher than expected is applied to the input / output terminals Po and No of the converter cell 10, which may cause an arc discharge or the like, resulting in a malfunction of peripheral devices of the converter cell 10. Therefore, a resistor as shown in FIG. 17 may be provided in the converter cell 10.

[0100] Fig. 17 is a diagram showing a modified example of the converter cell 10. Referring to Fig. 17, the converter cell 10 according to the modified example has a configuration in which a resistor 27 is added to the converter cell 10 of Fig. 2. The resistor 27 is connected in parallel to the bypass element 25. The resistor 27 has a high resistance such that the converter cell 10 does not enter an open state.

[0101] (2) Fig. 18 is a diagram illustrating an example configuration of cell control unit 15. Referring to Fig. 18, cell control unit 15 includes a control circuit 81 for controlling switching circuit 21 and a control circuit 82 for controlling switching circuit 22.

[0102] Specifically, the control circuit 81 performs on / off control of the semiconductor elements 31 and 32. The control circuit 82 performs on / off control of the semiconductor elements 33 and 34. In addition, the control circuit 81 detects short-circuit-related abnormalities in the semiconductor elements 31 and 32, and the control circuit 82 detects short-circuit-related abnormalities in the semiconductor elements 33 and 34.

[0103] For example, when control circuit 81 detects a short-circuit related abnormality in semiconductor element 31, it outputs an OFF signal to semiconductor element 31 and outputs an ON signal to semiconductor element 32. Control circuit 81 also transmits an abnormality signal indicating the short-circuit related abnormality to control circuit 82. When control circuit 82 receives the abnormality signal, it outputs an ON signal to semiconductor element 33 and outputs an OFF signal to semiconductor element 34.

[0104] For example, when control circuit 82 detects a short-circuit related abnormality in semiconductor element 34, it outputs an OFF signal to semiconductor element 34 and outputs an ON signal to semiconductor element 33. Control circuit 82 also transmits an abnormality signal indicating the short-circuit related abnormality to control circuit 81. When control circuit 81 receives the abnormality signal, it outputs an OFF signal to semiconductor element 31 and outputs an ON signal to semiconductor element 32.

[0105] Control circuit 81 includes a drive circuit for driving semiconductor element 31 and a drive circuit for driving semiconductor element 32. Control circuit 82 includes a drive circuit for driving semiconductor element 33 and a drive circuit for driving semiconductor element 34. These drive circuits must be electrically insulated from each other to prevent dielectric breakdown. For example, even if each drive circuit is mounted on the same universal board or the like, the patterns connected to each of semiconductor elements 31 to 34 must be insulated. To prevent electrical dielectric breakdown, each drive circuit may be mounted on an independent circuit board.

[0106] (3) Fig. 19 is a diagram illustrating another example of the configuration of the cell control unit 15. Referring to Fig. 19, the cell control unit 15 includes control circuits 91 to 94 for controlling the semiconductor elements 31 to 34, respectively. The control circuits 91 to 94 include drive circuits for driving the semiconductor elements 31 to 34, respectively. Note that the cell control unit 15 may be configured such that one control circuit controls the semiconductor elements 31 to 34. In this case, the control circuit includes four drive circuits for driving the four semiconductor elements 31 to 34.

[0107] (4) The configurations exemplified as the above-described embodiments are examples of the configurations of the present disclosure, and may be combined with other known technologies, or may be modified, such as by omitting some parts, within the scope of the gist of the present disclosure. Furthermore, the above-described embodiments may be implemented by appropriately adopting the processes and configurations described in other embodiments.

[0108] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0109] 10 converter cell, 14N, 14P reactor, 15 cell control unit, 21, 22 switching circuit, 25 bypass element, 27 resistor, 31-34 semiconductor element, 31d-34d diode, 31s-34s switching element, 40u-40w leg circuit, 51-55 current sensor, 60 gate drive circuit, 62 detection unit, 63 interruption unit, 71, 72 parasitic inductance, 81, 82, 91, 94 control circuit, 100 power conversion device, 110 power converter, 120 control device, 130 DC circuit, 140 transformer, 150 AC circuit, 320 semiconductor element group.

Claims

1. A power conversion device comprising a plurality of converter cells connected in series, Each of the plurality of converter cells comprises: A cell control unit; a first switching circuit and a second switching circuit connected in series; a first input / output terminal and a second input / output terminal; a bypass element connected between the first input / output terminal and the second input / output terminal; the first switching circuit includes a first semiconductor device, a second semiconductor device, and a first energy storage element connected in parallel to a series circuit including the first semiconductor device and the second semiconductor device; the first input / output terminal is connected to a connection point between a negative terminal of the first semiconductor element and a positive terminal of the second semiconductor element; the second switching circuit includes a third semiconductor device, a fourth semiconductor device, and a second energy storage element connected in parallel to a series circuit including the third semiconductor device and the fourth semiconductor device; the second input / output terminal is connected to a connection point between a negative terminal of the third semiconductor element and a positive terminal of the fourth semiconductor element; When a short-circuit current flowing through the first semiconductor element or a short-circuit current flowing through the fourth semiconductor element is detected, the cell control unit controls the first semiconductor element and the fourth semiconductor element to an off state.

2. The power conversion device according to claim 1 , wherein the cell control unit detects the short-circuit current flowing through the first semiconductor element based on a voltage of a parasitic inductance on an emitter side of the first semiconductor element.

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