Sensor Interface Circuit

Abstract

To convert a signal level of a sensor into a frequency change to improve the conversion accuracy thereof.SOLUTION: A frequency synchronization circuit of a sensor-interface circuit comprises: a voltage source for generating a voltage; a first frequency impedance converter circuit for converting a reference frequency into a first impedance; a current source for generating a current using the voltage and the first impedance that are generated; a voltage difference detection circuit having a first input node connected to the voltage source and a second input node and an output node connected to the current source, in which at least one of a voltage received at the first input node and a second voltage received at the second input node corresponds to a signal level of the sensor, and generating a control voltage according to a difference between the voltage received at the first input node and the voltage received at the second input node; a voltage control oscillation circuit for generating an oscillation signal according to the control voltage; and a second frequency impedance converter circuit for converting a frequency of a signal according to the oscillation signal into a second impedance.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION The embodiments herein relate to a sensor interface circuit. [Background technology]

[0002] A sensor interface circuit having an oscillator circuit oscillates the oscillator circuit in response to the signal level of the sensor, generating and outputting an oscillation signal having a frequency corresponding to the signal level of the sensor. The sensor interface circuit is required to convert the signal level of the sensor into a frequency with high accuracy. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Kaede Miyauchi, Taichi Taguchi, Yosuke Ishikawa, Hiroyuki Ito, Shiro Michimasa, Kazuya Masu, Noboru Ishihara, "Prototype Evaluation Results of Low-Power Wireless Sensor Terminal Module Using RF Backscattering," 2018 Institute of Electronics, Information and Communication Engineers General Conference, Japan, March 20-23, 2018, B-18-17, p.361 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, a sensor interface circuit may be configured such that the frequency of an oscillation signal corresponding to a sensor signal level varies depending on the characteristics of the sensor and the characteristics of elements within the sensor interface circuit. In this case, the accuracy of the oscillation signal frequency depends on the absolute accuracy of the sensor characteristics and the absolute accuracy of the element characteristics, and is therefore susceptible to variations due to factors such as the manufacturing process, power supply voltage, and / or temperature. This can easily reduce the accuracy of conversion of the sensor signal level to frequency.

[0005] An object of the present invention is to provide a sensor interface circuit that can convert the signal level of a sensor into a frequency change and improve the conversion accuracy. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, one aspect of the present invention provides a sensor interface circuit that includes a frequency synchronization circuit connectable to a sensor, the frequency synchronization circuit including: a voltage source that generates a voltage; a first frequency-impedance conversion circuit that converts a reference frequency into a first impedance; a current source connected to the voltage source and the first impedance conversion circuit and that generates a current using the generated voltage and the first impedance; a voltage difference detection circuit having a first input node connected to the voltage source and a second input node and an output node connected to the current source, wherein at least one of the voltage received at the first input node and the second voltage received at the second input node corresponds to a signal level of the sensor, and that generates a control voltage in accordance with the difference between the voltage received at the first input node and the voltage received at the second input node; a voltage-controlled oscillation circuit connected to the output node of the voltage difference detection circuit and that generates an oscillation signal in accordance with the control voltage; and a second frequency-impedance conversion circuit connected between the voltage-controlled oscillation circuit and a second input node of the voltage difference detection circuit and that converts the frequency of a signal corresponding to the oscillation signal into a second impedance. [Effects of the Invention]

[0007] According to the present invention, the accuracy of converting the signal level of a sensor into a frequency can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing the configuration of a system including a sensor interface circuit according to an embodiment. [Figure 2] FIG. 1 is a circuit diagram showing a schematic configuration of a sensor interface circuit according to an embodiment. [Figure 3] FIG. 1 is a circuit diagram showing a configuration of a frequency synchronization circuit according to an embodiment. [Figure 4] 5A and 5B are diagrams illustrating the operation of the frequency impedance conversion circuit according to the embodiment. [Figure 5] FIG. 4 is a circuit diagram showing a schematic configuration of a sensor interface circuit according to a first modified example of the embodiment. [Figure 6] FIG. 4 is a circuit diagram showing a configuration of a frequency synchronization circuit according to a first modified example of the embodiment. [Figure 7] FIG. 10 is a block diagram showing a schematic configuration of a sensor interface circuit according to a second modified example of the embodiment. [Figure 8] FIG. 10 is a circuit diagram showing a configuration of a frequency synchronization circuit according to a second modified example of the embodiment. [Figure 9] FIG. 10 is a block diagram showing the configuration of a system including a sensor interface circuit according to a third modified example of the embodiment. [Figure 10] FIG. 10 is a block diagram showing a schematic configuration of a sensor interface circuit according to a third modified example of the embodiment. [Figure 11] FIG. 10 is a circuit diagram showing the configuration of a system including a sensor interface circuit according to a fourth modified example of the embodiment. [Figure 12] FIG. 10 is a circuit diagram showing a schematic configuration of a sensor interface circuit according to a fourth modified example of the embodiment. [Figure 13] FIG. 10 is a circuit diagram showing a detailed configuration of a sensor interface circuit according to a fourth modified example of the embodiment. [Figure 14] FIG. 10 is a diagram showing the operation of a sensor interface circuit according to a fourth modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the sensor interface circuit will be described in detail with reference to the drawings. In the following embodiments, parts with the same reference numerals perform similar operations, and redundant explanations will be omitted as appropriate.

[0010] (Embodiment) The sensor interface circuit according to the embodiment is a circuit that converts a signal level of a sensor into a frequency. The frequency converted by the sensor interface circuit is subsequently converted into a digital value corresponding to the signal level of the sensor and used. The sensor interface circuit is designed to improve the accuracy of conversion of the signal level of the sensor into a frequency.

[0011] For example, the sensor interface circuit 1 is applied to a system as shown in Fig. 1. Fig. 1 is a block diagram showing the configuration of a system 100 including the sensor interface circuit 1. The system 100 has a sensor 2, the sensor interface circuit 1, and a controller 3.

[0012] The sensor interface circuit 1 is connected between the sensor 2 and the controller 3. The sensor 2 detects a predetermined physical quantity and supplies the signal to the sensor interface circuit 1. The controller 3 controls a reference frequency F REF A periodic signal F with REF and supplies it to the sensor interface circuit 1. The sensor interface circuit 1 has an oscillation circuit and generates a periodic signal F REF , and the oscillator circuit performs an oscillation operation in accordance with the signal level of the sensor 2. As a result, the sensor interface circuit 1 generates a frequency F OUT An oscillating signal F having OUT and outputs it to the controller 3. The controller 3 generates an oscillation signal F OUT Digital value CNT according to OUT and generate a digital value CNT OUT The predetermined processing is performed using

[0013] The controller 3 has a clock generation circuit 4, a periodic signal generation circuit 5, a counter 6, and a processing circuit 7. The clock generation circuit 4 generates a system clock CLK and supplies it to the periodic signal generation circuit 5, the counter 6, and the processing circuit 7. The periodic signal generation circuit 5 divides the system clock CLK to generate a periodic signal F REF Alternatively, an oscillation operation may be performed in synchronization with the system clock CLK to generate a periodic signal FREF The periodic signal generating circuit 5 may generate the periodic signal F REF to the sensor interface circuit 1. The counter 6 counts in synchronization with the system clock CLK, and outputs an oscillation signal F OUT The number of pulses is counted and the count value is converted to a digital value CNT OUT The processing circuit 7 generates the system clock CLK and the digital value CNT OUT For example, the processing circuit 7 performs a predetermined process using the digital value CNT OUT into a value of a predetermined physical quantity (sensor element equivalent value). The processing circuit 7 may perform predetermined statistical processing using the sensor element equivalent value.

[0014] 1, the periodic signal generating circuit 5 and the counter 6 operate in synchronization with the same system clock CLK. If the oscillation frequency of the system clock CLK fluctuates by +10% during operation, the periodic signal F generated by the periodic signal generating circuit 5 will REF The reference frequency F REF Even if the system clock CLK fluctuates by +10%, the measurement time of the counter 6, which also operates on the system clock CLK, fluctuates by -10% and is cancelled out, so fluctuations in the system clock CLK have little effect. Therefore, a system clock with low accuracy can be used, which reduces the cost of the entire system 100.

[0015] In the configuration of Figure 1, a highly accurate digital value CNT OUTTo achieve this, it is desirable to improve the accuracy of the conversion of the signal level of the sensor 2 to a frequency in the sensor interface circuit 1. In order to improve the conversion accuracy in the sensor interface circuit 1, it is possible to realize the oscillator circuit as a frequency synchronization circuit. The frequency synchronization circuit may be a frequency negative feedback circuit composed of a frequency comparison circuit, a voltage-controlled oscillator (VCO), etc. The frequency difference between the oscillation frequency of the voltage-controlled oscillator and a reference frequency is detected, and the voltage of the voltage-controlled oscillator is controlled so that the frequency difference approaches zero. The accuracy of this frequency synchronization circuit can be improved by configuring it to perform the feedback operation of the frequency-locked loop in the voltage domain instead of the frequency domain.

[0016] For example, a sensor interface circuit 1 including a frequency synchronization circuit 10 can be configured as shown in Fig. 2. Fig. 2 is a circuit diagram showing a schematic configuration of the sensor interface circuit 1. The sensor interface circuit 1 is connected between a sensor 2 and a controller 3.

[0017] The sensor 2 is, for example, a capacitive sensor, and has a variable capacitance element C whose capacitance value changes equivalently according to the signal level. SENS Includes variable capacitance element C SENS One end of the sensor is connected to the terminal 1a of the sensor interface circuit 1, and the other end is connected to the ground potential.

[0018] The sensor interface circuit 1 includes a frequency synchronization circuit 10, an LPF (Low Pass Filter) 27, and an RF switch .

[0019] The frequency synchronization circuit 10 has an input node 10a electrically connected to one end of the sensor 2 via a terminal 1a, an input node 10b electrically connected to the controller 3 via a terminal 1b, and an output node 10c electrically connected to the controller 3 via an LPF 27, an RF switch 26, and a terminal 1c. The LPF 27 has an input node connected to the frequency synchronization circuit 10 and an output node connected to the RF switch 26. The RF switch 26 is, for example, an NMOS transistor, and has a gate connected to the LPF 27, a source connected to ground potential, and a drain connected to the controller 3 via a terminal 1c of the sensor interface circuit 1.

[0020] The frequency synchronization circuit 10 synchronizes the signal level of the sensor 2 (for example, the variable capacitance element C SENS The RF switch 26 is turned on and off in response to the oscillation signal received from the frequency synchronization circuit 10 via the LPF 27, thereby controlling the frequency F OUT An oscillating signal F having OUT is output from the terminal 1c. At this time, the frequency synchronization circuit 10 performs a feedback operation of the frequency locked loop in the voltage domain.

[0021] 3 is a diagram showing the configuration of the frequency synchronization circuit 10. For simplicity, the LPF 27 and the RF switch 26 are not shown in FIG. 3. The frequency synchronization circuit 10 generates a reference voltage V REF1 The frequency synchronization circuit 10 generates a periodic signal F REF Receives periodic signal F REF is the reference frequency F REF The frequency synchronization circuit 10 synchronizes the signal level of the sensor 2 (for example, the variable capacitance element C SENS The reference frequency F REF is the impedance Z SENS1 Convert to the reference frequency F REF If is kept approximately constant, the impedance Z SENS1 The change in the signal level of the sensor 2 (for example, the variable capacitance element C SENS The frequency synchronization circuit 10 responds to changes in the impedance Z SENS1Current I according to SENS1 generates a current I SENS1 Current I proportional to SENS2 Further, a current I SENS2 is a current corresponding to the signal level of the sensor 2. At the same time, the frequency synchronization circuit 10 performs an oscillation operation to generate an oscillation signal having a frequency F OUT The frequency synchronization circuit 10 converts the converted impedance Z2 into a current I SENS2 Further, using the voltage V SENS2 The converted voltage V SENS2 is a voltage corresponding to the signal level of the sensor 2. The frequency synchronization circuit 10 controls the feedback operation of the frequency locked loop by using a voltage V SENS2 and the reference voltage V REF1 The difference between these is adjusted to approach zero.

[0022] In the frequency synchronization circuit 10, in order to realize a frequency synchronization function in the voltage domain with high accuracy, the frequency F OUT a frequency-impedance conversion circuit 13 (second frequency-impedance conversion circuit) that converts the reference frequency F REF is the impedance Z SENS1 The frequency impedance conversion circuit 13 and the frequency impedance conversion circuit 18 (first frequency impedance conversion circuit) that converts the frequency impedance into a signal level of the sensor are connected via a current source 15. The frequency impedance conversion circuit 13 and the frequency impedance conversion circuit 18 are respectively configured with switched capacitor circuits that correspond to each other. As a result, the frequency synchronization circuit 10 is configured so that the frequency of the oscillation signal corresponding to the signal level of the sensor changes depending on the relative ratio between the characteristics of the sensor and the characteristics of the elements in the sensor interface circuit 1.

[0023] For example, as shown in Fig. 2, the frequency synchronization circuit 10 includes a voltage controlled oscillator circuit 11, a frequency divider circuit 12, a frequency impedance conversion circuit 13, a frequency divider circuit 19, a frequency impedance conversion circuit 18, a voltage source 14, a current source 15, a voltage difference detection circuit 16, and a filter 17. The voltage difference detection circuit 16, the filter 17, the voltage controlled oscillator circuit 11, the frequency divider circuit 12, and the frequency impedance conversion circuit 13 are connected in a loop. This loop connection constitutes a frequency locked loop. In addition, in the frequency synchronization circuit 10, the sensor 2 is connected to the current source 15 via the frequency impedance conversion circuit 18, and the current I SENS2 The frequency synchronization circuit 10 can be called a current-varying type frequency synchronization circuit.

[0024] The voltage source 14 is connected in parallel to the current source 15 and the voltage difference detection circuit 16. The output node 14a of the voltage source 14 is connected to a control node 15c of the current source 15 and an input node 16a of the voltage difference detection circuit 16. The voltage source 14 generates a reference voltage.

[0025] For example, the voltage source 14 generates a reference voltage V REF1 The voltage source 14 has a plurality of resistor elements R1 and R2. One end of the resistor element R2 is connected to the ground potential and the other end is connected to the resistor element R1. The resistor element R1 is connected to the resistor element R2 and the other end is connected to the power supply potential Vdd. If the resistance value of the resistor element R1 is R1 and the resistance value of the resistor element R2 is R2, the voltage source 14 generates a reference voltage V REF1 may be generated. V REF1 ={R2 / (R1+R2)}×V dd Formula 1

[0026] The frequency divider circuit 19 is electrically connected between the terminal 1b and the frequency-impedance conversion circuit 18. The frequency divider circuit 19 has an input node 19a electrically connected to the terminal 1b and an output node 19b electrically connected to the frequency-impedance conversion circuit 18. The frequency divider circuit 19 divides the periodic signal F REFis divided to generate a periodic signal F REF The periodic signal F' is generated and supplied to the frequency-impedance conversion circuit 18. REF is the reference frequency F REF The periodic signal F REF ' is the reference frequency F REF '. Reference frequency F REF ' is the reference frequency F REF In this case, the frequency divider circuit 19 divides the periodic signal F REF The duty ratio of ' can be adjusted to, for example, about 50%.

[0027] 3 is configured to divide by 2. The frequency divider circuit 19 includes a flip-flop 191 and an inverter 192. The flip-flop 191 has a data input node D connected to the output node of the inverter 192, a clock node CK connected to the terminal 1b, and a data output node Q connected to the input node of the inverter 192 and the frequency-impedance conversion circuit 18. The flip-flop 191 receives the periodic signal F REF In synchronization with the rising edge of the waveform of the periodic signal F, the output signal is held as a logically inverted signal and toggled. REF is divided by 2 to obtain the reference frequency F REF '(=F REF / 2) REF The frequency divider circuit 19 also divides the received periodic signal F REF By toggling the signal output with a period of F REF The duty ratio of ' can be adjusted to around 50%.

[0028] The frequency divider circuit 19 shown in FIG. REF A periodic signal F with REF ' is output to the frequency-impedance conversion circuit 18.

[0029] The frequency impedance conversion circuit 18 is electrically connected between the terminals 1a and 1b and the current source 15, and is also electrically connected between the sensor 2, the frequency divider circuit 19 and the current source 15. The frequency impedance conversion circuit 18 has an input node 18a connected to the sensor 2, an input node 18b connected to an output node 19b of the frequency divider circuit 19, and an output node 18c connected to an input node 15d of the current source 15. The frequency impedance conversion circuit 18 receives the periodic signal F REF ' and receives the periodic signal F REF 's reference frequency F REF ' to impedance Z1.

[0030] For example, the frequency-impedance conversion circuit 18 may be configured as a switched capacitor circuit, as shown in Fig. 3. A switched capacitor circuit is a circuit that limits current or voltage like a resistor by combining a switch and a capacitance element. The frequency-impedance conversion circuit 18 converts a periodic signal F REF By charging and discharging the capacitance element according to ', the detection value of sensor 2 and the reference frequency F REF ' and impedance Z according to SENS1 can be generated.

[0031] The frequency-impedance conversion circuit 18 includes a capacitance element (third capacitance element) 182, a switch (third switch) 183, a switch (fourth switch) 184, and an inverter (second inverter) 185. SENS has one end connected to the ground potential and the other end connected to a node 186 between the switches 183 and 184. The capacitive element 182 has one end connected to the ground potential and the other end connected to an input node 15d of the current source 15. The switch 183 has one end connected to the input node 15d of the current source 15 and the other end connected to the node 186, and a control end connected to the terminal 1b via the frequency divider circuit 19. The switch 184 has one end connected to the node 186 and the other end connected to the ground potential and a control end connected to the inverter 185. The inverter 185 has an input node connected to the terminal 1b via the frequency divider circuit 19 and an output node connected to the switch 184.

[0032] In the frequency-impedance conversion circuit 18, the switches 183 and 184 are connected to the periodic signal F REF This allows the variable capacitance element C SENS is charged and discharged. Periodic signal F REF When the signal ' is at H level, the switch 183 is maintained in the OFF state and the switch 184 is maintained in the ON state, and the variable capacitance element C SENS The charge of the variable capacitance element C SENS is discharged. Periodic signal F REF When ' is at an L level, the switch 183 is maintained in an on state and the switch 184 is maintained in an off state, and the current I SENS1 The charge corresponding to the variable capacitance element C SENS is stored in the variable capacitance element C SENS At this time, the capacitance element 182 is charged with the periodic signal F REF Regardless of the level of ', the current I SENS1 The charge stored in the capacitor is maintained at a level corresponding to the charge.

[0033] That is, the frequency-impedance conversion circuit 18 is REF A periodic signal F with REF ' by the variable capacitance element C SENS By periodically repeating charging and discharging, the reference frequency F REF ' and variable capacitance element C SENS The impedance Z corresponding to SENS1 At this time, the voltage at the output node 18c of the frequency-impedance conversion circuit 18 is equal to the voltage at the variable capacitance element C SENS During charging, the voltage at the output node 18c varies with a time constant, but converges to a stable point while being averaged by the capacitance element 182 that maintains the charge storage. The voltage at the output node 18c at this stable point is equalized by the current source 15 to the reference voltage V REF1 Therefore, the current I generated at the input node 15d of the current source 15 when converging to a stable point is SENS1 is the impedance Z generated in the frequency-impedance conversion circuit 18SENS1 Using this, it can be expressed as the following Equation 2. I SENS1 =V REF1 / Z SENS1 Formula 2

[0034] That is, the capacitance value of the capacitive element 182 is C AVE1 , variable capacitance element C SENS The capacitance value of C SENS Then, the current I generated at the input node 15d of the current source 15 when converging to the stable point is SENS1 is expressed as the following formula 3. I SENS1 =V REF1 F REF '·C SENS =V REF1 F REF C SENS / 2···Equation 3

[0035] As shown in Equations 2 and 3, in the state where the frequency converges to a stable point, the reference frequency F REF The frequency-impedance conversion circuit 18 has an impedance Z SENS1 =2 / (F REF C SENS ) is converted into the impedance Z SENS1 =2 / (F REF C SENS ) is connected to the input node 15d of the current source 15, and the other end is connected to the ground potential. REF1 According to this, the current I SENS1 is generated. Current I SENS1 is the impedance Z SENS1 and corresponds to the detection value of sensor 2. Also, the current I SENS1 is the reference frequency F REF ' and the periodic signal F received at terminal 1b REF The reference frequency F REF It corresponds to.

[0036] The voltage source 14 shown in FIG. REF1are supplied to a current source 15 and a voltage difference detection circuit 16, respectively.

[0037] The current source 15 is electrically connected to the voltage source 14, the voltage difference detection circuit 16, the frequency impedance conversion circuit 18, and the frequency impedance conversion circuit 13. The current source 15 has an input node 15a connected to the power supply potential Vdd, a control node 15c connected to the voltage source 14, an input node 15d connected to the frequency impedance conversion circuit 18, and an output node 15b connected to an input node 16b of the voltage difference detection circuit 16 and the frequency impedance conversion circuit 13. The current source 15 generates a current I SENS2 is generated and flows to the input node 16b of the voltage difference detection circuit 16.

[0038] For example, the current source 15 may be configured as shown in FIG. 3 . The current source 15 includes a transistor 151, a transistor 152, and a differential amplifier circuit 153. The transistor 151 is electrically connected between a power supply potential Vdd and an input node 16b of the voltage difference detection circuit 16. The transistor 151 is, for example, a PMOS transistor, and has a source connected to the power supply potential Vdd, a drain connected to the input node 16b of the voltage difference detection circuit 16, and a gate connected to an output node 153c of the differential amplifier circuit 153. The transistor 152 can be electrically connected between the power supply potential Vdd and the frequency impedance conversion circuit 18. The transistor 152 is, for example, a PMOS transistor, and has a source connected to the power supply potential Vdd, a drain connected to the frequency impedance conversion circuit 18, and a gate connected to an output node 153c of the differential amplifier circuit 153 and the gate of the transistor 151. The differential amplifier circuit 153 includes an input node 153a, an input node 153b, and an output node 153c. The input node 153a is electrically connected to the voltage source 14 and receives the reference voltage V REF1 The input node 153b is electrically connected to a node 154 between the transistor 152 and the frequency-impedance conversion circuit 18. The output node 153c is commonly connected to the gates of the transistors 151 and 152.

[0039] That is, the transistor 151 and the transistor 152 form a current mirror circuit via the differential amplifier circuit 153. Using a feedback loop of the differential amplifier circuit 153 → transistor 152 → node 154 → differential amplifier circuit 153, the differential amplifier circuit 153 detects whether the potential of the node 154 is equal to the reference voltage V REF1 The gate voltage of the transistor 151 and the gate voltage of the transistor 152 are controlled so that the impedance Z of the frequency-impedance conversion circuit 18 is equal to SENS1 The current I SENS1 is expressed as in equations 2 and 3 above.

[0040] If the mirror ratio of the current mirror circuit is 1, the current I flowing from the current source 15 to the input node 16b of the voltage difference detection circuit 16 is SENS2 is expressed as the following equation 4. I SENS2 =I SENS1 =V REF1 / Z SENS1 =V REF1 F REF C SENS / 2···Equation 4

[0041] As shown in Equation 4, the current I of the current source 15 SENS2 is the capacitance value C of sensor 2 SENS Impedance Z according to SENS1 and the capacitance value of sensor 2, C SENS It changes according to the change of the reference voltage V REF1 and the reference frequency F REF If is approximately constant, the current I SENS2 The change in the capacitance of sensor 2, C SENS Shows the change in

[0042] 2 is electrically connected between the voltage difference detection circuit 16 and the output node 10c, and is electrically connected between the filter 17 and the frequency divider circuit 12. The input node 11a of the voltage controlled oscillator 11 is electrically connected to the output node 16c of the voltage difference detection circuit 16 via the filter 17, and the output node 11b is electrically connected to the output node 10c via the frequency divider circuit 12. The voltage controlled oscillator 11 receives a control voltage V CTRL The oscillator operates according to the control voltage V CTRL The frequency F SENS An oscillating signal F having SENS Generate.

[0043] For example, the voltage-controlled oscillator 11 may be configured as a relaxation oscillator circuit as shown in FIG. 3. The voltage-controlled oscillator 11 includes an inverter chain 111, a variable resistor 112, and a capacitor 113. The inverter chain 111 includes multiple inverters Inv1 to Inv3 connected in a ring and an inverter Inv4 provided on the output side outside the ring. Each inverter Inv is configured, for example, by inverter-connecting an NMOS transistor and a PMOS transistor. The number of inverters Inv connected in a ring is an odd number, for example, three. The output node of the first-stage inverter Inv1 is electrically connected to the input node of the next-stage inverter Inv2. The output node of the last-stage inverter Inv3 is electrically connected to the input node of the inverter Inv4 and the input node of the first-stage inverter Inv1, respectively. The output node of the inverter Inv4 is connected to the output node 11b of the voltage-controlled oscillator 11. The variable resistor 112 is electrically connected in series to the multiple inverters Inv1 to Inv3 in the inverter chain 111. The variable resistance element 112 is electrically connected between the output node of the inverter Inv2 and the input node of the inverter Inv3. The capacitance element 113 is connected in parallel to the inverter Inv and the variable resistance element 112 in the inverter chain 111. In Fig. 3, the capacitance element 113 is connected in parallel to the series connection of the second-stage inverter Inv2 and the variable resistance element 112.

[0044] In the voltage controlled oscillator circuit 11, the variable resistance element 112 generates a control voltage V CTRL The variable resistance element 112 receives the control voltage V CTRL Depending on the resistance R VCO The capacitance value of the capacitance element 113 is changed to C VCO Then, the resistance value R of the variable resistance element 112 VCO The time constant R VCO ×C VCO The oscillation frequency F of the voltage controlled oscillator circuit 11 changes. SENS is the time constant R VCO ×C VCO That is, the voltage controlled oscillator circuit 11 is determined according to the control voltage V CTRL Depending on the time constant R VCO ×C VCO changes, and the time constant R VCO ×C VCO The frequency F SENS 3, the variable resistance element 112 has a drain connected to the output node of the inverter Inv2, a source connected to the input node of the inverter Inv3, and a gate connected to a control voltage V CTRL Alternatively, the NMOS transistor may be configured with an NMOS transistor to which

[0045] The voltage controlled oscillator circuit 11 shown in FIG. SENS An oscillating signal F having SENS is supplied to the frequency divider circuit 12.

[0046] The frequency divider circuit 12 is electrically connected between the voltage controlled oscillator circuit 11 and the output node 10c. The input node 12a of the frequency divider circuit 12 is electrically connected to the output node 11b of the voltage controlled oscillator circuit 11, and the output node 12b is electrically connected to the output node 10c. The frequency divider circuit 12 divides the oscillation signal F SENS Divide to get frequency F OUT An oscillating signal F having OUT and supplies it to the LPF 27 and the frequency-impedance conversion circuit 13.OUT is the frequency F SENS In this case, the frequency divider circuit 12 can adjust the duty ratio of the oscillation signal to, for example, about 50%.

[0047] 3 is configured to perform frequency division by 2. The frequency divider circuit 12 includes a flip-flop 121 and an inverter 122. The flip-flop 121 has a data input node D connected to the output node of the inverter 122, a clock node CK connected to the output node 11b of the voltage controlled oscillator circuit 11, and a data output node Q connected to the input node of the inverter 122, the LPF 27, and the frequency impedance conversion circuit 13. The flip-flop 121 outputs the oscillation signal F SENS In synchronization with the rising edge of the waveform of the frequency divider 12, the frequency divider 12 holds the logically inverted signal and toggles the output signal. SENS is divided by 2 to get frequency F OUT (=F SENS / 2) OUT The frequency divider circuit 12 also generates the received oscillation signal F SENS By toggling the signal output at a period of OUT The duty ratio can be adjusted to around 50%.

[0048] The frequency divider circuit 12 shown in FIG. OUT An oscillating signal F having OUT is output to the LPF 27 and is also fed back to the frequency-impedance conversion circuit 13.

[0049] The frequency impedance conversion circuit 13 is electrically connected between the voltage controlled oscillator circuit 11 and the input node 16b of the voltage difference detection circuit 16, and is also electrically connected between the frequency divider circuit 12 and the input node 16b of the voltage difference detection circuit 16. The frequency impedance conversion circuit 13 is arranged on a feedback line leading from the output node 12b of the frequency divider circuit 12 to the input node 16b of the voltage difference detection circuit 16. The input node 13a of the frequency impedance conversion circuit 13 is connected to the frequency divider circuit 12, and the output node 13b is connected to the input node 16b of the voltage difference detection circuit 16. The frequency impedance conversion circuit 13 receives the oscillation signal F from the frequency divider circuit 12. OUT Receives the oscillation signal F OUT The frequency F OUT is converted into impedance Z2.

[0050] For example, the frequency-impedance conversion circuit 13 may be configured as a switched capacitor circuit as shown in Fig. 3. The frequency-impedance conversion circuit 13 converts the oscillation signal F OUT By charging and discharging the capacitance element according to the oscillation signal F OUT The frequency F OUT The value Z2 can be set according to the above.

[0051] The frequency-impedance conversion circuit 13 includes a capacitance element (first capacitance element) 131, a capacitance element (second capacitance element) 132, a switch (first switch) 133, a switch (second switch) 134, and an inverter 135. The capacitance element 131 has one end connected to the ground potential and the other end connected to a node 136 between the switches 133 and 134. The capacitance element 132 has one end connected to the ground potential and the other end connected to an input node 16b of the voltage difference detection circuit 16. The switch 133 has one end connected to the input node 16b of the voltage difference detection circuit 16 and the other end connected to the node 136, and a control end connected to the voltage-controlled oscillation circuit 11 via the frequency divider circuit 12. The switch 134 has one end connected to the node 136 and the other end connected to the ground potential and a control end connected to the inverter 135. The inverter 135 has an input node connected to the voltage controlled oscillator circuit 11 via the frequency divider circuit 12, and an output node connected to the switch .

[0052] In the frequency-impedance conversion circuit 13, the switches 133 and 134 are connected to the oscillation signal F OUT The oscillation signal F is turned on and off in a complementary manner according to the level of the oscillation signal F. This causes the capacitance element 131 to be charged and discharged. OUT When the oscillation signal F is at H level, the switch 133 is maintained in the OFF state and the switch 134 is maintained in the ON state, so that the charge in the capacitance element 131 is discharged to the ground potential, and the capacitance element 131 is discharged. OUT is at an L level, the switch 133 is maintained in an ON state and the switch 134 is maintained in an OFF state, and the current I SENS2 The capacitance element 132 is charged with a charge corresponding to the oscillation signal F OUT Regardless of the level of the current I SENS2 The charge stored in the capacitor is maintained at a level corresponding to the charge.

[0053] That is, the frequency impedance conversion circuit 13 converts the frequency F OUT An oscillating signal F having OUT By periodically repeating charging and discharging of the capacitance element 131, a frequency FOUT The output voltage of the frequency-impedance conversion circuit 13 is the voltage V at the input node 16b of the voltage difference detection circuit 16. SENS2 It appears as voltage V SENS2 changes with a time constant when the capacitance element 131 is charged, but the current I SENS2 The voltage V at the input node 16b of the voltage difference detection circuit 16 when converging to the stable point is averaged by the capacitance element 132 that maintains the accumulation of charge according to the voltage V. SENS2 can be expressed as the following Equation 5 using the impedance Z2 generated in the frequency-impedance conversion circuit 13. V SENS2 =I SENS2 / Z2... Formula 5

[0054] For example, as shown in Figure 4, the current I SENS2 When =I1, the voltage V when converging to a stable point SENS2 =V1. Current I SENS2 When =I2, the voltage V when converging to a stable point SENS2 =V2. Current I SENS2 =I 10 When the voltage V converges to the stable point, SENS2 =V 10 FIG. 4 is a diagram showing the operation of the frequency-impedance conversion circuit 13, where the vertical axis indicates the magnitude of the voltage and the horizontal axis indicates time. In the frequency-impedance conversion circuit 13, the flowing current I SENS2 As increases, the voltage V SENS2 In other words, the capacitance value of the capacitance element 132 increases in proportion to C AVE2 , the capacitance value of the capacitive element 131 is C SC2 Then, the voltage V of the input node 16b of the voltage difference detection circuit 16 when converging to the stable point is SENS2 is expressed as the following Equation 6. V SENS2 =I SENS2 / (F OUT C SC2 )···Equation 6

[0055] As shown in Equations 5 and 6, when the oscillation signal converges to a stable point, the frequency F OUT The frequency impedance conversion circuit 13 has an impedance Z2=1 / (F OUT C SC2 ) is converted into impedance Z2 = 1 / (F OUT C SC2 ) is connected to the input node 16b of the voltage difference detection circuit 16, and the other end is connected to the ground potential. Therefore, the current I from the current source 15 flows to the input node 16b of the voltage difference detection circuit 16. SENS2 is the equivalent impedance Z2=1 / (F OUT C SC2 ) and the equivalent impedance Z2=1 / (F OUT C SC2 ) causes the current I SENS2 is the voltage V SENS2 is converted into the voltage V SENS2 is the current I SENS2 and corresponds to the detected value of sensor 2. Also, the voltage V SENS2 is the frequency F OUT and the oscillation frequency F of the voltage controlled oscillator circuit 11. SENS It corresponds to.

[0056] 2, a voltage source 14, a current source 15, and a frequency-impedance conversion circuit 13 are connected to the input terminals of the voltage difference detection circuit 16, and a filter 17 is electrically connected to the output terminals. The voltage difference detection circuit 16 has an input node 16a connected to the voltage source 14, an input node 16b connected to the current source 15 and the frequency-impedance conversion circuit 13, and an output node 16c connected to the filter 17. The voltage difference detection circuit 16 detects a reference voltage V at the input node 16a. REF1 and a voltage V SENS2 The voltage difference detection circuit 16 generates a reference voltage V REF1 and voltage V SENS2 The control voltage V is used to reduce the difference depending on the difference between CTRL ' is generated.

[0057] 3, the voltage difference detection circuit 16 includes a differential amplifier circuit 161. The differential amplifier circuit 161 has an inverting input terminal (-) connected to the voltage source 14, a non-inverting input terminal (+) connected to the current source 15 and the frequency impedance conversion circuit 13, and an output terminal connected to the filter 17. The differential amplifier circuit 161 detects a reference voltage V REF1 and voltage V SENS2 The difference is amplified to produce the control voltage V CTRL ' is generated.

[0058] 2 is electrically connected between the voltage difference detection circuit 16 and the voltage controlled oscillation circuit 11. The filter 17 has an input node 17a connected to the voltage difference detection circuit 16 and an output node 17b connected to the voltage controlled oscillation circuit 11. The filter 17 receives the control voltage V CTRL ', and the control voltage V CTRL The filter 17 filters the filtered control voltage V CTRL is supplied to the voltage controlled oscillator circuit 11.

[0059] For example, the filter 17 may be configured as a low-pass filter as shown in Fig. 3. The filter 17 has a resistive element 171 and a capacitive element 172. One end of the resistive element 171 is connected to the output terminal of the differential amplifier circuit 161, and the other end is connected to one end of the capacitive element 172 and the voltage-controlled oscillator circuit 11. The other end of the capacitive element 172 is connected to the ground potential. With this configuration, the filter 17 is configured as a low-pass filter in response to a control voltage V CTRL ' is smoothed by low-pass filtering, and the smoothed control voltage V CTRL can be supplied to the voltage controlled oscillator circuit 11.

[0060] In the frequency synchronization circuit 10, the voltage difference detection circuit 16 is configured to detect the voltage V using a frequency synchronization loop of the voltage difference detection circuit 16 → filter 17 → voltage controlled oscillator circuit 11 → frequency divider circuit 12 → frequency impedance conversion circuit 13 → voltage difference detection circuit 16. SENS2 is the reference voltage V REF1 The control voltage V CTRLIn other words, if the feedback control functions normally, the following formula 7 holds true. V REF1 =V SENS2 Formula 7

[0061] Substituting Equation 6 into Equation 7, we obtain the following Equation 8. V REF1 =I SENS2 / (F OUT C SC2 )···Equation 8

[0062] Further substituting Equation 4 into Equation 8, we obtain the following Equation 9. V REF1 =V REF1 F REF C SENS / (2·F OUT C SC2 )···Equation 9

[0063] Equation 9 is converted to frequency F OUT By solving this, we obtain the following equation 10. F OUT =F REF ·(C SENS / C SC2 ) / 2···Equation 10

[0064] As shown in Equation 10, the oscillation signal F OUT The frequency F OUT is the capacitance value C of sensor 2 SENS and the capacitance value C of the capacitance element 131 in the sensor interface circuit 1 SC2 In other words, the accuracy of the frequency of the oscillation signal is obtained according to the ratio of the capacitance value C SENS and capacitance value C SC2 For example, the accuracy of the variable capacitance element C is affected by factors such as the manufacturing process, power supply voltage, and / or temperature. SENS If the capacitance element 131 fluctuates in approximately the same way, the relative ratio (C SENS / C SC2 ) will remain almost unchanged.

[0065] As described above, in this embodiment, the sensor interface circuit 1 has a frequency F OUT is obtained according to the ratio between the characteristics of the sensor 2 and the characteristics of an element (capacitance element 131) in the sensor interface circuit 1. As a result, if the sensor 2 and the element in the sensor interface circuit 1 are used that exhibit approximately the same fluctuations in response to changes in the fluctuation factors, it is possible to suppress fluctuations in the frequency of the oscillation signal that correspond to changes in the fluctuation factors. In other words, since the influence of the fluctuation factors can be suppressed, the accuracy of converting the signal level of the sensor 2 into a frequency can be easily improved.

[0066] In the frequency synchronization circuit 10, if the duty ratio of the oscillation signal output from the voltage controlled oscillation circuit 11 is close to 50%, the frequency divider circuit 12 may be omitted. REF If the duty ratio is close to 50%, the frequency divider circuit 19 may be omitted. Also, if the control voltage output from the voltage difference detection circuit 16 is substantially smooth, the filter 17 may be omitted.

[0067] (First Modification of the Embodiment) The sensor connected to the sensor interface circuit 1i in the system 100i may be a resistive sensor 2i instead of the capacitive sensor 2 (see FIG. 2), as shown in Fig. 5. Fig. 5 is a circuit diagram showing a schematic configuration of a sensor interface circuit 1i according to a first modified example of the embodiment.

[0068] The sensor interface circuit 1i is connected between the sensor 2i and the controller 3 (see FIG. 1).

[0069] The sensor 2i is, for example, a resistive sensor, and has a variable resistance element R whose resistance value changes equivalently according to the signal level. SENS Includes variable resistance element R SENS has one end connected to a terminal 1d of the sensor interface circuit 1i, and the other end connected to a terminal 1e of the sensor interface circuit 1i.

[0070] The sensor interface circuit 1i has a frequency synchronization circuit 10i instead of the frequency synchronization circuit 10 (see FIG. 2). The frequency synchronization circuit 10i has an input node 10d electrically connected to one end of the sensor 2i via a terminal 1d, and an input node 10e electrically connected to the other end of the sensor 2i via a terminal 1e.

[0071] The frequency synchronization circuit 10i synchronizes the signal level of the sensor 2i (for example, the variable resistance element R SENS At this time, the frequency synchronization circuit 10i performs a feedback operation of the frequency locked loop in the voltage domain.

[0072] FIG. 6 is a circuit diagram showing the configuration of a frequency synchronization circuit 10i according to a first modified example of the embodiment. For simplicity, the LPF 27 and the RF switch 26 are omitted from FIG. 6. The frequency synchronization circuit 10i synchronizes the signal level of the sensor 2i (for example, the signal level of the variable resistance element R SENS Depending on the resistance value of SENS11 and voltage V SENS12 The frequency synchronization circuit 10i generates a periodic signal F REF The frequency synchronization circuit 10i receives the reference frequency F REF The frequency synchronization circuit 10i converts the voltage V SENS12 and the current I according to the impedance Z1 SENS1 generates a current I SENS1 Current I proportional to SENS2 At the same time, the frequency synchronization circuit 10i performs an oscillation operation to generate an oscillation signal with an oscillation frequency F OUT The frequency synchronization circuit 10i converts the converted impedance Z2 into a current I SENS2 Further, using the voltage V SENS2 The converted voltage V SENS2 is a voltage corresponding to the signal level of the sensor 2i. The frequency synchronization circuit 10i controls the feedback operation of the frequency locked loop by using a voltage V SENS2 and the voltage V according to the signal level of sensor 2i SENS1This is done so that the difference between the two approaches zero. This enables highly accurate frequency synchronization in the voltage domain.

[0073] 5, the frequency synchronization circuit 10i has a voltage source 14i and a frequency impedance conversion circuit 18i instead of the voltage source 14 and the frequency impedance conversion circuit 18 (see FIG. 2). In the frequency synchronization circuit 10i, the sensor 2i is connected to the voltage source 14i and is also connected to a current source 15 via the voltage source 14i, and the current I that the current source 15 flows in response to the signal level of the sensor 2i is SENS2 As the voltage V changes, the voltage source 14i generates SENS11 The frequency synchronization circuit 10i can be called a current-voltage changing type frequency synchronization circuit.

[0074] Voltage source 14i is electrically connected between terminals 1d and 1e and current source 15 and voltage difference detection circuit 16, and is electrically connected between sensor 2i, current source 15, and voltage difference detection circuit 16. Input node 14b of voltage source 14i is connected to one end of sensor 2i, input node 14c is connected to the other end of sensor 2i, and output node 14a is connected to current source 15 and voltage difference detection circuit 16. Voltage source 14i generates a voltage according to the signal level of sensor 2i.

[0075] For example, the voltage source 14i generates two voltages V SENS11 ,V SENS12 The voltage source 14i generates a voltage by connecting the resistance element R1 to the voltage source 14 (see FIG. 3) with the variable resistance element R SENS In the sensor 2i, the variable resistance element R SENS Two bottles will be provided.

[0076] In the bridge on the left side of Figure 6, the variable resistance element R SENS is arranged on the power supply potential Vdd side, and the resistance element (first resistance element) R2 is arranged on the ground potential side. SENSOne end of the variable resistance element R is connected to the power supply potential Vdd via the input node 14d. SENS The other end of the variable resistance element R is connected to the ground potential via the input node 14e and the resistance element R2. SENS The intermediate node between the resistor element (first resistor element) R2 is electrically connected to the input node 16a of the voltage difference detection circuit 16. At the intermediate node, a voltage V SENS11 is generated and supplied to the input node 16 a of the voltage difference detection circuit 16 . V SENS11 ={R2 / (R SENS +R2)}×V dd Formula 11

[0077] In the bridge on the right side of FIG. 6, the resistance element (second resistance element) R2 is arranged on the power supply potential Vdd side, and the variable resistance element R SENS is placed on the ground potential side. SENS One end of the variable resistor R is connected to the power supply potential Vdd via the input node 14f and the resistor R2. SENS The other end of the resistor element (second resistor element) R2 is connected to the ground potential via an input node 14g. SENS The intermediate node is electrically connected to the input node 153a of the differential amplifier circuit 153 of the current source 15. At the intermediate node, a voltage V SENS12 is generated and supplied to the differential amplifier circuit 153 of the current source 15. V SENS12 ={R SENS / (R SENS +R2)}×V dd Formula 12

[0078] The frequency impedance conversion circuit 18i is not connected to the sensor 2 (see FIG. 3). As shown in FIG. 6, the frequency impedance conversion circuit 18i can be configured as a switched capacitor circuit, similar to the embodiment. The frequency impedance conversion circuit 18i is configured by connecting a variable capacitance element C SENS is replaced with the capacitance element (fourth capacitance element) 181.

[0079] That is, the frequency-impedance conversion circuit 18i is REF A periodic signal F with REF ', the capacitance element 181 is periodically charged and discharged, thereby equivalently generating a reference frequency F REF At this time, the voltage of the output node 18c of the frequency-impedance conversion circuit 18i varies with a time constant when the capacitance element 181 is charged, but converges to a stable point while being averaged by the capacitance element 182 that maintains the accumulated charge. The voltage of the output node 18c at this stable point is equalized by the current source 15 with the reference voltage V SENS12 Therefore, the current I generated at the input node 15d of the current source 15 when converging to a stable point is SENS1 can be expressed as the following Equation 13 using the impedance Z1 generated in the frequency-impedance conversion circuit 18i. I SENS1 =V SENS12 / Z1···Equation 13

[0080] That is, the capacitance value of the capacitive element 182 is C AVE1 , the capacitance value of the capacitive element 181 is C SC1 Then, the current I generated at the input node 15d of the current source 15 when converging to the stable point is SENS1 is expressed as the following Equation 14. I SENS1 =V SENS12 F REF '·C SC1 =V SENS12 F REF C SC1 / 2···Equation 14

[0081] As shown in Equations 13 and 14, in the state where the frequency converges to a stable point, the reference frequency F REF The frequency-impedance conversion circuit 18i has an impedance Z1=2 / (F REF C SC1 )

[0082] If the mirror ratio of the current mirror circuit in the current source 15 is 1, the current I flowing from the current source 15 to the input node 16b of the voltage difference detection circuit 16 is SENS2 is expressed as the following Equation 15. I SENS2 =I SENS1 =V SENS12 / Z1=V SENS12 F REF C SC1 / 2···Formula 15

[0083] On the other hand, the frequency impedance conversion circuit 13 is OUT An oscillating signal F having OUT By periodically repeating charging and discharging of the capacitance element 131, a frequency F OUT The voltage V at the input node 16b of the voltage difference detection circuit 16 when the voltage difference V converges to a stable point can be generated. SENS2 can be expressed as in the above equations 5 and 6.

[0084] In the frequency synchronization circuit 10i, the voltage difference detection circuit 16 detects the voltage V using a frequency synchronization loop of the voltage difference detection circuit 16 → filter 17 → voltage controlled oscillator circuit 11 → frequency divider circuit 12 → frequency impedance conversion circuit 13 → voltage difference detection circuit 16. SENS2 is the voltage V SENS11 The control voltage V CTRL That is, when the feedback control functions normally, the following formula 16 holds true. V SENS11 =V SENS2 Formula 16

[0085] Substituting Equation 6 into Equation 16, we obtain the following Equation 17. V SENS11 =I SENS2 / (F OUT C SC2 )···Equation 17

[0086] Further substituting the formulas 11, 12, and 15 into the formula 17, the following formula 18 is obtained. {R2 / (R SENS+R2)}×V dd ={R SENS / (R SENS +R2)}×V dd F REF C SC1 / (2·F OUT C SC2 )···Equation 18

[0087] Equation 18 is converted to frequency F OUT By solving for , we obtain the following Equation 19. F OUT =F REF ·(C SC1 / C SC2 )·(R SENS / R2) / 2···Equation 19

[0088] As shown in Equation 19, the oscillation signal F OUT The frequency F OUT is the capacitance value C of the capacitive element 181 in the sensor interface circuit 1i SC1 and the capacitance value C of the capacitive element 131 SC2 and the resistance value R of the sensor 2i SENS and the resistance value R2 of the resistor element R2 in the sensor interface circuit 1i. That is, the accuracy of the frequency of the oscillation signal is obtained according to the ratio of the capacitance value C SC1 and capacitance value C SC2 Relative accuracy and resistance value R SENS For example, the capacitance elements 181 and 131 may fluctuate in almost the same way due to the influence of fluctuation factors such as the manufacturing process, the power supply voltage, and / or the temperature, and the capacitance of the variable resistance element R SENS If the resistance element R1 and the resistance element R2 fluctuate in almost the same way, the relative ratio (C SC1 / C SC2 )·(R SENS / R2) will hardly fluctuate.

[0089] In this way, the sensor interface circuit 1i receives the oscillation signal F OUT The frequency F OUTis obtained according to the ratio of the characteristics of the elements (capacitance elements 181, 131) in the sensor interface circuit 1i and the ratio of the characteristics of the sensor 2i to the characteristics of the element (resistance element R2) in the sensor interface circuit 1i. As a result, by using elements in the sensor 2i and the sensor interface circuit 1i that exhibit approximately the same fluctuations in response to changes in the fluctuation factors, it is possible to suppress fluctuations in the frequency of the oscillation signal that occur in response to changes in the fluctuation factors. In other words, since the influence of the fluctuation factors can be suppressed, the accuracy of converting the signal level of the sensor 2i into a frequency can be easily improved.

[0090] (Second Modification of the Embodiment) The sensor connected to the sensor interface circuit 1j in the system 100j may be a resistive sensor 2i in addition to the capacitive sensor 2, as shown in Fig. 7. Fig. 7 is a circuit diagram showing a schematic configuration of a sensor interface circuit 1j according to a second modified example of the embodiment.

[0091] The sensor interface circuit 1j is connected between the sensors 2, 2i and the controller 3 (see FIG. 1).

[0092] The sensor 2 is, for example, a capacitive sensor, and has a variable capacitance element C whose capacitance value changes equivalently according to the signal level. SENS The sensor 2i is, for example, a resistive sensor, and includes a variable resistance element R whose resistance value changes equivalently according to the signal level. SENS Includes.

[0093] The sensor interface circuit 1j has a frequency synchronization circuit 10j instead of the frequency synchronization circuit 10 (see FIG. 2). The frequency synchronization circuit 10j has an input node 10d electrically connected to one end of the sensor 2i via a terminal 1d, and an input node 10e electrically connected to the other end of the sensor 2i via a terminal 1e.

[0094] The frequency synchronization circuit 10j synchronizes the signal level of the sensor 2 (for example, the variable capacitance element C SENS the capacitance value of the variable resistance element R SENSAt this time, the frequency synchronization circuit 10j performs a feedback operation of the frequency locked loop in the voltage domain.

[0095] FIG. 8 is a circuit diagram showing the configuration of a frequency synchronization circuit 10j according to a second modification of the embodiment. For simplicity, the LPF 27 and the RF switch 26 are omitted from FIG. 8. The frequency synchronization circuit 10j synchronizes the signal level of the sensor 2i (for example, the signal level of the variable resistance element R SENS Depending on the resistance value of SENS11 and voltage V SENS12 The frequency synchronization circuit 10j generates a periodic signal F REF The frequency synchronization circuit 10j receives the signal level of the sensor 2 (for example, the variable capacitance element C SENS The reference frequency F REF is the impedance Z SENS1 The frequency synchronization circuit 10j converts the voltage V SENS12 and impedance Z SENS1 and the current I SENS1 generates a current I SENS1 Current I proportional to SENS2 At the same time, the frequency synchronization circuit 10j performs an oscillation operation to generate an oscillation signal with an oscillation frequency F OUT The frequency synchronization circuit 10j converts the converted impedance Z2 into a current I SENS2 Further, using the voltage V SENS2 The converted voltage V SENS2 is a voltage corresponding to the signal level of the sensor 2i. The frequency synchronization circuit 10j controls the feedback operation of the frequency locked loop by using a voltage V SENS2 and the voltage V according to the signal level of sensor 2i SENS11 This is done so that the difference between the two approaches zero. This enables highly accurate frequency synchronization in the voltage domain.

[0096] 7, the frequency synchronization circuit 10j has a voltage source 14i instead of the voltage source 14 (see FIG. 2). In the frequency synchronization circuit 10j, the sensor 2i is connected to the voltage source 14i and is also connected to a current source 15 via the voltage source 14i. The current I SENS2 As the voltage V changes, the voltage source 14i generates SENS11 The frequency synchronization circuit 10j can be called a current-voltage changing type frequency synchronization circuit.

[0097] Voltage source 14i is electrically connected between terminals 1d and 1e and current source 15 and voltage difference detection circuit 16, and is electrically connected between sensor 2i, current source 15, and voltage difference detection circuit 16. Input node 14b of voltage source 14i is connected to one end of sensor 2i, input node 14c is connected to the other end of sensor 2i, and output node 14a is connected to current source 15 and voltage difference detection circuit 16. Voltage source 14i generates a voltage according to the signal level of sensor 2i.

[0098] For example, the voltage source 14i generates two voltages V SENS11 ,V SENS12 The voltage source 14i connects the resistance element R1 to the voltage source 14 (see FIG. 3) and the variable resistance element R of the sensor 2i. SENS In the sensor 2i, the variable resistance element R SENS Two bottles will be provided.

[0099] In the bridge on the left side of Figure 8, the variable resistance element R SENS is arranged on the power supply potential Vdd side, and the resistance element R2 is arranged on the ground potential side. SENS One end of the variable resistance element R is connected to the power supply potential Vdd via the input node 14d. SENS The other end of the resistor R2 is connected to the ground potential via the input node 14e and the resistor R2, and the voltage V SENS11 is generated.

[0100] In the bridge on the right side of FIG. 8, the resistance element R2 is arranged on the power supply potential Vdd side, and the variable resistance element R SENS is placed on the ground potential side. SENS One end of the variable resistor R is connected to the power supply potential Vdd via the input node 14f and the resistor R2. SENS The other end of the input terminal 14 is connected to the ground potential via the input node 14g, and the voltage V SENS12 is generated.

[0101] The frequency-impedance conversion circuit 18 converts the reference frequency F REF A periodic signal F with REF ' by the variable capacitance element C SENS By periodically repeating charging and discharging, the reference frequency F REF ' and variable capacitance element C SENS The impedance Z corresponding to SENS1 At this time, the voltage at the output node 18c of the frequency-impedance conversion circuit 18 is equal to the voltage at the variable capacitance element C SENS During charging, the voltage at the output node 18c varies with a time constant, but converges to a stable point while being averaged by the capacitance element 182 that maintains the charge storage. The voltage at the output node 18c at this stable point is equalized by the current source 15 to the reference voltage V SENS12 Therefore, the current I generated at the input node 15d of the current source 15 when converging to a stable point is SENS1 is the impedance Z generated in the frequency-impedance conversion circuit 18 SENS1 Using this, it can be expressed as the following Equation 20. I SENS1 =V SENS12 / Z SENS1 Formula 20

[0102] That is, the capacitance value of the capacitive element 182 is C AVE1 , variable capacitance element C SENS The capacitance value of C SENS Then, the current I generated at the input node 15d of the current source 15 when converging to the stable point is SENS1 is expressed as the following Equation 21. ISENS1 =V SENS12 F REF '·C SENS =V SENS12 F REF C SENS / 2···Formula 21

[0103] As shown in Equations 20 and 21, in the state where the frequency converges to a stable point, the reference frequency F REF The frequency-impedance conversion circuit 18 has an impedance Z SENS1 =2 / (F REF C SENS )

[0104] If the mirror ratio of the current mirror circuit in the current source 15 is 1, the current I flowing from the current source 15 to the input node 16b of the voltage difference detection circuit 16 is SENS2 is expressed as the following Equation 22. I SENS2 =I SENS1 =V SENS12 / Z SENS1 =V SENS12 F REF C SENS / 2···Formula 22

[0105] On the other hand, the frequency impedance conversion circuit 13 is OUT An oscillating signal F having OUT By periodically repeating charging and discharging of the capacitance element 131, a frequency F OUT The voltage V at the input node 16b of the voltage difference detection circuit 16 when the voltage difference V converges to a stable point can be generated. SENS2 can be expressed as in the above equations 5 and 6.

[0106] In the frequency synchronization circuit 10j, the voltage difference detection circuit 16 detects the voltage V using a frequency synchronization loop of the voltage difference detection circuit 16 → filter 17 → voltage controlled oscillator circuit 11 → frequency divider circuit 12 → frequency impedance conversion circuit 13 → voltage difference detection circuit 16. SENS2 is the voltage V SENS11 The control voltage V CTRLIn other words, when the feedback control functions normally, the above formula 16 holds.

[0107] Substituting Equation 6 into Equation 16 gives the above Equation 17. Further substituting Equations 11, 12, and 22 into Equation 17 gives the following Equation 23. {R2 / (R SENS +R2)}×V dd ={R SENS / (R SENS +R2)}×V dd F REF C SENS / (2·F OUT C SC2 )···Equation 23

[0108] Equation 23 is converted to frequency F OUT By solving this, we obtain the following equation 24. F OUT =F REF ·(C SENS / C SC2 )·(R SENS / R2) / 2···Equation 24

[0109] As shown in Equation 24, the oscillation signal F OUT The frequency F OUT is the capacitance value C of sensor 2 SENS and the capacitance value C of the capacitance element 131 in the sensor interface circuit 1j SC2 and the resistance value R of the sensor 2i SENS and the resistance value R2 of the resistor element R2 in the sensor interface circuit 1j. That is, the accuracy of the frequency of the oscillation signal is obtained according to the ratio of the capacitance value C SENS and capacitance value C SC2 Relative accuracy and resistance value R SENS The relative accuracy of the resistance R2 depends on the manufacturing process, power supply voltage, and / or temperature. SENS and the capacitance element 131 fluctuate in almost the same way, and the variable resistance element R SENS If the resistance element R1 and the resistance element R2 fluctuate in almost the same way, the relative ratio (C SENS / C SC2 )·(RSENS / R2) will hardly fluctuate.

[0110] In this way, the sensor interface circuit 1j receives the oscillation signal F OUT The frequency F OUT is obtained according to the ratio between the characteristics of the sensor 2 and the characteristics of an element (capacitor element 131) in the sensor interface circuit 1j, and the ratio between the characteristics of the sensor 2i and the characteristics of an element (resistance element R2) in the sensor interface circuit 1j. As a result, by using sensors 2 and 2i and elements in the sensor interface circuit 1j that exhibit approximately the same fluctuations in response to changes in fluctuation factors, fluctuations in the frequency of the oscillation signal that occur in response to changes in the fluctuation factors can be suppressed. In other words, since the influence of the fluctuation factors can be suppressed, the accuracy of converting the signal level of the sensors 2 and 2i into frequency can be easily improved.

[0111] (Third Modification of the Embodiment) A periodic signal F in a system 100k OUT The circuit for generating may be provided in a sensor interface circuit 1k, as shown in Fig. 9. Fig. 9 is a block diagram showing the configuration of a system 100k including a sensor interface circuit 1k according to a third modified example of the embodiment.

[0112] The system 100k has a sensor interface circuit 1k and a controller 3k instead of the sensor interface circuit 1 and the controller 3 (see FIG. 1). The controller 3k does not have the periodic signal generating circuit 5 (see FIG. 1). Accordingly, a periodic signal F is generated between the controller 3k and the sensor interface circuit 1k. REF In addition, the internal configuration of the controller 3k can be simplified.

[0113] As shown in FIG. 10, the sensor interface circuit 1k further includes an oscillator circuit 21k. The oscillator circuit 21k is electrically connected to a frequency divider circuit 19. FIG. 10 is a block diagram showing a schematic configuration of a sensor interface circuit 1k according to a third modified example of the embodiment. The output node 21a of the oscillator circuit 21k is connected to the input node 19a of the frequency divider circuit 19. The oscillator circuit 21k may be configured similarly to the voltage-controlled oscillator circuit 11 (see FIG. 13). In this case, the oscillator circuit 21k is supplied with, for example, a bias voltage Vb of a fixed level, and generates a reference frequency F REF A periodic signal F with REF may be generated and supplied to the frequency divider circuit 19.

[0114] Thus, the periodic signal F OUT By providing a circuit for generating this signal in the sensor interface circuit 1k, the number of lines between the controller 3k and the sensor interface circuit 1k can be reduced, and the configuration within the controller 3k can be simplified. Therefore, the cost of the system 100k can be reduced.

[0115] (Fourth Modification of the Embodiment) The digital value CNTout in the system 100n may be generated within the sensor interface circuit 1n, as shown in Fig. 11. Fig. 11 is a block diagram showing the configuration of the system 100n including the sensor interface circuit 1n according to a fourth modified example of the embodiment.

[0116] The system 100n has a sensor interface circuit 1n and a controller 3n instead of the sensor interface circuit 1k and the controller 3k (see FIG. 9). The counter 6 (see FIG. 9) is omitted from the controller 3n. Accordingly, the configuration within the controller 3n can be further simplified. When the digital value CNTout has multiple bits, the sensor interface circuit 1n and the controller 3n are connected by a bus with a multiple-bit width.

[0117] As shown in FIG. 12, the sensor interface circuit 1n uses a reference frequency F REF an oscillator circuit 21k that generates a periodic signal of frequency F OUT The frequency synchronization circuit 10n that generates an oscillation signal of the frequency F is connected to the counter 24n via the logic gate 23n. OUT and the reference frequency F REF The sensor interface circuit 1n is configured to change in accordance with the relative ratio of the digital value CNTout to the reference frequency F REF The variable is configured to change independently of the variable.

[0118] For example, a sensor interface circuit 1n shown in Fig. 12 further includes a frequency divider circuit 22n, a logic gate 23n, and a counter 24n in addition to the sensor interface circuit 1k (see Fig. 10). Fig. 12 is a circuit diagram showing a schematic configuration of a sensor interface circuit 1n according to a fourth modification of the embodiment. Note that the periodic signal F generated by the oscillation circuit 21k REF If the duty ratio is close to 50%, the frequency divider circuit 19 may be omitted. In Fig. 12, a configuration in which the frequency divider circuit 19 is omitted is illustrated.

[0119] The frequency divider circuit 22n is electrically connected between the oscillator circuit 21k and the logic gate 23n. The input node 22a of the frequency divider circuit 22n is connected to the output node 21a of the oscillator circuit 21k, and the output node 22b is connected to the input node 23b of the logic gate 23n. The frequency division ratio of the frequency divider circuit 22n may be variable.

[0120] As shown in Fig. 13, the frequency divider circuit 22n has a frequency division ratio N, where N is, for example, an arbitrary integer equal to or greater than 2. Fig. 13 is a circuit diagram showing a detailed configuration of a sensor interface circuit In according to a fourth modified example of the embodiment. For simplification, the LPF 27 and the RF switch 26 are not shown in Fig. 13.

[0121] The division ratio N may be a fixed value or may be variable. When the division ratio N is variable, the sensor interface circuit 1n determines the division ratio in response to a control signal from the outside (for example, the controller 3) and supplies a division control signal indicating the determined division ratio to the divider circuit 22n. The divider circuit 22n can change the value of the division ratio N in response to the division control signal.

[0122] For example, although not shown, a configuration in which the division ratio is variable can be realized by connecting flip-flops in series in multiple stages and connecting the circuit so that the number of flip-flops that are passed between the input node 22a and the output node 22b is changed according to the division control signal.

[0123] The frequency divider circuit 22n divides the periodic signal F generated by the oscillator circuit 21k. REF is divided by N to generate the divided signal F REF The frequency divider circuit 22n generates the frequency-divided signal F REF ' is fed to the logic gate. REF 'Frequency F REF ' is the periodic signal F REF The reference frequency F REF Using this, it can be expressed as the following Equation 25. F REF '=F REF / N···Formula 25

[0124] The oscillator circuit 21k may be configured as a relaxation oscillator circuit as shown in FIG. 13. The oscillator circuit 21k includes an inverter chain 211, a variable resistor 212, and a capacitor 213. The inverter chain 211 includes multiple inverters Inv11 to Inv13 connected in a ring shape and an inverter Inv14 provided on the output side outside the ring. Each inverter Inv is configured by inverter-connecting, for example, an NMOS transistor and a PMOS transistor. The number of inverters Inv connected in a ring shape is an odd number, for example, three. The output node of the inverter Inv11 in the first stage is electrically connected to the input node of the inverter Inv12 in the next stage. The output node of the inverter Inv13 in the last stage is electrically connected to the input node of the inverter Inv14 and the input node of the inverter Inv11 in the first stage, respectively. The output node of the inverter Inv14 is connected to the output node 21a of the oscillator circuit 21k. The variable resistance element 212 is electrically connected in series to the inverters Inv11 to Inv13 in multiple stages in the inverter chain 211. The variable resistance element 212 is electrically connected between the output node of the inverter Inv12 and the input node of the inverter Inv13. The capacitance element 213 is connected in parallel to the inverter Inv and the resistance element 212 in the inverter chain 211. Fig. 13 illustrates a configuration in which the capacitance element 213 is connected in parallel to the series connection of the second-stage inverter Inv12 and the variable resistance element 212.

[0125] As illustrated in FIG. 13, the variable resistance element 212 may be configured as an NMOS transistor having a drain connected to the output node of the inverter Inv12, a source connected to the input node of the inverter Inv13, and a gate to which, for example, a fixed level bias voltage Vb is applied.

[0126] 12 is electrically connected between the frequency synchronization circuit 10n, the oscillator circuit 21k, and the counter 24n. The logic gate 23n has an input node 23a connected to the frequency synchronization circuit 10n via the RF switch 26 and the LPF 27, an input node 23b connected to the oscillator circuit 21k via the frequency divider circuit 22n, and an output node 23c connected to the input node 24a of the counter 24n. The output node 24b of the counter 24n is connected to the terminal 1c of the sensor interface circuit 1n.

[0127] The logic gate 23n may be an AND gate 231 as shown in FIG. OUT is received at the input node 23a, and the frequency-divided signal F REF ' is received at the input node 23a, and the oscillation signal F OUT and frequency division signal F REF The counter 24n counts the number of pulses in the calculation result and outputs the count value as a digital value CNTout from the terminal 1c to the controller 3n.

[0128] In the sensor interface circuit 1n, the reference frequency F REF The voltage V converted from the first analog signal (the signal from sensor 2) SENS2 and the voltage V converted from the second analog signal (Sense 2i signal) SENS11 The oscillation signal F generated by the frequency locked loop is OUT , the reference frequency F REF or divided F REF The digital value CNTout can be obtained by counting while thinning out the counts by '. That is, the configuration of the sensor interface circuit 1n makes it possible to realize an AD conversion circuit of a novel type.

[0129] That is, the logic gate 23n receives the oscillation signal F from the frequency synchronization circuit 10n. OUT Divide the signal F REFTherefore, the digital value CNTout as the count value of the counter 24n is formally a frequency F OUT and the reference frequency F REF Since it changes depending on the relative ratio to ', it can be expressed as the following equation 26. CNT OUT =F OUT / {F REF ' / 2}···Formula 26

[0130] Substituting Equation 25 into Equation 26, we obtain the following Equation 27. CNT OUT =F OUT / {F REF / (2·N)}···Equation 27

[0131] Formula 27 in Formula 24 REF 2F REF Substituting the replaced equation into, we obtain the following Equation 28. CNT OUT ={F REF ·(C SENS / C SC2 )·(R SENS / R2)} / {F REF / (2·N)} =(C SENS / C SC2 )·(R SENS / R2)·2·N···Equation 28

[0132] On the right side of Equation 28, F is used in the numerator and denominator. REF Because of this, F REF As shown in Equation 28, the digital value CNTout is REF The relative ratio (C SENS / C SC2 )·(R SENS / R2), that is, the accuracy of the frequency of the oscillation signal changes substantially depending on the periodic signal F REF It does not depend on the absolute accuracy of the capacitance value C SENS and capacitance value C SC2 Relative accuracy and resistance value R SENSFor example, the capacitance elements 181 and 131 may fluctuate in almost the same way due to the influence of fluctuation factors such as the manufacturing process, the power supply voltage, and / or the temperature, and the capacitance of the variable resistance element R SENS If the resistance element R1 and the resistance element R2 fluctuate in almost the same way, the relative ratio (C SC1 / C SC2 )·(R SENS / R2) will hardly fluctuate.

[0133] Furthermore, as shown in Equation 28, by increasing the division ratio N of the frequency divider circuit 22n, the gain of the digital value CNTout relative to the signal level of the sensor 2, 2i can be increased, thereby easily increasing the sensitivity of the sensor interface circuit 1n to the signal of the sensor 2, 2i.

[0134] In this way, the sensor interface circuit 1n receives the oscillation signal F OUT The frequency F OUT is the reference frequency F REF This allows the reference frequency F REF Since the influence of the variations in the frequency can be suppressed, the accuracy of converting the signal levels of the sensors 2 and 2i into frequencies can be easily improved.

[0135] The sensor interface circuit 1n also receives the oscillation signal F OUT The frequency F OUT is obtained according to the ratio between the characteristics of the sensor 2 and the characteristics of an element (capacitor element 131) in the sensor interface circuit 1n, and the ratio between the characteristics of the sensor 2i and the characteristics of an element (resistance element R2) in the sensor interface circuit 1n. As a result, by using sensors 2 and 2i and elements in the sensor interface circuit 1n that exhibit approximately the same fluctuations in response to changes in fluctuation factors, fluctuations in the frequency of the oscillation signal that occur in response to changes in the fluctuation factors can be suppressed. In other words, since the influence of the fluctuation factors can be suppressed, the accuracy of converting the signal level of the sensor 2 and 2i into frequency can be easily improved.

[0136] For example, as a result of simulating the digital value CNTout in response to changes in the fluctuation factors, it was confirmed that approximately the same digital value CNTout was obtained, as shown in Fig. 14. Fig. 14 is a diagram showing the simulation results of the sensor interface circuit In according to the fourth modification of the embodiment, which is assumed to be integrated using a 0.13 µm CMOS process.

[0137] As shown in FIG. 14(a), the division ratio N=N1, and (R SENS 14(b), when R2)=1, it is shown that for Conditions 1 to 9 in which at least one of the manufacturing process and the power supply voltage is changed, even if the temperature is changed to three types (50°C, 25°C, and 125°C), almost the same digital value CNTout is obtained as a count value. Conditions 1 to 9 can be, for example, the following conditions. Condition 1: "Process conditions that lower the transistor threshold voltage" + "Power supply voltage Vdd = V 11 " Condition 2: "Process conditions that lower the transistor threshold voltage" + "Power supply voltage Vdd = V 12 (>V 11 )" Condition 3: "Process conditions that lower the transistor threshold voltage" + "Power supply voltage Vdd = V 13 (>V 12 )" Condition 4: "Process conditions under which the transistor threshold voltage becomes the standard value" + "Power supply voltage Vdd = V 11 " Condition 5: "Process conditions under which the transistor threshold voltage becomes the standard value" + "Power supply voltage Vdd = V 12 " Condition 6: "Process conditions under which the transistor threshold voltage becomes the standard value" + "Power supply voltage Vdd = V 13 " Condition 7: "Process conditions that increase the transistor threshold voltage" + "Power supply voltage Vdd = V 11 " Condition 8: "Process conditions that increase the threshold voltage of the transistor" + "Power supply voltage Vdd = V 12 " Condition 9: "Process conditions that increase the transistor threshold voltage" + "Power supply voltage Vdd = V 13 "

[0138] As shown in FIG. 14(a), the division ratio N=N1, and (R SENS When R2) = 1.5, as shown in Figure 14(c), for conditions 1 to 9 in which at least one of the manufacturing process and the power supply voltage is changed, even if the temperature is changed to three types (50°C, 25°C, and 125°C), the digital value CNTout as a count value is obtained which is approximately the same.

[0139] As shown in FIG. 14(d), the division ratio N=N2 (>N1), and (R SENS When R2) = 1, as shown in Figure 14(e), for conditions 1 to 9 in which at least one of the manufacturing process and the power supply voltage is changed, even if the temperature is changed to three types (50°C, 25°C, and 125°C), the digital value CNTout as a count value is obtained which is approximately the same.

[0140] As shown in FIG. 14(d), the division ratio N=N2, and (R SENS When R2) = 1.5, as shown in Figure 14(f), for conditions 1 to 9 in which at least one of the manufacturing process and the power supply voltage is changed, even if the temperature is changed to three types (50°C, 25°C, and 125°C), the digital value CNTout as a count value is obtained which is approximately the same.

[0141] Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments described above can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0142] 1,1i,1j,1k,1n Sensor interface circuit 2,2i sensor 3,3n controller 10, 10i, 10j, 10n frequency synchronization circuit 12 frequency divider circuit 13 Frequency-impedance conversion circuit 14,14i Voltage Source 15 Current source 16 Voltage difference detection circuit 17 Filters 18,18i Frequency Impedance Conversion Circuit 19 Frequency divider circuit 21k oscillator circuit 22n frequency divider circuit 23n logic gates 24n Counter 26 RF Switch 27 LPF 100, 100i, 100j, 100k, 100n systems

Claims

1. a frequency synchronization circuit connectable to the sensor; The frequency synchronization circuit a voltage source for generating a voltage; a first frequency-impedance conversion circuit that converts a reference frequency into a first impedance; a current source connected to the voltage source and the first frequency-impedance conversion circuit, the current source generating a current using the generated voltage and the first impedance; a voltage difference detection circuit having a first input node connected to the voltage source, a second input node connected to the current source, and an output node, wherein at least one of a voltage received at the first input node and a second voltage received at the second input node corresponds to a signal level of the sensor, and which generates a control voltage according to a difference between the voltage received at the first input node and the voltage received at the second input node; a voltage controlled oscillation circuit connected to an output node of the voltage difference detection circuit and generating an oscillation signal in response to the control voltage; a second frequency-impedance conversion circuit connected between the voltage-controlled oscillation circuit and a second input node of the voltage difference detection circuit, for converting a frequency of a signal corresponding to the oscillation signal into a second impedance; have Sensor interface circuit.

2. the first frequency-impedance conversion circuit is connected to the sensor and converts the reference frequency into the first impedance in accordance with a signal level of the sensor; The voltage difference detection circuit detects a voltage received at the second input node corresponding to the signal level of the sensor and the frequency of the signal. The sensor interface circuit of claim 1 .

3. the voltage source is connected to the sensor and generates a voltage according to a signal level of the sensor; The voltage difference detection circuit detects a voltage received at the first input node corresponding to the signal level of the sensor and the reference frequency. The sensor interface circuit of claim 1 .

4. The first frequency impedance conversion circuit and the second frequency impedance conversion circuit are respectively configured by switched capacitor circuits corresponding to each other. The sensor interface circuit of claim 1 .

5. The second frequency-impedance conversion circuit includes: a first capacitance element having one end connected to a first potential; a second capacitance element having one end connected to the first potential and the other end connected to a second input node of the voltage difference detection circuit; a first switch having one end connected to the second input node of the voltage difference detection circuit, the other end connected to the other end of the first capacitance element, and a control end connected to the voltage controlled oscillation circuit; a first inverter connected to the voltage controlled oscillator circuit; a second switch having one end connected to the other end of the first capacitive element, the other end connected to the first potential, and a control end connected to the first inverter; and The first frequency-impedance conversion circuit includes: a third capacitance element having one end connected to the first potential and the other end connected to the current source; a third switch having one end connected to the current source and the other end connected to the sensor, the third switch receiving the reference frequency at a control end; a second inverter to which the reference frequency is input; a fourth switch having one end connected to the sensor, the other end connected to the first potential, and a control end connected to the second inverter; have 3. The sensor interface circuit of claim 2.

6. The second frequency-impedance conversion circuit includes: a first capacitance element having one end connected to a first potential; a second capacitance element having one end connected to the first potential and the other end connected to a second input node of the voltage difference detection circuit; a first switch having one end connected to the second input node of the voltage difference detection circuit, the other end connected to the other end of the first capacitance element, and a control end connected to the voltage controlled oscillation circuit; a first inverter connected to the voltage controlled oscillator circuit; a second switch having one end connected to the other end of the first capacitive element, the other end connected to the first potential, and a control end connected to the first inverter; and The first frequency-impedance conversion circuit includes: a third capacitance element having one end connected to the first potential and the other end connected to the current source; a fourth capacitance element having one end connected to the first potential; a third switch having one end connected to the current source and the other end connected to the other end of the fourth capacitive element, and having a control end receiving the reference frequency; a second inverter to which the reference frequency is input; a fourth switch having one end connected to the other end of the fourth capacitive element, the other end connected to the first potential, and a control end connected to the second inverter; have 4. The sensor interface circuit of claim 3.

7. The voltage source is a first resistor element connected in series to the sensor on the side of the reference potential between a power supply potential and a reference potential; a second resistor element connected in series to the sensor on the side of the power supply potential between the power supply potential and a reference potential; and a node between the sensor and the first resistive element is electrically connected to a first input node of the voltage difference detection circuit; A node between the sensor and the second resistive element is electrically connected to the current source.

4. The sensor interface circuit of claim 3.

8. a frequency divider circuit connected to the first frequency-impedance conversion circuit; a logic gate having a first input node connected to the voltage controlled oscillator circuit, a second input node connected to the frequency divider circuit, and an output node; a counter connected to an output node of the logic gate; Further equipped The sensor interface circuit of claim 1 .

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