Server and its server management system

Abstract

This application discloses a server and its server management system, which belongs to the server field and is used for managing the server. The server management system can support the startup of two CPUs, receive PCIe signals sent from the two CPUs to display an operating system interface, and send the received keyboard and mouse commands to the CPU whose gating switch (3) is currently on via the USB controller (2), thereby realizing the application of a keyboard and mouse. When the USB controller (2) converts between USB signals and PCIe signals, the first USB interface (4) can realize communication with the CPU whose gating switch (3) is currently on. Obviously, this system can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

Description

[Technical Field]

[0001] This application relates to the field of servers, and more particularly to server management systems and servers.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to a Chinese patent application filed with the China Patent Office on April 29, 2022, bearing application number 202210466930.0 and entitled "Server and Server Management System Thereof," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Traditionally, server management units have been included on server motherboards, but the advantages of modularizing and separating them from the server motherboard have become apparent. As server CPU technology continues to evolve, server applications will continue to evolve. In the future, the south bridge of the CPU (Central Processing Unit) will be integrated with the CPU, low-speed interfaces such as USB (Universal Serial Bus) will be eliminated, and CPU partitioning applications will allow two-way CPUs to run operating systems independently. For these new CPU designs, existing technology lacks a mature server management system. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present application is to provide a server management system, which is applicable to future solutions in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability. Another object of the present application is to provide a server including the server management system, which is applicable to future solutions in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability. [Means for solving the problem]

[0005] In order to solve the above technical problems, the present application provides a server management system, which includes: a board management control device that receives a PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) signal transmitted from the CPU via the gating switch, transmits a keyboard / mouse command received via the first USB interface to the CPU whose gating switch is currently turned on, and assists in starting up the CPU whose gating switch is currently turned on; a USB controller connected to the board management control device, the USB controller converting between a USB signal and a PCIe signal to realize communication between the CPU whose gating switch is currently on and the first USB interface; a gating switch connected to each of two CPUs of the server, the board management control device, and the USB controller, the gating switch turning on one set of PCIe signals in a designated CPU of the two CPUs to the board management control device, and turning on the other set of PCIe signals to the USB controller; a first USB interface connected to the board management control device and the USB controller, respectively;

[0006] In some embodiments, the substrate management controller comprises: a BMC (Baseboard Management Controller) connected to an ESPI (Enhanced Serial Peripheral Interface) interface of one of the CPUs, the BMC receiving a PCIe signal sent from the CPU via a gating switch, sending keyboard / mouse commands received via a first USB interface to the CPU whose gating switch is currently on, and receiving boot information sent from the one of the CPUs via its own ESPI interface; a control module connected to the BMC, the ESPI interface of the other CPU, and the gating switch, respectively, for processing boot information sent by the other CPU via the ESPI interface using a preset program, and for controlling the state of the gating switch; and a root of trust security management device connected to the two CPUs and the BMC, the root of trust security management device providing an authenticated boot program to the CPUs and the BMC at the power-on stage of the server.

[0007] In some embodiments, the control module is further connected to a Low Voltage Differential Signaling (LVDS) interface of the motherboard; The control module is further configured to decouple an LVDS signal, which is formed by combining a plurality of designated types of low-speed signals transmitted from the motherboard, and then transmit the decoupled LVDS signal to the BMC, and to combine a plurality of designated types of low-speed signals transmitted from the BMC as an LVDS signal and then transmit the LVDS signal to the motherboard.

[0008] In some embodiments, the server management system: a protocol conversion device connected to a UART (Universal Asynchronous Receiver / Transmitter) interface of the BMC, the protocol conversion device converting between a USB protocol and a UART protocol; a second USB interface connected to the protocol conversion device; The BMC is further configured to output UART signals received from the control module from the UART interface and to transmit UART signals transmitted from the protocol converter to the control module.

[0009] In some embodiments, the control module is further connected to an I3C (Improved Inter Integrated Circuit) interface of the CPU; The control module further comprises: This is to turn on the CPU's I3C signal to the BMC, and the BMC will debug the CPU using the I3C signal.

[0010] In some embodiments, the gating switch comprises: a first alternative PCIe switch, the first end of which is connected to the first PCIe signal channels of the two CPUs respectively and the second end of which is connected to the USB controller, for turning on the first PCIe signal of one way of the first PCIe switch to the USB controller under the control of the control module; a second alternative PCIe switch, the first end of which is connected to the second PCIe signal channels of the two CPUs respectively and the second end of which is connected to the BMC, for turning on the second PCIe signal of one way of the second PCIe switch to the BMC under the control of the control module; and a two-way logic switch having a first end connected to the clock signals of the two CPUs, respectively, and a second end connected to the USB controller and the BMC, the two-way logic switch for transmitting the clock signals of the two CPUs to the USB controller and the BMC, respectively.

[0011] In some embodiments, the server management system further includes a third USB interface connected to the USB controller; The USB controller is for converting between USB signals and PCIe signals so as to realize communication between the CPU whose gating switch is currently on and the first USB interface and the third USB interface, respectively.

[0012] In some embodiments, the control module is a Field Programmable Gate Array (FPGA).

[0013] In some embodiments, the root of trust security manager: a Cerberus root of trust security management module connected to each of the two CPUs and the BMC, the Cerberus root of trust security management module providing an authenticated boot program to the CPUs and the BMCs at the power-on stage of the server; a first CPU Flash for storing a boot program for one of the CPUs; a second CPU Flash for storing a boot program for the other CPU; and BMC Flash for storing the BMC boot program.

[0014] To solve the above technical problems, the present application further provides a server including the above server management system.

[0015] The present application provides a server management system, which can support the startup of two CPUs, receive PCIe signals sent from the two CPUs, and display an operating system interface. The received keyboard / mouse commands can be sent by a USB controller to the CPU whose gating switch is currently on, thereby realizing a keyboard / mouse application. When the USB controller converts between USB signals and PCIe signals, communication with the CPU whose gating switch is currently on can be realized through the first USB interface. Obviously, the present application can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

[0016] The present application further provides a server having the same beneficial effects as the above server management system. [Brief explanation of the drawings]

[0017] In order to more clearly explain the technical solutions of the embodiments of the present application, the drawings necessary for use in the prior art and embodiments will be briefly described. Of course, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can further obtain other drawings based on these drawings without creative work. [Figure 1] 1 is a structural diagram of a server management system according to some embodiments of the present disclosure; [Figure 2] FIG. 1 is a structural schematic diagram of a conventional server management system. [Figure 3] FIG. 2 is a structural diagram of another server management system according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] The gist of this application is to provide a server management system, which is applicable to future solutions in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability. Another gist of this application is to provide a server including the server management system, which is applicable to future solutions in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

[0019] In order to clarify the objectives, technical solutions and advantages of some embodiments of the present application, the technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings, and it is obvious that the described embodiments are not all embodiments but only some of the embodiments of the present application. All other embodiments that can be obtained by those skilled in the art based on the embodiments of the present application without any creative work fall within the protection scope of the present invention.

[0020] Referring to FIG. 1, FIG. 1 is a structural diagram of a server management system according to some embodiments of the present application, and the server management system includes: a board management control device 1 for receiving a PCIe signal transmitted from a CPU via a gating switch 3, transmitting a keyboard / mouse command received via a first USB interface 4 to the CPU whose gating switch 3 is currently on, and supporting the startup of the CPU whose gating switch 3 is currently on; a USB controller 2 connected to the board management control device 1, for converting between a USB signal and a PCIe signal so as to realize communication between a CPU whose gating switch 3 is currently on and a first USB interface 4; a gating switch 3 connected to each of two CPUs of the server, the board management control device 1, and the USB controller 2, for turning on one set of PCIe signals in a designated CPU of the two CPUs to the board management control device 1 and turning on the other set of PCIe signals to the USB controller 2; and a first USB interface 4 connected to the board management control device 1 and the USB controller 2, respectively.

[0021] Referring to Figure 2, Figure 2 is a schematic diagram of the structure of a conventional server management system. A conventional two-way general-purpose server motherboard includes two CPUs, CPU0 and CPU1. CPU0 boots independently and only needs to run the operating system. CPU1 is primarily used for expanding computing power and PCIe resources and does not need to run the operating system; CPU1 is guided by CPU0 to complete booting. The BMC chip participates in the CPU0 boot process. The PCIe bus of CPU0 is connected to the PCIe controller of the BMC chip and used to display the operating system interface. The ESPI bus of the CPU0 south bridge is connected to the BMC chip to transmit CPU0 serial interface information. The USB bus of the CPU0 south bridge is connected to the BMC chip to realize keyboard and mouse applications. The BMC's UART interface has an external serial interface COM connector to output serial interface information. The BMC is connected to the FPGA via a serial general-purpose input / output (SGPIO) bus. The FPGA in this module is interconnected with the motherboard's SGPIO bus to realize IO (Input / Output) interface expansion functions. Platform Firmware Resilience (PFR) is a widely used safe boot technology, primarily implemented using FPGAs. During the initial power-on phase, the PFR FPGA checks memory units such as the CPU flash and BMC flash to determine whether the system is ready to boot. In traditional approaches, CPU0, CPU1, and the BMC chip all need to be connected to the flash, requiring a large number of binary 1-input (2-in 1-out) logic switches for gating. The introduction of multiple logic switches in current PFR solutions significantly increases link branching, posing risks to signal integrity. The PFR test logic program is lengthy and difficult to develop, and production burst cutting takes time, significantly reducing production efficiency.

[0022] Current CPU products are rapidly updating, and in the future, the CPU south bridge and CPU will be integrated, eliminating low-speed interfaces such as USB, making the traditional USB scheme incompatible with next-generation CPUs. With the increasing demand for low-energy consumption applications in data centers, the concept of CPU partitioning applications has been proposed, but traditional server management solutions do not support CPU partitioning applications. CPU partitioning applications allow two CPUs to run independently, and have the following features: 1. Meet the multi-system needs of users. 2. Realize 1+1 backup of operating systems. When one system fails, the system can quickly switch to the other system. 3. Improve resource utilization. If the user's single system configuration is not high, the original two-way server will run a single system, resulting in a waste of CPU1.

[0023] PFR technology is primarily based on logic, which results in redundant logic and a high risk to signal integrity in the PFR circuit. These characteristics significantly increase the difficulty of development, production, and maintenance. Traditional servers can only remotely debug the CPU via a COM (cluster communication port) or BMC.

[0024] Considering the technical issues in the background art as described above, in order to accommodate new CPU designs (by integrating the CPU south bridge and the CPU, low-speed interfaces such as USB are eliminated, and in CPU partitioning applications, the two-way CPUs can run operating systems independently), the next-generation CPU will no longer have a USB interface, and the two CPUs (CPU0, CPU1) of the server will each have a two-way PCIe bus connected to a new server management system, and the gating switch 3 will collectively control the four-way PCIe bus channels of the two-way CPUs, and the gating switch 3 can turn on the two-way PCIe bus of the currently operating CPU to the board management control device 1 and the USB controller, respectively, for example: When the CPU0 is operating, the gating switch 3 can turn on and control the two-way PCIe bus of the CPU0 to the board management control device 1 and the USB, where the CPU can send PCIe signals via the PCIe bus connected to the board management control device 1, for example, can send correlation data of the operating system interface so that the board management control device 1 performs display control of the operating system interface, and the USB controller 2 to which the first USB interface 4 is connected can convert between USB signals and PCIe signals, so that the first USB interface 4 can realize USB communication with the CPU whose gating switch 3 is currently on via the USB controller 2.

[0025] Here, in order to realize the keyboard mouse function of the server, the signal of the keyboard mouse device can be sent to the board management control device 1 via the first USB interface 4, and the board management control device 1 can process the keyboard mouse command and then send it to the CPU whose gating switch 3 is currently on via the USB controller 2 and the gating switch 3 so as to realize the keyboard mouse application.

[0026] In some embodiments, the substrate management control device 1 can also assist in booting the CPU whose gating switch 3 is currently on, including providing an authenticated boot program to the CPU during the server boot phase and receiving boot information sent from the CPU.

[0027] Due to the presence of the gating switch 3, the server management system in some embodiments of the present invention can also support conventional CPUs, and has high compatibility and versatility.

[0028] In some embodiments of the present application, a server management system is provided, which can support the startup of two CPUs, receive PCIe signals sent from the two CPUs and display an operating system interface, and can send the received keyboard / mouse commands via a USB controller to the CPU whose gating switch is currently on, thereby realizing a keyboard / mouse application. When the USB controller converts between USB signals and PCIe signals, communication with the CPU whose gating switch is currently on can be realized via a first USB interface. This can be applied to a future solution in which the CPU is partitioned and the USB interface is removed, and has a simple structure and strong stability.

[0029] To better explain the embodiments of the present application, please refer to Figure 3. Figure 3 is a structural diagram of another server management system according to some embodiments of the present application, which in addition to the above embodiments, In some embodiments, the substrate management controller 1 includes: a board management controller BMC connected to the ESPI interface of one of the CPUs, the board management controller BMC receiving a PCIe signal sent from the CPU via a gating switch 3, sending a keyboard / mouse command received via a first USB interface 4 to the CPU whose gating switch 3 is currently on, and receiving boot information sent from the one of the CPUs via its own ESPI interface; a control module connected to the BMC, the ESPI interface of the other CPU, and the gating switch 3, the control module using a preset program to process boot information sent by the other CPU via the ESPI interface and to control the state of the gating switch 3; and a root of trust security management device connected to the two CPUs and the BMC, the root of trust security management device providing an authenticated boot program to the CPUs and the BMC at the power-on stage of the server.

[0030] The configuration of the BMC, control module and root of trust security management module has advantages such as simple structure, low cost and high stability.

[0031] Of course, in addition to the above configuration, the board management control device 1 may have other configurations.

[0032] Considering the traditional two-way server, CPU0 transmits UART information to BMC via ESPI bus and outputs it via BMC's COM interface. ESPI bus is fast and UART bus is slow. ESPI transmits UART information, which greatly reduces the utilization rate of ESPI bus. After the new server management system is improved to support CPU partitioning application, ESPI mainly carries CPU boot information, improving CPU boot efficiency. Since BMC chips only support one ESPI interface, in this application, the ESPI of one CPU (CPU0) can be connected to the ESPI interface of BMC to participate in CPU0 boot, and the ESPI of CPU1 can be connected to the control module to allow the control module to participate in CPU1's independent boot.

[0033] The control module can also control the state of the gating switch 3, and can control the state of the gating switch 3 according to instructions sent from the BMC.

[0034] In some embodiments, the control module is further connected to an LVDS interface of the motherboard; The control module is further configured to decouple an LVDS (Low-Voltage Differential Signaling) signal, which is formed by combining a plurality of designated types of low-speed signals transmitted from the motherboard, and then transmit the decoupled signal to the BMC, and to combine a plurality of designated types of low-speed signals transmitted from the BMC as an LVDS signal and then transmit the LVDS signal to the motherboard.

[0035] The introduction of the PCIe bus and ESPI bus on the CPU inevitably puts strain on the BMC and motherboard interface. Some low-speed signals interconnecting the BMC and motherboard, such as I2C, UART, and GPIO signals, are logically coupled to the LVDS bus for transmission and can then be decoupled by the control module on the motherboard. This allows the LVDS bus to complete the information interaction between the BMC module and the motherboard, thereby increasing the signal transmission speed and reducing the number of BMC-motherboard interface signals.

[0036] In some embodiments, the server management system: a protocol conversion device connected to a UART interface of the BMC for converting between a USB protocol and a UART protocol; a second USB interface connected to the protocol conversion device; The BMC is further configured to output UART signals received from the control module from the UART interface and to transmit UART signals transmitted from the protocol converter to the control module.

[0037] In some embodiments of the server management system of the present application, the UART signal logically decoupled from the control module is output through the UART interface of the BMC and connected to a second USB interface via a protocol conversion device (UART-USB chip, USB UART BRIDGE in FIG. 3 ), so as to realize communication with the UART signal on the motherboard via the second USB interface.

[0038] In some embodiments, the control module is further connected to an I3C interface of the CPU; The control module further comprises: This is to turn on the CPU's I3C signal to the BMC, and the BMC will debug the CPU using the I3C signal.

[0039] In order to enable the BMC to debug the CPU through the I3C signal, the control module is further connected to the I3C interface of the CPU, and the control module turns on the I3C signal of the CPU to the BMC so that the BMC can debug the CPU through the I3C signal.

[0040] In addition, the I3C signal of the CPU can also be directly connected to the second USB interface (in this case, the second USB interface can be a TYPEC connector), allowing the serial interface information to be debugged through the TYPEC interface, and the CPU to be debugged via I3C, improving test efficiency.

[0041] In some embodiments, the gating switch 3 is a first alternative PCIe switch, the first ends of which are respectively connected to the first PCIe signal channels of the two CPUs and the second ends of which are connected to the USB controller 2, for turning on the first PCIe signal of one of the first two-way PCIe switches to the USB controller 2 under the control of the control module; a second alternative PCIe switch, the first end of which is connected to the second PCIe signal channels of the two CPUs respectively and the second end of which is connected to the BMC, for turning on the second PCIe signal of one way of the second PCIe switch to the BMC under the control of the control module; and a two-way logic switch having a first end connected to the clock signals of the two CPUs, respectively, and a second end connected to the USB controller 2 and the BMC, respectively, for transmitting the clock signals of the two CPUs to the USB controller 2 and the BMC, respectively.

[0042] The gating switch 3 in some embodiments of the present invention includes two one-way PCIe switches and one one-way logic switch, and has a simple structure and low cost.

[0043] Of course, the gating switch 3 may have other structures.

[0044] In some embodiments, the server management system further includes a third USB interface connected to the USB controller 2; The USB controller 2 is for converting between USB signals and PCIe signals so as to realize communication between the CPU whose gating switch 3 is currently on and the first USB interface 4 and the third USB interface, respectively.

[0045] In addition to keyboards and mice, servers may have the need to connect more USB devices, so multiple USB interfaces can be provided. To improve user experience, the first USB interface 4 may be a USB 2.0 interface, and the third USB interface may be a USB 3.0 or higher protocol interface.

[0046] In some embodiments, the control module is an FPGA.

[0047] FPGAs have the advantages of small volume, high performance, and low cost.

[0048] Of course, in addition to FPGAs, the control modules may be of other types.

[0049] In some embodiments, the root of trust security manager: a Cerberus root of trust security management module connected to each of the two CPUs and the BMC, the Cerberus root of trust security management module providing an authenticated boot program to the CPUs and the BMCs at the power-on stage of the server; a first CPU Flash for storing a boot program for one of the CPUs; a second CPU Flash for storing a boot program for the other CPU; and BMC Flash for storing the BMC boot program.

[0050] Cerberus is a root of trust security management module based on ARM processing, which provides multiple SPI interfaces to the outside world and can complete chip testing and recovery for CPU, BMC, etc. while the server is powered on. The Cerberus solution avoids the stuck logic switches in the PFR solution, reducing the difficulty of PCB design and also significantly reducing the difficulty of logic development, improving production efficiency.

[0051] Of course, in addition to the above structures, the root of trust security manager may be of other types.

[0052] Some embodiments of the present application further provide a server including the server management system of the above embodiments.

[0053] For a description of the server according to some embodiments of the present application, please refer to the above embodiments of the server management system.

[0054] Each embodiment in this specification is described in a progressive manner, with the emphasis on differences between the other embodiments. References to similar or identical parts between the embodiments may be made. Note that, in this specification, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," and other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or device that includes a set of elements not only includes those elements, but also other elements not explicitly listed, or elements inherent in the process, method, article, or device. Absent further limitations, an element defined by the phrase "comprising ..." does not exclude the presence of other identical elements within a process, method, article, or device that includes that element.

[0055] The above description of the disclosed embodiments will enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. a board management control device for receiving a high-speed serial computer expansion bus standard PCIe signal transmitted from a central processor CPU by a gating switch, and transmitting a keyboard / mouse command received via a first USB interface to the CPU whose gating switch is currently turned on, thereby assisting in the startup of the CPU whose gating switch is currently turned on; a Universal Serial Bus (USB) controller connected to the board management control device, the Universal Serial Bus (USB) controller converting between a USB signal and a PCIe signal to realize communication between a CPU whose gating switch is currently turned on and a first USB interface; the gating switches are respectively connected to two CPUs of the server, the board management control device, and the USB controller, and the gating switches turn on one set of PCIe signals in a designated CPU of the two CPUs to the board management control device, and turn on the other set of PCIe signals in the designated CPU to the USB controller; the first USB interface connected to the board management control device and the USB controller, respectively.

2. The substrate management control device a board management controller BMC connected to an extended serial peripheral interface (ESP) interface of one of the CPUs, the board management controller BMC receiving a PCIe signal transmitted from the CPU via a gating switch, transmitting a keyboard / mouse command received via a first USB interface to the CPU whose gating switch is currently turned on, and receiving boot information transmitted from the one of the CPUs via its own ESPI interface; a control module connected to the BMC, the ESPI interface of the other CPU, and the gating switch, the control module using a preset program to process boot information sent by the other CPU via the ESPI interface and to control the state of the gating switch; 2. The server management system of claim 1, further comprising: a root of trust security management device connected to two CPUs and the BMC, the root of trust security management device providing an authenticated boot program to the CPUs and the BMC when the server is powered on.

3. The control module is further connected to a low voltage differential signal LVDS interface of a motherboard; 3. The server management system of claim 2, wherein the control module is further configured to decouple an LVDS signal, which is a combination of multiple specified types of low-speed signals transmitted from the motherboard, and then transmit the decoupled LVDS signal to the BMC, and to combine multiple specified types of low-speed signals transmitted from the BMC as an LVDS signal and then transmit the LVDS signal to the motherboard.

4. a protocol conversion device connected to a universal asynchronous receiver-transmitter (UART) interface of the BMC, the protocol conversion device being for converting between a USB protocol and a UART protocol; a second USB interface connected to the protocol conversion device; 4. The server management system according to claim 3, wherein the BMC is further configured to output a UART signal received from the control module from the UART interface and to transmit a UART signal transmitted from the protocol conversion device to the control module.

5. The control module is further connected to an I3C interface of the CPU; The control module further comprises:

5. The server management system according to claim 4, wherein the improved internal integrated circuit of the CPU is configured to send an I3C signal to the BMC, so that the BMC can debug the CPU through the I3C signal.

6. The gating switch is a first alternative PCIe switch, the first end of which is connected to first PCIe signal channels of two CPUs respectively and the second end of which is connected to the USB controller, for turning on a first PCIe signal of one way of the first PCIe switch to the USB controller under the control of the control module; a second alternative PCIe switch, the first end of which is connected to the second PCIe signal channels of the two CPUs, respectively, and the second end of which is connected to the BMC, the second alternative PCIe switch being for turning on one-way second PCIe signals of the second alternative PCIe switch to the BMC under the control of the control module; 3. The server management system of claim 2, further comprising: a two-way logic switch having a first end connected to the clock signals of two CPUs, respectively, and a second end connected to the USB controller and the BMC, respectively, for transmitting the clock signals of the two CPUs to the USB controller and the BMC, respectively.

7. a third USB interface connected to the USB controller; 3. The server management system according to claim 2, wherein the USB controller is configured to convert between USB signals and PCIe signals so as to realize communication between the CPU whose gating switch is currently on and the first USB interface and the third USB interface, respectively.

8. 4. The server management system according to claim 3, wherein the control module is a field programmable gate array FPGA.

9. The root of trust security management device a Cerberus root of trust security management module connected to two CPUs and the BMC, respectively, for providing an authenticated boot program to the CPUs and the BMC at a power-on stage of a server; a first CPU Flash for storing a boot program for one of the CPUs; a second CPU Flash for storing a boot program for the other CPU; 3. The server management system according to claim 2, further comprising a BMC Flash for storing a boot program for the BMC.

10. 2. The server management system according to claim 1, wherein the gating switch is for turning on a two-way PCIe bus of a currently operating CPU to the board management control device and the USB controller, respectively.

11. The server management system of claim 1 , wherein the board management control device provides an authenticated startup program to a CPU in a server startup step.

12. The server management system according to claim 2 , wherein the control module is for controlling the state of the gating switch according to a command sent from the BMC.

13. 6. The server management system of claim 5, wherein the control module is further for directly connecting an I3C signal of a CPU to the second USB interface, and the second USB interface is a TYPE C connector.

14. 2. The server management system according to claim 1, wherein the first USB interface is a USB 2.0 protocol interface.

15. 8. The server management system according to claim 7, wherein the third USB interface is USB 3.

0.

16. A server comprising the server management system according to any one of claims 1 to 15.

17. 17. The server according to claim 16, wherein each of the two CPUs of the server is connected to the server management system via a two-way PCIe bus.

18. 17. The server according to claim 16, wherein the channels of the four-way PCIe bus of the two CPUs of the server are collectively controlled by a gating switch in the server management system.

19. The server according to claim 16, wherein a CPU in the server transmits a PCIe signal via a PCIe bus connected to a board management control device in the server management system.

20. 20. The server of claim 19, wherein the PCIe signal includes correlation data of an operating system interface, and the correlation data of the operating system interface is used by the board management control device to control the display of the operating system interface.

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