Test Method

Abstract

To accurately select a semiconductor device.SOLUTION: A method for testing a semiconductor device includes: a first testing step of testing a semiconductor device by bringing at least one probe pin into contact with a pad of a semiconductor device; and a second testing step of testing a semiconductor device by making the position of the probe pin which is in contact with the pad different from that in the first testing step. In the first testing step, the probe pin is in contact with a first position and a second position on a pad. In the second testing step, the probe pin may be in contact with the first position and the second position on the pad.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a method for testing a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, a method for screening semiconductor devices such as transistors is known (see, for example, Patent Document 1). Patent Document 1: Japanese Patent Application Laid-Open No. 2010-276477 Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to be able to screen semiconductor devices with high accuracy. [Means for solving the problem]

[0004] To solve the above problems, one aspect of the present invention provides a method for testing a semiconductor device. The method may include a first test stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device. The test method may also include a second test stage in which the contact positions of the probe pins with respect to the pads are changed from those in the first test stage to test the semiconductor device.

[0005] The first test stage and the second test stage may test the semiconductor device under different conditions.

[0006] The first test stage and the second test stage may test the semiconductor device under the same conditions.

[0007] In a first test stage, the probe pin may be brought into contact with a first position and a second position on the pad, and in a second test stage, the probe pin may be brought into contact with the pad between the first position and the second position.

[0008] In a second test stage, the probe pin may be brought into contact with the pad at a position midway between the first position and the second position.

[0009] In the first test stage, a first test area of ​​a predetermined size may be set around the position where each probe pin contacts the pad. In the second test stage, a second test area of ​​a predetermined size may be set around the position where each probe pin contacts the pad. The contact positions in the second test stage may be set so that the overlapping area between the first test area and the second test area is minimized.

[0010] The size of at least one of the first test area and the second test area may be adjusted depending on the test conditions.

[0011] In the first test stage and the second test stage, a contact portion provided with a plurality of probe pins may be used at different positions relative to the pad. The pad and the diode element may be arranged on the upper surface of the semiconductor device so as not to overlap with each other. The contact portion may have the probe pins arranged at a constant interval in a first direction. The contact portion may have a first width in the first direction greater than the interval and may have a non-arrangement area where no probe pins are arranged. In both the first test stage and the second test stage, the contact portion may be arranged so that the diode element overlaps with the non-arrangement area.

[0012] In the first test stage and the second test stage, the contact portion may be shifted by a first amount in a first direction. The diode element may have a first length in the first direction. A first width of the non-placement area in the first direction may be greater than the sum of the first amount of movement and the first length.

[0013] In the first test stage and the second test stage, a contact portion provided with a plurality of probe pins may be used at different positions relative to the pad. The semiconductor device may have transistor portions and diode portions alternately arranged in a first direction. At least one of the probe pins may overlap the same transistor portion in the first test stage and the second test stage.

[0014] A first test stage may use a first contact portion having a plurality of probe pins, and a second test stage may use a second contact portion having a plurality of probe pins and different from the first contact portion.

[0015] The first contactor may have a first reference probe pin and one or more first probe pins. The second contactor may have a second reference probe pin and one or more second probe pins. The relative positions of the one or more second probe pins with respect to the second reference probe pin may be different from the relative positions of the one or more first probe pins with respect to the first reference probe pin. The first contactor and the second contactor may be arranged so that the position of the first reference probe pin in the pad during the first test stage is the same as the position of the second reference probe pin in the pad during the second test stage.

[0016] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0017] [Figure 1A] 1 is a diagram showing an overview of a test apparatus 100 for testing a semiconductor device 200 according to an embodiment of the present invention. [Figure 1B] FIG. 1 is a circuit diagram showing an overview of a test apparatus 100. [Figure 2] 1 is a diagram showing an outline of the top surface structure of a semiconductor device 200. FIG. [Figure 3] 3 is a diagram illustrating an example of a path of a current flowing through a probe pin 20. FIG. [Figure 4] 1A to 1C are diagrams illustrating an embodiment of a test method for a semiconductor device 200. [Figure 5] FIG. 2 is a diagram illustrating the relationship between positions 22 and 23. [Figure 6] 10 is a diagram showing another example of the test area 40 and the test area 41. FIG. [Figure 7] 10 is a diagram showing another example of the contact position between the probe pin 20 and the upper surface pad 210. FIG. [Figure 8] FIG. 2 is a diagram illustrating another configuration example of the semiconductor device 200. [Figure 9] 10 is a diagram showing an example of a position 22 of the probe pin 20 in a first test stage S401 and a position 23 of the probe pin 20 in a second test stage S402. [Figure 10] FIG. 2 is a diagram illustrating another configuration example of the semiconductor device 200. [Figure 11] 10 is a diagram showing an example of a position 22 of the probe pin 20 in a first test stage S401 and a position 23 of the probe pin 20 in a second test stage S402. [Figure 12] FIG. 2 is a diagram illustrating another configuration example of the semiconductor device 200. [Figure 13] 10 is a diagram showing an example of a position 22 of the probe pin 20 in a first test stage S401 and a position 23 of the probe pin 20 in a second test stage S402. [Figure 14] 10A and 10B are diagrams showing other examples of the contact portion 10. FIG. [Figure 15] 2 is a diagram showing the positions of the pins on the top surface of the semiconductor device 200. FIG. [Figure 16] 10A and 10B are diagrams showing other examples of the contact portion 10. FIG. [Figure 17] 1 is a diagram showing an example of a position 22 of a first probe pin 20-1 and a position 23 of a second probe pin 20-2. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate (or semiconductor device) is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0020] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0021] In this specification, orthogonal axes parallel to the top and bottom surfaces of a semiconductor substrate (or semiconductor device) are referred to as the X-axis and Y-axis. An axis perpendicular to the top and bottom surfaces of a semiconductor substrate (or semiconductor device) is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, a direction parallel to the top and bottom surfaces of a semiconductor substrate (or semiconductor device), including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0022] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0023] FIG. 1A is a diagram illustrating an overview of a test apparatus 100 for testing a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 includes, for example, an IGBT (Insulated Gate Bipolar Transistor) element, but may also include other semiconductor elements. One semiconductor device 200 may be composed of one chip. When testing the semiconductor device 200, it may be in the form of a wafer on which multiple chips are formed, or in the form of a chip cut from the wafer.

[0024] In this example, an upper surface pad 210 and a lower surface pad 220 are provided on the upper and lower surfaces of the semiconductor device 200. The upper surface pad 210 is, for example, an emitter electrode of an IGBT. The lower surface pad 220 is, for example, a collector electrode of the IGBT. The semiconductor device 200 in this example is a vertical device in which, when controlled to an on state, current flows between the upper surface pad 210 and the lower surface pad 220. In another example, the semiconductor device 200 may be a horizontal device in which both the emitter electrode and the collector electrode are disposed on the upper surface. The upper surface pad 210 and the lower surface pad 220 in this example are formed of a metal material such as aluminum. Pads other than the upper surface pad 210 and the lower surface pad 220 may be provided on at least one of the upper surface and the lower surface of the semiconductor device 200.

[0025] The test device 100 tests the semiconductor device 200. The test device 100 of this example passes a current through the semiconductor device 200 under predetermined conditions, and separates the semiconductor device 200 into those that are destroyed and those that are not. By performing such a test, it is possible to exclude in advance semiconductor devices 200 that are prone to destruction, thereby reducing the probability of the semiconductor device 200 failing after shipment, etc.

[0026] The test apparatus 100 of this example includes a test control unit 110, a contact unit 10, and a stage 120. The stage 120 supports the semiconductor device 200 to be tested. The stage 120 may be provided with terminals that are electrically connected to the lower surface pads 220.

[0027] The contact unit 10 has one or more probe pins 20. The probe pins 20 are formed of a metal material such as copper. The test apparatus 100 electrically connects to the semiconductor device 200 by bringing the probe pins 20 into contact with the top surface pads 210. The contact unit 10 may also include probe pins 20 that contact pads other than the top surface pads 210.

[0028] The test control unit 110 controls the test of the semiconductor device 200. In this example, the test control unit 110 controls at least one of the current and voltage applied to the semiconductor device 200 via the probe pins 20. The test control unit 110 may be electrically connected to the lower surface pads 220 via the stage 120. The test control unit 110 may control the timing of increasing and decreasing the current and voltage, and may also control waveforms such as amplitude and slope. In this example, the test control unit 110 may be connected to each of the emitter electrode E, collector electrode C, and gate electrode G of the semiconductor device 200. The test control unit 110 may also measure at least one of the current and voltage applied to the semiconductor device 200 via the probe pins 20. The test control unit 110 may determine whether the semiconductor device 200 has been destroyed based on the electrical measurement results. For example, the test control unit 110 determines that the semiconductor device 200 has been destroyed when a current greater than or equal to a reference value flows through the semiconductor device 200.

[0029] 1B is a circuit diagram showing an overview of the test apparatus 100. The test apparatus 100 supplies a voltage and a current to the semiconductor device 200 under predetermined conditions and judges whether the semiconductor device 200 is good or bad based on the operation of the semiconductor device 200. The test apparatus 100 may measure at least one of the voltage between the emitter electrode E and the collector electrode C of the semiconductor device 200 and the current Ic flowing through the collector electrode C. As described in FIG. 1A, the test apparatus 100 of this example is connected to each of the emitter electrode E, the collector electrode C, and the gate electrode G of the semiconductor device 200 via the probe pins 20 and the stage 120.

[0030] The test apparatus 100 includes a test control section 110, a power supply 310, a capacitor 311, a coil 312, a coil 316, and a diode 314. The test control section 110 supplies a gate voltage Vge to each of the semiconductor devices 200.

[0031] The power supply 310 generates power to be supplied to the semiconductor device 200. The capacitor 311 is a capacitor for stabilizing the power supply. The coil 312 is disposed between the power supply 310 and the collector electrode C of the semiconductor device 200. The coil 316 is disposed between the coil 312 and the collector electrode C of the semiconductor device 200. The diode 314 is connected in parallel with the coil 312. When the semiconductor device 200 is turned off, the diode 314 returns the current flowing through the semiconductor device 200 to the power supply 310 side.

[0032] Furthermore, the value of the inductive component of the coil 316 may be adjustable. For example, the test apparatus 100 may be provided with a plurality of coils 316 in parallel, each having a different inductive component value, and may be provided with a switch for selecting the coil 316 to be connected between the coil 312 and the semiconductor device 200. By adjusting the inductive component of the coil 316, the slope of the waveform of the current Ic of the semiconductor device 200 can be adjusted.

[0033] The test control unit 110 of this example determines whether the semiconductor device 200 is good or bad based on the operation of the semiconductor device 200 when the semiconductor device 200 is turned off. The test control unit 110 may determine whether the semiconductor device 200 is good or bad based on the waveform of at least one of the current Ic and the voltage Vce of the semiconductor device 200.

[0034] The test control unit 110 may test the reverse bias safe operating area (RBSOA) of the semiconductor device 200. The test control unit 110 of this example may determine whether the current Ic and voltage Vce change within a predetermined range when the semiconductor device 200, through which a predetermined test current flows, is turned off. The test control unit 110 may also determine whether the magnitude of a surge in the voltage Vce at the time of turn-off meets a predetermined standard.

[0035] FIG. 2 is a diagram showing an outline of the top surface structure of a semiconductor device 200. FIG. 2 shows a chip-shaped semiconductor device 200. The semiconductor device 200 has a semiconductor substrate 202. The semiconductor substrate 202 is a substrate made of a semiconductor material such as silicon. An upper surface pad 210 is provided on the upper surface of the semiconductor substrate 202. In this example, a control pad 204, which is electrically isolated from the upper surface pad 210, is provided on the upper surface of the semiconductor substrate 202. As an example, a gate voltage is applied to the control pad 204 to control the semiconductor device 200 to be in an on or off state.

[0036] One or more probe pins 20 contact the upper surface pads 210. In FIG. 2, one probe pin 20 is indicated by one black circle. A current flows through the semiconductor device 200 via the probe pin 20. It is preferable that multiple probe pins 20 contact the upper surface pads 210 so that the current flowing through the semiconductor device 200 is uniform across the upper surface of the semiconductor device 200. It is preferable that the multiple probe pins 20 are arranged two-dimensionally. Two-dimensionally means that the multiple probe pins 20 are arranged along at least two directions on the XY plane. In the example of FIG. 2, the probe pins 20 are arranged at regular intervals along each of the X-axis direction and the Y-axis direction.

[0037] 3 is a diagram illustrating an example of a current flowing through the probe pin 20. In this example, the point on the upper surface pad 210 where the probe pin 20 makes contact is designated as position 22. Also, the point on the upper surface pad 210 that is distant from the probe pin 20 is designated as position 24.

[0038] The current I1 that flows from the lower surface pad 220 to the upper surface pad 210 directly below position 22 passes through the upper surface pad 210 in the thickness direction (Z-axis direction). On the other hand, the current I2 that flows from the lower surface pad 220 to the upper surface pad 210 directly below position 24 passes through the upper surface pad 210 from position 24 to position 22. Therefore, the path through which the current I2 passes through the upper surface pad 210 is longer than the path through which the current I1 passes through the upper surface pad 210. Therefore, the resistance value of the path through which the current I2 passes is greater than the resistance value of the path through which the current I1 passes. The resistance value of the path through which the current I2 passes increases as the distance between position 24 and position 22 increases.

[0039] Since the resistance value of the current path increases, the current I2 becomes smaller than the current I1. As a result, there is a location that is prone to breakdown (referred to as a defective location in this specification) directly below the position 24, and the semiconductor device 200 that should have been screened out as a defective product may end up being determined as a non-defective product without any breakdown occurring during the test.

[0040] That is, if a defective portion exists near the probe pin 20, it can be screened in the test of the semiconductor device 200, but if a defective portion exists at a position away from the probe pin 20, it may not be possible to screen it and the semiconductor device 200 may be shipped. When a semiconductor device 200 that is destroyed after shipment is analyzed, a destroyed portion is detected at a position away from the probe pin 20, but not near the probe pin 20. Since it is considered that a defective portion existed in the semiconductor device 200 before the test regardless of the position of the probe pin 20, it can be seen that a semiconductor device 200 that has a defective portion near the probe pin 20 may be screened during the test, but a semiconductor device 200 that has a defective portion away from the probe pin 20 may not be screened during the test.

[0041] In FIG. 3 , if a defective portion is present, the range in which the defective portion will be destroyed during testing is defined as test area 40. Test area 40 may be set in advance in test control unit 110. For example, test area 40 is a circular range centered at position 22 on the XY plane. Test area 40 may be a range determined by analyzing a semiconductor device 200 that has been destroyed after shipment. That is, in a semiconductor device 200 that has been destroyed after shipment, an area in which no destruction is detected may be defined as test area 40. A contact mark remains at position 22 where the probe pin 20 contacts the upper surface pad 210. In a semiconductor device 200 that has been destroyed after shipment, test area 40 can be determined by analyzing the positional relationship between the contact mark and the destruction point.

[0042] The test area 40 may also be a range determined by the structure of the semiconductor device 200 and the test conditions. The test conditions may include the amplitude and gradient of the voltage and current applied to the semiconductor device 200, as well as the ambient temperature. If the test conditions make the semiconductor device 200 more likely to be damaged, the test area 40 will be larger, and if the test conditions make the semiconductor device 200 less likely to be damaged, the test area 40 will be smaller. The structure of the semiconductor device 200 may be, for example, the resistance value per unit length of the top surface pad 210 in the XY plane. The higher the resistance value of the top surface pad 210, the more difficult it is for the current I2 to flow to a position 24 farther from the probe pin 20, and therefore the test area 40 will be smaller.

[0043] 4 is a diagram illustrating an example of a test method for semiconductor device 200. The test method of this example has a first test stage S401 and a second test stage S402. Both the first test stage S401 and the second test stage S402 are tests in which a current is passed through semiconductor device 200 under predetermined conditions to select semiconductor device 200 that has been destroyed.

[0044] 4, the position on the surface of the upper surface pad 210 where the probe pin 20 comes into contact is indicated by a black circle, and the test area centered on that position is indicated by a circle. In FIG. 4, a portion of the upper surface pad 210 is shown enlarged.

[0045] In the first test stage S401 of this example, the probe pins 20 are brought into contact with the upper surface pads 210 at one or more positions 22. A test area 40 (first test area) exists near each of the positions 22. In the first test stage S401, the size (e.g., radius) of the test area 40 may or may not be set in the test control unit 110. If a defective portion exists in any of the test areas 40, the semiconductor device 200 will be destroyed in the first test stage S401. However, a semiconductor device 200 that has a defective portion outside the test area 40 is likely to be determined to be a good product without being destroyed. In this case, there is a relatively high possibility that the semiconductor device 200 will be destroyed after shipping.

[0046] In the second test stage S402, the probe pins 20 are brought into contact with the upper surface pads 210 at one or more positions 23. A test area 41 (second test area) exists near each of the positions 23. In the second test stage S402, the size (e.g., radius) of the test area 41 may or may not be set in the test control unit 110.

[0047] In the second test stage S402, the position 23 of the probe pin 20 is made different from the position 22 of the probe pin 20 in the first test stage S401. This allows the test area 41 to be placed in a position different from the test area 40. Therefore, defective areas in areas that could not be covered by the test area 40 can be covered by the test area 41. This makes it easier to select semiconductor devices 200 that have defective areas.

[0048] The first test stage S401 and the second test stage S402 may be stages in which the semiconductor device 200 is tested under different conditions. For example, a test is known in which a current is passed through the semiconductor device 200 at different ambient temperatures to determine whether the semiconductor device 200 is broken. The first test stage S401 and the second test stage S402 may be tests performed at different ambient temperatures. This improves the accuracy of sorting the semiconductor device 200 without increasing the number of test processes. The test conditions may be the magnitude of the voltage or current applied to the semiconductor device 200, the slope of the waveform, etc.

[0049] The first test step S401 and the second test step S402 may be steps in which the semiconductor device 200 is tested under the same conditions. As described above, a test is known in which a current is passed through the semiconductor device 200 at different ambient temperatures to determine whether the semiconductor device 200 is broken. In this case, the first test step S401 and the second test step S402 may be performed at the same ambient temperature. For example, when testing the semiconductor device 200 at two ambient temperatures, namely, room temperature (25° C.) and a temperature higher than room temperature, both the first test step S401 and the second test step S402 may be performed at room temperature, both the first test step S401 and the second test step S402 may be performed at the high temperature, or both the first test step S401 and the second test step S402 may be performed at both room temperature and the high temperature. In this case, although the number of test steps increases, the screening accuracy of the semiconductor device 200 can be further improved. In addition, in the four test stages, namely the first test stage S401 and the second test stage S402 performed under the first conditions, and the first test stage S401 and the second test stage S402 performed under the second conditions, the position at which the probe pin 20 contacts the upper surface pad 210 may be different.

[0050] The first test stage S401 and the second test stage S402 may use the same contact portion 10, or different contact portions 10 may be used. When the same contact portion 10 is used, the relative positions of the contact portion 10 and the upper surface pads 210 are shifted in the first test stage S401 and the second test stage S402. In FIG. 4, the amount of shift in the relative positions of the contact portion 10 and the upper surface pads 210 is indicated by arrow 42. When different contact portions 10 are used, the positions of the probe pins 20 on each contact portion 10 are shifted.

[0051] FIG. 5 is a diagram illustrating the relationship between the positions 22 and 23. FIG. 5 shows an enlarged view of one position 23 and four positions 22 surrounding the position 23. The positions 22 are arranged at regular intervals along the X-axis direction and the Y-axis direction. The four positions 22 shown in FIG. 5 are arranged adjacent to each other in the X-axis direction or the Y-axis direction. That is, the first position 22-1 and the third position 22-3 are adjacent to each other in the X-axis direction, the second position 22-2 and the fourth position 22-4 are adjacent to each other in the X-axis direction, the first position 22-1 and the fourth position 22-4 are adjacent to each other in the Y-axis direction, and the third position 22-3 and the second position 22-2 are adjacent to each other in the X-axis direction. The four positions 22 are located at the vertices of a rectangle or a square. The first position 22-1 and the second position 22-2 are located diagonally, and the third position 22-3 and the fourth position 22-4 are located diagonally.

[0052] In this example, position 23 is located between first position 22-1 and second position 22-2. In other words, test area 41 is located so as to fill the area between first test area 40-1 and second test area 40-2. Between first position 22-1 and second position 22-2 refers to area 51 connecting the ends of first position 22-1 and second position 22-2. In FIG. 5, area 51 is the portion sandwiched between the dashed dotted lines. At least a portion of position 23 is located in area 51. Position 23 may be located entirely in area 51.

[0053] When the position of the probe pin 20 is shifted only once, the position 23 is preferably positioned midway between the first position 22-1 and the second position 22-2. The midway between the first position 22-1 and the second position 22-2 refers to a point between the first position 22-1 and the second position 22-2 where the distance from the first position 22-1 is equal to the distance from the second position 22-2. The position 23 may be positioned to overlap with the midpoint. The center of the position 23 may coincide with or be shifted from the midpoint. Alternatively, the position 23 may be positioned so that the midpoint is included in the test region 41.

[0054] Position 23 may be located at the center of a rectangle formed by four positions 22. The center of the rectangle refers to the point where diagonals 50 intersect. Position 23 may be located so as to overlap with the point where diagonals 50 intersect. The center of position 23 may coincide with or deviate from the center of the rectangle.

[0055] Furthermore, if the sizes of the respective test areas are preset in the test control unit 110, it is preferable to set the position 23 in the second test stage S401 so that the overlapping portion between the test area 40 and the test area 41 is minimized. This maximizes the area that can be covered by each test area. As shown in FIG. 5, the test area 40 and the test area 41 may be arranged so that they do not overlap.

[0056] FIG. 6 shows another example of test area 40 and test area 41. Test area 40 and test area 41 in this example are larger than those in the example of FIG. 5. Other parts are similar to the examples described with reference to FIGS. 1A to 5. In the example of FIG. 5, test area 40 and test area 41 do not overlap, but as shown in FIG. 6, test area 40 and test area 41 may overlap. Even in this case, it is preferable to set position 23 in the second test stage S401 so that the overlapping area between test area 40 and test area 41 is minimized. For example, position 23 is located at the center of a rectangle formed by four positions 22. Position 23 may also be located so as not to overlap with test area 40.

[0057] FIG. 7 is a diagram showing another example of the contact positions between the probe pins 20 and the upper surface pads 210. FIG. 7 shows the contact positions of some of the probe pins 20 in the contact section 10. In this example, in addition to the first test stage S401 and the second test stage S402, a third test stage is provided. In the third test stage, the probe pins 20 are brought into contact with the upper surface pads 210 at positions different from those in the first test stage S401 and the second test stage S402. The contact positions of the probe pins 20 in the third test stage are designated as position 25. A test area 43 exists with position 25 as its center.

[0058] Positions 23 and 25 may be located between first position 22-1 and second position 22-2. First position 22-1, second position 22-2, position 23, and position 25 may be located at equal intervals or at different intervals. For example, the interval between each probe pin 20 may be determined according to the size of the corresponding test area. It is preferable that each test area 40, 41, and 43 be located so that overlapping portions with each other are minimized. Each test area 40, 41, and 43 may be located without overlapping as shown in FIG. 7, or may be located with overlapping portions as shown in the example of FIG. 6.

[0059] The sizes of the test area 40, the test area 41, and the test area 43 may be the same or different. The test control unit 110 may adjust the size of at least one of the test area 40, the test area 41, and the test area 43 according to the test conditions of each test stage. Furthermore, in a case where the first test stage S401 and the second test stage S402 are present but the third test stage is not, the test control unit 110 may adjust the size of at least one of the test area 40 and the test area 41 according to the test conditions of each test stage. As described above, the test area may be set larger when the test conditions make the semiconductor device 200 more fragile. Even when the sizes of the test area 40 and the test area 41 are different, it is preferable to set the position 23 of the probe pin 20 in each test stage so that the overlapping portion of the respective test areas is minimized.

[0060] FIG. 8 is a diagram showing another example of the configuration of the semiconductor device 200. In this example, a diode element 208 is arranged on the top surface of the semiconductor device 200 so as not to overlap with the top surface pad 210. For example, the diode element 208 is arranged near the center of the semiconductor substrate 202. The diode element 208 may be used to measure the temperature of the semiconductor device 200. The diode element 208 is connected to a measurement pad 206 via a wiring 209. Although FIG. 8 schematically shows one wiring 209 and one measurement pad 206, a wiring 209 and a measurement pad 206 are provided for each of the anode terminal and cathode terminal of the diode element 208. The wiring 209 has a portion extending from the diode element 208 in the Y-axis direction.

[0061] The contact portion 10 of this example has a plurality of probe pins 20 arranged at a constant interval P1 in the X-axis direction (first direction). The contact portion 10 also has a non-arrangement area 26 where no probe pins 20 are arranged. In the X-axis direction, probe pins 20 are arranged on both sides of the non-arrangement area 26. The non-arrangement area 26 is an area having a first width W1 that is larger than the arrangement interval P1 in the X-axis direction. For example, the first width W1 is at least twice the arrangement interval P1.

[0062] 9 is a diagram showing an example of a position 22 of the probe pin 20 in the first test stage S401 and a position 23 of the probe pin 20 in the second test stage S402. In FIG. 9, the vicinity of the diode element 208 is enlarged. In this example, the same contact portion 10 is moved to a different position relative to the upper surface pad 210 in the first test stage S401 and the second test stage S402. That is, the same non-placement area 26 exists in both the first test stage S401 and the second test stage S402. The amount of shift of the contact portion 10 in the X-axis direction between the first test stage S401 and the second test stage S402 is defined as a first movement amount S1.

[0063] In this example, the contact portion 10 is placed in each test stage so that it overlaps with the diode element 208 in both the non-placement region 26-1 in the first test stage S401 and the non-placement region 26-2 in the second test stage S402. It is preferable that the entire diode element 208 overlaps with both the non-placement region 26-1 and the non-placement region 26-2. This prevents the probe pin 20 from coming into contact with the diode element 208 even when the contact portion 10 is moved. In this example, the first width W1 of the non-placement region 26 is greater than the sum S1+L1 of the first movement amount S1 of the contact portion 10 in the X-axis direction and the first length L1 of the diode element 208 in the X-axis direction.

[0064] 10 is a diagram showing another example of the configuration of the semiconductor device 200. In this example, a gate runner 222 is arranged on the top surface of the semiconductor device 200 so as not to overlap with the top surface pad 210. The gate runner 222 is a wiring that electrically connects the control pad 204 to the gate electrode of a transistor such as an IGBT. In this example, the gate runner 222 has a portion that is arranged so as to surround the top surface pad 210 and a portion that is arranged so as to divide the top surface pad 210. For example, the gate runner 222 has a portion that extends in the X-axis direction near the center of the semiconductor substrate 202 in the Y-axis direction.

[0065] The contact portion 10 of this example has a plurality of probe pins 20 arranged at a constant interval P2 in the Y-axis direction (second direction). The contact portion 10 also has a non-arrangement area 26 where no probe pins 20 are arranged. In the Y-axis direction, probe pins 20 are arranged on both sides of the non-arrangement area 26. The non-arrangement area 26 is an area having a second width W2 in the Y-axis direction that is larger than the arrangement interval P2. For example, the second width W2 is at least twice the arrangement interval P2.

[0066] 11 is a diagram showing an example of the position 22 of the probe pin 20 in the first test stage S401 and the position 23 of the probe pin 20 in the second test stage S402. In FIG. 11, the vicinity of the gate runner 222 that divides the top surface pad 210 is enlarged. In this example, the same contact unit 10 is moved to a different position relative to the top surface pad 210 in the first test stage S401 and the second test stage S402. That is, the same non-placement area 26 exists in both the first test stage S401 and the second test stage S402. The amount of shift of the contact unit 10 in the Y-axis direction between the first test stage S401 and the second test stage S402 is defined as a second movement amount S2.

[0067] In this example, the contact portion 10 is placed in each test stage so that both the non-placement region 26-1 in the first test stage S401 and the non-placement region 26-2 in the second test stage S402 overlap with the gate runner 222. It is preferable that the entire gate runner 222 in the Y-axis direction overlaps with both the non-placement region 26-1 and the non-placement region 26-2. This prevents the probe pin 20 from coming into contact with the gate runner 222 even when the contact portion 10 is moved. In this example, the second width W2 of the non-placement region 26 is greater than the sum S2 + L2 of the second movement amount S2 of the contact portion 10 in the Y-axis direction and the second length L2 of the gate runner 222 in the Y-axis direction.

[0068] FIG. 12 is a diagram showing another example of the configuration of the semiconductor device 200. In FIG. 12, the black circles indicating the positions of the probe pins 20 are omitted. In the semiconductor device 200 of this example, transistor sections 230 and diode sections 240 are alternately arranged in the X-axis direction (first direction). The regions where the transistor sections 230 and the diode sections 240 are provided are covered with upper surface pads 210. The transistor sections 230 include transistors such as IGBTs provided on the semiconductor substrate 202. The diode sections 240 include diodes such as free-wheeling diodes (FWDs) provided on the semiconductor substrate 202. The region of the transistor section 230 is marked with the symbol "I," and the region of the diode section 240 is marked with the symbol "F." The semiconductor device 200 of this example is a so-called reverse-conducting IGBT (RC-IGBT).

[0069] 13 is a diagram showing an example of a position 22 of the probe pin 20 in the first test stage S401 and a position 23 of the probe pin 20 in the second test stage S402. In FIG. 13, the vicinity of the transistor section 230 and the diode section 240 is shown enlarged. In the first test stage S401 and the second test stage S402 of this example, the same contact section 10 is moved to a different position relative to the upper surface pad 210. The amount of shift of the contact section 10 in the X-axis direction between the first test stage S401 and the second test stage S402 is defined as a third movement amount S3.

[0070] In this example, at least one of the probe pins 20 overlaps the same transistor portion 230 in the first test stage S401 and the second test stage S402. In the example of FIG. 13, for multiple probe pins 20 arranged along the Y-axis direction, position 22 in the first test stage S401 and position 23 in the second test stage S402 overlap the same transistor portion 230. This allows for accurate selection of semiconductor devices 200 having defective portions in the transistor portion 230. Since defective portions in the transistor portion 230 that cause so-called latch-up can be detected, semiconductor devices 200 that are prone to breakdown can be accurately selected. In this example, the length L3 of one transistor portion L3 in the X-axis direction is greater than the third movement amount S3 of the contact portion 10 in the X-axis direction.

[0071] The contact portion 10 may have probe pins 20 that overlap with the diode portion 240 in either the first test stage S401 or the second test stage S402. In another example, all of the probe pins 20 may be arranged on the contact portion 10 so as to overlap with the transistor portion 230 in both the first test stage S401 and the second test stage S402. The period P3 at which the transistor portions 230 are arranged in the X-axis direction may be the same as the period P4 at which the probe pins 20 are arranged in the X-axis direction.

[0072] FIG. 14 is a diagram showing another example of the contact unit 10. The contact unit 10 of this example has a reference probe pin 30 and one or more probe pins 20. The arrangement of the probe pins 20 is the same as in the examples of FIGS. 1A to 13. In this example, the multiple probe pins 20 are arranged two-dimensionally. The distance between the reference probe pin 30 and the nearest probe pin 20 may be greater than the interval between the probe pins 20. In other words, the reference probe pin 30 may be arranged away from the multiple probe pins 20. The contact unit 10 may also have the non-arrangement area 26 described with reference to FIGS. 8 to 11.

[0073] 15 is a diagram showing the position of each pin on the top surface of the semiconductor device 200. In this example, the contact portion 10 shown in FIG. 14 is used at a different position in the first test stage S401 and the second test stage S402. In the first test stage S401, the reference probe pin 30 contacts the semiconductor device 200 at a position 33-1. In the second test stage S402, the reference probe pin 30 contacts the semiconductor device 200 at a position 33-2.

[0074] In the first test stage S401 and the second test stage S402, the reference probe pin 30 may be brought into contact with a pad smaller than the upper surface pad 210. For example, the reference probe pin 30 may be brought into contact with the control pad 204, the measurement pad 206, or another pad. In this example, the reference probe pin 30 is in contact with the control pad 204. The test control unit 110 controls the position of the probe pin 20 by positioning the reference probe pin 30 relative to the control pad 204.

[0075] In this example, positions 33-1 and 33-2 of the reference probe pin 30 are arranged on the control pad 204. In Fig. 15, the amount of shift between positions 33-1 and 33-2 is indicated by vector 35. Between the first test stage S401 and the second test stage S402, the position of the contact part 10 is changed in the direction and by the amount of movement indicated by vector 35. Therefore, the amount of shift of position 23 relative to position 22 on the upper surface pad 210 is represented by vector 35.

[0076] At the time of shipment, each pad of semiconductor device 200 has contact marks at the positions where the probe pins made contact. In this example, there are two contact marks on control pad 204 and more on top surface pad 210. The positions of the contact marks are similar to positions 22, 23, and 33 of the probe pins.

[0077] In this specification, the two contact marks on the control pad 204 are referred to as reference contact marks. Furthermore, the numerous contact marks on the top surface pad 210 are referred to as measurement contact marks. The amount of offset between the two reference contact marks is represented by vector 35. Furthermore, each measurement contact mark on the top surface pad 210 is positioned with an offset corresponding to vector 35 relative to the other measurement contact marks. In other words, the direction and distance of the positional offset between the two reference contact marks are equal to the direction and distance of the positional offset between the two paired measurement contact marks. A semiconductor device 200 having such a structure is inspected for defects over a wide test area as described with reference to FIGS. 1A to 13, thereby reducing the possibility of the device being damaged after shipping.

[0078] 16 is a diagram showing another example of the contact unit 10. The test apparatus 100 of this example uses a first contact unit 10-1 having a plurality of probe pins 20-1 in a first test stage S401, and uses a second contact unit 10-2 having a plurality of probe pins 20-2 in a second test stage S402. The first contact unit 10-1 and the second contact unit 10-2 are different components.

[0079] The first contact portion 10-1 has a first reference probe pin 30-1 and one or more first probe pins 20-1. In this example, the multiple first probe pins 20-1 are arranged two-dimensionally.

[0080] The second contact portion 10-2 has a second reference probe pin 30-2 and one or more second probe pins 20-1. In this example, the plurality of second probe pins 20-2 are arranged two-dimensionally.

[0081] The relative positions of one or more second probe pins 20-2 with respect to the second reference probe pin 30-2 are different from the relative positions of one or more first probe pins 20-1 with respect to the first reference probe pin 30-1. In the second contact portion 10-2, when the first reference probe pin 30-1 and the second reference probe pin 30-2 are in the same position, the first probe pin 20-1 is indicated by a dashed line and the second probe pin 20-2 is indicated by a black circle.

[0082] 16, when the reference probe pin 30 is positioned at a common location, the second probe pins 20-2 are shifted by a predetermined amount relative to the first probe pins 20-1. The amount of shift between the first probe pin 20-1 and the second probe pins 20-2 may be the same as the amount of shift between the positions 22 and 23 described with reference to FIGS. 1A to 15. Each contact portion 10 may also have a non-placement area 26 described with reference to FIGS. 8 to 11.

[0083] FIG. 17 is a diagram showing an example of the position 22 of the first probe pin 20-1 and the position 23 of the second probe pin 20-2. In this example, the first contact portion 10-1 and the second contact portion 10-2 are arranged so that the position 33 of the first reference probe pin 30-1 in the first test step S401 is the same as the position 33 of the second reference probe pin 30-2 in the second test step S402. In this example, the first reference probe pin 30-1 and the second reference probe pin 30-2 contact pads other than the top surface pads 210. The first reference probe pin 30-1 and the second reference probe pin 30-2 may both contact the control pads 204. In another example, the first reference probe pin 30-1 and the second reference probe pin 30-2 may both contact the measurement pads 206.

[0084] 16, by contacting the first reference probe pin 30-1 and the second reference probe pin 30-2 with the control pad 204 at the same position 33, the positions 22 and 23 on the upper surface pad 210 can be shifted. Even with this method, it is possible to detect defective portions in a wide test area and screen the semiconductor device 200 with high accuracy.

[0085] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0086] 10...contact part, 20...probe pin, 22...position, 23...position, 24...position, 25...position, 26...non-placement area, 30...reference probe pin, 33...position, 35...vector, 40...test area, 41...test area, 42...arrow, 43...test area, 50...diagonal line, 51...area, 100...test equipment, 110...test control part, 120...stage, 20 0 semiconductor device, 202 semiconductor substrate, 204 control pad, 206 measurement pad, 208 diode element, 209 wiring, 210 upper surface pad, 220 lower surface pad, 222 gate runner, 230 transistor section, 240 diode section, 310 power supply, 311 capacitor, 312 coil, 314 diode, 316 coil

Claims

1. A method for testing a semiconductor device, comprising: a first testing stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device; a second test stage in which the semiconductor device is tested by bringing the probe pin into contact with the same pad as the pad with which the probe pin was brought into contact in the first test stage, and by changing the contact position of the probe pin with respect to the pad from that in the first test stage; Equipped with In the first test stage, the probe pin is brought into contact with a first position and a second position on the pad; In the second test stage, the probe pin is brought into contact with the pad between the first position and the second position. Test method.

2. The first test stage and the second test stage test the semiconductor device under different conditions. The test method of claim 1.

3. The first test stage and the second test stage test the semiconductor device under the same conditions. The test method of claim 1.

4. In the second test stage, the probe pin is brought into contact with the pad at a position midway between the first position and the second position.

4. The test method according to claim 1.

5. In the first test stage, a first test area having a predetermined size is set around a position where each of the probe pins contacts the pad; In the second test stage, a second test area having a predetermined size is set around a position where each of the probe pins contacts the pad; The contact position in the second test stage is set so that the overlap between the first test area and the second test area is minimized.

5. The test method according to any one of claims 1 to 4.

6. A method for testing a semiconductor device, comprising: a first testing stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device; a second test stage in which the semiconductor device is tested by changing the contact position of the probe pin with respect to the pad from that in the first test stage; Equipped with In the first test stage, a first test area having a predetermined size is set around a position where each of the probe pins contacts the pad; In the second test stage, a second test area having a predetermined size is set around a position where each of the probe pins contacts the pad; setting the contact position in the second test stage to minimize overlap between the first test area and the second test area; The size of at least one of the first test area and the second test area is changed according to test conditions. Test method.

7. A method for testing a semiconductor device, comprising: a first testing stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device; a second test stage in which the semiconductor device is tested by changing the contact position of the probe pin with respect to the pad from that in the first test stage; Equipped with In the first test stage and the second test stage, the contact portion provided with the plurality of probe pins is used at different positions relative to the pad; the pad and the diode element are arranged on the upper surface of the semiconductor device so as not to overlap each other; the probe pins are arranged at regular intervals in the contact portion in a first direction; the contact portion has a first width in the first direction that is greater than the arrangement interval, and has a non-arrangement area in which the probe pins are not arranged; In both the first test stage and the second test stage, the contact portion is arranged so that the diode element overlaps the non-arrangement region. Test method.

8. In the first test stage and the second test stage, the contact portion is shifted in the first direction by a first movement amount, the diode element has a first length in the first direction; The first width of the non-placement area in the first direction is greater than the sum of the first movement amount and the first length. The test method according to claim 7.

9. A method for testing a semiconductor device, comprising: a first testing stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device; a second test stage in which the semiconductor device is tested by changing the contact position of the probe pin with respect to the pad from that in the first test stage; Equipped with In the first test stage and the second test stage, the contact portion provided with the plurality of probe pins is used at different positions relative to the pad; a gate runner that separates the pads is disposed on the top surface of the semiconductor device; the probe pins are arranged at regular intervals in the second direction in the contact portion; the contact portion has a second width in the second direction that is greater than the arrangement interval, and has a non-arrangement area where the probe pins are not arranged; In both the first test stage and the second test stage, the contact portion is arranged so that the gate runner overlaps the non-arrangement area. Test method.

10. A method for testing a semiconductor device, comprising: a first testing stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device; a second test stage in which the semiconductor device is tested by changing the contact position of the probe pin with respect to the pad from that in the first test stage; Equipped with In the first test stage and the second test stage, the contact portion provided with the plurality of probe pins is used at different positions relative to the pad; In the semiconductor device, transistor portions and diode portions are alternately arranged in a first direction, At least one of the probe pins overlaps the same transistor portion in the first test stage and the second test stage. Test method.

11. In the first test stage, a first contact portion having a plurality of the probe pins is used, In the second test stage, a second contact portion having a plurality of the probe pins and different from the first contact portion is used.

7. The test method according to any one of claims 1 to 6.

12. A method for testing a semiconductor device, comprising: a first testing stage in which one or more probe pins are brought into contact with pads of the semiconductor device to test the semiconductor device; a second test stage in which the semiconductor device is tested by changing the contact position of the probe pin with respect to the pad from that in the first test stage; Equipped with In the first test stage, a first contact portion having a plurality of the probe pins is used, In the second test stage, a second contact portion having a plurality of the probe pins and different from the first contact portion is used; the first contact portion has a first reference probe pin and one or more first probe pins; the second contact portion has a second reference probe pin and one or more second probe pins; a relative position of one or more of the second probe pins with respect to the second reference probe pin is different from a relative position of one or more of the first probe pins with respect to the first reference probe pin; The first contact portion and the second contact portion are arranged so that the position of the first reference probe pin in the pad in the first test stage is the same as the position of the second reference probe pin in the pad in the second test stage. Test method.

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