Transmission / reception system and transmission / reception method

Abstract

To secure an excellent communication quality in a data transmission using an LDPC code.SOLUTION: An LDPC coding is performed on the basis of a check matrix where a code length N is 17280 bits and a coding rate r is a 6 / 16 LDPC code. The check matrix includes: an A-matrix of M1 rows and K columns represented by a predetermined value M1 and an information length K=N×r of the LDPC coding; a B-matrix of a step structure of M1 rows and M1 columns; a Z-matrix as a zero matrix of M1 rows and N-K-M1 columns; a C-matrix of a N-K-M1 rows and K+M1 columns; and a D-matrix as a unit matrix of N-K-M1 rows and N-K-M1 columns. The A-matrix and the C-matrix are represented by a check matrix initial value table. The check matrix initial value table is a table representing positions of elements of 1 of the A-matrix and the C-matrix for every 360 columns and is a predetermined table. The present technique can be applied to, for example, data transmission using an LDPC code.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] The present technology relates to a transmission / reception system and a transmission / reception method, and in particular to a transmission / reception system and a transmission / reception method that can ensure good communication quality in data transmission using, for example, LDPC codes. [Background technology]

[0002] LDPC (Low Density Parity Check) codes have high error correction capabilities, and in recent years have been widely adopted in transmission systems for digital broadcasting, such as DVB (Digital Video Broadcasting)-S.2, DVB-T.2, and DVB-C.2 in Europe, and ATSC (Advanced Television Systems Committee) 3.0 in the United States (see, for example, Non-Patent Document 1).

[0003] Recent research has shown that LDPC codes, like turbo codes, can achieve performance approaching the Shannon limit as the code length is increased. LDPC codes also have the property that the minimum distance is proportional to the code length, which gives them good block error probability characteristics. Another advantage is that they rarely suffer from the so-called error floor phenomenon observed in the decoding characteristics of turbo codes and the like. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] ATSC Standard:Physical Layer Protocol(A / 322), 7 September 2016 Summary of the Invention [Problem to be solved by the invention]

[0005] In data transmission using LDPC codes, for example, the LDPC codes are converted (symbolized) into symbols for quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbols are mapped to signal points of the quadrature modulation and transmitted.

[0006] Data transmission using LDPC codes as described above is becoming more widespread worldwide, and there is a demand for ensuring good communication (transmission) quality.

[0007] The present technology has been made in view of such circumstances, and makes it possible to ensure good communication quality in data transmission using LDPC codes. [Means for solving the problem]

[0008] A first transmission device / transmission method of the present technology includes a coding unit / step for performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 5 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix including an A matrix with M1 rows and K columns at the top left of the parity check matrix, an M1 row and M1 column B matrix with a staircase structure adjacent to the right of the A matrix, and an M1 row, N-K-M1 column B matrix at the top right of the B matrix. a Z matrix which is a zero matrix adjacent to said A matrix and said B matrix, a C matrix which is adjacent below said A matrix and said B matrix, with N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of said C matrix, with N-K-M1 rows and N-K-M1 columns, wherein said predetermined value M1 is 720, said A matrix and said C matrix are represented by a parity check matrix initial value table, and said parity check matrix initial value table is a table which represents positions of elements of 1 in said A matrix and said C matrix for every 360 columns, 301 342 350 1797 7970 8230 10820 11305 139 530 615 1566 6290 6425 9185 9466 48 419 444 1773 3213 4793 8594 10480 246 455 531 3011 5845 7383 8393 10709 39 262 290 3282 5208 9539 10955 11204 234 267 623 1033 1537 8766 11527 11557 494 661 671 1123 4497 ​​6601 6715 10473 164 425 436 3259 4505 5614 8192 10221 326 377 477 7699 10162 11174 11878 206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549 402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398 39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879 639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518 337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254 32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173 910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863 790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498 The transmitting device / transmitting method is as follows.

[0009] In the first transmitting device and transmitting method of the present technology, LDPC encoding is performed based on a parity check matrix of an LDPC code whose code length N is 17280 bits and whose coding rate r is 5 / 16.The parity check matrix includes: an A matrix of M1 rows and K columns at the top left of the parity check matrix, which is expressed by a predetermined value M1 and an information length K=N×r of the LDPC code; a B matrix of M1 rows and M1 columns with a staircase structure adjacent to the right of the A matrix; a Z matrix of M1 rows and N-K-M1 columns, which is a zero matrix adjacent to the right of the B matrix; a C matrix of N-K-M1 rows and K+M1 columns, which is adjacent below the A matrix and the B matrix; and a D matrix of N-K-M1 rows and N-K-M1 columns, which is an identity matrix adjacent to the right of the C matrix, wherein the predetermined value M1 is 720; the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, 301 342 350 1797 7970 8230 10820 11305 139 530 615 1566 6290 6425 9185 9466 48 419 444 1773 3213 4793 8594 10480 246 455 531 3011 5845 7383 8393 10709 39 262 290 3282 5208 9539 10955 11204 234 267 623 1033 1537 8766 11527 11557 494 661 671 1123 4497 ​​6601 6715 10473 164 425 436 3259 4505 5614 8192 10221 326 377 477 7699 10162 11174 11878 206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549 402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398 39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879 639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518 337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254 32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173 910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863 790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498 It has become.

[0010] a first receiving device / receiving method according to the present technology comprising: a coding step of performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 5 / 16, the parity check matrix including: an A matrix of M1 rows and K columns located at the top left of the parity check matrix, expressed by a predetermined value M1 and an information length K=N×r of the LDPC code; a B matrix of M1 rows and M1 columns having a staircase structure adjacent to the right of the A matrix; a Z matrix of M1 rows and N-K-M1 columns which is a zero matrix adjacent to the right of the B matrix; a C matrix of N-K-M1 rows and K+M1 columns which is adjacent below the A matrix and the B matrix; and a D matrix of N-K-M1 rows and N-K-M1 columns which is an identity matrix adjacent to the right of the C matrix; 301 342 350 1797 7970 8230 10820 11305 139 530 615 1566 6290 6425 9185 9466 48 419 444 1773 3213 4793 8594 10480 246 455 531 3011 5845 7383 8393 10709 39 262 290 3282 5208 9539 10955 11204 234 267 623 1033 1537 8766 11527 11557 494 661 671 1123 4497 6601 6715 10473 164 425 436 3259 4505 5614 8192 10221 326 377 477 7699 10162 11174 11878 206 360 557 891 930 1847 2427 3888 4491 6494 6911 8084 8945 9549 402 588 657 888 3271 4858 5257 6398 6631 6972 9678 11140 11159 11398 39 111 168 1192 1879 3121 3127 5987 8385 8488 9302 9884 10891 11879 639 640 693 1477 1790 2442 3388 3547 4622 6890 7315 7478 7905 11518 337 544 604 1184 1238 1334 2434 5239 6832 7770 9123 9397 9646 10254 32 77 604 762 1428 2756 2758 6854 7193 7311 7517 9105 10765 11173 910 1918 2342 3280 3362 3913 4586 6316 7693 8878 10922 11145 11863 790 1177 1386 1961 2437 3571 5179 5961 8222 9195 9569 10414 11498 The receiving device / receiving method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the above transmission method.

[0011] In the first receiving device and receiving method of the present technology, the LDPC code obtained from data transmitted by the first transmitting method is decoded.

[0012] A second transmission device / transmission method of the present technology includes a coding unit / step for performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 6 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix including an A matrix with M1 rows and K columns at the top left of the parity check matrix, an M1 row and M1 column B matrix with a staircase structure adjacent to the right of the A matrix, and an M1 row, N-K-M1 column B matrix at the top left of the B matrix. a Z matrix which is a zero matrix adjacent to said A matrix and said B matrix, a C matrix which is adjacent below said A matrix and said B matrix, with N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of said C matrix, with N-K-M1 rows and N-K-M1 columns, wherein said predetermined value M1 is 720, said A matrix and said C matrix are represented by a parity check matrix initial value table, and said parity check matrix initial value table is a table which represents positions of elements of 1 in said A matrix and said C matrix for every 360 columns, 416 437 444 1657 2662 4109 4405 6308 8251 75 498 687 3903 4582 7035 7650 7871 10382 394 419 474 3515 6708 7277 8703 9969 10489 167 289 612 1847 5277 5900 8326 8508 9462 196 439 620 2128 2375 2501 6902 9308 9552 154 495 623 5024 6241 8364 9996 10104 10346 230 329 661 879 1474 3222 4109 8079 8865 97 172 692 1018 1629 1752 3170 5930 359 377 712 6273 7131 7278 8292 10457 368 551 708 787 2891 6140 7195 9555 44 512 655 2196 6692 7975 8410 10727 27 94 611 5585 7258 8091 9867 10714 608 639 691 3560 6819 7492 7754 7916 46 115 214 2175 5986 7177 8589 10757 282 589 604 969 1856 2433 5742 8900 243 262 669 1330 1366 3339 5517 7517 62 392 651 4175 8349 8557 9192 10015 206 375 697 1449 2015 2390 3926 4428 5084 5236 5872 8486 9398 9997 10469 1079 1384 1664 2936 4618 5359 5455 5537 5726 5875 8044 8521 9746 791 1106 1497 1885 2682 3473 3716 4506 5671 5829 8388 8641 9454 The transmitting device / transmitting method is as follows.

[0013] In a second transmitting device and transmitting method of the present technology, LDPC encoding is performed based on a parity check matrix of an LDPC code whose code length N is 17280 bits and whose coding rate r is 6 / 16. The parity check matrix includes: an A matrix of M1 rows and K columns at the top left of the parity check matrix, which is expressed by a predetermined value M1 and an information length K=N×r of the LDPC code; a B matrix of M1 rows and M1 columns with a staircase structure adjacent to the right of the A matrix; a Z matrix of M1 rows and N-K-M1 columns, which is a zero matrix adjacent to the right of the B matrix; a C matrix of N-K-M1 rows and K+M1 columns, which is adjacent below the A matrix and the B matrix; and a D matrix of N-K-M1 rows and N-K-M1 columns, which is an identity matrix adjacent to the right of the C matrix, wherein the predetermined value M1 is 720; the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, 416 437 444 1657 2662 4109 4405 6308 8251 75 498 687 3903 4582 7035 7650 7871 10382 394 419 474 3515 6708 7277 8703 9969 10489 167 289 612 1847 5277 5900 8326 8508 9462 196 439 620 2128 2375 2501 6902 9308 9552 154 495 623 5024 6241 8364 9996 10104 10346 230 329 661 879 1474 3222 4109 8079 8865 97 172 692 1018 1629 1752 3170 5930 359 377 712 6273 7131 7278 8292 10457 368 551 708 787 2891 6140 7195 9555 44 512 655 2196 6692 7975 8410 10727 27 94 611 5585 7258 8091 9867 10714 608 639 691 3560 6819 7492 7754 7916 46 115 214 2175 5986 7177 8589 10757 282 589 604 969 1856 2433 5742 8900 243 262 669 1330 1366 3339 5517 7517 62 392 651 4175 8349 8557 9192 10015 206 375 697 1449 2015 2390 3926 4428 5084 5236 5872 8486 9398 9997 10469 1079 1384 1664 2936 4618 5359 5455 5537 5726 5875 8044 8521 9746 791 1106 1497 1885 2682 3473 3716 4506 5671 5829 8388 8641 9454 It has become.

[0014] a second receiving device / receiving method of the present technology comprising: a coding step of performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 6 / 16, the parity check matrix including: an A matrix of M1 rows and K columns at the top left of the parity check matrix expressed by a predetermined value M1 and an information length K=N×r of the LDPC code; a B matrix of M1 rows and M1 columns with a staircase structure adjacent to the right of the A matrix; a Z matrix of M1 rows and N-K-M1 columns which is a zero matrix adjacent to the right of the B matrix; a C matrix of N-K-M1 rows and K+M1 columns which is adjacent below the A matrix and the B matrix; and a D matrix of N-K-M1 rows and N-K-M1 columns which is an identity matrix adjacent to the right of the C matrix; 416 437 444 1657 2662 4109 4405 6308 8251 75 498 687 3903 4582 7035 7650 7871 10382 394 419 474 3515 6708 7277 8703 9969 10489 167 289 612 1847 5277 5900 8326 8508 9462 196 439 620 2128 2375 2501 6902 9308 9552 154 495 623 5024 6241 8364 9996 10104 10346 230 329 661 879 1474 3222 4109 8079 8865 97 172 692 1018 1629 1752 3170 5930 359 377 712 6273 7131 7278 8292 10457 368 551 708 787 2891 6140 7195 9555 44 512 655 2196 6692 7975 8410 10727 27 94 611 5585 7258 8091 9867 10714 608 639 691 3560 6819 7492 7754 7916 46 115 214 2175 5986 7177 8589 10757 282 589 604 969 1856 2433 5742 8900 243 262 669 1330 1366 3339 5517 7517 62 392 651 4175 8349 8557 9192 10015 206 375 697 1449 2015 2390 3926 4428 5084 5236 5872 8486 9398 9997 10469 1079 1384 1664 2936 4618 5359 5455 5537 5726 5875 8044 8521 9746 791 1106 1497 1885 2682 3473 3716 4506 5671 5829 8388 8641 9454 The receiving device / receiving method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the above transmission method.

[0015] In the second receiving device and receiving method of the present technology, the LDPC code obtained from data transmitted by the second transmission method is decoded.

[0016] A third transmission device / transmission method of the present technology includes a coding unit / step for performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix including an A matrix at the top left of the parity check matrix, an M1 row and M1 column B matrix with a staircase structure adjacent to the right of the A matrix, and an M1 row, N-K-M1 column B matrix at the right of the B matrix. a Z matrix which is an adjacent zero matrix, a C matrix which is adjacent below the A matrix and the B matrix, with N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, with N-K-M1 rows and N-K-M1 columns, wherein the predetermined value M1 is 1080, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 512 531 598 3235 3447 5630 5765 6208 7026 9012 88 486 926 1714 5140 5725 6006 6506 7619 8191 200 447 460 1088 2612 3297 4001 4275 4992 8638 106 434 618 5357 5713 9045 9335 9429 9696 23 192 661 1220 2962 3867 5783 6410 6790 311 744 934 1267 1428 1959 2462 2865 5461 69 494 991 1278 4441 5620 5705 5936 8872 297 637 1031 2346 2946 4519 7235 7264 9243 330 599 790 3674 5457 6535 6660 7398 8110 263 630 826 1978 3384 4259 5159 5588 5885 196 648 983 1529 1821 2312 2428 7249 7359 59 774 1036 1427 2005 5811 6998 7987 8222 454 474 986 1633 4040 6880 7786 8518 9039 433 443 849 2517 3617 5477 6294 7914 9456 175 242 906 2924 3412 4063 7737 9084 9338 385 624 1004 3218 5225 6479 7684 7933 8875 233 622 807 2302 3315 3898 4079 7109 9201 3 877 1070 1331 2607 3552 4672 7549 8083 247 753 806 12 242 598 221 561 643 1135 1424 2228 9426 4998 5209 7742 8652 2042 5925 6236 9405 The transmitting device / transmitting method is as follows.

[0017] In the third transmission device and third transmission method of the present technology, LDPC coding is performed based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16. the parity check matrix includes: an A matrix at the top left of the parity check matrix, of M1 rows and K columns, represented by a predetermined value M1 and an information length K=N×r of the LDPC code; a B matrix of a staircase structure adjacent to the right of the A matrix, of M1 rows and M1 columns; a Z matrix which is a zero matrix adjacent to the right of the B matrix, of M1 rows and N-K-M1 columns; a C matrix adjacent below the A matrix and the B matrix, of N-K-M1 rows and K+M1 columns; and a D matrix which is an identity matrix adjacent to the right of the C matrix, of N-K-M1 rows and N-K-M1 columns; 512 531 598 3235 3447 5630 5765 6208 7026 9012 88 486 926 1714 5140 5725 6006 6506 7619 8191 200 447 460 1088 2612 3297 4001 4275 4992 8638 106 434 618 5357 5713 9045 9335 9429 9696 23 192 661 1220 2962 3867 5783 6410 6790 311 744 934 1267 1428 1959 2462 2865 5461 69 494 991 1278 4441 5620 5705 5936 8872 297 637 1031 2346 2946 4519 7235 7264 9243 330 599 790 3674 5457 6535 6660 7398 8110 263 630 826 1978 3384 4259 5159 5588 5885 196 648 983 1529 1821 2312 2428 7249 7359 59 774 1036 1427 2005 5811 6998 7987 8222 454 474 986 1633 4040 6880 7786 8518 9039 433 443 849 2517 3617 5477 6294 7914 9456 175 242 906 2924 3412 4063 7737 9084 9338 385 624 1004 3218 5225 6479 7684 7933 8875 233 622 807 2302 3315 3898 4079 7109 9201 3 877 1070 1331 2607 3552 4672 7549 8083 247 753 806 12 242 598 221 561 643 1135 1424 2228 9426 4998 5209 7742 8652 2042 5925 6236 9405 It has become.

[0018] A third receiving device / receiving method of the present technology includes a coding step of performing LDPC coding based on a parity check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16, the parity check matrix being represented by a predetermined value M1 and an information length K=N×r of the LDPC code, the parity check matrix including an A matrix at the top left of the parity check matrix, an M1 row and M1 column B matrix with a staircase structure adjacent to the right of the A matrix, and an M1 row, N-K-M1 column B matrix adjacent to the right of the B matrix. a Z matrix which is a zero matrix adjacent to the A matrix and the B matrix, a C matrix which is adjacent below the A matrix and the B matrix, and which has N-K-M1 rows and N-K-M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, and which has N-K-M1 rows and N-K-M1 columns, wherein the predetermined value M1 is 1080, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 512 531 598 3235 3447 5630 5765 6208 7026 9012 88 486 926 1714 5140 5725 6006 6506 7619 8191 200 447 460 1088 2612 3297 4001 4275 4992 8638 106 434 618 5357 5713 9045 9335 9429 9696 23 192 661 1220 2962 3867 5783 6410 6790 311 744 934 1267 1428 1959 2462 2865 5461 69 494 991 1278 4441 5620 5705 5936 8872 297 637 1031 2346 2946 4519 7235 7264 9243 330 599 790 3674 5457 6535 6660 7398 8110 263 630 826 1978 3384 4259 5159 5588 5885 196 648 983 1529 1821 2312 2428 7249 7359 59 774 1036 1427 2005 5811 6998 7987 8222 454 474 986 1633 4040 6880 7786 8518 9039 433 443 849 2517 3617 5477 6294 7914 9456 175 242 906 2924 3412 4063 7737 9084 9338 385 624 1004 3218 5225 6479 7684 7933 8875 233 622 807 2302 3315 3898 4079 7109 9201 3 877 1070 1331 2607 3552 4672 7549 8083 247 753 806 12 242 598 221 561 643 1135 1424 2228 9426 4998 5209 7742 8652 2042 5925 6236 9405 The receiving device / receiving method includes a decoding unit / step for decoding the LDPC code obtained from data transmitted by the above transmission method.

[0019] In the third receiving device and receiving method of the present technology, the LDPC code obtained from data transmitted by the third transmission method is decoded.

[0020] The transmitting device and receiving device may be independent devices or may be internal blocks constituting a single device. [Effects of the Invention]

[0021] According to the present technology, good communication quality can be ensured in data transmission using LDPC codes.

[0022] The effects described here are not necessarily limited to those described herein, and may be any of the effects described in this disclosure. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 2 is a diagram illustrating a check matrix H of an LDPC code. [Figure 2] 10 is a flowchart illustrating a decoding procedure for an LDPC code. [Figure 3] FIG. 1 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 4] FIG. 10 is a diagram illustrating an example of a Tanner graph of a parity check matrix. [Figure 5] FIG. 10 is a diagram illustrating an example of a variable node. [Figure 6] FIG. 2 is a diagram illustrating an example of a check node. [Figure 7] 1 is a diagram illustrating an example of the configuration of an embodiment of a transmission system to which the present technology is applied. [Figure 8] FIG. 2 is a block diagram showing an example of the configuration of a transmission device 11. [Figure 9] FIG. 10 is a block diagram showing an example of the configuration of a bit interleaver 116. [Figure 10] FIG. 10 is a diagram illustrating an example of a check matrix. [Figure 11] FIG. 10 is a diagram illustrating an example of a parity matrix. [Figure 12] 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 13] 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 14] FIG. 1 is a diagram illustrating an example of a Tanner graph for decoding an LDPC code. [Figure 15] FIG. 1 is a diagram illustrating an example of a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T. [Figure 16] FIG. 10 is a diagram illustrating an example of a parity matrix H T of a check matrix H corresponding to an LDPC code after parity interleaving. [Figure 17] 10 is a flowchart illustrating an example of processing performed by the bit interleaver 116 and the mapper 117. [Figure 18] FIG. 2 is a block diagram showing an example of the configuration of an LDPC encoder 115. [Figure 19] 10 is a flowchart illustrating an example of processing performed by the LDPC encoder 115. [Figure 20] FIG. 10 is a diagram illustrating an example of a check matrix initial value table for a coding rate of 1 / 4 and a code length of 16200. [Figure 21] 10 is a diagram illustrating a method for obtaining a check matrix H from a check matrix initial value table. FIG. [Figure 22] FIG. 10 is a diagram illustrating the structure of a parity check matrix. [Figure 23] FIG. 10 is a diagram illustrating an example of a check matrix initial value table. [Figure 24]FIG. 10 is a diagram illustrating matrix A generated from the check matrix initial value table. [Figure 25] FIG. 10 is a diagram illustrating parity interleaving of a B matrix. [Figure 26] FIG. 10 is a diagram illustrating a C matrix generated from a check matrix initial value table. [Figure 27] FIG. 10 is a diagram illustrating parity interleaving of a D matrix. [Figure 28] FIG. 10 is a diagram showing a parity check matrix obtained by performing column permutation on the parity check matrix as parity deinterleaving to restore parity interleaving to its original state. [Figure 29] FIG. 10 is a diagram showing a transformed check matrix obtained by performing row permutation on a check matrix. [Figure 30] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=2 / 16. [Figure 31] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=3 / 16. [Figure 32] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=4 / 16. [Figure 33] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=5 / 16. [Figure 34] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=6 / 16. [Figure 35] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=17280 bits and r=7 / 16. [Figure 36] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=7 / 16. [Figure 37] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=8 / 16. [Figure 38]FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=9 / 16. [Figure 39] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=10 / 16. [Figure 40] FIG. 10 is a diagram showing an example of a parity check matrix initial value table for a Type B code where N=17280 bits and r=11 / 16. [Figure 41] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=12 / 16. [Figure 42] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=13 / 16. [Figure 43] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=17280 bits and r=14 / 16. [Figure 44] FIG. 10 is a diagram illustrating an example of a Tanner graph of an ensemble of degree sequences with column weight 3 and row weight 6. [Figure 45] FIG. 10 is a diagram illustrating an example of a Tanner graph of a multi-edge type ensemble. [Figure 46] FIG. 10 is a diagram illustrating a parity check matrix of the Type A method. [Figure 47] FIG. 10 is a diagram illustrating a parity check matrix of the Type A method. [Figure 48] FIG. 10 is a diagram illustrating a parity check matrix of the Type B method. [Figure 49] FIG. 10 is a diagram illustrating a parity check matrix of the Type B method. [Figure 50] FIG. 10 is a diagram illustrating an example of coordinates of UC signal points when the modulation method is QPSK. [Figure 51] FIG. 10 is a diagram illustrating an example of the coordinates of signal points of 2D-NUC when the modulation method is 16QAM. [Figure 52] FIG. 10 is a diagram illustrating an example of the coordinates of signal points of 1D-NUC when the modulation method is 1024QAM. [Figure 53] FIG. 10 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. [Figure 54] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of QPSK-UC. [Figure 55] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of QPSK-UC. [Figure 56] FIG. 10 is a diagram illustrating an example of coordinates zq of a 16QAM-UC signal point. [Figure 57] FIG. 10 is a diagram illustrating an example of coordinates zq of a 16QAM-UC signal point. [Figure 58] FIG. 10 is a diagram illustrating an example of coordinates zq of a 64QAM-UC signal point. [Figure 59] FIG. 10 is a diagram illustrating an example of coordinates zq of a 64QAM-UC signal point. [Figure 60] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of 256QAM-UC. [Figure 61] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of 256QAM-UC. [Figure 62] FIG. 10 is a diagram illustrating an example of coordinates zq of a 1024QAM-UC signal point. [Figure 63] FIG. 10 is a diagram illustrating an example of coordinates zq of a 1024QAM-UC signal point. [Figure 64] FIG. 10 is a diagram illustrating an example of coordinates zq of a 4096QAM-UC signal point. [Figure 65] FIG. 10 is a diagram illustrating an example of coordinates zq of a 4096QAM-UC signal point. [Figure 66] FIG. 10 is a diagram illustrating an example of coordinates zs of a signal point of 16QAM-2D-NUC. [Figure 67] FIG. 10 is a diagram illustrating an example of coordinates zs of a signal point of 64QAM-2D-NUC. [Figure 68] FIG. 10 is a diagram illustrating an example of the coordinates zs of a signal point of 256QAM-2D-NUC. [Figure 69] FIG. 10 is a diagram illustrating an example of the coordinates zs of a signal point of 256QAM-2D-NUC. [Figure 70] FIG. 10 is a diagram illustrating an example of the coordinates zs of a signal point of 1024QAM-1D-NUC. [Figure 71] FIG. 10 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. [Figure 72] FIG. 10 is a diagram illustrating an example of coordinates zs of a signal point of 4096QAM-1D-NUC. [Figure 73] FIG. 10 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. [Figure 74] FIG. 10 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. [Figure 75] FIG. 2 is a diagram illustrating block interleaving performed by the block interleaver 25. [Figure 76] FIG. 2 is a diagram illustrating block interleaving performed by the block interleaver 25. [Figure 77] FIG. 2 is a diagram illustrating group-wise interleaving performed by group-wise interleaver 24. [Figure 78] FIG. 10 is a diagram illustrating an example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 79] FIG. 2 is a block diagram showing an example of the configuration of a receiving device 12. [Figure 80] FIG. 10 is a block diagram showing an example of the configuration of a bit deinterleaver 165. [Figure 81] 10 is a flowchart illustrating an example of processing performed by a demapper 164, a bit deinterleaver 165, and an LDPC decoder 166. [Figure 82] FIG. 1 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 83] FIG. 10 is a diagram showing an example of a matrix (transformed parity check matrix) obtained by performing row permutation and column permutation on a parity check matrix. [Figure 84] FIG. 10 is a diagram showing an example of a transformed check matrix divided into 5×5 units. [Figure 85] FIG. 10 is a block diagram showing an example of the configuration of a decoding device that performs P node operations at once. [Figure 86] FIG. 2 is a block diagram showing an example of the configuration of an LDPC decoder 166. [Figure 87] FIG. 10 is a diagram illustrating block deinterleaving performed by the block deinterleaver 54. [Figure 88]It is a block diagram showing another configuration example of the bit deinterleaver 165. [Figure 89] It is a block diagram showing a first configuration example of a reception system to which the reception device 12 is applicable. [Figure 90] It is a block diagram showing a second configuration example of a reception system to which the reception device 12 is applicable. [Figure 91] It is a block diagram showing a third configuration example of a reception system to which the reception device 12 is applicable. [Figure 92] It is a block diagram showing a configuration example of an embodiment of a computer to which the present technology is applied.

Embodiments of the Invention

[0024] Hereinafter, embodiments of the present technology will be described. Prior to that, the LDPC code will be described.

[0025] <LDPC code>

[0026] Note that the LDPC code is a linear code and does not necessarily have to be binary, but here it will be described as being binary.

[0027] The LDPC code is characterized in that the parity check matrix defining the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of "1"s in the elements of the matrix is very small (a matrix in which most elements are 0).

[0028] FIG. 1 is a diagram showing an example of the parity check matrix H of the LDPC code.

[0029] In the parity check matrix H of FIG. 1, the weight of each column (column weight) (the number of "1"s) (weight) is "3", and the weight of each row (row weight) is "6".

[0030] In coding using an LDPC code (LDPC coding), for example, a generator matrix G is generated based on a check matrix H, and binary information bits are multiplied by this generator matrix G to generate a codeword (LDPC code).

[0031] Specifically, the coding device that performs LDPC coding first generates a transposed matrix H of the check matrix H. T Between the equation GH T = 0. Here, if generator matrix G is a K × N matrix, the encoding device multiplies generator matrix G by a bit string (vector u) of K information bits to generate a codeword c (= uG) consisting of N bits. The codeword (LDPC code) generated by this encoding device is received at the receiving side via a predetermined communication channel.

[0032] Decoding of LDPC codes is an algorithm proposed by Gallager called Probabilistic Decoding, and can be performed by a message-passing algorithm using belief propagation on a Tanner graph consisting of variable nodes (also called message nodes) and check nodes. Hereinafter, variable nodes and check nodes will be referred to simply as nodes where appropriate.

[0033] FIG. 2 is a flowchart showing the procedure for decoding an LDPC code.

[0034] In the following, the real value (received LLR) that expresses the likelihood of the value being "0" of the i-th code bit of the LDPC code (one code word) received on the receiving side as a log likelihood ratio is referred to as the received value u 0i Also, the message output from the check node is called u j The message output from the variable node is v i Let's say.

[0035] First, in decoding an LDPC code, as shown in FIG. 2, in step S11, an LDPC code is received and a message (check node message) u j is initialized to "0", and a variable k that takes an integer and serves as a counter for repeated processing is initialized to "0", and the process proceeds to step S12. In step S12, the received value u obtained by receiving the LDPC code is 0i Based on this, the message (variable node message) v is generated by performing the calculation (variable node calculation) shown in Equation (1). i is required, and furthermore, this message v i Based on this, the message u is generated by performing the operation (check node operation) shown in equation (2). j is required.

[0036]

number

[0037]

number

[0038] Here, d in Equation (1) and Equation (2) v and d c are arbitrarily selectable parameters that indicate the number of "1"s in the vertical direction (columns) and horizontal direction (rows) of the check matrix H. For example, in the case of an LDPC code ((3,6) LDPC code) for a check matrix H with a column weight of 3 and a row weight of 6 as shown in FIG. 1, d v =3,d c =6.

[0039] In the variable node operation of formula (1) and the check node operation of formula (2), messages input from edges (lines connecting variable nodes and check nodes) that are about to output messages are not included in the operation, so the range of operation is from 1 to d. v-1 or 1 to d c The check node operation of equation (2) is actually performed by creating a table of the function R(v1, v2) shown in equation (3), which is defined as one output for two inputs v1 and v2, in advance, and then using this table continuously (recursively) as shown in equation (4).

[0040]

number

[0041]

number

[0042] In step S12, the variable k is further incremented by "1", and the process proceeds to step S13. In step S13, it is determined whether the variable k is greater than a predetermined number of decoding iterations C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and the same processes are repeated thereafter.

[0043] If it is determined in step S13 that the variable k is greater than C, the process proceeds to step S14, where the message v i is calculated and output, and the LDPC code decoding process is completed.

[0044]

number

[0045] Here, the operation of formula (5) differs from the variable node operation of formula (1) in that it receives messages u from all edges connected to the variable node. j This is done using

[0046] FIG. 3 is a diagram showing an example of a parity check matrix H of a (3,6) LDPC code (coding rate 1 / 2, code length 12).

[0047] In the parity check matrix H in FIG. 3, the column weight is 3 and the row weight is 6, similar to FIG.

[0048] FIG. 4 is a diagram showing a Tanner graph of the parity check matrix H of FIG.

[0049] Here, in Figure 4, check nodes are represented by plus signs "+" and variable nodes are represented by equal signs "=". Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connection between a check node and a variable node is an edge, which corresponds to the element "1" of the parity check matrix.

[0050] That is, when the element in the j-th row and i-th column of the parity check matrix is ​​1, in FIG. 4, the i-th variable node from the top (node ​​marked "=") and the j-th check node from the top (node ​​marked "+") are connected by a branch. The branch indicates that the code bit corresponding to the variable node has a constraint corresponding to the check node.

[0051] In a sum product algorithm, which is a decoding method for LDPC codes, variable node calculations and check node calculations are repeatedly performed.

[0052] FIG. 5 is a diagram showing variable node operations performed at the variable node.

[0053] At the variable node, the message v corresponding to the branch to be calculated is i is the message u1 and u2 from the remaining branches connected to the variable node, and the received value u 0i The messages corresponding to the other branches can be calculated in the same way.

[0054] FIG. 6 is a diagram illustrating check node operations performed at a check node.

[0055] Here, the check node operation of equation (2) can be rewritten as equation (6) using the relationship of the equation a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), where sign(x) is 1 when x≧0 and −1 when x<0.

[0056]

number

[0057] If we define the function φ(x) as φ(x)=ln(tanh(x / 2)) for x≧0, then the function φ -1 (x)=2tanh -1 (e -x ) holds, so equation (6) can be transformed into equation (7).

[0058]

number

[0059] At the check nodes, the check node operation of equation (2) is performed according to equation (7).

[0060] That is, at the check node, as shown in Figure 6, the message u corresponding to the branch to be calculated is j is calculated by the check node calculation of equation (7) using messages v1, v2, v3, v4, and v5 from the remaining edges connected to the check node. Messages corresponding to other edges can be calculated in the same way.

[0061] The function φ(x) in equation (7) is expressed as φ(x)=ln((e x +1) / (e x -1), and for x>0, φ(x)=φ -1 (x). The functions φ(x) and φ -1When (x) is implemented in hardware, it may be implemented using an LUT (Look Up Table), but both will be the same LUT.

[0062] <Configuration example of a transmission system applying this technology>

[0063] FIG. 7 is a diagram showing an example of the configuration of an embodiment of a transmission system to which the present technology is applied (a system refers to a logical collection of multiple devices, and it does not matter whether the devices are located in the same housing or not).

[0064] In FIG. 7, the transmission system is made up of a transmitting device 11 and a receiving device 12.

[0065] The transmitting device 11 transmits (broadcasts) (transmits), for example, television broadcast programs, etc. That is, the transmitting device 11 encodes target data to be transmitted, such as image data or audio data as a program, into an LDPC code, and transmits the encoded data via a communication path 13, such as a satellite line, terrestrial wave, or cable (wired line).

[0066] The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.

[0067] Here, the LDPC code used in the transmission system of FIG. 7 is known to exhibit extremely high performance in an AWGN (Additive White Gaussian Noise) communication channel.

[0068] On the other hand, burst errors and erasures may occur in the communication path 13. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, particularly when the communication path 13 is a terrestrial wave, in a multipath environment where the D / U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power is equal to Desired = main path power), the power of a specific symbol may become 0 (erasure) depending on the delay of the echo (path other than the main path).

[0069] Furthermore, even in a flutter channel (a channel with zero delay and an echo with a Doppler frequency added), if the D / U is 0 dB, the Doppler frequency can cause the power of the entire OFDM symbol at a specific time to become 0 (erasure).

[0070] Furthermore, burst errors may occur due to the condition of the wiring from the receiving unit (not shown) such as an antenna that receives signals from the transmitting device 11 to the receiving device 12, or due to instability in the power supply of the receiving device 12.

[0071] On the other hand, in decoding the LDPC code, the columns of the check matrix H, and in turn, the variable nodes corresponding to the code bits of the LDPC code, are used to decode the received values ​​u 0i Since the variable node operation of equation (1) involves the addition of (a) and (b), if an error occurs in the sign bit used in the variable node operation, the accuracy of the message obtained will decrease.

[0072] In decoding an LDPC code, the check node calculation of equation (7) is performed at a check node using a message obtained at a variable node connected to that check node. Therefore, if there are a large number of check nodes where multiple connected variable nodes (corresponding code bits of the LDPC code) simultaneously have errors (including erasures), the decoding performance will deteriorate.

[0073] That is, for example, when two or more variable nodes connected to the check node are simultaneously erased, a check node returns to all variable nodes a message with an equal probability that the value is 0 and that the value is 1. In this case, the check node that returns a message with equal probability does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, the decoding process needs to be repeated many times, degrading the decoding performance and further increasing the power consumption of the receiving device 12 that decodes the LDPC code.

[0074] Therefore, the transmission system of FIG. 7 can improve the tolerance to burst errors and erasures while maintaining the performance in an AWGN communication path (AWGN channel).

[0075] <Configuration example of transmitter 11>

[0076] FIG. 8 is a block diagram showing an example of the configuration of the transmitting device 11 of FIG.

[0077] In the transmitting device 11, one or more input streams as target data are supplied to a mode adaptation / multiplexer 111.

[0078] The mode adaptation / multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112 .

[0079] The padder 112 performs necessary zero padding (insertion of nulls) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to a BB scrambler 113 .

[0080] The BB scrambler 113 performs BB scrambling (Base-Band Scrambling) on ​​the data from the padder 112 and supplies the resulting data to a BCH encoder 114 .

[0081] The BCH encoder 114 performs BCH encoding on the data from the BB scrambler 113, and supplies the resulting data to an LDPC encoder 115 as LDPC target data that is to be LDPC encoded.

[0082] The LDPC encoder 115 (encoding unit) performs LDPC encoding on the LDPC target data from the BCH encoder 114, for example, according to a check matrix in which the parity matrix, which is the part corresponding to the parity bits of the LDPC code, has a staircase (dual diagonal) structure, and outputs an LDPC code in which the LDPC target data is information bits.

[0083] That is, the LDPC encoder 115 performs LDPC encoding on the LDPC target data to encode the LDPC target data into an LDPC code (corresponding to a check matrix) specified in a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, or ATSC3.0, or another LDPC code, and outputs the resulting LDPC code.

[0084] Here, the LDPC code specified in the DVB-S.2 and ATSC3.0 standards is an IRA (Irregular Repeat Accumulate) code, and the parity matrix (part or all) in the check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. The IRA code is described, for example, in "Irregular Repeat-Accumulate Codes," by H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of the 2nd International Symposium on Turbo Codes and Related Topics, pp. 1-8, September 2000.

[0085] The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116 .

[0086] The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115 and supplies the bit-interleaved LDPC code to a mapper 117 .

[0087] The mapper 117 performs quadrature modulation (multi-level modulation) by mapping the LDPC code from the bit interleaver 116 to a signal point representing one symbol of quadrature modulation in units of one or more code bits (symbol units) of the LDPC code.

[0088] That is, the mapper 117 performs orthogonal modulation by mapping the LDPC code from the bit interleaver 116 to a signal point determined by a modulation method for orthogonally modulating the LDPC code on a constellation, which is an IQ plane defined by an I axis representing an I component that is in-phase with the carrier wave and a Q axis representing a Q component that is orthogonal to the carrier wave.

[0089] The number of signal points of the constellation used in the modulation method of the quadrature modulation performed by the mapper 117 is 2m In this case, the m-bit code bits of the LDPC code are treated as a symbol (1 symbol), and the mapper 117 divides the LDPC code from the bit interleaver 116 into 2 symbols. m are mapped to signal points representing symbols among the signal points.

[0090] Here, the modulation method of the quadrature modulation performed by the mapper 117 includes, for example, modulation methods defined in the DVB-S.2 and ATSC3.0 standards, and other modulation methods, that is, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. Which modulation method is used for quadrature modulation in the mapper 117 is set in advance, for example, according to an operation by an operator of the transmission device 11.

[0091] The data obtained by the processing in the mapper 117 (the mapping result of mapping symbols to signal points) is supplied to a time interleaver 118 .

[0092] The time interleaver 118 performs time interleaving (interleaving in the time direction) on a symbol-by-symbol basis on the data from the mapper 117, and supplies the resulting data to a SISO / MISO (Single Input Single Output / Multiple Input Single Output) encoder 119.

[0093] The SISO / MISO encoder 119 performs space-time coding on the data from the time interleaver 118 and supplies the data to a frequency interleaver 120 .

[0094] The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on the data from the SISO / MISO encoder 119 in units of symbols, and supplies the data to a frame builder & resource allocation unit (Frame Builder & Resource Allocation) 131 .

[0095] On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control, such as BB signaling (Base Band Signaling) (BB Header).

[0096] The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114 , and supplies the resulting data to the LDPC encoder 122 .

[0097] The LDPC encoder 122 LDPC-encodes the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115 , and supplies the resulting LDPC code to the mapper 123 .

[0098] Similar to the mapper 117, the mapper 123 performs orthogonal modulation by mapping the LDPC code from the LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code, and supplies the resulting data to the frequency interleaver 124.

[0099] Similar to the frequency interleaver 120 , the frequency interleaver 124 performs frequency interleaving on the data from the mapper 123 in units of symbols, and supplies the data to a frame builder / resource allocation unit 131 .

[0100] The frame builder / resource allocation unit 131 inserts pilot symbols into required positions in the data (symbols) from the frequency interleavers 120 and 124, and constructs a frame (e.g., a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) consisting of a predetermined number of symbols from the resulting data (symbols), and supplies it to an OFDM generation unit (OFDM generation) 132.

[0101] The OFDM generating unit 132 generates an OFDM signal corresponding to the frame from the frame supplied from the frame builder / resource allocating unit 131, and transmits the signal via the communication path 13 (FIG. 7).

[0102] The transmitting device 11 can be configured without some of the blocks shown in FIG. 8, such as the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124.

[0103] <Configuration example of bit interleaver 116>

[0104] FIG. 9 is a block diagram showing an example of the configuration of the bit interleaver 116 in FIG.

[0105] The bit interleaver 116 has a function of interleaving data, and is made up of a parity interleaver 23 , a group-wise interleaver 24 , and a block interleaver 25 .

[0106] The parity interleaver 23 performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0107] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23, and supplies the LDPC code after the group-wise interleaving to the block interleaver 25.

[0108] Here, in the group-wise interleaving, the LDPC code for one code is divided into 360-bit units equal to the parallel factor P described later from the beginning, and the 360 bits of one division are used as a bit group, and the LDPC code from the parity interleaver 23 is interleaved in bit group units.

[0109] When performing group-wise interleaving, the error rate can be improved compared to the case where group-wise interleaving is not performed, and as a result, good communication quality can be ensured in data transmission.

[0110] The block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the group-wise interleaver 24. For example, the LDPC code for one code is symbolized into m-bit symbols that are the units of mapping, and supplied to the mapper 117 (FIG. 8).

[0111] Here, in the block interleaving, for example, columns as storage areas for storing a predetermined number of bits in the column (vertical) direction are arranged in the row (horizontal) direction in a storage area arranged in a number equal to the number of bits m of the symbol. The LDPC code from the group-wise interleaver 24 is written in the column direction and read in the row direction, so that the LDPC code is symbolized into m-bit symbols.

[0112] <Check Matrix of LDPC Code>

[0113] FIG. 10 is a diagram showing an example of a check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8.

[0114] The check matrix H has an LDGM (Low-Density Generation Matrix) structure, and the information matrix H of the part of the code bits of the LDPC code corresponding to the information bits is A and the parity matrix H corresponding to the parity bits T Therefore, the formula H=[H A |H T ](information matrix H A The elements of are the left elements, and the parity matrix H T The right-hand element of the matrix is ​​the element of

[0115] Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one code word) are called the information length K and the parity length M, respectively, and the number of code bits of one LDPC code (one code word) is called the code length N (= K + M).

[0116] The information length K and parity length M for an LDPC code with a certain code length N are determined by the coding rate. The check matrix H is an M×N matrix (a matrix with M rows and N columns). A is an M×K matrix, and the parity matrix H T is an M×M matrix.

[0117] FIG. 11 shows the parity matrix H of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. T FIG.

[0118] The parity matrix H of the check matrix H used for LDPC encoding in the LDPC encoder 115 T For example, a parity matrix H similar to the check matrix H of the LDPC code specified in standards such as DVB-T.2 is used. T can be adopted.

[0119] Parity matrix H of the check matrix H of the LDPC code specified in standards such as DVB-T.2 TAs shown in Figure 11, the parity matrix H is a lower bidiagonal matrix in which the elements of 1 are arranged in a staircase pattern. T The row weight is 1 for the first row and 2 for all remaining rows. The column weight is 1 for the last column and 2 for all remaining columns.

[0120] As mentioned above, the parity matrix H T An LDPC code for a check matrix H having a staircase structure can be easily generated using the check matrix H.

[0121] That is, the LDPC code (one code word) is represented by a row vector c, and the column vector obtained by transposing the row vector is c T In addition, the information bit portion of row vector c, which is an LDPC code, is represented by row vector A, and the parity bit portion is represented by row vector T.

[0122] In this case, row vector c can be expressed as c = [A|T] (a row vector with elements of row vector A as the left elements and elements of row vector T as the right elements) using row vector A as the information bits and row vector T as the parity bits.

[0123] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c=[A|T] is the check matrix H=[H A |H T ]'s parity matrix H T When the step structure shown in Figure 11 is formed, the formula Hc T =0 column vector Hc T It can be calculated sequentially (in order) by setting the elements of each row to 0, starting from the first row.

[0124] FIG. 12 is a diagram illustrating a check matrix H of an LDPC code defined in standards such as DVB-T.2.

[0125] The first KX columns of the check matrix H of an LDPC code specified in standards such as DVB-T.2 have a column weight of X, the next K3 columns have a column weight of 3, the next M-1 columns have a column weight of 2, and the last column has a column weight of 1.

[0126] Here, KX+K3+M-1+1 is equal to the code length N.

[0127] FIG. 13 is a diagram showing the numbers of columns KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in standards such as DVB-T.2.

[0128] Standards such as DVB-T.2 prescribe LDPC codes with code lengths N of 64,800 bits and 16,200 bits.

[0129] For an LDPC code with a code length N of 64,800 bits, eleven coding rates (nominal rates) 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10 are specified, and for an LDPC code with a code length N of 16,200 bits, ten coding rates 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 are specified.

[0130] Hereinafter, a code length N of 64,800 bits will also be referred to as 64 kbits, and a code length N of 16,200 bits will also be referred to as 16 kbits.

[0131] In an LDPC code, the code bits corresponding to columns with larger column weights in the parity check matrix H tend to have lower error rates.

[0132] In the check matrix H specified in standards such as DVB-T.2 shown in Figures 12 and 13, the column weight tends to be larger as it approaches the beginning (left side). Therefore, for the LDPC code corresponding to the check matrix H, the code bits at the beginning tend to be more resistant to errors (more resistant to errors), and the code bits at the end tend to be more susceptible to errors.

[0133] <Parity interleave>

[0134] Parity interleaving by the parity interleaver 23 of FIG. 9 will be described with reference to FIGS.

[0135] FIG. 14 is a diagram showing an example of (a part of) a Tanner graph of a parity check matrix of an LDPC code.

[0136] As shown in Fig. 14, when two or more of the variable nodes (corresponding code bits) connected to the check node simultaneously become erasure or other errors, the check node returns a message to all variable nodes connected to the check node, with the probability that the value is 0 and the probability that the value is 1 being equal. For this reason, when multiple variable nodes connected to the same check node simultaneously become erasure or other errors, decoding performance deteriorates.

[0137] Incidentally, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code, similar to the LDPC code defined in the standards such as DVB-T.2, and the parity matrix H of the check matrix H is T As shown in Figure 11, the structure is a staircase.

[0138] Figure 15 shows the parity matrix H T and its parity matrix H T FIG. 1 is a diagram illustrating an example of a Tanner graph corresponding to

[0139] A in Figure 15 shows the parity matrix H T15A shows an example of the parity matrix H T The Tanner graph corresponding to

[0140] The parity matrix H has a staircase structure T In each row, elements with a value of 1 are adjacent (except the first row). Therefore, the parity matrix H T In the Tanner graph of T Two adjacent variable nodes corresponding to a column of two adjacent elements where the value of is 1 are connected to the same check node.

[0141] Therefore, when parity bits corresponding to the two adjacent variable nodes described above become erroneous at the same time due to a burst error, erasure, or the like, the check nodes connected to the two variable nodes corresponding to the two erroneous parity bits (variable nodes that use the parity bits to find a message) return messages with equal probabilities of being 0 and 1 to the variable nodes connected to those check nodes, degrading decoding performance.As the burst length (the number of consecutive erroneous parity bits) increases, the number of check nodes that return messages with equal probabilities increases, further degrading decoding performance.

[0142] Therefore, in order to prevent the above-mentioned degradation of decoding performance, the parity interleaver 23 (FIG. 9) performs parity interleaving, which interleaves the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits.

[0143] FIG. 16 shows the parity matrix H of the check matrix H corresponding to the LDPC code after parity interleaving performed by the parity interleaver 23 in FIG. T FIG.

[0144] Here, the information matrix H of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 is Ahas a cyclic structure, similar to the information matrix of the check matrix H corresponding to the LDPC code defined in standards such as DVB-T.2.

[0145] A cyclic structure is a structure in which a column is the same as a cyclic shift of another column, and includes, for example, a structure in which the position of 1 in each row of each P column is cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the first column of each P column by the parity length M. Hereinafter, the P columns in a cyclic structure will be referred to as a parallel factor as appropriate.

[0146] As described with reference to FIGS. 12 and 13, there are two types of LDPC codes defined in standards such as DVB-T.2, with code lengths N of 64,800 bits and 16,200 bits, and for both of these two types of LDPC codes, the parallel factor P is defined as 360, which is one of the divisors of the parity length M excluding 1 and M.

[0147] Furthermore, the parity length M is a value other than a prime number expressed by the equation M = q × P = q × 360, with the value q varying depending on the coding rate. Therefore, like the parallel factor P, the value q is one of the divisors of the parity length M other than 1 and M, and is obtained by dividing the parity length M by the parallel factor P (the product of P and q, which are divisors of the parity length M, is the parity length M).

[0148] As described above, the parity interleaver 23 interleaves the K+qx+y+1-th code bit of the code bits of the N-bit LDPC code to the K+Py+x+1-th code bit position, where K is the information length, x is an integer greater than or equal to 0 and less than P, and y is an integer greater than or equal to 0 and less than q, as parity interleaving.

[0149] The K+qx+y+1th code bit and the K+Py+x+1th code bit are both parity bits since they are code bits after the K+1th bit. Therefore, according to parity interleaving, the position of the parity bit of the LDPC code is moved.

[0150] With such parity interleaving, variable nodes (corresponding parity bits) connected to the same check node are spaced apart by the parallel factor P, i.e., 360 bits in this case. Therefore, if the burst length is less than 360 bits, it is possible to avoid a situation in which multiple variable nodes connected to the same check node experience an error at the same time, thereby improving resistance to burst errors.

[0151] The LDPC code after parity interleaving, in which the K+qx+y+1-th code bit is interleaved at the K+Py+x+1-th code bit position, matches the LDPC code of the check matrix (hereinafter also referred to as the transformed check matrix) obtained by performing column permutation, in which the K+qx+y+1-th column of the original check matrix H is replaced with the K+Py+x+1-th column.

[0152] Furthermore, as shown in FIG. 16, a quasi-cyclic structure appears in the parity matrix of the converted parity check matrix, with P columns (360 columns in FIG. 16) as a unit.

[0153] Here, the pseudo-cyclic structure means a structure in which all but a part are cyclic structures.

[0154] The transformed check matrix obtained by performing column permutation equivalent to parity interleaving on the check matrix of an LDPC code specified in standards such as DVB-T.2 has a 360 row x 360 column part in the upper right corner of the transformed check matrix (the shift matrix described below) that is missing one element of 1 (it becomes an element of 0), and in that respect it is not a (complete) cyclic structure, but rather a quasi-cyclic structure.

[0155] The conversion check matrix for the check matrix of the LDPC code output by the LDPC encoder 115 has a quasi-cyclic structure, similar to the conversion check matrix for the check matrix of the LDPC code defined in standards such as DVB-T.2.

[0156] The transformed check matrix in Figure 16 is a matrix in which, in addition to column permutation equivalent to parity interleaving, row permutation (row permutation) has also been performed on the original check matrix H so that the transformed check matrix is ​​composed of the constituent matrices described below.

[0157] FIG. 17 is a flowchart illustrating the processing performed by the LDPC encoder 115, the bit interleaver 116, and the mapper 117 in FIG.

[0158] The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101 encodes the LDPC target data into an LDPC code and supplies the LDPC code to the bit interleaver 116, after which the process proceeds to step S102.

[0159] In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, and supplies the symbols obtained by the bit interleaving to the mapper 117, after which the process proceeds to step S103.

[0160] That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 115, and supplies the parity-interleaved LDPC code to the group-wise interleaver 24.

[0161] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 and supplies the result to the block interleaver 25 .

[0162] The block interleaver 25 performs block interleaving on the LDPC code after group-wise interleaving by the group-wise interleaver 24 , and supplies the resulting m-bit symbol to the mapper 117 .

[0163] In step S103, the mapper 117 converts the symbols from the block interleaver 25 into two symbols determined by the modulation method of the quadrature modulation performed by the mapper 117. m signal points and orthogonally modulated, and the resulting data is supplied to a time interleaver 118.

[0164] As described above, by performing parity interleaving or group-wise interleaving, it is possible to improve the error rate when multiple code bits of an LDPC code are transmitted as one symbol.

[0165] Here, in Figure 9, for the sake of convenience of explanation, the parity interleaver 23, which is a block that performs parity interleaving, and the group-wise interleaver 24, which is a block that performs group-wise interleaving, are configured separately, but the parity interleaver 23 and the group-wise interleaver 24 can be configured as an integrated unit.

[0166] In other words, both parity interleaving and group-wise interleaving can be performed by writing and reading code bits to memory, and can be represented by a matrix that converts the address at which the code bits are written (write address) into the address at which the code bits are read (read address).

[0167] Therefore, if we obtain a matrix obtained by multiplying a matrix representing parity interleaving and a matrix representing group-wise interleaving, by using these matrices, by converting the code bits, we can perform parity interleaving, and further obtain the result of group-wise interleaving the LDPC code after the parity interleaving.

[0168] Also, in addition to the parity interleaver 23 and the group-wise interleaver 24, the block interleaver 25 can also be integrally configured.

[0169] That is, the block interleaving performed by the block interleaver 25 can also be represented by a matrix that converts the write address of the memory storing the LDPC code into the read address.

[0170] Therefore, if we obtain a matrix obtained by multiplying a matrix representing parity interleaving, a matrix representing group-wise interleaving, and a matrix representing block interleaving, by using these matrices, we can perform parity interleaving, group-wise interleaving, and block interleaving all at once.

[0171] Note that one or both of the parity interleaving and the group-wise interleaving can be not performed.

[0172] <Configuration example of LDPC encoder 115>

[0173] FIG. 18 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG. 8.

[0174] Note that the LDPC encoder 122 of FIG. 8 is also configured in the same way.

[0175] As described in FIGS. 12 and 13, in standards such as DVB-T.2, LDPC codes with two code lengths N of 64800 bits and 16200 bits are defined.

[0176] For an LDPC code with a code length N of 64,800 bits, eleven coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10, and for an LDPC code with a code length N of 16,200 bits, ten coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 (Figures 12 and 13).

[0177] The LDPC encoder 115 can perform, for example, encoding (error correction encoding) using an LDPC code with a code length N of 64,800 bits or 16,200 bits and each coding rate, in accordance with a check matrix H prepared for each code length N and each coding rate.

[0178] Furthermore, the LDPC encoder 115 can perform LDPC encoding in accordance with a parity check matrix H of an LDPC code having a code length N of 17280 bits or any other arbitrary code length N and a coding rate r of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 or any other arbitrary coding rate.

[0179] The LDPC encoder 115 is made up of an encoding processing unit 601 and a storage unit 602 .

[0180] The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generation unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616, and performs LDPC encoding of the LDPC target data supplied to the LDPC encoder 115, and supplies the resulting LDPC code to the bit interleaver 116 (FIG. 8).

[0181] That is, the coding rate setting unit 611 sets the code length N and coding rate r of the LDPC code, and other specific information that identifies the LDPC code, in response to, for example, an operation by an operator.

[0182] The initial value table reading unit 612 reads from the storage unit 602 a check matrix initial value table, which will be described later, that indicates the check matrix of the LDPC code specified by the specification information set by the coding rate setting unit 611 .

[0183] The check matrix generation unit 613 generates a check matrix H based on the check matrix initial value table read by the initial value table reading unit 612, and stores the generated check matrix H in the storage unit 602. For example, the check matrix generation unit 613 generates an information matrix H corresponding to an information length K (=code length N-parity length M) according to the code length N and coding rate r set by the coding rate setting unit 611. A The elements of 1 are arranged in the column direction at a period of 360 columns (parallel factor P) to generate a check matrix H, which is stored in the storage unit 602.

[0184] The information bit reading unit 614 reads (extracts) information bits of an information length K from the LDPC target data supplied to the LDPC encoder 115.

[0185] The encoding parity calculation unit 615 reads out the check matrix H generated by the check matrix generation unit 613 from the memory unit 602, and uses the check matrix H to calculate parity bits for the information bits read out by the information bit reading unit 614 based on a predetermined formula, thereby generating a codeword (LDPC code).

[0186] The control unit 616 controls each block that constitutes the encoding processing unit 601 .

[0187] The storage unit 602 stores a plurality of check matrix initial value tables corresponding to a plurality of coding rates shown in Fig. 12 and Fig. 13 for each code length N of 64800 bits, 16200 bits, etc., a check matrix initial value table corresponding to each coding rate of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 for a code length N of 17280 bits, and other check matrix initial value tables of the check matrix H of the LDPC code of any code length N and any coding rate r.In addition, the storage unit 602 temporarily stores data required for the processing of the encoding processing unit 601.

[0188] FIG. 19 is a flowchart illustrating an example of processing by the LDPC encoder 115 of FIG.

[0189] In step S201, the coding rate setting unit 611 sets the code length N and coding rate r for LDPC coding, as well as other specific information for specifying the LDPC code.

[0190] In step S202, the initial value table reading unit 612 reads from the storage unit 602 a predetermined check matrix initial value table that is specified by the code length N, the coding rate r, and the like, as the specific information set by the coding rate setting unit 611.

[0191] In step S203, the check matrix generation unit 613 uses the check matrix initial value table read out from the storage unit 602 by the initial value table reading unit 612 to determine (generate) the check matrix H of the LDPC code having the code length N and coding rate r set by the coding rate setting unit 611, and supplies it to the storage unit 602 for storage.

[0192] In step S204, the information bit reading unit 614 reads out information bits of an information length K (=N×r) corresponding to the code length N and coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, and also reads out the check matrix H calculated by the check matrix generation unit 613 from the storage unit 602 and supplies it to the encoding parity calculation unit 615.

[0193] In step S205, the coded parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the check matrix H to sequentially calculate parity bits of the codeword c that satisfy equation (8).

[0194] Hc T =0 ···(8)

[0195] In equation (8), c represents a row vector as a codeword (LDPC code), and c T represents the transpose of the row vector c.

[0196] Here, as described above, in the row vector c as an LDPC code (one code word), when the information bit portion is represented by row vector A and the parity bit portion is represented by row vector T, the row vector c can be expressed by the formula c = [A|T] using the row vector A as the information bit and the row vector T as the parity bit.

[0197] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c=[A|T] is the check matrix H=[H A |H T ]'s parity matrix H T When the step structure shown in Figure 11 is formed, the formula Hc T =0 column vector Hc TIt can be calculated sequentially by setting the elements of each row to 0, starting from the elements of the first row.

[0198] The encoding parity calculation unit 615 calculates a parity bit T for the information bit A from the information bit reading unit 614, and outputs the code word c = [A|T] represented by the information bit A and the parity bit T as the LDPC encoding result of the information bit A.

[0199] Thereafter, in step S206, the control unit 616 determines whether or not to end the LDPC encoding. If it is determined in step S206 that the LDPC encoding should not be ended, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the processes of steps S201 (or step S204) to S206 are repeated.

[0200] Also, if it is determined in step S206 that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the process.

[0201] A check matrix initial value table (representing a check matrix) for LDPC codes with various code lengths N and coding rates r can be prepared in advance for the LDPC encoder 115. The LDPC encoder 115 can perform LDPC encoding into LDPC codes with various code lengths N and coding rates r by using a check matrix H generated from the check matrix initial value table prepared in advance.

[0202] <Example of a check matrix initial value table>

[0203] The check matrix initial value table is, for example, an information matrix H corresponding to an information length K according to the code length N and coding rate r of the LDPC code (LDPC code defined by the check matrix H) of the check matrix H. A10 for each of 360 columns (parallel factor P), and is created in advance for each check matrix H for each code length N and each coding rate r.

[0204] That is, the check matrix initial value table includes at least the information matrix H A The position of the 1 element is represented for each of the 360 ​​columns (parallel factor P).

[0205] In addition, the check matrix H contains a parity matrix H T All of the check matrices have a staircase structure, and the parity matrix H T There is a check matrix in which a part of it has a staircase structure and the remaining part is a diagonal matrix (identity matrix).

[0206] Below, the parity matrix H T The representation method of the parity check matrix initial value table, which represents a parity check matrix in which a part of the matrix has a staircase structure and the remaining part is a diagonal matrix, is also called the Type A method. T The representation method of the check matrix initial value table representing the check matrix in which all of the check matrices have a staircase structure is also called Type B method.

[0207] An LDPC code for a parity check matrix indicated by a parity check matrix initial value table of the Type A system is also called a Type A code, and an LDPC code for a parity check matrix indicated by a parity check matrix initial value table of the Type B system is also called a Type B code.

[0208] The designations "Type A" and "Type B" are based on the ATSC 3.0 standard. For example, ATSC 3.0 uses both Type A and Type B codes.

[0209] In addition, DVB-T.2 and the like use Type B coding.

[0210] FIG. 20 is a diagram showing an example of a parity check matrix initial value table of the Type B method.

[0211] That is, Figure 20 shows a check matrix initial value table (representing the check matrix H) for a Type B code (defined in the DVB-T.2 standard) with a code length N of 16,200 bits and a coding rate (the notational coding rate in DVB-T.2) r of 1 / 4.

[0212] The check matrix generation unit 613 (FIG. 18) uses the check matrix initial value table of the Type B method to obtain the check matrix H as follows.

[0213] FIG. 21 is a diagram for explaining a method for obtaining a check matrix H from a check matrix initial value table of the Type B method.

[0214] That is, FIG. 21 shows a check matrix initial value table for a Type B code with a code length N of 16200 bits and a coding rate r of 2 / 3, as defined in the DVB-T.2 standard.

[0215] The check matrix initial value table of the Type B method is an information matrix H corresponding to the information length K according to the code length N and the coding rate r of the LDPC code. A It is a table that represents the positions of all elements of 1 in each of 360 columns (parallel factor P), and in the i-th row, the row numbers of elements of 1 in the 1+360×(i-1)th column of the check matrix H (row numbers where the row number of the first row of the check matrix H is 0) are arranged in the same order as the column weight of the 1+360×(i-1)th column.

[0216] Here, the parity matrix H corresponding to the parity length M of the check matrix H of the Type B system is T Since (Fig. 10) is determined to have a staircase structure as shown in Fig. 15, the information matrix H corresponding to the information length K is calculated using the check matrix initial value table. A If (FIG. 10) can be obtained, the check matrix H can be obtained.

[0217] The number of rows k+1 of the check matrix initial value table of the Type B method varies depending on the information length K.

[0218] The relationship of equation (9) holds between the information length K and the number of rows k+1 of the parity check matrix initial value table.

[0219] K = (k + 1) × 360 ···(9)

[0220] Here, 360 in equation (9) is the parallel factor P explained in FIG.

[0221] In the parity check matrix initial value table of FIG. 21, 13 numerical values ​​are arranged in the first to third rows, and 3 numerical values ​​are arranged in the fourth to k+1th rows (the 30th row in FIG. 21).

[0222] Therefore, the column weight of the check matrix H obtained from the check matrix initial value table of Figure 21 is 13 from the 1st column to the 1+360×(3-1)-1th column, and 3 from the 1+360×(3-1)th column to the Kth column.

[0223] The first row of the parity check matrix initial value table in Figure 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which indicates that in the first column of parity check matrix H, the elements in the rows with row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are 1 (and the other elements are 0).

[0224] In addition, the second row of the parity check matrix initial value table in Figure 21 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which indicates that in the 361st (=1+360×(2-1))th column of the parity check matrix H, the elements of the rows with row numbers 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108 are 1.

[0225] As described above, the check matrix initial value table is the information matrix H A Represents the position of the 1 element in every 360 columns.

[0226] Columns other than the 1+360×(i-1)th column of the check matrix H, i.e., each column from the 2+360×(i-1)th column to the 360×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+360×(i-1)th column, which is determined by the check matrix initial value table, downward (downward in the column) according to the parity length M.

[0227] That is, for example, the 2+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by M / 360(=q), and the next 3+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by 2×M / 360(=2×q) (the 2+360×(i-1)th column cyclically shifted downward by M / 360(=q)).

[0228] Now, let the value in the ith row (ith from the top) and jth column (jth from the left) of the check matrix initial value table be h i,j and the row number of the j-th element of 1 in the w-th column of the check matrix H is expressed as H w-j Then, the row number H of the element of 1 in the w-th column, which is a column other than the 1+360×(i-1)-th column of the check matrix H, is w-j can be calculated using equation (10).

[0229] H w-j =mod{h i,j +mod((w-1),P)×q,M) ···(10)

[0230] Here, mod(x,y) means the remainder when x is divided by y.

[0231] Furthermore, P is the above-mentioned parallel factor, which in this embodiment is 360, similar to the standards such as DVB-T.2 and ATSC3.0. Furthermore, q is a value M / 360 obtained by dividing the parity length M by the parallel factor P (=360).

[0232] The check matrix generation unit 613 (FIG. 18) identifies the row number of the element of 1 in the 1+360×(i−1)th column of the check matrix H using the check matrix initial value table.

[0233] Furthermore, the check matrix generation unit 613 (FIG. 18) generates a row number H of an element of 1 in the w-th column, which is a column other than the 1+360×(i−1)-th column of the check matrix H. w-j is calculated according to equation (10), and a check matrix H is generated in which the elements of the row numbers obtained above are set to 1.

[0234] FIG. 22 is a diagram showing the structure of the parity check matrix H of the Type A method.

[0235] The check matrix of the Type A method is made up of an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

[0236] Matrix A is an upper left matrix of parity check matrix H, with M1 rows and K columns, expressed by a predetermined value M1 and information length K of the LDPC code = code length N × coding rate r.

[0237] The B matrix is ​​a step structure matrix adjacent to the A matrix on the right, with M1 rows and M1 columns.

[0238] The C matrix is ​​a matrix adjacent below the A and B matrices, with N−M1 rows and K+M1 columns.

[0239] The D matrix is ​​an identity matrix adjacent to the right of the C matrix, with N-K-M1 rows and N-K-M1 columns.

[0240] The Z matrix is ​​a zero matrix (0 matrix) adjacent to the right of the B matrix, with M1 rows and NK-M1 columns.

[0241] In the type A check matrix H composed of the above-mentioned A matrix to D matrix and Z matrix, part of A matrix and C matrix constitutes the information matrix, and the remaining parts of B matrix, C matrix, D matrix and Z matrix constitute the parity matrix.

[0242] Since the B matrix is ​​a matrix with a staircase structure and the D matrix is ​​a unit matrix, part of the parity matrix of the check matrix H of the Type A method (the B matrix part) has a staircase structure, and the remaining part (the D matrix part) is a diagonal matrix (unit matrix).

[0243] Like the information matrix of the check matrix H of the Type B method, the A matrix and the C matrix have a cyclic structure for each column of the parallel factor P (for example, 360 columns), and the check matrix initial value table of the Type A method represents the positions of elements of 1 in the A matrix and the C matrix for each 360 columns.

[0244] Here, as mentioned above, the A matrix and a part of the C matrix constitute an information matrix, so it can be said that the Type A method check matrix initial value table, which represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, at least represents the positions of elements of 1 in the information matrix every 360 columns.

[0245] In addition, since the Type A method check matrix initial value table represents the positions of elements of 1 in the A matrix and C matrix every 360 columns, it can also be said that it represents the positions of elements of 1 in a part of the check matrix (the remaining part of the C matrix) every 360 columns.

[0246] FIG. 23 is a diagram showing an example of a parity check matrix initial value table of the Type A method.

[0247] That is, FIG. 23 shows an example of a parity check matrix initial value table that represents a parity check matrix H with a code length N of 35 bits and a coding rate r of 2 / 7.

[0248] The Type A method check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for each parallel factor P, and in its i-th row, the row numbers of elements of 1 in the 1+P×(i-1)th column of the check matrix H (row numbers where the row number of the first row of the check matrix H is 0) are arranged as many times as the column weight of the 1+P×(i-1)th column.

[0249] For ease of explanation, the parallel factor P is assumed to be 5, for example.

[0250] The check matrix H of the Type A system has parameters M1, M2, Q1, and Q2.

[0251] M1 (FIG. 22) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the parallel factor P. By adjusting M1, the performance of the LDPC code changes, and when determining the check matrix H, it is adjusted to a predetermined value. Here, it is assumed that 15, which is three times the parallel factor P=5, is adopted as M1.

[0252] M2 (FIG. 22) is the value M-M1 obtained by subtracting M1 from the parity length M.

[0253] Here, the information length K is N×r=35×2 / 7=10, and the parity length M is NK=35−10=25, so M2 is M−M1=25−15=10.

[0254] Q1 is calculated according to the formula Q1=M1 / P, and represents the number of cyclic shifts (number of rows) in the A matrix.

[0255] That is, the columns other than the 1+P×(i-1)th column of the A matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q1 represents the number of cyclic shifts in the A matrix.

[0256] Q2 is calculated according to the formula Q2=M2 / P, and represents the number of cyclic shifts (number of rows) in the C matrix.

[0257] That is, the columns other than the 1+P×(i-1)th column of the C matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q2 represents the number of cyclic shifts in the C matrix.

[0258] Here, Q1 is M1 / P=15 / 5=3, and Q2 is M2 / P=10 / 5=2.

[0259] In the parity check matrix initial value table of Figure 23, three numerical values ​​are arranged in the first and second rows, and one numerical value is arranged in the third to fifth rows. According to this arrangement of numerical values, the column weight of the A matrix and C matrix portion of the parity check matrix H obtained from the parity check matrix initial value table of Figure 23 is 3 from the 1=1+5×(1-1)th column to the 10=5×2nd column, and is 1 from the 11=1+5×(3-1)th column to the 25=5×5th column.

[0260] That is, the first row of the check matrix initial value table in Figure 23 is 2, 6, 18, which indicates that in the first column of the check matrix H, the elements in the rows with row numbers 2, 6, 18 are 1 (and the other elements are 0).

[0261] In this case, the A matrix (Figure 22) is a matrix with 15 rows and 10 columns (M1 rows and K columns), and the C matrix (Figure 22) is a matrix with 10 rows and 25 columns (NK-M1 rows and K+M1 columns), so the rows with row numbers 0 to 14 of the check matrix H are rows of the A matrix, and the rows with row numbers 15 to 24 of the check matrix H are rows of the C matrix.

[0262] Therefore, of the rows with row numbers 2, 6, and 18 (hereinafter referred to as rows #2, #6, and #18), rows #2 and #6 are rows of the A matrix, and row #18 is a row of the C matrix.

[0263] The second row of the parity check matrix initial value table in Figure 23 is 2, 10, 19, which indicates that the elements of rows #2, #10, and #19 in the 6th (=1+5×(2-1)) column of parity check matrix H are 1.

[0264] Here, in the 6th (=1+5×(2−1)) column of parity check matrix H, of rows #2, #10, and #19, rows #2 and #10 are rows of the A matrix, and row #19 is a row of the C matrix.

[0265] The third row of the parity check matrix initial value table in FIG. 23 is 22, which indicates that the element of row #22 in the 11th (=1+5×(3−1)) column of parity check matrix H is 1.

[0266] Here, in the 11th (=1+5×(3−1)) column of the parity check matrix H, row #22 is a row of the C matrix.

[0267] Similarly, the 19 in the fourth row of the parity check matrix initial value table of Figure 23 indicates that the element of row #19 in the 16th (=1+5×(4-1)) column of the parity check matrix H is 1, and the 15 in the fifth row of the parity check matrix initial value table of Figure 23 indicates that the element of row #15 in the 21st (=1+5×(5-1)) column of the parity check matrix H is 1.

[0268] As described above, the parity check matrix initial value table indicates the positions of elements of 1 in the A matrix and C matrix of the parity check matrix H for each parallel factor P=5 columns.

[0269] Columns other than the 1+5×(i-1)th column of the A matrix and C matrix of the check matrix H, i.e., each column from the 2+5×(i-1)th column to the 5×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+5×(i-1)th column determined by the check matrix initial value table downward (downward in the column direction) according to parameters Q1 and Q2.

[0270] That is, for example, the 2+5×(i-1)th column of matrix A is the 1+5×(i-1)th column cyclically shifted downward by Q1 (=3), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q1 (=2×3) (the 2+5×(i-1)th column cyclically shifted downward by Q1).

[0271] For example, the 2+5×(i-1)th column of matrix C is the 1+5×(i-1)th column cyclically shifted downward by Q2 (=2), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q2 (=2×2) (the 2+5×(i-1)th column cyclically shifted downward by Q2).

[0272] FIG. 24 is a diagram showing matrix A generated from the check matrix initial value table of FIG.

[0273] In matrix A in FIG. 24, elements of rows #2 and #6 in the 1st (=1+5×(1−1))th column are 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0274] Each of the columns from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) is a cyclic shift of the previous column downward by Q1=3.

[0275] Furthermore, in matrix A in FIG. 24, elements of rows #2 and #10 in the 6th (=1+5×(2−1)) column are 1, in accordance with the second row of the parity check matrix initial value table in FIG.

[0276] Each column from the 7th (=2+5×(2-1)) column to the 10th (=5+5×(2-1)) column is cyclically shifted downward by Q1=3 from the previous column.

[0277] FIG. 25 is a diagram showing parity interleaving of a B matrix.

[0278] The check matrix generation unit 613 (FIG. 18) uses a check matrix initial value table to generate matrix A, and arranges matrix B of a staircase structure to the immediate right of matrix A. Then, the check matrix generation unit 613 regards matrix B as a parity matrix, and performs parity interleaving so that adjacent elements of 1 in matrix B of the staircase structure are spaced apart by a parallel factor P=5 in the row direction.

[0279] FIG. 25 shows the A and B matrices after parity interleaving of the B matrix of FIG.

[0280] FIG. 26 is a diagram showing a C matrix generated from the parity check matrix initial value table of FIG.

[0281] In matrix C in FIG. 26, the element in row #18 of the 1st (=1+5×(1−1))th column of parity check matrix H is 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0282] Each column from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) column of the C matrix is ​​a cyclic shift of the previous column downward by Q2=2.

[0283] Furthermore, in matrix C of Figure 26, in accordance with rows 2 to 5 of the parity check matrix initial value table of Figure 23, the elements of row #19 in the 6th (=1+5×(2-1)) column, row #22 in the 11th (=1+5×(3-1)) column, row #19 in the 16th (=1+5×(4-1)) column, and row #15 in the 21st (=1+5×(5-1)) column of parity check matrix H are 1.

[0284] Each of the columns from the 7th (=2+5×(2-1)) to the 10th (=5+5×(2-1)) columns, the 12th (=2+5×(3-1)) to the 15th (=5+5×(3-1)) columns, the 17th (=2+5×(4-1)) to the 20th (=5+5×(4-1)) columns, and the 22nd (=2+5×(5-1)) to the 25th (=5+5×(5-1)) columns are cyclically shifted downward by Q2=2 from the previous column.

[0285] The check matrix generation section 613 (FIG. 18) generates the C matrix using the check matrix initial value table, and places the C matrix below the A matrix and the B matrix (after parity interleaving).

[0286] Furthermore, parity check matrix generation section 613 places matrix Z to the right of matrix B, and matrix D to the right of matrix C, thereby generating parity check matrix H shown in FIG.

[0287] FIG. 27 is a diagram illustrating parity interleaving of a D matrix.

[0288] After generating the check matrix H of FIG. 26, the check matrix generation unit 613 regards the D matrix as a parity matrix and performs parity interleaving (of only the D matrix) so that elements of 1 in odd-numbered rows and the next even-numbered rows of the unit matrix D matrix are separated in the row direction by a parallel factor P=5.

[0289] FIG. 27 shows the parity check matrix H after D matrix parity interleaving is performed on the parity check matrix H of FIG.

[0290] The LDPC encoder 115 (the encoding parity calculation unit 615 (FIG. 18)) performs LDPC encoding (generation of LDPC code) using, for example, the check matrix H in FIG.

[0291] Here, the LDPC code generated using the parity check matrix H of Fig. 27 is an LDPC code that has been parity interleaved, and therefore, for the LDPC code generated using the parity check matrix H of Fig. 27, there is no need to perform parity interleaving in the parity interleaver 23 (Fig. 9). In other words, the LDPC code generated using the parity check matrix H after parity interleaving of the D matrix is ​​an LDPC code that has been parity interleaved, and therefore, for such an LDPC code, parity interleaving in the parity interleaver 23 is skipped.

[0292] FIG. 28 is a diagram showing a check matrix H in which column permutation is performed on the B matrix, part of the C matrix (the part of the C matrix that is arranged below the B matrix), and the D matrix of the check matrix H in FIG. 27 as parity deinterleaving that restores the parity interleaving to its original state.

[0293] The LDPC encoder 115 can perform LDPC encoding (generation of LDPC codes) using the parity check matrix H in FIG.

[0294] When LDPC coding is performed using the check matrix H in Fig. 28, an LDPC code that is not parity interleaved is obtained by the LDPC coding. Therefore, when LDPC coding is performed using the check matrix H in Fig. 28, parity interleaving is performed in the parity interleaver 23 (Fig. 9).

[0295] FIG. 29 is a diagram showing a transformed parity check matrix H obtained by performing row permutation on the parity check matrix H of FIG.

[0296] As will be described later, the conversion check matrix is ​​a matrix expressed by a combination of a P×P unit matrix, a quasi-unit matrix in which one or more of the 1's in the unit matrix are changed to 0, a shift matrix obtained by cyclically shifting a unit matrix or quasi-unit matrix, a sum matrix which is the sum of two or more of a unit matrix, a quasi-unit matrix, or a shift matrix, and a P×P 0 matrix.

[0297] By using the transformed parity check matrix for decoding an LDPC code, it is possible to employ an architecture for simultaneously performing P check node operations and variable node operations in decoding the LDPC code, as will be described later.

[0298] <New LDPC code>

[0299] In data transmission using LDPC codes, one method for ensuring good communication quality is to use high-performance LDPC codes.

[0300] A new LDPC code with good performance (hereinafter also referred to as a new LDPC code) will be described below.

[0301] As the new LDPC code, for example, a type A code or type B code can be adopted in which the parallel factor P is 360, which is the same as that of DVB-T.2, ATSC3.0, etc., and which corresponds to a check matrix H with a cyclic structure.

[0302] The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC encoding into an LDPC code using a check matrix initial value table (a check matrix H obtained from) of an LDPC code having a code length N longer than 64 k bits, for example, 69120 bits, and a coding rate r of, for example, 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16.

[0303] Furthermore, the LDPC encoder 115 can perform LDPC encoding into a new LDPC code using a check matrix initial value table (a check matrix H obtained from) of a new LDPC code in which the code length N is shorter than 64 k bits, for example, 17280 bits (17 k bits), and the coding rate r is, for example, any one of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16, as shown below.

[0304] When LDPC encoding is performed to obtain a new LDPC code with a code length N of 17280 bits, a check matrix initial value table for the new LDPC code is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).

[0305] FIG. 30 is a diagram showing an example of a check matrix initial value table (for the Type A method) that represents the check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=2 / 16) that is a new LDPC code having a code length N of 17280 bits and a coding rate r of 2 / 16.

[0306] FIG. 31 is a diagram showing an example of a parity check matrix initial value table that represents a parity check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=3 / 16) that is a new LDPC code having a code length N of 17280 bits and a coding rate r of 3 / 16.

[0307] FIG. 32 is a diagram showing an example of a parity check matrix initial value table that represents a parity check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=4 / 16) that is a new LDPC code having a code length N of 17280 bits and a coding rate r of 4 / 16.

[0308] FIG. 33 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=5 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 5 / 16.

[0309] FIG. 34 is a diagram showing an example of a parity check matrix initial value table representing a parity check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=6 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 6 / 16.

[0310] FIG. 35 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=7 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16.

[0311] FIG. 36 is a diagram showing an example of a check matrix initial value table (for the Type B method) that represents the check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=7 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 7 / 16.

[0312] FIG. 37 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=8 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 8 / 16.

[0313] FIG. 38 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=9 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 9 / 16.

[0314] FIG. 39 is a diagram showing an example of a check matrix initial value table that represents a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=10 / 16) that is a new LDPC code having a code length N of 17280 bits and a coding rate r of 10 / 16.

[0315] FIG. 40 is a diagram showing an example of a check matrix initial value table that represents a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=11 / 16) that is a new LDPC code having a code length N of 17280 bits and a coding rate r of 11 / 16.

[0316] FIG. 41 is a diagram showing an example of a check matrix initial value table that represents a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=12 / 16) that is a new LDPC code having a code length N of 17280 bits and a coding rate r of 12 / 16.

[0317] FIG. 42 is a diagram showing an example of a check matrix initial value table that represents a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=13 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 13 / 16.

[0318] FIG. 43 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type B code (hereinafter also referred to as a Type B code with r=14 / 16) as a new LDPC code having a code length N of 17280 bits and a coding rate r of 14 / 16.

[0319] The new LDPC code is an LDPC code with good performance.

[0320] Here, an LDPC code with good performance is an LDPC code obtained from an appropriate check matrix H.

[0321] An appropriate check matrix H is, for example, a check matrix H that can be used to obtain an LDPC code with low E s / N0 or E b / N o It is a check matrix that satisfies certain conditions and reduces the BER (bit error rate) (and FER (frame error rate)) when transmitted at a signal power to noise power ratio per bit.

[0322] An appropriate check matrix H is, for example, a method for converting LDPC codes obtained from various check matrices that satisfy predetermined conditions into low E s / N o This can be obtained by performing a simulation to measure the BER when transmitting at

[0323] The predetermined conditions that an appropriate check matrix H should satisfy include, for example, that the analysis results obtained by a code performance analysis method called Density Evolution are good, that there is no loop of elements of 1, called cycle 4, and so on.

[0324] Here, the information matrix H A It is known that if elements of 1 are concentrated, as in cycle 4, the decoding performance of the LDPC code deteriorates. For this reason, it is desirable that cycle 4 does not exist in the parity check matrix H.

[0325] In the parity check matrix H, the minimum length of a loop formed by elements of 1 (loop length) is called a girth. The absence of a cycle of 4 means that the girth is greater than 4.

[0326] The predetermined conditions that an appropriate check matrix H should satisfy can be determined appropriately from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and so on.

[0327] 44 and 45 are diagrams for explaining density evolution that obtains analysis results as predetermined conditions that an appropriate parity check matrix H should satisfy.

[0328] Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ∞, characterized by a degree sequence (described later).

[0329] For example, in an AWGN channel, if the noise variance is increased from 0, the expected error probability of a certain ensemble is initially 0, but once the noise variance exceeds a certain threshold, it no longer becomes 0.

[0330] According to density evolution, the performance of the ensemble (the appropriateness of the check matrix) can be determined by comparing the threshold of the noise variance (hereinafter referred to as the performance threshold) at which the expected value of the error probability is no longer zero.

[0331] For a specific LDPC code, if the ensemble to which the LDPC code belongs is determined and density evolution is performed on the ensemble, the rough performance of the LDPC code can be predicted.

[0332] Therefore, if an ensemble with good performance is found, an LDPC code with good performance can be found from among the LDPC codes that belong to that ensemble.

[0333] Here, the above-mentioned degree sequence indicates the proportion of variable nodes and check nodes having each weight value with respect to the code length N of the LDPC code.

[0334] For example, a regular (3,6) LDPC code with a coding rate of 1 / 2 belongs to an ensemble characterized by a degree sequence in which all variable nodes have a weight (column weight) of 3 and all check nodes have a weight (row weight) of 6.

[0335] Figure 44 shows the Tanner graph of such an ensemble.

[0336] In the Tanner graph of Figure 44, there are N variable nodes, indicated by circles (○) in the figure, which is equal to the code length N, and there are N / 2 check nodes, indicated by squares (□) in the figure, which is equal to the product of the code length N and the coding rate 1 / 2.

[0337] Each variable node is connected to three edges equal to the column weight, so there are a total of 3N edges connecting to the N variable nodes.

[0338] Each check node is connected to six edges, the number of which is equal to the row weight. Therefore, there are a total of 3N edges connected to the N / 2 check nodes.

[0339] Furthermore, in the Tanner graph of Figure 44, there is one interleaver.

[0340] The interleaver randomly rearranges the 3N branches connected to the N variable nodes, and then connects each rearranged branch to one of the 3N branches connected to the N / 2 check nodes.

[0341] There are (3N)! (=(3N) × (3N-1) × × 1) possible permutation patterns for permuting 3N branches connected to N variable nodes in an interleaver. Therefore, an ensemble characterized by a degree sequence in which all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

[0342] In the simulation to find a high-performance LDPC code (appropriate check matrix), a multi-edge type ensemble was used in density evolution.

[0343] In the multi-edge type, the interleaver through which the branches connected to the variable nodes and the branches connected to the check nodes pass is divided into multiple (multi-edge) sections, which allows for more precise characterization of the ensemble.

[0344] Figure 45 shows an example of a Tanner graph of a multi-edge type ensemble.

[0345] In the Tanner graph of FIG. 45, there are two interleavers: a first interleaver and a second interleaver.

[0346] In addition, in the Tanner graph of Figure 45, there are only v1 variable nodes with one branch connected to the first interleaver and zero branches connected to the second interleaver, only v2 variable nodes with one branch connected to the first interleaver and two branches connected to the second interleaver, and only v3 variable nodes with zero branches connected to the first interleaver and two branches connected to the second interleaver.

[0347] Furthermore, in the Tanner graph of Figure 45, there are only c1 check nodes with two branches connected to the first interleaver and no branches connected to the second interleaver, only c2 check nodes with two branches connected to the first interleaver and two branches connected to the second interleaver, and only c3 check nodes with no branches connected to the first interleaver and three branches connected to the second interleaver.

[0348] Here, density evolution and its implementation are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit," by S.Y. Chung, G.D. Forney, T.J. Richardson, and R. Urbane, IEEE Communications Leggers, Vol. 5, No. 2, February 2001.

[0349] In the simulation to find the new LDPC code (check matrix), the BER starts to drop (become smaller) due to the multi-edge type density evolution. b We found an ensemble where the performance threshold, / N0 (signal power to noise power ratio per bit), is below a specified value, and from among the LDPC codes belonging to that ensemble, we selected the LDPC code that reduces the BER when using orthogonal modulation of 1 or more, such as QPSK, as the LDPC code with good performance.

[0350] The new LDPC code (the check matrix initial value table representing the check matrix of the new LDPC code) was obtained by the above simulation.

[0351] Therefore, the new LDPC code can ensure good communication quality in data transmission.

[0352] FIG. 46 is a diagram for explaining column weights of a check matrix H of a type A code as a new LDPC code.

[0353] As for the check matrix H of the type A code, as shown in FIG. 46, the column weight of the first K1 columns of the A matrix and the C matrix is ​​represented by X1, the column weight of the subsequent K2 columns of the A matrix and the C matrix is ​​represented by X2, the column weight of the further subsequent K3 columns of the A matrix and the C matrix is ​​represented by X3, and the column weight of the further subsequent M1 columns of the C matrix is ​​represented by XM1.

[0354] Note that K1+K2+K3 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+K3+M1+M2 is equal to the code length N=17280 bits.

[0355] In addition, for the check matrix H of the type A code, the column weight of the first to M1-1 columns of the B matrix is ​​2, and the column weight of the M1-th column (the last column) of the B matrix is ​​1. Furthermore, the column weight of the D matrix is ​​1, and the column weight of the Z matrix is ​​0.

[0356] FIG. 47 is a diagram showing parameters of the parity check matrix H of the type A code (represented by the parity check matrix initial value tables) of FIGS.

[0357] K, X1, K1, X2, K2, X3, K3, XM1, M1, and M2 as parameters of the check matrix H of the type A code for r=2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, and 7 / 16 are as shown in FIG. 47.

[0358] The parameters X1, K1, X2, K2, X3, K3, XM1, and M1 (or M2) are set so as to further improve the performance (for example, error rate) of the LDPC code.

[0359] FIG. 48 is a diagram for explaining column weights of a check matrix H of a Type B code as a new LDPC code.

[0360] For the check matrix H of the Type B code, as shown in FIG. 48, the column weight of the first to KX1 columns is represented as X1, the column weight of the subsequent KX2 columns is represented as X2, the column weight of the subsequent KX3 columns is represented as X3, the column weight of the subsequent KX4 columns is represented as X4, and the column weight of the subsequent KY1 columns is represented as Y1.

[0361] Note that KX1+KX2+KX3+KX4+KY1 is equal to the information length K, and KX1+KX2+KX3+KX4+KY1+M is equal to the code length N=17280 bits.

[0362] Furthermore, in the parity check matrix H of the type B code, of the last M columns, the column weight of M−1 columns excluding the last column is 2, and the column weight of the last column is 1.

[0363] FIG. 49 is a diagram showing parameters of the check matrix H of the type B code (represented by the check matrix initial value tables) of FIGS.

[0364] The parameters K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, and M of the check matrix H of the type B code for r=7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16 are as shown in Figure 49.

[0365] The parameters X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, and KY1 are set to further improve the performance of the LDPC code.

[0366] The new LDPC code achieves a good BER / FER and a capacity (channel capacity) close to the Shannon limit.

[0367] <Constellation>

[0368] 50 to 74 are diagrams showing examples of constellations that can be used in the transmission system of FIG.

[0369] In the transmission system of FIG. 7, for example, a constellation to be used in a MODCOD, which is a combination of a modulation method (MODulation) and an LDPC code (CODe), can be set.

[0370] For a MODCOD of 1, more than one constellation can be set.

[0371] Constellations include UC (Uniform Constellation), in which the signal points are arranged uniformly, and NUC (Non Uniform Constellation), in which the signal points are not arranged uniformly.

[0372] In addition, there are various types of NUCs, such as 1D-NUC (1-dimensional (M 2 There are constellations called 2D-NUC (2-dimensional (QQAM) non-uniform constellation) and 2D-NUC (2-dimensional (QQAM) non-uniform constellation).

[0373] In general, 1D-NUC provides a better BER than UC, and 2D-NUC provides a better BER than 1D-NUC.

[0374] The constellation for a QPSK modulation scheme is UC. For example, UC or 2D-NUC can be used as a constellation for modulation schemes such as 16QAM, 64QAM, and 256QAM, and for example, UC or 1D-NUC can be used as a constellation for modulation schemes such as 1024QAM and 4096QAM.

[0375] In the transmission system of FIG. 7, various constellations that improve the error rate, such as constellations defined in ATSC3.0, DVB-C.2, etc., can be used.

[0376] That is, when the modulation method is QPSK, for example, the same UC can be used for each coding rate r of the LDPC code.

[0377] In addition, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, the same UC can be used for each coding rate r of the LDPC code.Furthermore, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, different 2D-NUCs can be used for each coding rate r of the LDPC code.

[0378] In addition, when the modulation method is 1024QAM or 4096QAM, for example, the same UC can be used for each coding rate r of the LDPC code.Furthermore, when the modulation method is 1024QAM or 4096QAM, for example, different 1D-NUCs can be used for each coding rate r of the LDPC code.

[0379] Here, UC of QPSK is also written as QPSK-UC, and m QAM UC, 2 m Also referred to as QAM-UC. m QAM 1D-NUC and 2D-NUC are respectively m QAM-1D-NUC and 2 m Also written as QAM-2D-NUC.

[0380] Below, we will explain some of the constellations specified in ATSC3.0.

[0381] FIG. 50 is a diagram showing the coordinates of QPSK-UC signal points used for all coding rates of LDPC codes specified in ATSC3.0 when the modulation scheme is QPSK.

[0382] In Figure 50, "Input Data cell y" represents a 2-bit symbol to be mapped to QPSK-UC, and "Constellation point z" represents a 2-bit symbol to be mapped to QPSK-UC. s " is the signal point z s The coordinates of the signal point z s The index s of the signal point z q The index q of the symbol sigma is also used), which represents the discrete time of the symbol (the time interval between one symbol and the next symbol).

[0383] In Figure 50, signal point z s The coordinates of are expressed in the form of complex numbers, and j represents the imaginary unit (√(-1)).

[0384] Figure 51 is a diagram showing the coordinates of 16QAM-2D-NUC signal points used for coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 16QAM.

[0385] In Figure 51, as in Figure 50, signal point z s The coordinates of are expressed in the form of complex numbers, and j represents the imaginary unit.

[0386] In FIG. 51, w#k represents the coordinates of the signal point in the first quadrant of the constellation.

[0387] In 2D-NUC, the signal points in the second quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically about the Q axis, the signal points in the third quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically about the origin, and the signal points in the fourth quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically about the I axis.

[0388] Here, the modulation method is 2 m In the case of QAM, m bits are treated as one symbol, and each symbol is mapped to a signal point corresponding to that symbol.

[0389] An m-bit symbol can be, for example, 0 to 2 m It can be expressed as an integer value of -1, but now, b=2 m / 4, 0 to 2 m Symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

[0390] In Figure 51, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) ranging from symbol y(0) to y(b-1).

[0391] The coordinates of the constellation point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), the coordinates of the constellation point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), and the coordinates of the constellation point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

[0392] Here, conj(w#k) represents the complex conjugate of w#k.

[0393] For example, when the modulation method is 16QAM, the m=4-bit symbols y(0), y(1), . . . , y(15) are 4 / 4=4, the symbols are classified into four: y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15).

[0394] Of the symbols y(0) to y(15), for example, symbol y(12) is a symbol y(k+3b)=y(0+3×4) in the range of symbols y(3b) to y(4b−1), where k=0, and therefore the coordinates of the signal point corresponding to symbol y(12) are -w#k=-w0.

[0395] Now, if the coding rate r(CR) of the LDPC code is, for example, 9 / 15, then according to FIG. 51, when the modulation method is 16QAM and the coding rate r is 9 / 15, w0 is 0.2386+j0.5296, and therefore the coordinate −w0 of the signal point corresponding to the symbol y(12) is −(0.2386+j0.5296).

[0396] Figure 52 is a diagram showing an example of the coordinates of 1024QAM-1D-NUC signal points used for coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 1024QAM.

[0397] In FIG. 52, u#k is the signal point z of 1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and are the components of a vector u=(u0, u1,..., u#V-1) called the position vector. The number V of components u#k of the position vector u is given by the formula V=√(2 m ) / 2.

[0398] FIG. 53 is a diagram showing the relationship between the 1024QAM symbol y and the position vector u (component u#k of the position vector u).

[0399] Now, let's consider the 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s This will be expressed as follows.

[0400] A in Figure 53 shows the even-numbered 5 bits of symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to that symbol y s The real part of the coordinates Re(z s ) represents the correspondence with u#k.

[0401] B in Figure 53 shows the odd-numbered 5 bits y of the symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to that symbol y s Imaginary Part Im(z s ) represents the correspondence with u#k.

[0402] 1024QAM 10-bit symbol y=(y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ) is, for example, (0,0,1,0,0,1,1,1,0,0), the odd-numbered 5 bits (y 0,s ,y 2,s,y 4,s ,y 6,s ,y 8,s ) is (0,1,0,1,0), and the even-numbered 5 bits (y 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ) is (0,0,1,1,0).

[0403] In Figure 53A, the even-numbered 5 bits (0,0,1,1,0) are associated with u11, and therefore the signal point z corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11.

[0404] In FIG. 53B, the odd-numbered 5 bits (0,1,0,1,0) are associated with u3, and therefore the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s Imaginary Part Im(z s ) becomes u3.

[0405] On the other hand, if the coding rate r of the LDPC code is, for example, 6 / 15, according to the above-mentioned FIG. 52, for the 1D-NUC used when the modulation method is 1024QAM and the coding rate of the LDPC code r(CR)=6 / 15, u3 is 0.1295 and u11 is 0.7196.

[0406] Therefore, the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11=0.7196, and the imaginary part Im(z s ) results in u3=0.1295. As a result, the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The coordinates of are expressed as 0.7196+j0.1295.

[0407] In addition, the signal points of 1D-NUC are arranged in a grid pattern on a line parallel to the I axis or a line parallel to the Q axis in the constellation. However, the intervals between signal points are not constant. In addition, when transmitting the signal points (data mapped to them), the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all the signal points (coordinates of the signal points) on the constellation as P ave Then, the mean square value P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z on the constellation s This can be done by multiplying

[0408] The transmission system of FIG. 7 can use the constellations defined in ATSC 3.0 as described above.

[0409] 54 to 65 are diagrams showing the coordinates of UC signal points defined in DVB-C.2.

[0410] That is, FIG. 54 shows the coordinates z of the signal point of QPSK-UC (UC of QPSK) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the signal point of QPSK-UC defined in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0411] Figure 56 shows the coordinates z of the signal point of 16QAM-UC (UC of 16QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 16QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0412] Figure 58 shows the coordinates z of the signal point of 64QAM-UC (UC of 64QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 64QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0413] Figure 60 shows the coordinates z of the signal point of 256QAM-UC (UC of 256QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 256QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0414] Figure 62 shows the coordinates z of the signal point of 1024QAM-UC (UC of 1024QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 1024QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0415] Figure 64 shows the coordinates z of the signal point of 4096QAM-UC (UC of 4096QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 4096QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0416] In addition, in Figures 54 to 65, y i,q is 2 mIt represents the (i+1)th bit from the beginning of the m-bit QAM symbol (for example, 2 bits in QPSK). In addition, when transmitting (data mapped to) a UC signal point, the average power of the signal point on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all of the signal points (coordinates of the signal points) on the constellation as P ave Then, the mean square value P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z on the constellation q This can be done by multiplying

[0417] In the transmission system of FIG. 7, the UC defined in DVB-C.2 as described above can be used.

[0418] That is, for the new LDPC codes (corresponding to the check matrix initial value tables) in Figures 30 to 43 where the code length N is 17280 bits and the coding rate r is 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16, the UCs shown in Figures 54 to 65 can be used.

[0419] 66 to 74 are diagrams showing examples of coordinates of NUC signal points that can be used for the new LDPC codes in FIGS. 30 to 43, where the code length N is 17280 bits and the coding rate r is 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16.

[0420] That is, FIG. 66 is a diagram showing an example of the coordinates of 16QAM-2D-NUC signal points that can be used for the new LDPC code.

[0421] FIG. 67 is a diagram showing an example of the coordinates of 64QAM-2D-NUC signal points that can be used for the new LDPC code.

[0422] 68 and 69 are diagrams showing examples of the coordinates of 256QAM-2D-NUC signal points that can be used for the new LDPC code.

[0423] Note that FIG. 69 is a continuation of FIG.

[0424] In Figures 66 to 69, similarly to Figure 51, signal point z s The coordinates of are expressed in the form of complex numbers, and j represents the imaginary unit.

[0425] 66 to 69, w#k represents the coordinates of the signal point in the first quadrant of the constellation, as in FIG.

[0426] Here, as explained in FIG. 51, the m-bit symbol is divided into 0 to 2 m It is expressed as an integer value of -1, and b=2 m / 4, 0 to 2 m Symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

[0427] In Figures 66 to 69, as in Figure 51, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) ranging from symbol y(0) to y(b-1).

[0428] Furthermore, in Figures 66 to 69, as in Figure 51, the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are expressed as -w#k.

[0429] However, in Figure 51, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), but in Figures 66 to 69, the sign of conj is reversed.

[0430] That is, in Figures 66 to 69, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by -conj(w#k).

[0431] FIG. 70 is a diagram showing an example of the coordinates of 1024QAM-1D-NUC signal points that can be used for the new LDPC code.

[0432] That is, FIG. 70 shows the signal point z of 1024QAM-1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and the position vector u (its component u#k).

[0433] FIG. 71 is a diagram showing the relationship between the 1024QAM symbol y and the position vector u (component u#k of the vector) in FIG.

[0434] That is, let us now consider a 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s This will be expressed as follows.

[0435] A in Figure 71 shows the odd-numbered 5 bits y (from the beginning) of the 10-bit symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to that symbol y s (coordinates) real part Re(z s ) and the position vector u#k.

[0436] B in Figure 71 shows the even-numbered 5 bits y of the 10-bit symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to that symbol y s Imaginary Part Im(z s ) and the position vector u#k.

[0437] The 10-bit symbol y of 1024QAM corresponds to the signal point z of 1024QAM-1D-NUC defined in Figures 70 and 71. s When the signal point z is mapped to s The method for determining the coordinates is the same as that explained in FIGS. 52 and 53, so the explanation will be omitted.

[0438] FIG. 72 is a diagram showing an example of the coordinates of 4096QAM-1D-NUC signal points that can be used for the new LDPC code.

[0439] That is, FIG. 72 shows the signal point z of 4096QAM-1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and the position vector u(u#k).

[0440] 73 and 74 are diagrams showing the relationship between the 4096QAM symbol y and the position vector u (component u#k of the vector) in FIG.

[0441] That is, let us now consider a 12-bit symbol y of 4096QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ,y 10,s ,y 11,s This will be expressed as follows.

[0442] Figure 73 shows the odd-numbered 6 bits y of the 12-bit symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s ,y 10,s and the signal point z corresponding to that symbol y s The real part of Re(z s ) and the position vector u#k.

[0443] Figure 74 shows the even-numbered 6 bits y of the 12-bit symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ,y 11,s and the signal point z corresponding to that symbol y s Imaginary Part Im(z s ) and the position vector u#k.

[0444] The 12-bit symbol y of 4096QAM corresponds to the signal point z of 4096QAM-1D-NUC defined in Figures 72 to 74. s When the signal point z is mapped to s The method for determining the coordinates is the same as that explained in FIGS. 52 and 53, so the explanation will be omitted.

[0445] When transmitting the NUC signal points (data mapped to them) in Figures 66 to 74, the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all of the signal points (coordinates) on the constellation as P ave Then, the mean square value P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z on the constellation s In addition, in FIG. 53, odd-numbered bits of symbol y are multiplied by signal point z. s Imaginary Part Im(z s ) and the even-numbered bits of the symbol y correspond to the signal point z s The real part of Re(z s ), but in Figures 71, 73 and 74, the odd-numbered bits of the symbol y correspond to the signal point z s The real part of Re(z s ) and the even-numbered bits of the symbol y correspond to the signal point z s Imaginary Part Im(z s ) is associated with a position vector u#k representing the

[0446] <Block Interleaver 25>

[0447] FIG. 75 is a diagram for explaining the block interleaving performed by the block interleaver 25 of FIG.

[0448] Block interleaving is performed by dividing an LDPC code of one codeword into a part called part 1 and a part called part 2, starting from the beginning.

[0449] If the length (number of bits) of part 1 is represented as Npart1 and the length of part 2 is represented as Npart2, then Npart1+Npart2 is equal to the code length N.

[0450] Conceptually, in block interleaving, columns as storage areas for storing Npart1 / m bits are arranged in one direction (vertical) as a column direction, and m columns, which is equal to the number of bits m of a symbol, are arranged in a row direction perpendicular to the column direction, and each column is divided from the top into small units of 360 bits, which is the parallel factor P. These small units of columns are also called column units.

[0451] In block interleaving, as shown in FIG. 75, part 1 of an LDPC code of one codeword is written from top to bottom (column direction) in the first column unit of a column, moving from left to right toward the column.

[0452] Then, when writing to the first column unit of the rightmost column is completed, as shown in Figure 75, it returns to the leftmost column and writing from top to bottom of the second column unit of the column is performed from left to right column, and so on, and so on, writing part 1 of one codeword LDPC code is performed.

[0453] When writing of part 1 of the LDPC code of one codeword is completed, part 1 of the LDPC code is read out in m-bit units in the row direction from the first row of all m columns, as shown in FIG.

[0454] The m-bit units of part 1 are supplied as m-bit symbols from block interleaver 25 to mapper 117 (FIG. 8).

[0455] Part 1 is read out in m-bit units sequentially moving down the m columns, and when reading of part 1 is completed, part 2 is divided into m-bit units from the beginning and supplied as m-bit symbols from block interleaver 25 to mapper 117.

[0456] Therefore, part 1 is symbolized while being interleaved, and part 2 is symbolized sequentially, separated into m bits, without being interleaved.

[0457] The length of the column, Npart1 / m, is a multiple of 360, which is the parallel factor P, and an LDPC code of one code word is divided into part 1 and part 2 so that Npart1 / m is a multiple of 360.

[0458] FIG. 76 is a diagram showing examples of part 1 and part 2 of an LDPC code with a code length N of 69120 bits when the modulation scheme is QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

[0459] In Figure 76, when the modulation method is 1024QAM, part 1 is 68,400 bits and part 2 is 720 bits, and when the modulation method is QPSK, 16QAM, 64QAM, 256QAM, or 4096QAM, in all cases part 1 is 69,120 bits and part 2 is 0 bits.

[0460] <Group-wise interleaving>

[0461] FIG. 77 is a diagram for explaining group-wise interleaving performed by the group-wise interleaver 24 of FIG.

[0462] In group-wise interleaving, as shown in FIG. 77, the LDPC code of one codeword is divided into 360-bit units, which is equal to the parallel factor P, from the beginning, and the 360 ​​bits of each unit are treated as a bit group, and the LDPC code of one codeword is interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as a GW pattern).

[0463] Here, when an LDPC code of one codeword is divided into bit groups, the (i+1)th bit group from the beginning will hereinafter also be referred to as bit group i.

[0464] When the parallel factor P is 360, for example, an LDPC code having a code length N of 1800 bits is divided into 5 (=1800 / 360) bit groups, namely, bit groups 0, 1, 2, 3, and 4. Furthermore, for example, an LDPC code having a code length N of 69120 bits is divided into 192 (=69120 / 360) bit groups, namely, bit groups 0, 1, . . . , 191. Furthermore, for example, an LDPC code having a code length N of 17280 bits is divided into 48 (=17280 / 360) bit groups, namely, bit groups 0, 1, . . . , 47.

[0465] In the following, the GW pattern will be represented by a sequence of numbers representing the bit group. For example, for an LDPC code with a code length N of 1800 bits and five bit groups 0, 1, 2, 3, 4, a GW pattern of 4, 2, 0, 3, 1 indicates that the sequence of bit groups 0, 1, 2, 3, 4 is interleaved (rearranged) into the sequence of bit groups 4, 2, 0, 3, 1.

[0466] For example, let us consider the i+1th code bit from the beginning of an LDPC code whose code length N is 1800 bits as x i Let us express it as:

[0467] In this case, according to the group-wise interleaving of GW pattern 4,2,0,3,1, the 1800-bit LDPC code {x0,x1,...,x 1799} is {x 1440 ,x 1441 ,...,x 1799},{x 720 ,x 721 ,...,x 1079},{x0,x1,...,x 359},{x 1080 ,x 1081 ,...,x 1439},{x 360 ,x 361 ,...,x 719} are interleaved.

[0468] The GW pattern can be set for each code length N of the LDPC code, for each coding rate r, for each modulation method, for each constellation, and further for each combination of two or more of the code length N, coding rate r, modulation method, and constellation.

[0469] <Example of GW Pattern for LDPC Code>

[0470] FIG. 78 is a diagram showing an example of a GW pattern for an LDPC code with a code length N of 69,120 bits.

[0471] According to the GW pattern of FIG. 78, the arrangement of bit groups 0 to 191 of the 69,120-bit LDPC code is the bit group 191, 12, 188, 158, 173, 48, 75, 146, 113, 15, 51, 119, 132, 161, 91, 189, 142, 93, 120, 29, 156, 101, 100, 22, 165, 65, 98, 153, 127, 74, 39, 80, 38, 130, 148, 81, 13, 24, 125, 0, 174, 140, 124, 5, 68, 3, 104, 136, 63, 162, 106, 8, 25, 182, 178, 90, 96, 79, 168, 172, 128, 64, 69, 102, 45, 66, 86, 155, 163, 6, 152, 164, 108, 9, 111, 16, 177, 53, 94, 85, 72, 32, 147, 184, 117, 30, 54, 34, 70, 149, 157, 109, 73, 41, 131, 187, 185, 18, 4, 150, 92, 143, 14, 115, 20, 50, 26, 83, 36, 58, 169, 107, 129, 121, 43, 103, 21, 139, 52, 167, 19, 2, 40, 116, 181, 61, 141, 17, 33, 11, 135, 1, 37, 123, 180, 137, 77, 166, 183, 82, 23, 56, 88, 67, 176, 76, 35, 71, 105, 87, 78, 171, 55, 62, 44, 57, 97, 122, 112, 59, 27, 99, 84, 10, 134, 42, 118, 144, 49, 28, 126, 95, 7, 110, 186, 114, 151, 145, 175, 138, 133, 31, 179, 89, 46, 160, 170, 60, 154, 159, 47, 190 are interleaved in the sequence.

[0472] <Configuration example of receiving device 12>

[0473] FIG. 79 is a block diagram showing an example of the configuration of the receiving device 12 of FIG.

[0474] The OFDM operation unit 151 receives an OFDM signal from the transmitting device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data obtained by the signal processing by the OFDM operation unit 151 is supplied to a frame management unit (Frame Management) 152.

[0475] The frame management unit 152 processes (frame interpretation) the frames composed of data supplied from the OFDM processing unit 151, and supplies the resulting target data signal and control data signal to frequency deinterleavers 161 and 153, respectively.

[0476] The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a demapper 154 .

[0477] The demapper 154 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (data on a constellation) from the frequency deinterleaver 153 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data (LDPC code (likelihood)) to an LDPC decoder 155.

[0478] The LDPC decoder 155 (decoding unit) performs LDPC decoding on the LDPC code from the demapper 154 and supplies the resulting LDPC target data (here, BCH code) to a BCH decoder 156.

[0479] The BCH decoder 156 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and outputs the resulting control data (signaling).

[0480] On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a SISO / MISO decoder 162 .

[0481] The SISO / MISO decoder 162 performs space-time decoding on the data from the frequency deinterleaver 161 and supplies the result to a time deinterleaver 163 .

[0482] The time deinterleaver 163 performs time deinterleaving on the data from the SISO / MISO decoder 162 in units of symbols, and supplies the result to a demapper 164 .

[0483] The demapper 164 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (data on a constellation) from the time deinterleaver 163 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data to a bit deinterleaver 165.

[0484] The bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164 and supplies the LDPC code (likelihood), which is the bit deinterleaved data, to the LDPC decoder 166.

[0485] The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165 and supplies the resulting LDPC target data (here, BCH code) to the BCH decoder 167.

[0486] The BCH decoder 167 performs BCH decoding on the LDPC target data from the LDPC decoder 155 and supplies the resulting data to a BB descrambler 168 .

[0487] The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to a null deletion unit (Null Deletion) 169 .

[0488] The null deletion unit 169 deletes the nulls inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the data to a demultiplexer 170 .

[0489] The demultiplexer 170 separates one or more streams (target data) multiplexed into the data from the null deletion unit 169, performs necessary processing, and outputs the result as an output stream.

[0490] The receiving device 12 can be configured without some of the blocks shown in Fig. 79. That is, for example, when the transmitting device 11 (Fig. 8) is configured without the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiving device 12 can be configured without the time deinterleaver 163, the SISO / MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153, which are blocks corresponding to the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmitting device 11, respectively.

[0491] <Configuration example of bit deinterleaver 165>

[0492] FIG. 80 is a block diagram showing an example of the configuration of the bit deinterleaver 165 of FIG.

[0493] The bit deinterleaver 165 is made up of the block deinterleaver 54 and the group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols that are the data from the demapper 164 (FIG. 79).

[0494] That is, the block deinterleaver 54 performs block deinterleaving (the reverse process of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 of Figure 9 on the symbol bits of the symbol from the demapper 164, that is, block deinterleaving that returns the positions of the code bits (of the likelihoods) of the LDPC code rearranged by block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0495] The group-wise deinterleaver 55 performs group-wise deinterleaving (the reverse process of group-wise interleaving) on ​​the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving performed by the group-wise interleaver 24 in Figure 9. That is, the group-wise deinterleaving restores the original arrangement of the code bits of the LDPC code, whose arrangement has been changed on a bit group basis by the group-wise interleaving described in Figure 77, by rearranging them on a bit group basis.

[0496] Here, when the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has been subjected to parity interleaving, group-wise interleaving, and block interleaving, the bit deinterleaver 165 can perform all of the following: parity deinterleaving corresponding to parity interleaving (the inverse process of parity interleaving, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by parity interleaving to their original order), block deinterleaving corresponding to block interleaving, and group-wise deinterleaving corresponding to group-wise interleaving.

[0497] However, in the bit deinterleaver 165 of Figure 80, a block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving and a group-wise deinterleaver 55 that performs group-wise deinterleaving corresponding to group-wise interleaving are provided, but a block that performs parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

[0498] Therefore, the LDPC decoder 166 is supplied with an LDPC code that has been block deinterleaved and group-wise deinterleaved, but not parity deinterleaved, from the bit deinterleaver 165 (the group-wise deinterleaver 55 thereof).

[0499] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a transformed parity check matrix obtained by performing at least column permutation equivalent to parity interleaving on the parity check matrix H of the Type B method used for LDPC encoding by the LDPC encoder 115 of FIG. 8, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation on the parity check matrix of the Type A method (FIG. 27), and outputs the resulting data as the decoded result of the LDPC target data.

[0500] FIG. 81 is a flowchart illustrating the processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166 in FIG.

[0501] In step S111, the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to signal points), and supplies the data to the bit deinterleaver 165, and the process proceeds to step S112.

[0502] In step S112, the bit deinterleaver 165 deinterleaves (bit deinterleaves) the data from the demapper 164, and the process proceeds to step S113.

[0503] That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbols) from the demapper 164, and supplies the resulting code bits of the LDPC code to the group-wise deinterleaver 55.

[0504] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, and supplies the resulting LDPC code (the likelihood of the LDPC code) to the LDPC decoder 166.

[0505] In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 using the check matrix H that the LDPC encoder 115 of FIG. 8 used for LDPC encoding, that is, using, for example, a converted check matrix obtained from the check matrix H, and outputs the resulting data to the BCH decoder 167 as the decoded result of the LDPC target data.

[0506] In Figure 80, as in Figure 9, for the sake of convenience of explanation, the block deinterleaver 54 that performs block deinterleaving and the group-wise deinterleaver 55 that performs group-wise deinterleaving are configured separately, but the block deinterleaver 54 and the group-wise deinterleaver 55 can be configured as an integrated unit.

[0507] Furthermore, if group-wise interleaving is not performed in transmitting device 11, receiving device 12 can be configured without providing group-wise deinterleaver 55 that performs group-wise deinterleaving.

[0508] <LDPC Decoding>

[0509] The LDPC decoding performed by the LDPC decoder 166 in FIG. 79 will be further described.

[0510] In the LDPC decoder 166 in FIG. 79, as described above, block deinterleaving and group-wise deinterleaving are performed on the LDPC code from the group-wise deinterleaver 55, and LDPC decoding of the LDPC code without parity deinterleaving is performed using a transformed check matrix obtained by performing at least column permutation corresponding to parity deinterleaving on the type B check matrix H used by the LDPC encoder 115 in FIG. 8 for LDPC encoding, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the type A check matrix (FIG. 27).

[0511] Here, LDPC decoding using a transformed check matrix has been previously proposed (see, for example, Japanese Patent No. 4224777), which can suppress the circuit scale and keep the operating frequency within a sufficiently achievable range.

[0512] Therefore, first, referring to FIGS. 82 to 85, the previously proposed LDPC decoding using a transformed check matrix will be described.

[0513] FIG. 82 is a diagram showing an example of the check matrix H of an LDPC code with a code length N of 90 and a coding rate of 2 / 3.

[0514] In FIG. 82 (the same applies to FIGS. 83 and 84 described later), 0 is represented by a period (.).

[0515] In the check matrix H of FIG. 82, the parity matrix has a staircase structure.

[0516] FIG. 83 is a diagram showing the check matrix H' obtained by performing row permutation of Equation (11) and column permutation of Equation (12) on the check matrix H of FIG. 82.

[0517] Line replacement: 6s+t+1st line → 5t+s+1st line ···(11)

[0518] Column replacement: 6x+y+61st column → 5y+x+61st column ···(12)

[0519] In the formulas (11) and (12), s, t, x, and y are integers in the ranges of 0≦s<5, 0≦t<6, 0≦x<5, and 0≦t<6, respectively.

[0520] According to the row permutation of equation (11), lines 1, 7, 13, 19, and 25, which have a remainder of 1 when divided by 6, are permuted into lines 1, 2, 3, 4, and 5, respectively, and lines 2, 8, 14, 20, and 26, which have a remainder of 2 when divided by 6, are permuted into lines 6, 7, 8, 9, and 10, respectively.

[0521] Furthermore, according to the column permutation in equation (12), for columns 61 and beyond (parity matrix), columns 61, 67, 73, 79, and 85, which have a remainder of 1 when divided by 6, are permuted as columns 61, 62, 63, 64, and 65, respectively, and columns 62, 68, 74, 80, and 86, which have a remainder of 2 when divided by 6, are permuted as columns 66, 67, 68, 69, and 70, respectively.

[0522] In this way, the matrix obtained by permuting rows and columns on the parity check matrix H in FIG. 82 is the parity check matrix H' in FIG.

[0523] Here, even if row permutation is performed on the check matrix H, it does not affect the arrangement of code bits of the LDPC code.

[0524] Furthermore, the column permutation in equation (12) corresponds to the parity interleaving described above, in which the K+qx+y+1-th code bit is interleaved at the K+Py+x+1-th code bit position, when the information length K is 60, the parallel factor P is 5, and the divisor q (=M / P) of the parity length M (here, 30) is 6.

[0525] Therefore, the check matrix H' in Figure 83 is a transformed check matrix obtained by at least performing column permutation to replace the K+qx+y+1-th column of the check matrix H in Figure 82 (hereinafter referred to as the original check matrix, as appropriate) with the K+Py+x+1-th column.

[0526] For the converted parity check matrix H' in Figure 83, when the LDPC code of the original parity check matrix H in Figure 82 is multiplied by the one that has been permuted the same as in equation (12), a zero vector is output. That is, when the row vector c as the LDPC code (1 codeword) of the original parity check matrix H is permuted by the column in equation (12) and the row vector obtained is expressed as c', from the properties of the parity check matrix, Hc T is a 0 vector, so H'c' T Naturally, this also becomes a zero vector.

[0527] From the above, the converted parity check matrix H' in FIG. 83 is a parity check matrix of an LDPC code c' obtained by performing the column permutation of equation (12) on the LDPC code c of the original parity check matrix H.

[0528] Therefore, by performing the column permutation of equation (12) on the LDPC code c of the original check matrix H, and then decoding (LDPC decoding) the LDPC code c' after the column permutation using the converted check matrix H' in FIG. 83, and then performing the inverse permutation of the column permutation of equation (12) on the decoded result, it is possible to obtain the same decoding result as when the LDPC code of the original check matrix H is decoded using that check matrix H.

[0529] FIG. 84 is a diagram showing the converted parity check matrix H' of FIG. 83, with intervals provided in units of a 5×5 matrix.

[0530] In Figure 84, the conversion check matrix H' is expressed as a combination of a 5x5 (=PxP) identity matrix, which is the parallel factor P; a matrix in which one or more of the 1s in the identity matrix have become 0 (hereinafter referred to as a quasi-identity matrix, as appropriate); a matrix in which the identity matrix or quasi-identity matrix has been cyclically shifted (hereinafter referred to as a shift matrix, as appropriate); a sum of two or more identity matrices, quasi-identity matrices, or shift matrices (hereinafter referred to as a sum matrix, as appropriate); and a 5x5 0 matrix.

[0531] It can be said that the transformation check matrix H' in Figure 84 is composed of a 5x5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a 0 matrix. Therefore, these 5x5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, and 0 matrix) that compose the transformation check matrix H' will hereinafter be referred to as constituent matrices as appropriate.

[0532] For decoding an LDPC code of a parity check matrix represented by a P×P constituent matrix, an architecture that simultaneously performs P check node operations and P variable node operations can be used.

[0533] FIG. 85 is a block diagram showing an example of the configuration of a decoding device that performs such decoding.

[0534] That is, FIG. 85 shows an example of the configuration of a decoding device that decodes an LDPC code using a transformed check matrix H′ in FIG. 84 obtained by performing at least the column permutation of equation (12) on the original check matrix H in FIG. 82.

[0535] The decoding device of FIG. 85 includes an edge data storage memory 300 consisting of six FIFOs 3001 to 3006, a selector 301 for selecting one of the FIFOs 3001 to 3006, a check node calculation unit 302, two cyclic shift circuits 303 and 308, and 18 FIFOs 3041 to 3044. 18 The edge data storage memory 304 includes FIFOs 3041 to 3044. 18 a receive data memory 306 for storing the receive data, a variable node calculation unit 307, a decoded word calculation unit 309, a receive data rearrangement unit 310, and a decoded data rearrangement unit 311.

[0536] First, the method of storing data in the edge data storage memories 300 and 304 will be described.

[0537] The edge data storage memory 300 is composed of six FIFOs 3001 to 3006, the number of which is obtained by dividing the number of rows of the conversion check matrix H' in FIG. 84 (30) by the number of rows of the constituent matrix (parallel factor P) (5). y (y=1, 2, . . . , 6) consists of a storage area with multiple stages, and the storage area of ​​each stage can simultaneously read and write messages corresponding to five branches, which are the number of rows and columns (parallel factor P) of the constituent matrix. y The number of stages of the storage area is 9, which is the maximum number of 1s (Hamming weights) in the row direction of the transformed check matrix in FIG.

[0538] The FIFO 3001 stores data corresponding to the positions of 1 from the first row to the fifth row of the transformation check matrix H′ in FIG. 84 (message v from the variable node). i ) are stored in a form that is packed horizontally in each row (with zeros ignored). That is, if the j-th row and i-th column are represented as (j,i), the first-stage storage area of ​​FIFO 3001 stores data corresponding to the positions of 1 in the 5×5 identity matrix from (1,1) to (5,5) of the transformed parity check matrix H'. The second-stage storage area stores data corresponding to the positions of 1 in the shift matrix from (1,21) to (5,25) of the transformed parity check matrix H' (a shift matrix obtained by cyclically shifting the 5×5 identity matrix by three places to the right). Similarly, the third to eighth-stage storage areas store data in association with the transformed parity check matrix H'. Then, the ninth-stage storage area stores data corresponding to the positions of 1 in the shift matrix from (1,86) to (5,90) of the transformed parity check matrix H' (a shift matrix obtained by replacing the 1 in the first row of the 5×5 identity matrix with a 0 and cyclically shifting it by one place to the left).

[0539] FIFO3002 stores data corresponding to the positions of 1 in the sixth to tenth rows of the transformed parity check matrix H' in Fig. 84. That is, the first-stage storage area of ​​FIFO3002 stores data corresponding to the positions of 1 in the first shift matrix that constitutes the sum matrix of (6,1) to (10,5) of the transformed parity check matrix H' (the sum matrix is ​​the sum of a first shift matrix obtained by cyclically shifting a 5x5 identity matrix by one position to the right and a second shift matrix obtained by cyclically shifting a 5x5 identity matrix by two positions to the right). Also, the second-stage storage area stores data corresponding to the positions of 1 in the second shift matrix that constitutes the sum matrix of (6,1) to (10,5) of the transformed parity check matrix H'.

[0540] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1 elements of the identity matrix have become 0, or a shift matrix obtained by cyclically shifting the identity matrix or quasi-identity matrix, data corresponding to the position of 1 in the identity matrix, quasi-identity matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the identity matrix, quasi-identity matrix, or shift matrix) is stored at the same address (the same FIFO among FIFOs 3001 to 3006).

[0541] Similarly, in the storage areas in the third to ninth stages, data is stored in association with the converted check matrix H'.

[0542] Similarly, FIFOs 3003 to 3006 store data in association with the conversion check matrix H'.

[0543] The edge data storage memory 304 has 18 FIFOs 3041 to 3044, which are obtained by dividing the number of columns of the conversion check matrix H', 90, by the number of columns of the constituent matrix (parallel factor P), 5. 18 It consists of FIFO304 x(x=1,2,...,18) consists of multiple stages of memory areas, and each stage of the memory area can simultaneously read and write messages corresponding to five branches, which are the number of rows and columns (parallel factor P) of the constituent matrix.

[0544] The FIFO 3041 stores data corresponding to the positions of 1 in the first to fifth columns of the conversion check matrix H' in FIG. 84 (message u from the check node). j ) are stored in a vertically packed manner (ignoring zeros) in each column. That is, the first-stage storage area of ​​FIFO 3041 stores data corresponding to the positions of 1 in the 5×5 identity matrix from (1,1) to (5,5) of transformed parity check matrix H'. The second-stage storage area stores data corresponding to the positions of 1 in the first shift matrix constituting the sum matrix from (6,1) to (10,5) of transformed parity check matrix H' (the sum matrix is ​​the sum of a first shift matrix obtained by cyclically shifting the 5×5 identity matrix by one position to the right and a second shift matrix obtained by cyclically shifting the 5×5 identity matrix by two positions to the right). The third-stage storage area stores data corresponding to the positions of 1 in the second shift matrix constituting the sum matrix from (6,1) to (10,5) of transformed parity check matrix H'.

[0545] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1 elements of the identity matrix are 0, or a shift matrix obtained by cyclically shifting the identity matrix or quasi-identity matrix, data corresponding to the position of 1 in the identity matrix, quasi-identity matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the identity matrix, quasi-identity matrix, or shift matrix) are stored at the same address (FIFO 3041 to 3044). 18 The data is stored in the same FIFO.

[0546] Similarly, data is stored in the fourth and fifth storage areas in association with the transformed check matrix H'. The number of storage areas in this FIFO 3041 is 5, which is the maximum number of 1s (Hamming weights) in the row direction in the first to fifth columns of the transformed check matrix H'.

[0547] FIFOs 3042 and 3043 similarly store data in association with the conversion check matrix H', and each has a length (number of stages) of 5. 12 Similarly, FIFO 304 stores data in association with the converted check matrix H′, and each has a length of 3. 13 or 304 18 Similarly, data is stored in association with the converted check matrix H′, and each has a length of 2.

[0548] Next, the operation of the decoding device shown in FIG. 85 will be described.

[0549] The edge data storage memory 300 is made up of six FIFOs 3001 to 3006, and selects a FIFO from FIFOs 3001 to 3006 to store data in, according to information (Matrix data) D312 indicating to which row of the conversion check matrix H' in FIG. 84 the five messages D311 supplied from the preceding-stage cyclic shift circuit 308 belong, and stores the five messages D311 collectively in the selected FIFO in order. When reading data, the edge data storage memory 300 reads the five messages D3001 in order from FIFO 3001 and supplies them to the next-stage selector 301. After finishing reading the messages from FIFO 3001, the edge data storage memory 300 also reads messages in order from FIFOs 3002 to 3006 and supplies them to the selector 301.

[0550] Selector 301 selects five messages from the FIFO from which data is currently being read out of FIFOs 3001 to 3006 in accordance with select signal D301, and supplies them to check node calculation unit 302 as message D302.

[0551] The check node calculation unit 302 is composed of five check node calculators 3021 to 3025, and receives the message D302 (D3021 to D3025) (the message v in Equation (7)) supplied through the selector 301. i ), check node calculation is performed according to formula (7), and five messages D303 (D3031 to D3035) obtained as a result of the check node calculation (message u in formula (7)) are j ) is supplied to the cyclic shift circuit 303.

[0552] The cyclic shift circuit 303 cyclically shifts the five messages D3031 to D3035 calculated by the check node calculation unit 302 based on information (Matrix data) D305 indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) of the corresponding branch in the transformed parity check matrix H' has been made, and supplies the result as message D304 to the branch data storage memory 304.

[0553] The edge data storage memory 304 includes 18 FIFOs 3041 to 3044. 18 The FIFOs for storing data are selected from FIFOs 3041 to 3044 according to information D305 indicating which row of the converted check matrix H' the five messages D304 supplied from the previous stage cyclic shift circuit 303 belong to. 18 The edge data storage memory 304 selects one of the messages D3061 from the FIFO 3041 and stores the five messages D304 in the selected FIFO in order. When reading data, the edge data storage memory 304 reads five messages D3061 from the FIFO 3041 in order and supplies them to the next stage selector 305. After reading data from the FIFO 3041, the edge data storage memory 304 reads five messages D3061 from the FIFO 3042 to 3044 in order. 18 , and supplies the messages to the selector 305.

[0554] The selector 305 selects one of the FIFOs 3041 to 3044 according to the select signal D307. 18Among these, five messages are selected from the FIFO from which data is currently being read, and are supplied to the variable node calculation unit 307 and the decoded word calculation unit 309 as message D308.

[0555] On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 received through the communication channel 13 and corresponding to the parity check matrix H in FIG. 82 by performing column permutation of equation (12), and supplies the resulting data as received data D314 to the received data memory 306. The received data memory 306 calculates and stores received LLRs (log-likelihood ratios) from the received data D314 supplied from the received data rearrangement unit 310, and supplies these received LLRs in groups of five as received values ​​D309 to the variable node calculation unit 307 and the decoded word calculation unit 309.

[0556] The variable node calculation unit 307 is composed of five variable node calculators 3071 to 3075, and receives the message D308 (D3081 to D3085) (message u in Equation (1)) supplied through the selector 305. j ) and five received values ​​D309 (received values ​​u in Equation (1)) supplied from the received data memory 306. 0i ) to perform a variable node operation according to the formula (1), and the message D310 (D3101 to D3105) obtained as a result of the operation (the message v i ) is supplied to the cyclic shift circuit 308.

[0557] The cyclic shift circuit 308 cyclically shifts the messages D3101 to D3105 calculated by the variable node calculation unit 307 based on information indicating how many cyclic shifts the original unit matrix (or quasi-unit matrix) in the transformation check matrix H' that the corresponding edge is made by, and supplies the result as message D311 to the edge data storage memory 300.

[0558] By repeating the above operations once, one decoding of the LDPC code (variable node calculation and check node calculation) can be performed. After the decoding device in Fig. 85 decodes the LDPC code a predetermined number of times, the decoded word calculation unit 309 and the decoded data rearrangement unit 311 calculate and output the final decoding result.

[0559] That is, the decoded word calculation unit 309 is composed of five decoded word calculators 3091 to 3095, and the five messages D308 (D3081 to D3085) (message u in equation (5)) output by the selector 305 are j ) and five received values ​​D309 (received values ​​u in Equation (5)) supplied from the received data memory 306. 0i ), and calculates the decoding result (decoded word) based on equation (5) as the final stage of multiple decoding operations, and supplies the resulting decoded data D315 to the decoded data rearrangement unit 311.

[0560] The decoded data rearrangement unit 311 rearranges the order of the decoded data D315 supplied from the decoded word calculation unit 309 by performing the inverse permutation of the column permutation in equation (12), and outputs the result as the final decoded result D316.

[0561] As described above, by carrying out one or both of row permutation and column permutation on a parity check matrix (original parity check matrix), and converting it into a P×P identity matrix, a quasi-identity matrix in which one or more of the 1s in its elements are changed to 0, a shift matrix in which an identity matrix or a quasi-identity matrix is ​​cyclically shifted, a sum matrix which is a sum of a plurality of identity matrices, a quasi-identity matrix, or a shift matrix, a combination of P×P 0 matrices, that is, a parity check matrix (transformed parity check matrix) that can be expressed by a combination of constituent matrices, it becomes possible to adopt an architecture for decoding LDPC codes, in which P check node operations and variable node operations are simultaneously performed, the number of which is smaller than the number of rows or columns of a parity check matrix.When adopting an architecture in which P node operations (check node operations and variable node operations) are simultaneously performed, the number of which is smaller than the number of rows or columns of a parity check matrix, it is possible to suppress the operating frequency within a feasible range and perform a large number of iterative decoding, compared to the case in which node operations are simultaneously performed by the number equal to the number of rows or columns of a parity check matrix.

[0562] The LDPC decoder 166 constituting the receiving device 12 in FIG. 79 performs LDPC decoding by simultaneously performing P check node operations and variable node operations, similar to the decoding device in FIG. 85, for example.

[0563] That is, for the sake of simplicity, if the parity check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmitting device 11 in FIG. 8 is, for example, the parity check matrix H shown in FIG. 82, in which the parity matrix has a staircase structure, then the parity interleaver 23 of the transmitting device 11 performs parity interleaving, interleaving the K+qx+y+1-th code bit at the K+Py+x+1-th code bit position, by setting the information length K to 60, the parallel factor P to 5, and the divisor q (=M / P) of the parity length M to 6, respectively.

[0564] As described above, this parity interleaving corresponds to the column permutation of equation (12), and therefore LDPC decoder 166 does not need to perform the column permutation of equation (12).

[0565] For this reason, in the receiving device 12 of FIG. 79, as described above, the group-wise deinterleaver 55 supplies the LDPC decoder 166 with an LDPC code that has not been subjected to parity deinterleaving, that is, an LDPC code that has undergone the column permutation of equation (12), and the LDPC decoder 166 performs the same processing as the decoding device of FIG. 85, except that the column permutation of equation (12) is not performed.

[0566] 86 is a diagram showing an example of the configuration of the LDPC decoder 166 in FIG.

[0567] 86, LDPC decoder 166 is configured in the same manner as the decoding device in FIG. 85 except that it does not have received data rearrangement unit 310 in FIG. 85, and performs the same processing as the decoding device in FIG. 85 except that the column permutation of equation (12) is not performed, so a description thereof will be omitted.

[0568] As described above, the LDPC decoder 166 can be configured without the received data rearrangement unit 310, and therefore can be made smaller in scale than the decoding device in FIG.

[0569] In Figures 82 to 86, for ease of explanation, the code length N of the LDPC code is set to 90, the information length K is set to 60, the parallel factor (number of rows and columns of the constituent matrix) P is set to 5, and the divisor q (= M / P) of the parity length M is set to 6, but the code length N, information length K, parallel factor P, and divisor q (= M / P) are not limited to the values ​​described above.

[0570] That is, in the transmitting device 11 of FIG. 8, the LDPC encoder 115 outputs an LDPC code having, for example, a code length N of 64800, 16200, 69120, 17280, etc., an information length K of N-Pq (=NM), a parallel factor P of 360, and a divisor q of M / P, and the LDPC decoder 166 of FIG. 86 is applicable to the case where LDPC decoding is performed by simultaneously performing P check node operations and variable node operations on such an LDPC code.

[0571] Furthermore, if, after the LDPC decoder 166 decodes the LDPC code, the parity portion of the decoded result is not necessary and only the information bits of the decoded result are output, the LDPC decoder 166 can be configured without the decoded data rearrangement unit 311.

[0572] <Configuration example of block deinterleaver 54>

[0573] FIG. 87 is a diagram for explaining the block deinterleaving performed in the block deinterleaver 54 of FIG.

[0574] In block deinterleaving, the reverse process of the block interleaving by the block interleaver 25 described in FIG. 75 is performed, and the arrangement of the code bits of the LDPC code is restored (restored) to the original arrangement.

[0575] That is, in block deinterleaving, for example, similarly to block interleaving, the arrangement of the code bits of the LDPC code is restored to the original arrangement by writing and reading the LDPC code into m columns, which is equal to the number of bits m of the symbol.

[0576] However, in block deinterleaving, the LDPC codes are written in the same order as they are read in block interleaving, and further, in block deinterleaving, the LDPC codes are read in the same order as they are written in block interleaving.

[0577] That is, for part 1 of the LDPC code, as shown in Fig. 87, part 1 of the LDPC code, which is made up of m-bit symbol units, is written in the row direction from the first row of all m columns. That is, the code bits of the LDPC code, which is made up of m-bit symbols, are written in the row direction.

[0578] Writing of part 1 in m-bit units is performed sequentially toward the bottom row of m columns, and when writing of part 1 is completed, reading of part 1 is performed from the top of the first column unit of the column downwards, toward the columns from left to right, as shown in Figure 87.

[0579] When reading up to the rightmost column is completed, as shown in FIG. 87, return to the leftmost column, and read part 1 from the top of the second column unit of the column downward, proceeding from left to right toward the column, and so on, reading part 1 of one codeword of LDPC code.

[0580] When reading of part 1 of the LDPC code of one code word is completed, for part 2, which is made up of m-bit symbol units, the m-bit symbol units are sequentially concatenated after part 1, and the symbol-unit LDPC code is thereby returned to the sequence of code bits of the original LDPC code of one code word (the LDPC code before block interleaving).

[0581] <Another example of the configuration of the bit deinterleaver 165>

[0582] FIG. 88 is a block diagram showing another example of the configuration of the bit deinterleaver 165 of FIG.

[0583] In the figure, parts corresponding to those in FIG. 80 are given the same reference numerals, and the description thereof will be omitted below as appropriate.

[0584] That is, the bit deinterleaver 165 in FIG. 88 has the same configuration as that in FIG. 80, except that a parity deinterleaver 1011 is newly provided.

[0585] In FIG. 88, the bit deinterleaver 165 is made up of a block deinterleaver 54, a group-wise deinterleaver 55, and a parity deinterleaver 1011, and performs bit deinterleaving of the code bits of the LDPC code from the demapper 164.

[0586] That is, the block deinterleaver 54 performs block deinterleaving (the reverse process of block interleaving) on ​​the LDPC code from the demapper 164, which corresponds to the block interleaving performed by the block interleaver 25 of the transmitting device 11, i.e., block deinterleaving that returns the positions of the code bits swapped by the block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0587] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC codes from the block deinterleaver 54, which corresponds to the group-wise interleaving performed as rearrangement processing by the group-wise interleaver 24 of the transmitter 11.

[0588] The LDPC code obtained as a result of the group-wise deinterleaving is supplied from the group-wise deinterleaver 55 to the parity deinterleaver 1011 .

[0589] The parity deinterleaver 1011 performs parity deinterleaving (the reverse process of parity interleaving) on ​​the code bits after group-wise deinterleaving in the group-wise deinterleaver 55, which corresponds to the parity interleaving performed by the parity interleaver 23 of the transmitting device 11, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by parity interleaving to their original order.

[0590] The LDPC code obtained as a result of the parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166 .

[0591] Therefore, in the bit deinterleaver 165 of FIG. 88, the LDPC decoder 166 is supplied with an LDPC code that has been block deinterleaved, group-wise deinterleaved, and parity deinterleaved, that is, an LDPC code obtained by LDPC encoding in accordance with the check matrix H.

[0592] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H that the LDPC encoder 115 of the transmitting device 11 used for LDPC encoding.

[0593] That is, for the Type B method, LDPC decoder 166 performs LDPC decoding of the LDPC code from bit deinterleaver 165 using check matrix H (of Type B method) that LDPC encoder 115 of transmitting device 11 used for LDPC encoding, or using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on check matrix H. Also, for the Type A method, LDPC decoder 166 performs LDPC decoding of the LDPC code from bit deinterleaver 165 using a check matrix (of Type A method) (FIG. 27) that LDPC encoder 115 of transmitting device 11 used for LDPC encoding (FIG. 28) obtained by performing column permutation on the check matrix (of Type A method) (FIG. 27) that LDPC encoder 115 used for LDPC encoding, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the check matrix (FIG. 27) used for LDPC encoding.

[0594] Here, in FIG. 88, the LDPC decoder 166 is supplied with an LDPC code obtained by LDPC encoding in accordance with the check matrix H from (the parity deinterleaver 1011 of) the bit deinterleaver 165. Therefore, when LDPC decoding of the LDPC code is performed using the check matrix H of the Type B method used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or a check matrix (FIG. 28) obtained by performing column permutation on the check matrix of the Type A method used for LDPC encoding (FIG. 27), the LDPC decoder 166 can be configured, for example, as a decoding device that performs LDPC decoding by a full serial decoding method in which calculations on messages (check node messages, variable node messages) are performed sequentially for each node, or as a decoding device that performs LDPC decoding by a full parallel decoding method in which calculations on messages are performed simultaneously (in parallel) for all nodes.

[0595] Furthermore, in the LDPC decoder 166, when LDPC decoding of an LDPC code is performed using a transformed check matrix obtained by performing at least column permutation equivalent to parity interleaving on check matrix H of the Type B method used for LDPC encoding by the LDPC encoder 115 of the transmitting device 11, or a transformed check matrix (FIG. 29) obtained by performing row permutation on the check matrix of the Type A method used for LDPC encoding (FIG. 27), the LDPC decoder 166 is a decoding device with an architecture that simultaneously performs P (or a divisor of P other than 1) check node operations and variable node operations, and can be configured as a decoding device (FIG. 85) that has a received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column permutation on the LDPC code similar to the column permutation (parity interleaving) for obtaining the transformed check matrix.

[0596] In Figure 88, for the sake of convenience of explanation, the block deinterleaver 54 that performs block deinterleaving, the group-wise deinterleaver 55 that performs group-wise deinterleaving, and the parity deinterleaver 1011 that performs parity deinterleaving are each configured separately, but two or more of the block deinterleaver 54, group-wise deinterleaver 55, and parity deinterleaver 1011 can be configured integrally, similar to the parity interleaver 23, group-wise interleaver 24, and block interleaver 25 of the transmitting device 11.

[0597] <Example of receiving system configuration>

[0598] FIG. 89 is a block diagram showing a first example of the configuration of a receiving system to which the receiving device 12 can be applied.

[0599] In FIG. 89, the receiving system is made up of an acquisition unit 1101, a transmission path decoding unit 1102, and an information source decoding unit 1103.

[0600] The acquisition unit 1101 acquires a signal including an LDPC code obtained by LDPC encoding at least LDPC target data such as program image data and audio data via a transmission path (communication path) (not shown), such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, or other networks, and supplies the signal to a transmission path decoding processing unit 1102.

[0601] Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcast station via terrestrial waves, satellite waves, a CATV (Cable Television) network, etc., the acquisition unit 1101 is configured with a tuner, an STB (Set Top Box), etc. Furthermore, when the signal acquired by the acquisition unit 1101 is transmitted by multicast from a web server, as in IPTV (Internet Protocol Television), for example, the acquisition unit 1101 is configured with a network I / F (Interface) such as a NIC (Network Interface Card).

[0602] The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs transmission path decoding processing, which includes at least processing for correcting errors that occur in the transmission path, on the signal acquired by the acquisition unit 1101 via the transmission path, and supplies the resulting signal to the information source decoding processing unit 1103.

[0603] In other words, the signal acquired by the acquisition unit 1101 via the transmission path is a signal obtained by at least performing error correction coding to correct errors that occur on the transmission path, and the transmission path decoding processing unit 1102 performs transmission path decoding processing such as error correction processing on such a signal.

[0604] Here, examples of error correction coding include LDPC coding, BCH coding, etc. Here, at least LDPC coding is used as the error correction coding.

[0605] Furthermore, the transmission path decoding process may include demodulation of modulated signals.

[0606] The information source decoding processor 1103 performs information source decoding processing on the signal that has been subjected to transmission path decoding processing, which includes at least a process of expanding compressed information to the original information.

[0607] In other words, the signal acquired by the acquisition unit 1101 via the transmission path may have undergone compression encoding to compress the information in order to reduce the amount of data such as images and audio.In such a case, the information source decoding processing unit 1103 performs information source decoding processing on the signal that has undergone transmission path decoding processing, such as a process of expanding the compressed information to the original information (expansion processing).

[0608] In addition, if the signal acquired by the acquisition unit 1101 via the transmission path has not been compression-encoded, the information source decoding processing unit 1103 does not perform processing to expand the compressed information to the original information.

[0609] Here, the decompression process includes, for example, MPEG decoding, etc. Furthermore, the transmission path decoding process may include descrambling and the like in addition to the decompression process.

[0610] In the receiving system configured as described above, in the acquisition unit 1101, for example, data such as images and audio is subjected to compression encoding such as MPEG encoding, and the signal that has been further subjected to error correction encoding such as LDPC encoding is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.

[0611] In the transmission path decoding processing unit 1102, the signal from the acquisition unit 1101 is subjected to transmission path decoding processing, such as processing similar to that performed by the receiving device 12, and the resulting signal is supplied to the information source decoding processing unit 1103.

[0612] The information source decoding processor 1103 performs information source decoding such as MPEG decoding on the signal from the transmission path decoding processor 1102, and outputs the resulting image or sound.

[0613] The receiving system of FIG. 89 as described above can be applied to, for example, a television tuner that receives television broadcasts as digital broadcasts.

[0614] The acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as a single independent device (hardware (such as an IC (Integrated Circuit)) or a software module).

[0615] Furthermore, with regard to the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, it is possible to configure a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, or a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 as a single independent device.

[0616] FIG. 90 is a block diagram showing a second example of the configuration of a receiving system to which the receiving device 12 can be applied.

[0617] In the figure, parts corresponding to those in FIG. 89 are given the same reference numerals, and the description thereof will be omitted below as appropriate.

[0618] The receiving system of Figure 90 is similar to the case of Figure 89 in that it has an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103, but differs from the case of Figure 89 in that it newly has an output unit 1111.

[0619] The output unit 1111 is, for example, a display device that displays images or a speaker that outputs audio, and outputs images, audio, etc. as signals output from the information source decoding processing unit 1103. That is, the output unit 1111 displays images or outputs audio.

[0620] The receiving system of FIG. 90 as described above can be applied to, for example, a TV (television receiver) that receives television broadcasts as digital broadcasts, a radio receiver that receives radio broadcasts, and the like.

[0621] If the signal acquired by the acquisition unit 1101 has not been subjected to compression encoding, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111 .

[0622] FIG. 91 is a block diagram showing a third example configuration of a receiving system to which the receiving device 12 can be applied.

[0623] In the figure, parts corresponding to those in FIG. 89 are given the same reference numerals, and the description thereof will be omitted below as appropriate.

[0624] The receiving system in FIG. 91 is common to the case in FIG. 89 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.

[0625] However, the receiving system in FIG. 91 differs from the system in FIG. 89 in that it does not include the information source decoding processing unit 1103 and instead includes a new recording unit 1121.

[0626] The recording unit 1121 records (stores) the signal (for example, TS packets of MPEG TS) output by the transmission path decoding processing unit 1102 on a recording (storage) medium such as an optical disk, a hard disk (magnetic disk), or a flash memory.

[0627] The receiving system shown in FIG. 91 as described above can be applied to a recorder for recording television broadcasts.

[0628] In FIG. 91, the receiving system is configured to include an information source decoding processing unit 1103, and the signal after information source decoding processing has been performed by the information source decoding processing unit 1103, i.e., the image and audio obtained by decoding, can be recorded in a recording unit 1121.

[0629] <An embodiment of the computer>

[0630] Next, the above-described series of processes can be performed by hardware or software. When the series of processes is performed by software, the programs constituting the software are installed on a general-purpose computer or the like.

[0631] FIG. 92 shows an example of the configuration of an embodiment of a computer in which a program for executing the above-described series of processes is installed.

[0632] The program can be pre-recorded on the hard disk 705 or ROM 703 as a recording medium built into the computer.

[0633] Alternatively, the program can be temporarily or permanently stored (recorded) on a removable recording medium 711 such as a flexible disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, a semiconductor memory, etc. Such a removable recording medium 711 can be provided as a so-called package software.

[0634] In addition to being installed on a computer from the removable recording medium 711 described above, the program can also be transferred wirelessly from a download site to a computer via an artificial satellite for digital satellite broadcasting, or transferred wired to a computer via a network such as a LAN (Local Area Network) or the Internet, and the computer can receive the program transferred in this way via the communication unit 708 and install it on its built-in hard disk 705.

[0635] The computer includes a built-in CPU (Central Processing Unit) 702. An input / output interface 710 is connected to the CPU 702 via a bus 701. When a user inputs commands via the input / output interface 710 by operating an input unit 707 including a keyboard, mouse, microphone, etc., the CPU 702 executes a program stored in a read-only memory (ROM) 703 in accordance with the commands. Alternatively, the CPU 702 loads into a random access memory (RAM) 704 and executes a program stored on a hard disk 705, a program transferred from a satellite or a network, received by a communication unit 708, and installed on the hard disk 705, or a program read from a removable recording medium 711 attached to a drive 709 and installed on the hard disk 705. As a result, the CPU 702 performs processing according to the flowchart described above or processing performed using the configuration shown in the block diagram described above. Then, the CPU 702 outputs the processing results, as necessary, from an output unit 706 consisting of an LCD (Liquid Crystal Display) and a speaker, etc., via an input / output interface 710, or transmits them from a communication unit 708, or even records them on a hard disk 705, etc.

[0636] Here, in this specification, the processing steps that describe a program for causing a computer to perform various processes do not necessarily have to be processed chronologically in the order described in the flowchart, but also include processes that are executed in parallel or individually (for example, parallel processing or processing by objects).

[0637] The program may be processed by a single computer, or may be distributed among multiple computers, or may be transferred to a remote computer for execution.

[0638] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0639] For example, the new LDPC code (its check matrix initial value table) and GW pattern described above can be used for satellite links, terrestrial waves, cables (wired links), and other communication paths 13 (FIG. 7). Furthermore, the new LDPC code and GW pattern can also be used for data transmission other than digital broadcasting.

[0640] The effects described in this specification are merely examples and are not limiting, and other effects may also be present. [Explanation of symbols]

[0641] 11 Transmitter, 12 Receiver, 23 Parity Interleaver, 24 Group-Wise Interleaver, 25 Block Interleaver, 54 Block Deinterleaver, 55 Group-Wise Deinterleaver, 111 Mode Adaptation / Multiplexer, 112 Padder, 113 BB Scrambler, 114 BCH Encoder, 115 LDPC Encoder, 116 Bit Interleaver, 117 Mapper, 118 Time Interleaver, 119 SISO / MISO Encoder, 120 Frequency Interleaver, 121 BCH Encoder, 122 LDPC Encoder, 123 Mapper, 124 Frequency Interleaver, 131 Frame Builder / Resource Allocation Unit, 132 OFDM Generation Unit, 151 OFDM Processing Unit, 152 Frame Management Unit, 153 Frequency Deinterleaver, 154 Demapper, 155 LDPC decoder, 156 BCH decoder, 161 frequency deinterleaver, 162 SISO / MISO decoder, 163 time deinterleaver, 164 demapper, 165 bit deinterleaver, 166 LDPC decoder, 167 BCH decoder, 168 BB descrambler, 169 null deletion unit, 170 demultiplexer, 300 edge data storage memory, 301 selector, 302 check node calculation unit, 303 cyclic shift circuit, 304 edge data storage memory, 305 selector, 306 received data memory, 307 variable node calculation unit, 308 cyclic shift circuit, 309 decoded word calculation unit, 310 received data rearrangement unit, 311 decoded data rearrangement unit, 601 encoding processing unit, 602 memory unit, 611 coding rate setting unit, 612 initial value table reading unit, 613 check matrix generation unit, 614 information bit reading unit, 615 coded parity calculation unit, 616 control unit, 701 bus, 702 CPU, 703 ROM, 704 RAM, 705 hard disk, 706 output unit, 707 input unit, 708 communication unit, 709 drive, 710 input / output interface, 711 removable recording medium, 1001 reverse exchange unit, 1002 memory,1011 parity deinterleaver, 1101 acquisition unit, 1101 transmission path decoding processing unit, 1103 information source decoding processing unit, 1111 output unit, 1121 recording unit,

Claims

1. A transmitting device including an encoding unit that performs LDPC encoding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 6 / 16; a receiving device including a decoding unit that decodes the LDPC code obtained from data transmitted by the transmitting device; Equipped with The check matrix is A matrix A in the upper left corner of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code; A B matrix having a staircase structure adjacent to the right of the A matrix, with M1 rows and M1 columns; a Z matrix, which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns; a C matrix adjacent below the A matrix and the B matrix, the C matrix having N−M1 rows and K+M1 columns; A D matrix, which is an identity matrix adjacent to the right of the C matrix and has N-K-M1 rows and N-K-M1 columns, Including, The predetermined value M1 is 720, The A matrix and the C matrix are represented by a check matrix initial value table, The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 416 437 444 1657 2662 4109 4405 6308 8251 75 498 687 3903 4582 7035 7650 7871 10382 394 419 474 3515 6708 7277 8703 9969 10489 167 289 612 1847 5277 5900 8326 8508 9462 196 439 620 2128 2375 2501 6902 9308 9552 154 495 623 5024 6241 8364 9996 10104 10346 230 329 661 879 1474 3222 4109 8079 8865 97 172 692 1018 1629 1752 3170 5930 359 377 712 6273 7131 7278 8292 10457 368 551 708 787 2891 6140 7195 9555 44 512 655 2196 6692 7975 8410 10727 27 94 611 5585 7258 8091 9867 10714 608 639 691 3560 6819 7492 7754 7916 46 115 214 2175 5986 7177 8589 10757 282 589 604 969 1856 2433 5742 8900 243 262 669 1330 1366 3339 5517 7517 62 392 651 4175 8349 8557 9192 10015 206 375 697 1449 2015 2390 3926 4428 5084 5236 5872 8486 9398 9997 10469 1079 1384 1664 2936 4618 5359 5455 5537 5726 5875 8044 8521 9746 791 1106 1497 1885 2682 3473 3716 4506 5671 5829 8388 8641 9454 is Transmitting and receiving system.

2. a coding step in which the transmitting device performs LDPC coding based on a check matrix of an LDPC code having a code length N of 17280 bits and a coding rate r of 6 / 16; a decoding step in which a receiving device decodes the LDPC code obtained from data transmitted by the transmitting device; Equipped with The check matrix is A matrix A in the upper left corner of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code; A B matrix having a staircase structure adjacent to the right of the A matrix, with M1 rows and M1 columns; a Z matrix, which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns; a C matrix adjacent below the A matrix and the B matrix, the C matrix having N−M1 rows and K+M1 columns; A D matrix, which is an identity matrix adjacent to the right of the C matrix and has N-K-M1 rows and N-K-M1 columns, Including, The predetermined value M1 is 720, The A matrix and the C matrix are represented by a check matrix initial value table, The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 416 437 444 1657 2662 4109 4405 6308 8251 75 498 687 3903 4582 7035 7650 7871 10382 394 419 474 3515 6708 7277 8703 9969 10489 167 289 612 1847 5277 5900 8326 8508 9462 196 439 620 2128 2375 2501 6902 9308 9552 154 495 623 5024 6241 8364 9996 10104 10346 230 329 661 879 1474 3222 4109 8079 8865 97 172 692 1018 1629 1752 3170 5930 359 377 712 6273 7131 7278 8292 10457 368 551 708 787 2891 6140 7195 9555 44 512 655 2196 6692 7975 8410 10727 27 94 611 5585 7258 8091 9867 10714 608 639 691 3560 6819 7492 7754 7916 46 115 214 2175 5986 7177 8589 10757 282 589 604 969 1856 2433 5742 8900 243 262 669 1330 1366 3339 5517 7517 62 392 651 4175 8349 8557 9192 10015 206 375 697 1449 2015 2390 3926 4428 5084 5236 5872 8486 9398 9997 10469 1079 1384 1664 2936 4618 5359 5455 5537 5726 5875 8044 8521 9746 791 1106 1497 1885 2682 3473 3716 4506 5671 5829 8388 8641 9454 is Sending and receiving methods.

Images