Multilayer ceramic capacitors

Abstract

A multilayer ceramic capacitor (100) is provided with: a capacitor main body (1) which is obtained by stacking a plurality of dielectric layers (2), a plurality of first internal electrodes (3) and a plurality of second internal electrodes (4); a first via conductor (5) which is provided within the capacitor main body (1) and is electrically connected to the plurality of first internal electrodes (3); and a second via conductor (6) which is provided within the capacitor main body (1) and is electrically connected to the plurality of second internal electrodes (4). In the stacking direction of the dielectric layers (2), the first internal electrodes (3) and the second internal electrodes (4), the dimension of the multilayer ceramic capacitor (100) is equal to the dimension of the capacitor main body (1).

Description

[Technical Field]

[0001] The present disclosure relates to multilayer ceramic capacitors. [Background technology]

[0002] Multilayer capacitors are known in which the ESL (equivalent series inductance) is reduced by widening the route through which current flows, shortening the route through which current flows, canceling out magnetic fields generated by currents of opposite polarity, etc. Patent Document 1 discloses an example of a multilayer capacitor with reduced ESL.

[0003] The multilayer capacitor disclosed in Patent Document 1 (JP 2006-135333 A) includes a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated. The capacitor body is provided with a plurality of first via conductors electrically connected to the plurality of first internal electrodes and extending to one main surface of the capacitor body, and a plurality of second via conductors electrically connected to the plurality of second internal electrodes and extending to the one main surface of the capacitor body. The one main surface of the capacitor body is provided with a plurality of first external electrodes electrically connected to the plurality of first via conductors, respectively, and a plurality of second external electrodes electrically connected to the plurality of second via conductors, respectively. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-135333 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the multilayer capacitor disclosed in Patent Document 1, the first and second external electrodes are provided on the surface of the capacitor body, so when the size of the multilayer capacitor is fixed, the thickness of the capacitor body is reduced by the thickness of the external electrodes. In other words, the provision of the external electrodes places a restriction on the number of laminated internal electrodes, making it impossible to increase the capacitance.

[0006] The present disclosure is intended to solve the above-mentioned problems, and has an object to provide a multilayer ceramic capacitor that can increase the capacitance. [Means for solving the problem]

[0007] The multilayer ceramic capacitor of the present disclosure comprises: a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the second internal electrodes; Equipped with a multilayer ceramic capacitor, wherein the dimensions of the multilayer ceramic capacitor in the lamination direction of the dielectric layers, the first internal electrodes, and the second internal electrodes are the same as the dimensions of the capacitor body; [Effects of the Invention]

[0008] According to the multilayer ceramic capacitor of the present disclosure, no external electrodes are provided on the surfaces of the capacitor body, and the dimensions of the multilayer ceramic capacitor in the stacking direction are the same as the dimensions of the capacitor body. This configuration maximizes the dimensions of the capacitor body in the stacking direction, allowing for a larger number of first internal electrodes and second internal electrodes to be stacked, thereby increasing the capacitance. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view of a multilayer ceramic capacitor according to a first preferred embodiment of the present invention; [Figure 2] 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. [Figure 3] 1 is a cross-sectional view schematically showing the configuration of a first modified example of the multilayer ceramic capacitor according to the first preferred embodiment of the present invention. [Figure 4] FIG. 3 is a cross-sectional view schematically showing the configuration of a second modified example of the multilayer ceramic capacitor according to the first preferred embodiment. [Figure 5] FIG. 3 is a cross-sectional view schematically showing the configuration of a third modified example of the multilayer ceramic capacitor according to the first preferred embodiment. [Figure 6] FIG. 4 is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor according to a second embodiment. [Figure 7] FIG. 10 is a cross-sectional view schematically showing the configuration of a modified example of the multilayer ceramic capacitor according to the second embodiment. [Figure 8] FIG. 10 is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor according to a third embodiment. [Figure 9] FIG. 10 is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor according to a fourth embodiment. [Figure 10] 10 is a cross-sectional view schematically showing a state in which the multilayer ceramic capacitor according to the fourth preferred embodiment is mounted on a mounting substrate using a bonding material. FIG. [Figure 11] FIG. 1(a) is a plan view schematically showing the configuration of a multilayer ceramic capacitor whose shape when viewed in the stacking direction is a rectangle with rounded corners, and FIG. 1(b) is a plan view schematically showing the configuration of a multilayer ceramic capacitor whose shape when viewed in the stacking direction is an octagon. [Figure 12] FIG. 1(a) is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor having inclined side surfaces, and FIG. 1(b) is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor having an end portion of a main surface of a capacitor body in a direction perpendicular to the stacking direction that is recessed inward in the stacking direction compared to other portions. [Figure 13] 13(a) is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor having first via conductors and second via conductors whose dimensions in a direction perpendicular to the stacking direction gradually increase from one end to the other end in the stacking direction, and FIG. 13(b) is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor in which a recess is provided in the multilayer ceramic capacitor shown in FIG. 13(a). DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be shown, and the features of the present disclosure will be specifically described.

[0011] First Embodiment Fig. 1 is a plan view of a multilayer ceramic capacitor 100 according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 100 taken along line II-II of Fig. 1.

[0012] The multilayer ceramic capacitor 100 includes a capacitor body 1, a first via conductor 5, and a second via conductor 6.

[0013] The capacitor body 1 has a structure in which a plurality of dielectric layers 2, a plurality of first internal electrodes 3, and a plurality of second internal electrodes 4 are laminated. More specifically, the capacitor body 1 has a structure in which the first internal electrodes 3 and the second internal electrodes 4 are alternately laminated with the dielectric layers 2 interposed therebetween.

[0014] The dielectric layer 2 may be made of any material, such as a ceramic material containing BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 as a main component. These main components may contain a minor component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, the content of which is less than that of the main component.

[0015] The capacitor body 1 may have any shape. In this embodiment, the capacitor body 1 has a rectangular parallelepiped shape as a whole. A rectangular parallelepiped shape as a whole refers to a shape that is not a perfect rectangular parallelepiped shape, such as a shape in which the corners and ridges of a rectangular parallelepiped are rounded, but has six surfaces and can be regarded as a rectangular parallelepiped as a whole.

[0016] The dimensions of the capacitor body 1 are arbitrary, but for example, the rectangular vertical dimension in plan view can be 0.3 mm to 3.0 mm, the horizontal dimension can be 0.3 mm to 3.0 mm, and the dimension in the stacking direction T of the dielectric layers 2, first internal electrodes 3, and second internal electrodes 4 (hereinafter simply referred to as the stacking direction T) can be 50 μm to 200 μm. The dimension of the capacitor body 1 in the stacking direction T refers to the thickness of the capacitor body 1.

[0017] As will be described later, no external electrodes or other components are provided on the first main surface 1a and the second main surface 1b of the capacitor body 1 that face each other in the stacking direction T. Therefore, the dimensions of the multilayer ceramic capacitor 100 in the stacking direction T are the same as the dimensions of the capacitor body 1. Note that the dimensions of the multilayer ceramic capacitor 100 in the stacking direction T refer to the distance between the outermost portion of the components of the multilayer ceramic capacitor 100 on the first main surface 1a side and the outermost portion of the components of the multilayer ceramic capacitor 100 on the second main surface 1b side in the stacking direction T.

[0018] The first internal electrode 3 and the second internal electrode 4 may be made of any material, and may contain, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing such a metal, as a main component. The first internal electrode 3 and the second internal electrode 4 may contain, as a common material, the same ceramic material as the dielectric ceramic contained in the dielectric layer 2. In this case, the proportion of the common material contained in the first internal electrode 3 and the second internal electrode 4 is, for example, 20 vol % or less.

[0019] The thickness of the first internal electrode 3 and the second internal electrode 4 is arbitrary, but can be, for example, about 0.3 μm or more and 1.0 μm or less. The number of layers of the first internal electrode 3 and the second internal electrode 4 is arbitrary, but can be, for example, about 10 layers or more and 150 layers or less in total.

[0020] The first inner electrode 3 has a plurality of first through holes 3a formed therein for inserting a plurality of second via conductors 6 (described later). The second inner electrode 4 has a plurality of second through holes 4a formed therein for inserting a plurality of first via conductors 5 (described later).

[0021] In the multilayer ceramic capacitor 100, a capacitance is formed by the first internal electrode 3 and the second internal electrode 4 facing each other with the dielectric layer 2 interposed therebetween.

[0022] 2, the first via conductors 5 are provided inside the capacitor body 1 and are electrically connected to the plurality of first internal electrodes 3. The first via conductors 5 pass through second through holes 4a formed in the second internal electrodes 4 and are insulated from the second internal electrodes 4.

[0023] 2, the first via conductor 5 is provided inside the capacitor body 1 so as to extend in the stacking direction T from the first main surface 1a to the second main surface 1b of the capacitor body 1. That is, the first via conductor 5 is exposed on the first main surface 1a and the second main surface 1b of the capacitor body 1. However, as will be described later, the first via conductor 5 does not have to be exposed on the first main surface 1a or the second main surface 1b of the capacitor body 1.

[0024] 2, the second via conductors 6 are provided inside the capacitor body 1 and are electrically connected to the plurality of second internal electrodes 4. The second via conductors 6 pass through first through holes 3a formed in the first internal electrodes 3 and are insulated from the first internal electrodes 3.

[0025] 2, the second via conductor 6 is provided inside the capacitor body 1 so as to extend in the stacking direction T from the first main surface 1a to the second main surface 1b of the capacitor body 1. That is, the second via conductor 6 is exposed on the first main surface 1a and the second main surface 1b of the capacitor body 1. However, as will be described later, the second via conductor 6 does not have to be exposed on the first main surface 1a or the second main surface 1b of the capacitor body 1.

[0026] The first via conductor 5 and the second via conductor 6 do not protrude beyond the first principal surface 1a and the second principal surface 1b of the capacitor body 1 in the stacking direction T. That is, the dimensions of the first via conductor 5 and the second via conductor 6 in the stacking direction T are equal to or smaller than the dimensions of the capacitor body 1. In the example shown in FIG. 2 , the dimensions of the first via conductor 5 and the second via conductor 6 in the stacking direction T are the same as the dimensions of the capacitor body 1.

[0027] The material of the first via conductor 5 and the second via conductor 6 is arbitrary, and may contain, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn or Au, or an alloy containing these metals, as its main component.

[0028] The first via conductors 5 and the second via conductors 6 can be provided at any positions. In this embodiment, as shown in Fig. 1, a plurality of first via conductors 5 and a plurality of second via conductors 6 are provided in a matrix. The number of first via conductors 5 and second via conductors 6 can be any number.

[0029] The first and second via conductors 5 and 6 may have any shape, for example, a cylindrical shape. In this case, the diameter of the first and second via conductors 5 and 6 is, for example, about 30 μm or more and 150 μm or less. The distance between adjacent first and second via conductors 5 and 6, more specifically, the distance L1 (see FIG. 2) between the centers of the first and second via conductors 5 and 6, is, for example, about 50 μm or more and 500 μm or less.

[0030] 2, the dimensions of the multilayer ceramic capacitor 100 in the stacking direction T are the same as the dimensions of the capacitor body 1. That is, the first principal surface 1a and the second principal surface 1b of the capacitor body 1 are not provided with external electrodes connected to the first via conductors 5, external electrodes connected to the second via conductors 6, or other components. For example, when the multilayer ceramic capacitor 100 is mounted on lands on a mounting board, the first via conductors 5 and the second via conductors 6 exposed on the first principal surface 1a or the second principal surface 1b of the capacitor body 1 are connected to the lands via solder or the like.

[0031] As described above, in the multilayer ceramic capacitor 100 of this embodiment, no external electrodes are provided on the first main surface 1a and the second main surface 1b of the capacitor body 1, and the dimensions of the multilayer ceramic capacitor 100 in the stacking direction T are the same as the dimensions of the capacitor body 1. With this configuration, when comparing multilayer ceramic capacitors of the same size, the multilayer ceramic capacitor 100 of this embodiment can maximize the dimensions of the capacitor body 1 in the stacking direction T compared to conventional multilayer ceramic capacitors in which external electrodes are provided on the surfaces of the capacitor body. This allows the number of layers of the first internal electrodes 3 and the second internal electrodes 4 to be increased, and the capacitance to be increased, compared to conventional multilayer ceramic capacitors in which external electrodes are provided.

[0032] Furthermore, in the stacking direction T, the dimensions of the first via conductors 5 and the second via conductors 6 are the same as the dimensions of the capacitor body 1, so that the first via conductors 5 and the second via conductors 6 are exposed on the first principal surface 1a and the second principal surface 1b of the capacitor body 1. This allows the first via conductors 5 and the second via conductors 6 to be connected in direct contact with lands or the like of the mounting board when the multilayer ceramic capacitor 100 is mounted, thereby further improving connection reliability.

[0033] (Manufacturing method of multilayer ceramic capacitors) An example of a method for manufacturing the multilayer ceramic capacitor 100 described above will now be described.

[0034] First, ceramic green sheets and a conductive paste for the internal electrodes are prepared. Known ceramic green sheets can be used, and can be obtained, for example, by applying a ceramic slurry containing ceramic powder, a resin component, and a solvent onto a substrate and drying it.

[0035] The conductive paste for internal electrodes is a conductive paste for forming the first internal electrodes 3 and the second internal electrodes 4, and a known conductive paste can be used. The conductive paste for internal electrodes contains particles made of a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or a precursor thereof, and a solvent. The conductive paste for internal electrodes may further contain a resin component that serves as a dispersant or binder.

[0036] Next, an internal electrode pattern is formed by applying a conductive paste for internal electrodes to the ceramic green sheets by a method such as printing. Here, an explanation will be given of forming an internal electrode pattern that allows multiple multilayer ceramic capacitors 100 to be manufactured at once.

[0037] Next, a mother laminate is produced by stacking a plurality of ceramic green sheets on which internal electrode patterns have been formed. When producing the mother laminate, ceramic green sheets on which internal electrode patterns have not been formed may be arranged on the outer sides in the stacking direction T. The produced mother laminate is preferably pressed by a method such as a rigid press or a hydrostatic press.

[0038] Next, through holes for forming the first via conductors 5 and through holes for forming the second via conductors 6 are formed in the mother laminate. The through holes are formed, for example, by irradiating with a laser beam.

[0039] Next, the formed through holes are filled with a conductive paste for via conductors to form the first via conductors 5 and the second via conductors 6. The conductive paste for via conductors contains particles made of a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or a precursor thereof, and a solvent. The conductive paste for via conductors may further contain a resin component that acts as a dispersant or binder.

[0040] Next, the mother laminate is cut to a predetermined size by a cutting method such as press cutting, dicing, laser cutting, etc. to obtain a laminated chip. The obtained laminated chip is fired with a predetermined profile to obtain a multilayer ceramic capacitor 100.

[0041] (Variation 1) 3 is a cross-sectional view schematically showing the configuration of Modification 1 of the multilayer ceramic capacitor 100 according to the first preferred embodiment. The cut position of the cross-sectional view shown in FIG. 3 is the same as the cut position of the cross-sectional view shown in FIG.

[0042] In the multilayer ceramic capacitor 100 shown in FIG. 3, the dimensions of the first via conductors 5 and the second via conductors 6 in the stacking direction T are smaller than the dimensions of the capacitor body 1. Also, as shown in FIG. 3, the first via conductors 5 and the second via conductors 6 are exposed on the second main surface 1b but not on the first main surface 1a. Therefore, the positions on the first main surface 1a of the capacitor body 1 where the first via conductors 5 and the second via conductors 6 are provided form recesses recessed inward in the stacking direction T. In this case, when the multilayer ceramic capacitor 100 is mounted, the second main surface 1b of the capacitor body 1 can be used as the mounting surface.

[0043] The dimensions of the first via conductors 5 and the second via conductors 6 in the stacking direction T can be adjusted, for example, by pressing the conductive paste for via conductors filled in the through holes during manufacturing. Alternatively, the dimensions of the first via conductors 5 and the second via conductors 6 in the stacking direction T may be adjusted by increasing the content of the resin component in the conductive paste for via conductors. That is, by increasing the content of the resin component in the conductive paste for via conductors, more of the resin component is lost during firing, thereby reducing the dimensions of the first via conductors 5 and the second via conductors 6 that are formed.

[0044] 1 and 2, the multilayer ceramic capacitor 100 shown in FIG. 3 can also increase the number of laminated first internal electrodes 3 and second internal electrodes 4, thereby increasing the capacitance. Furthermore, in the multilayer ceramic capacitor 100 shown in FIG. 3, the dimensions of the first via conductors 5 and the second via conductors 6 in the lamination direction T are smaller than the dimensions of the capacitor body 1, and the first via conductors 5 and the second via conductors 6 are not exposed on the first principal surface 1a. This prevents the first via conductors 5 and the second via conductors 6 from making unintended electrical contact with other electronic components on the first principal surface 1a side. The same applies to the case where the first via conductors 5 and the second via conductors 6 are not exposed on the second principal surface 1b of the capacitor body 1, but on the first principal surface 1a.

[0045] However, when mounting the multilayer ceramic capacitor 100, the first main surface 1a of the capacitor body 1 may be used as the mounting surface.

[0046] (Variation 2) 4 is a cross-sectional view schematically showing the configuration of Modification 2 of the multilayer ceramic capacitor 100 according to the first preferred embodiment. The cut position of the cross-sectional view shown in FIG. 4 is the same as the cut position of the cross-sectional view shown in FIG.

[0047] 3, in the multilayer ceramic capacitor 100 shown in FIG. 4, the dimensions of the first via conductors 5 and the second via conductors 6 are smaller than the dimensions of the capacitor body 1 in the stacking direction T. Also, as shown in FIG. 4, the first via conductors 5 and the second via conductors 6 are exposed on the first main surface 1a but not on the second main surface 1b. In this case, when the multilayer ceramic capacitor 100 is mounted, the first main surface 1a of the capacitor body 1 becomes the mounting surface.

[0048] 4, the second main surface 1b of the capacitor body 1 is flat. That is, of the ends of the first via conductors 5 and the second via conductors 6 in the stacking direction T, the ends on the second main surface 1b side are covered with the dielectric layer 2.

[0049] 4 can be manufactured by forming holes in the mother laminate for forming the first via conductors 5 and the second via conductors 6, either through holes that pass from one main surface to the other main surface, or holes that do not. After the through holes are formed in the mother laminate, a ceramic green sheet may be attached to close one end of the through holes.

[0050] 1 and 2, the multilayer ceramic capacitor 100 shown in FIG. 4 can also increase the number of laminated first internal electrodes 3 and second internal electrodes 4, thereby increasing the capacitance. Furthermore, in the multilayer ceramic capacitor 100 shown in FIG. 4, the first via conductors 5 and the second via conductors 6 are not exposed on the second main surface 1b, which prevents the first via conductors 5 and the second via conductors 6 from making unintended electrical contact with other electronic components on the second main surface 1b side. In particular, the ends of the first via conductors 5 and the second via conductors 6 that are not exposed on the second main surface 1b are covered by the dielectric layer 2, which more reliably prevents unintended electrical contact with other electronic components than the multilayer ceramic capacitor 100 shown in FIG. 3. The same applies to the case where the first via conductors 5 and the second via conductors 6 are not exposed on the first main surface 1a, but on the second main surface 1b, of the capacitor body 1.

[0051] (Variation 3) 5 is a cross-sectional view schematically showing the configuration of Modification 3 of the multilayer ceramic capacitor 100 according to the first preferred embodiment. The cut position of the cross-sectional view shown in FIG. 5 is the same as the cut position of the cross-sectional view shown in FIG.

[0052] In the multilayer ceramic capacitor 100 shown in FIG. 5, similarly to the multilayer ceramic capacitor 100 shown in FIG. 3, the dimensions of the first via conductors 5 and the second via conductors 6 in the stacking direction T are smaller than the dimensions of the capacitor body 1. Furthermore, the first via conductors 5 and the second via conductors 6 are not exposed on the first principal surface 1a or the second principal surface 1b. The ends of the first via conductors 5 and the second via conductors 6 on the first principal surface 1a side are open, and the ends on the second principal surface 1b side are covered by the dielectric layer 2. In this case, when the multilayer ceramic capacitor 100 is mounted, the first principal surface 1a of the capacitor body 1 serves as the mounting surface.

[0053] The multilayer ceramic capacitor 100 shown in FIG. 5 can be manufactured using the manufacturing technique for the multilayer ceramic capacitor 100 shown in FIGS. 3 and 4 described above.

[0054] The multilayer ceramic capacitor 100 shown in FIG. 5 provides the same effects as the multilayer ceramic capacitor 100 shown in FIG.

[0055] <Second embodiment> 6 is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor 100A according to Preferred Embodiment 2. The cut position of the cross-sectional view shown in FIG.

[0056] Similar to the multilayer ceramic capacitor 100 of the first embodiment, the dimensions of the multilayer ceramic capacitor 100A of the second embodiment are the same as the dimensions of the capacitor body 1 in the stacking direction T. In the multilayer ceramic capacitor 100A of the second embodiment, the dimensions of the first via conductors 5 and the second via conductors 6 are smaller than the dimensions of the capacitor body 1 in the stacking direction T.

[0057] In the multilayer ceramic capacitor 100A of this preferred embodiment, the capacitor body 1 is provided with an outer layer 10 on the outer side in the stacking direction T, which is stronger than the dielectric layer 2 and covers one end of the first via conductors 5 and the second via conductors 6 in the stacking direction T. In the example shown in FIG. 6 , the outer layer 10 is provided on the second principal surface 1b side of the capacitor body 1. The ends of the first via conductors 5 and the second via conductors 6 on the first principal surface 1a side are exposed to the first principal surface 1a. However, the outer layer 10 may be provided on the first principal surface 1a side of the capacitor body 1 instead of the second principal surface 1b side.

[0058] The outer layer 10 is made of a ceramic material stronger than the ceramic material that makes up the dielectric layer 2, such as a ceramic material containing particles of aluminum oxide, glass, resin, or the like, or a ceramic material containing metal particles, preferably particles of the same metal as the metal that makes up the first via conductors 5 and the second via conductors 6. However, if the outer layer 10 is made of a ceramic material containing metal particles, it is necessary to interpose an insulating sheet or the like between the outer layer 10 and the first via conductors 5 and the second via conductors 6.

[0059] The multilayer ceramic capacitor 100A of the second embodiment can be manufactured basically in the same manner as the multilayer ceramic capacitor 100 of the first embodiment, but requires a step for forming the outer layer 10. That is, after through holes are formed in the mother laminate, ceramic green sheets for forming the outer layer 10 are attached to the outside of the mother laminate in the stacking direction T. Then, the formed holes are filled with a conductive paste for via conductors. The subsequent steps are the same as the manufacturing process for the multilayer ceramic capacitor 100 of the first embodiment.

[0060] According to the multilayer ceramic capacitor 100A of the second embodiment, as with the multilayer ceramic capacitor 100 of the first embodiment, the number of laminated first internal electrodes 3 and second internal electrodes 4 can be increased, thereby increasing the capacitance. Furthermore, on the outside of the capacitor body 1 in the lamination direction T, an outer layer 10 having a strength greater than that of the dielectric layer 2 and covering one end of the first via conductor 5 and the second via conductor 6 in the lamination direction T is provided. This improves the strength of the multilayer ceramic capacitor 100A and prevents the capacitor body 1 from cracking.

[0061] (Variation) 7 is a cross-sectional view schematically showing the configuration of a modified example of the multilayer ceramic capacitor 100A according to Preferred Embodiment 2. The cut position of the cross-sectional view shown in FIG.

[0062] The multilayer ceramic capacitor 100A shown in Fig. 7 differs from the multilayer ceramic capacitor 100A shown in Fig. 6 in the positions of the ends of the first via conductors 5 and the second via conductors 6. That is, the ends of the first via conductors 5 and the second via conductors 6 on the first principal surface 1a side are located more inward in the stacking direction T than the first principal surface 1a, and are not exposed to the first principal surface 1a.

[0063] Furthermore, when an outer layer 10 is provided on the first main surface 1a side of the capacitor body 1, the ends of the first via conductor 5 and the second via conductor 6 on the second main surface 1b side should be configured so that they are not exposed to the second main surface 1b.

[0064] The multilayer ceramic capacitor 100A shown in FIG. 7 also has the same effects as the multilayer ceramic capacitor 100A shown in FIG.

[0065] <Third embodiment> 8 is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor 100B according to Preferred Embodiment 3. The cut position of the cross-sectional view shown in FIG.

[0066] Similar to the multilayer ceramic capacitor 100 according to the first preferred embodiment, the dimensions of the multilayer ceramic capacitor 100B according to the third preferred embodiment in the stacking direction T are the same as the dimensions of the capacitor body 1.

[0067] 8, the first via conductor 5 and the second via conductor 6 are exposed on the first main surface 1a of the capacitor body 1 but not on the second main surface 1b. However, the first via conductor 5 and the second via conductor 6 may also be exposed on the second main surface 1b.

[0068] In this embodiment, the first via conductor 5 and the second via conductor 6 each include a first material layer 21 and a second material layer 22 made of a material different from that of the first material layer 21. The second material layer 22 is provided on at least one open end of the first via conductor 5 and the second via conductor 6 in the stacking direction T, where the surface is not covered. In the example shown in FIG. 8 , the second material layer 22 is provided on the open end of the first via conductor 5 and the second via conductor 6 on the first principal surface 1a side of the capacitor body 1 and is exposed on the first principal surface 1a. However, the second material layer 22 does not necessarily have to be exposed on the first principal surface 1a of the capacitor body 1. In this case, the principal surface on which the second material layer 22 is provided, of the first principal surface 1a or the second principal surface 1b of the capacitor body 1, serves as the mounting surface.

[0069] The first material layer 21 contains, for example, Ni as a main component. The second material layer 22 contains, for example, any one of Sn, Sn—Ag, Sn—Bi, Sn—In, Sn—Ag—Cu, and Au as a main component. However, Sn—Ag is an alloy of Sn and Ag, Sn—Bi is an alloy of Sn and Bi, Sn—In is an alloy of Sn and In, and Sn—Ag—Cu is an alloy of Sn, Ag, and Cu. Ni is a metal that oxidizes easily, but Sn, Sn—Ag, Sn—Bi, Sn—In, Sn—Ag—Cu, and Au are metals with excellent oxidation resistance. Therefore, the mounting reliability of the multilayer ceramic capacitor 100B can be improved by providing the second material layer 22 containing one of Sn, Sn-Ag, Sn-Bi, Sn-In, Sn-Ag-Cu, and Au as a main component at the open ends of at least one of the first via conductors 5 and the second via conductors 6. However, the main component of the first material layer 21 is not limited to Ni, and may be a metal such as Cu, Ag, Pd, Pt, Fe, Ti, Cr, or Au, or an alloy containing these metals.

[0070] The first via conductors 5 and the second via conductors 6 can be formed using, for example, one type of conductive paste for via conductors. For example, holes formed in a mother laminate are filled with a conductive paste for via conductors containing Ni and Sn, and the laminate is singulated and then fired. This causes Sn, which has a lower melting point than Ni, to appear on the surface. This allows the formation of the first via conductors 5 and the second via conductors 6, each of which includes a first material layer 21 primarily composed of Ni and a second material layer 22 primarily composed of Sn. In this case, the first material layer 21 and the second material layer 22 do not form a neat two-layer structure as shown in FIG. 8, but are formed so that Ni is mainly present on the inside and Sn is mainly present on the outside.

[0071] Alternatively, the first via conductors 5 and the second via conductors 6 may be formed using two different materials. For example, holes formed in a mother laminate are filled with a conductive paste for via conductors containing Ni as a main component, and the mother laminate is singulated and then fired. This forms a first material layer 21 containing Ni as a main component, which shrinks during firing and its end is positioned more inward in the stacking direction T than the surface of the capacitor body 1. However, when filling the holes in the mother laminate with the conductive paste for via conductors containing Ni as a main component, it is not necessary to fill it all the way to the surface. Next, Sn is injected onto the first material layer 21 and reflowed to form a second material layer 22 containing Sn as a main component on the first material layer 21.

[0072] <Fourth embodiment> 9 is a cross-sectional view schematically showing the configuration of a multilayer ceramic capacitor 100C according to the fourth preferred embodiment of the present invention, taken along the same line as the cross-sectional view shown in FIG.

[0073] In the multilayer ceramic capacitor 100C of the fourth embodiment, a recess 30 recessed inward in the stacking direction T is provided on the surface of the capacitor body 1 at a position where the first via conductor 5 and the second via conductor 6 are provided when viewed in the stacking direction T. The recess 30 can be formed, for example, by producing a mother laminate and then irradiating it with laser light to remove a portion of the surface, or by forming a recess by pressing or the like.

[0074] 9, recesses 30 are provided on second main surface 1b of capacitor body 1. However, recesses 30 of capacitor body 1 may be provided on first main surface 1a, or may be provided on both first main surface 1a and second main surface 1b.

[0075] The shape of the recess 30 when viewed in the stacking direction T is arbitrary. However, it is preferable that the recess 30 is provided so that the first via conductor 5 and the second via conductor 6 are completely exposed when viewed in the stacking direction T. In the example shown in Fig. 9, the dimension of the recess 30 is larger than the dimension of the first via conductor 5 and the second via conductor 6 in any direction perpendicular to the stacking direction T.

[0076] 9, the first via conductor 5 and the second via conductor 6 are each exposed in the recess 30 of the capacitor body 1. The first via conductor 5 and the second via conductor 6 are also each exposed on the first principal surface 1a. However, the first via conductor 5 and the second via conductor 6 do not necessarily have to be exposed on the first principal surface 1a.

[0077] The multilayer ceramic capacitor 100C according to the fourth embodiment can improve the strength when mounted using a bonding material such as solder. That is, in a configuration without the recess 30, the amount of bonding material at the bonding position may be reduced due to the spreading of the bonding material. In contrast, in the multilayer ceramic capacitor 100C according to the present embodiment, as shown in FIG. 10 , the bonding material 41 can be confined within the recess 30 when mounted on the mounting substrate 40, so the amount of bonding material 41 at the bonding position can be increased, thereby improving the mounting strength.

[0078] 9, the ends of the first via conductor 5 and the second via conductor 6 on the recess 30 side are located at the same position as the inner wall that constitutes the recess 30 and is perpendicular to the stacking direction T, but they may be located further inward in the stacking direction T than the inner wall, or further outward in the stacking direction T. However, even when the ends of the first via conductor 5 and the second via conductor 6 are located further outward in the stacking direction T than the inner wall that constitutes the recess 30, they do not protrude further outward in the stacking direction T than the surface of the capacitor body 1 other than the recess 30.

[0079] As described above, in the multilayer ceramic capacitor 100C shown in FIG. 9, the dimensions of the recess 30 are larger than the dimensions of the first via conductor 5 and the second via conductor 6 in any direction perpendicular to the stacking direction T. On the other hand, the dimensions of the recess 30 may be configured to be the same as the dimensions of the first via conductor 5 and the second via conductor 6 in any direction perpendicular to the stacking direction T. The multilayer ceramic capacitor 100 shown in FIG. 3 is a multilayer ceramic capacitor with such a configuration, and therefore can also be said to be a multilayer ceramic capacitor according to the fourth embodiment.

[0080] The present disclosure is not limited to the above-described embodiments, and various applications and modifications can be made within the scope of the present disclosure. For example, the characteristic configurations of the above-described embodiments and their modifications can be combined as appropriate.

[0081] The multilayer ceramic capacitor 100 shown in Fig. 1 has a square shape when viewed in the stacking direction T, but may have a rectangular shape or other shapes. For example, the shape of the multilayer ceramic capacitor 100 when viewed in the stacking direction T may be a rectangle with rounded corners as shown in Fig. 11(a) or an octagon as shown in Fig. 11(b).

[0082] 1 and 2, the side surfaces of the capacitor body 1 are perpendicular to the first principal surface 1a and the second principal surface 1b, but may be inclined as shown in Fig. 12(a). Also, as shown in Fig. 12(b), the end portion of at least one of the first principal surface 1a and the second principal surface 1b of the capacitor body 1 in the direction perpendicular to the stacking direction T may be recessed inward in the stacking direction T compared to the other portions.

[0083] In the multilayer ceramic capacitor 100 shown in Fig. 2, the dimensions of the first via conductor 5 and the second via conductor 6 are the same at any position in the stacking direction T, but may be different. For example, as shown in Fig. 13(a), the first via conductor 5 and the second via conductor 6 may have a shape in which the dimension in the direction perpendicular to the stacking direction T gradually increases from one end to the other end in the stacking direction T. When the first via conductor 5 and the second via conductor 6 have a cylindrical shape, the diameter gradually increases from one end to the other end in the stacking direction T.

[0084] The multilayer ceramic capacitor 100 shown in FIG. 13(a) may be provided with a recess 30, similar to the multilayer ceramic capacitor 100C according to the fourth preferred embodiment (see FIG. 13(b)).

[0085] The multilayer ceramic capacitor in this application is as follows. <1> a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the second internal electrodes; Equipped with a multilayer ceramic capacitor in which the dimensions of the multilayer ceramic capacitor in the lamination direction of the dielectric layers, the first internal electrodes, and the second internal electrodes are the same as the dimensions of the capacitor body; <2> In the stacking direction, the dimensions of the first via conductor and the second via conductor are the same as the dimensions of the capacitor body. <1> The multilayer ceramic capacitor according to claim 1. <3> In the stacking direction, the dimensions of the first via conductor and the second via conductor are smaller than the dimensions of the capacitor body. <1> The multilayer ceramic capacitor according to claim 1. <4> the capacitor body includes an outer layer provided on the outside in the stacking direction, having a strength greater than that of the dielectric layer, and covering one end of the first via conductor and one end of the second via conductor in the stacking direction; <3> The multilayer ceramic capacitor according to claim 1. <5> each of the first via conductor and the second via conductor includes a first material layer and a second material layer made of a material different from the first material layer; the second material layer is provided on at least one open end of the first via conductor and the second via conductor in the stacking direction, the open end having an uncovered surface; <1> ~ <4> 1. The multilayer ceramic capacitor according to claim 1, <6> the second material layer contains any one of Sn, Sn—Ag, Sn—Bi, Sn—In, Sn—Ag—Cu, and Au as a main component; <5> The multilayer ceramic capacitor according to claim 1. <7> a recessed portion recessed inward in the stacking direction is provided on the surface of the capacitor body at a position where the first via conductor and the second via conductor are provided when viewed in the stacking direction; <1> ~ <6> 1. The multilayer ceramic capacitor according to claim 1,

[0086] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0087] 1. Capacitor body 2. Dielectric layer 3 First inner electrode 4 Second internal electrode 5 First via conductor 6 Second via conductor 10 outer layer 21 First material layer 22 Second material layer 30 recess 40 Mounting board 41 Bonding material 100, 100A, 100B, 100C multilayer ceramic capacitors

Claims

1. a capacitor body in which a plurality of dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes are laminated; a first via conductor provided inside the capacitor body and electrically connected to the first internal electrodes; second via conductors provided inside the capacitor body and electrically connected to the second internal electrodes; Equipped with a dimension of the multilayer ceramic capacitor in a lamination direction of the dielectric layers, the first internal electrodes, and the second internal electrodes is the same as a dimension of the capacitor body; each of the first via conductor and the second via conductor includes a first material layer and a second material layer made of a material different from the first material layer; A multilayer ceramic capacitor, wherein the second material layer is provided at at least one open end of the first via conductor and the second via conductor in the stacking direction, the open end having an uncovered surface.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the dimensions of the first via conductor and the second via conductor in the stacking direction are the same as the dimensions of the capacitor body.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein the dimensions of the first via conductor and the second via conductor in the stacking direction are smaller than the dimensions of the capacitor body.

4. 4. The multilayer ceramic capacitor according to claim 3, wherein the capacitor body includes an outer layer that is provided on the outside in the stacking direction, has a strength greater than that of the dielectric layer, and covers one end of the first via conductor and the second via conductor in the stacking direction.

5. 2. The multilayer ceramic capacitor according to claim 1, wherein the second material layer contains any one of Sn, Sn--Ag, Sn--Bi, Sn--In, Sn--Ag--Cu, and Au as a main component.

6. 6. The multilayer ceramic capacitor according to claim 1, wherein a recess recessed inward in the stacking direction is provided on the surface of the capacitor body at a position where the first via conductor and the second via conductor are provided when viewed in the stacking direction.

Images