Multilayer ceramic capacitors

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor (1) in which a decrease in moisture resistance can be inhibited, while having a small size and a high capacity. The multilayer ceramic capacitor (1) includes a first corner portion (C1) that curves across a first main surface (M1) and a first main portion side surface (SS1) of a capacitor main portion (3), a second corner portion (C2) that curves across a second main surface (M2) and the first main portion side surface (SS1), a third corner portion that curves across the first main surface (M1) and a second main portion side surface (SS2), and a fourth corner portion (C4) that curves across the second main surface (M2) and the second main portion side surface (SS2). A first insulating portion (8a) covers the first corner portion (C1) and the second corner portion (C2), and a second insulating portion (8b) covers the third corner portion (C3) and the fourth corner portion (C4). The roughness of the first corner portion (C1) is greater than that of a first outside corner portion (K1), the roughness of the second corner portion (C2) is greater than that of a second outside corner portion (K2), the roughness of the third corner portion (C3) is greater than that of a third outside corner portion (K3), and the roughness of the fourth corner portion (C4) is greater than that of a fourth outside corner portion (K4).

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component, and more particularly to a multilayer ceramic capacitor. [Background technology]

[0002] In recent years, the dimensions of electronic components have become smaller as the electronic devices they are used in become smaller. As the dimensions of electronic components become smaller, the overlapping area between internal electrodes also becomes smaller, making it a challenge to make them smaller and increase their capacity. Therefore, a method is known in which the internal electrode layer is exposed on the side surface and a dielectric laminate sheet is later provided on the side surface of the chip to maximize the area of ​​the internal electrodes in the lateral direction. Patent Document 1 describes a related technology. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 62-237714 Summary of the Invention [Problem to be solved by the invention]

[0004] However, electronic components manufactured in this manner have a risk of moisture penetration from the insulating layer edges due to insufficient adhesion between the capacitor body and the insulating layer edges, resulting in a decrease in moisture resistance. Therefore, an object of the present invention is to provide a multilayer ceramic capacitor that is small in size and has a large capacitance, yet is capable of suppressing a decrease in moisture resistance. [Means for solving the problem]

[0005] The multilayer ceramic capacitor includes a plurality of laminated dielectric layers, and has first and second main surfaces opposing each other in a lamination direction, first and second main side surfaces opposing each other in a width direction perpendicular to the lamination direction, first end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction, first internal electrode layers alternately laminated with the plurality of dielectric layers and exposed at the first end surfaces, the first and second main side surfaces, and second internal electrode layers alternately laminated with the plurality of dielectric layers and exposed at the second end surfaces, the first and second main side surfaces. a first insulating portion disposed on a first main side surface of the capacitor main portion, and a second insulating portion disposed on a second main side surface of the capacitor main portion; a first external electrode provided so as to wrap around from the first end face to the first main surface, the second main surface, the surface of the first insulating portion, and the surface of the second insulating portion; and a second external electrode provided so as to wrap around from the second end face to the first main surface, the second main surface, the surface of the first insulating portion, and the surface of the second insulating portion. the laminate has a first corner curved across the first main surface and the first main side surface of the main portion, a second corner curved across the second main surface and the first main side surface, a third corner curved across the first main surface and the second main side surface, and a fourth corner curved across the second main surface and the second main side surface, the first insulating portion covers the first corner and the second corner, the second insulating portion covers the third corner and the fourth corner, a surface of the first insulating portion opposite to a surface in contact with the first main side surface is a first side surface of the laminate, The surface opposite to the surface in contact with the second main portion side surface is the second side surface of the laminate, the first insulating portion has a first outer corner where the first main surface and the first side surface intersect, and a second outer corner where the second main surface and the first side surface intersect, the second insulating portion has a third outer corner where the first main surface and the second side surface intersect, and a fourth outer corner where the second main surface and the second side surface intersect, the roughness of the first corner is greater than the roughness of the first outer corner, the roughness of the second corner is greater than the roughness of the second outer corner, and the roughness of the third corner isThe roughness of the third outer corner is greater than the roughness of the fourth outer corner, and the roughness of the fourth corner is greater than the roughness of the fourth outer corner. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor that is small in size and has a large capacitance, and is capable of suppressing a decrease in moisture resistance. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 2] 1 is a perspective view of a laminate according to an embodiment of the present invention. [Figure 3] FIG. 2 is a perspective view of a capacitor main body according to an embodiment of the present invention. [Figure 4] FIG. 2 is a cross-sectional view taken along line II in FIG. [Figure 5] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 6] 2, and (b) is a view corresponding to the cross section of the conventional multilayer ceramic capacitor taken along line III-III in FIG. [Figure 7] 3 is a cross-sectional view corresponding to the cross-sectional view taken along line III-III in FIG. 2 according to another embodiment of the present invention. [Figure 8] FIG. 8 is a diagram showing a region R of FIG. 7 in another embodiment of the present invention. [Figure 9] FIG. 2 is a perspective view showing a portion of a capacitor main body according to an embodiment of the present invention. [Figure 10] FIG. 10 is a perspective view showing a portion of a capacitor body according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment of the present invention will now be described with reference to the accompanying drawings. In the following description, a multilayer ceramic capacitor will be described as an example of a multilayer ceramic electronic component. Note that the same or corresponding parts in each drawing will be designated by the same reference numerals.

[0009] <External view of multilayer ceramic capacitor> An outline of the appearance of a multilayer ceramic capacitor 1 will be described with reference to Fig. 1. Fig. 1 is a perspective view showing the multilayer ceramic capacitor 1 of this embodiment. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 20. The external electrodes 20 include a first external electrode 20a and a second external electrode 20b.

[0010] <Direction definition> 1 to 7 show the L direction, W direction, and T direction. The L direction is the length direction L of the multilayer ceramic capacitor 1. The W direction is the width direction W of the multilayer ceramic capacitor 1. The T direction is the stacking direction T of the multilayer ceramic capacitor 1. Therefore, the cross section shown in FIG. 4 is called an LT cross section, and the cross section shown in FIG. 5 is called a WT cross section. The length direction L, width direction W, and stacking direction T do not necessarily have to be orthogonal to each other. The length direction L, width direction W, and stacking direction T may intersect each other.

[0011] <External shape of laminate> As shown in FIG. 1, the laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has two main surfaces M, two end surfaces E, and two side surfaces S. The main surfaces M are surfaces facing the stacking direction T. The end surfaces E are surfaces facing the length direction L. The side surfaces S are surfaces facing the width direction W. The two main surfaces M are referred to as a first main surface M1 and a second main surface M2. The two end surfaces E are referred to as a first end surface E1 and a second end surface E2. The two side surfaces S are referred to as a first side surface S1 and a second side surface S2.

[0012] The corners of the laminate 2 are preferably rounded. A corner is a portion where at least two surfaces of the laminate 2 intersect. Furthermore, the two main surfaces M, the two end surfaces E, and the two side surfaces S may all or partly have irregularities formed on their surfaces. The size of the laminate 2 is not particularly limited.

[0013] <Capacitor main part> The configuration of the laminate 2 will be described with reference to FIGS. 2 and 3. FIG. 2 is a perspective view of the laminate 2 according to an embodiment of the present invention. FIG. 3 is a perspective view of a capacitor main section 3 according to an embodiment of the present invention. The laminate 2 includes the capacitor main section 3 and two insulating sections 8. One of the two insulating sections 8 is a first insulating section 8a, and the other is a second insulating section 8b. The capacitor main section 3 has a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked on top of each other in the stacking direction T. The internal electrode layers 10 include a first internal electrode layer 10a and a second internal electrode layer 10b. Details of the internal electrode layers 10 will be described later.

[0014] Here, the two surfaces of the capacitor main part 3 that face each other in the width direction W are referred to as main part side surfaces SS. Specifically, as shown in FIG. 3, one of the two main part side surfaces SS is referred to as a first main part side surface SS1, and the other is referred to as a second main part side surface SS2. The laminate 2 is formed by arranging an insulating part 8 on each of the two main part side surfaces SS of the capacitor main part 3. Specifically, a first insulating part 8a is arranged on the first main part side surface SS1, and a second insulating part 8b is arranged on the second main part side surface SS2.

[0015] <Insulation section> The insulating portion 8 is a member disposed on the two main portion side surfaces SS of the capacitor main portion 3. The insulating portion 8 has a sheet-like shape. The material constituting the insulating portion 8 is not particularly limited as long as it has insulating properties. The material constituting the insulating portion 8 may have the same main component as the material constituting the dielectric layer 4. Alternatively, the material constituting the insulating portion 8 may be a resin component.

[0016] <Laminate and capacitor body surface> As described above, the laminate 2 is configured by disposing insulating portions 8 on the two main portion side surfaces SS of the capacitor main portion 3. Therefore, the end surface E of the laminate 2 is the same as the end surface E of the capacitor main portion 3. Similarly, the main surface M of the laminate 2 is the same as the main surface M of the capacitor main portion 3. In contrast, the side surface M of the laminate 2 becomes the surface of the insulating portion 8 disposed on the main portion side surface SS of the capacitor main portion 3. Specifically, the surface of the first insulating portion 8a facing the first main portion side surface SS1 becomes the first side surface S1 of the laminate 2. Similarly, the surface of the second insulating portion 8b facing the second main portion side surface SS2 becomes the second side surface S2 of the laminate 2.

[0017] The internal electrode layers 10 are exposed from the two main-part side surfaces SS and two end surfaces E of the capacitor main part 3. Specifically, the first internal electrode layer 10a is exposed from the first end surface E1 of the capacitor main part 3, and the second internal electrode layer 10b is exposed from the second end surface E2 of the capacitor main part 3. The first internal electrode layer 10a and the second internal electrode layer 10b are exposed from the first main-part side surface SS1 and the second main-part side surface SS2 of the capacitor main part 3. The first internal electrode layer 10a and the second internal electrode layer 10b exposed from the first main-part side surface SS1 and the second main-part side surface SS2 are insulated from the outside by arranging a first insulating portion 8a on the first main-part side surface SS1 and a second insulating portion 8b on the second main-part side surface SS2. The first internal electrode layer 10a and the second internal electrode layer 10b may also be configured not to be exposed from the first main portion side surface SS1 and the second main portion side surface SS2. That is, the first internal electrode layer 10a and the second internal electrode layer 10b may be covered by the dielectric layer 4 on the first main portion side surface SS1 and the second main portion side surface SS2. The specific configuration of the capacitor main portion 3 will be described with reference to FIGS. 4 and 5.

[0018] <Internal structure of laminate (LT cross section)> The internal structure of the laminate 2 will be described with reference to Fig. 4. Fig. 4 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II. The cross-section of the portion of the laminate 2 shown in Fig. 4 is a cross-section taken along line LT of a portion corresponding to the capacitor main portion 3. As shown in Fig. 4, the laminate 2 has a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked on top of each other in the stacking direction T.

[0019] <Inner and outer layers> The laminate 2 has an inner layer portion IL and two outer layer portions OL in the stacking direction T. The outer layer portions OL include a first outer layer portion OL1 and a second outer layer portion OL2. The first outer layer portion OL1 and the second outer layer portion OL2 are arranged to sandwich the inner layer portion IL.

[0020] The inner layer portion IL includes a portion of the plurality of dielectric layers 4 and a plurality of internal electrode layers 10. In the inner layer portion IL, the plurality of internal electrode layers 10 are arranged opposite each other with the dielectric layer 4 interposed therebetween. The inner layer portion IL is a portion that forms capacitance and essentially functions as a capacitor. For this reason, the inner layer portion IL is also referred to as an effective portion.

[0021] The first outer layer portion OL1 is disposed on the first main surface M1 side of the laminate 2, and the second outer layer portion OL2 is disposed on the second main surface M2 side of the laminate 2. Specifically, the first outer layer portion OL1 is disposed between the first main surface M1 and the internal electrode layer 10 closest to the first main surface M1 among the multiple internal electrode layers 10. The second outer layer portion OL2 is disposed between the second main surface M2 and the internal electrode layer 10 closest to the second main surface M2 among the multiple internal electrode layers 10. The first outer layer portion OL1 and the second outer layer portion OL2 do not include the internal electrode layer 10, but include the remaining dielectric layers 4 of the multiple dielectric layers 4 excluding the dielectric layer 4 for the internal layer portion IL. The first outer layer portion OL1 and the second outer layer portion OL2 function as protective layers for the internal layer portion IL.

[0022] <Dielectric layer> The dielectric layer 4 includes an outer dielectric layer 5 and an inner dielectric layer 6 . <Outer dielectric layer> The outer dielectric layers 5 are the dielectric layers 4 that constitute the first outer layer portion OL1 and the second outer layer portion OL2 among the dielectric layers 4. The outer dielectric layers 5 are located between the first main surface M1 and the internal electrode layer 10 closest to the first main surface M1, and between the second main surface M2 and the internal electrode layer 10 closest to the second main surface M2.

[0023] <Inner dielectric layer> The inner dielectric layer 6 is a dielectric layer 4 located between the internal electrode layers 10 and constituting the inner layer portion IL together with the internal electrode layers 10. The inner dielectric layer 6 is located between a first internal electrode layer 10a and a second internal electrode layer 10b, which will be described below.

[0024] <Number of dielectric layers> The number of dielectric layers 4 stacked in the laminate 2 can be, for example, 5 to 2000. This number of dielectric layers 4 includes the number of outer dielectric layers 5 and the number of inner dielectric layers 6.

[0025] <Dielectric layer material> The dielectric layer 4 may be made of a dielectric ceramic whose main component is, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, a material containing a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be added to the main component.

[0026] The dielectric layer 4 can have multiple crystal grains containing a perovskite-type compound whose basic structure is BaTiO3. Here, the thinner the dielectric layer 4, the greater the capacitance as a capacitor. Therefore, it is preferable that the crystal grain size be 1 μm or less. Furthermore, as the thickness of the dielectric layer becomes thinner, the crystal grains become smaller, but if the crystal grains become too small, the relative dielectric constant will decrease due to the size effect. Therefore, the size of the crystal grains is appropriately designed depending on the thickness of the dielectric layer.

[0027] It should be noted that the multilayer ceramic electronic component functions as a ceramic piezoelectric element when a piezoelectric ceramic is used for the laminate 2. Specific examples of piezoelectric ceramic materials include PZT (lead zirconate titanate) ceramic materials.

[0028] The multilayer ceramic electronic component functions as a thermistor element when a semiconducting ceramic is used for the laminate 2. Specific examples of semiconducting ceramic materials include spinel ceramic materials.

[0029] Furthermore, when a magnetic ceramic is used in the laminate, the multilayer ceramic electronic component functions as an inductor element. Furthermore, when the multilayer ceramic electronic component functions as an inductor element, the internal electrode layers become coil-shaped conductors. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0030] <Thickness of dielectric layer> The thickness of the dielectric layer 4 can be, for example, 0.3 μm or more and 100 μm or less. The outer dielectric layer 5 may be a single layer or a plurality of layers.

[0031] <Internal electrode layer> The internal electrode layers 10 include a first internal electrode layer 10a and a second internal electrode layer 10b. The first internal electrode layer 10a is an internal electrode layer 10 connected to a first external electrode 20a. The second internal electrode layer 10b is an internal electrode layer 10 connected to a second external electrode 20b. The external electrodes 20 will be described later. The first internal electrode layer 10a extends from a first end face E1 toward a second end face E2. The second internal electrode layer 10b extends from the second end face E2 toward the first end face E1.

[0032] <Facing part and pull-out part> The first internal electrode layer 10a and the second internal electrode layer 10b each have a counter electrode portion 11 and an extraction electrode portion 12. The counter electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. The extraction electrode portion 12 is a portion of the internal electrode layer 10 that is extracted from the counter electrode portion 11 to the end face E1 or the end face E2 of the laminate 2.

[0033] The opposing electrode portion 11 of the first internal electrode layer 10a is referred to as the first opposing electrode portion 11a, and the extracted electrode portion 12 of the first internal electrode layer 10a is referred to as the first extracted electrode portion 12a. The first extracted electrode portion 12a is a portion extracted from the first opposing electrode portion 11a to the first end face E1 of the laminate 2. Similarly, the opposing electrode portion 11 of the second internal electrode layer 10b is referred to as the second opposing electrode portion 11b, and the extracted electrode portion 12 of the second internal electrode layer 10b is referred to as the second extracted electrode portion 12b. The second extracted electrode portion 12b is a portion extracted from the second opposing electrode portion 11b to the second end face E2 of the laminate 2.

[0034] <Number of internal electrode layers> The number of the internal electrode layers 10 can be, for example, from 10 to 2000. This number of the internal electrode layers 10 includes the number of the first internal electrode layers 10a and the number of the second internal electrode layers 10b.

[0035] <Thickness of the internal electrode layer> The thickness of the internal electrode layer 10 can be, for example, 0.1 μm to 5.0 μm, preferably 0.2 μm to 2.0 μm. If the thickness of the internal electrode layer 10 is 0.5 μm or more, a plating film is likely to grow when the metal layer of the external electrode 20 is formed by plating. The metal layer will be described later.

[0036] <Internal electrode layer material> The material of the internal electrode layers 10 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys of Ni and Cu, alloys of Ag and Pd, etc. In addition, the material of the internal electrode layers 10 may contain dielectric particles of the same composition as the ceramic contained in the dielectric layers 4.

[0037] <Electrode facing part> The divisions of the laminate 2 in the length direction L will be described. The laminate 2 has an electrode facing portion LF and two end gap portions EG in the length direction L. The end gap portion EG has a first end gap portion EG1 and a second end gap portion EG2. The electrode facing portion LF is a portion where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. In the electrode facing portion LF, the first facing electrode portion 11a and the second facing electrode portion 11b face each other in the stacking direction T. The electrode facing portion LF is located in the center portion in the length direction L of the laminate 2. The first facing electrode portion 11a and the second facing electrode portion 11b face each other with the inner dielectric layer 6 interposed therebetween, thereby forming a capacitance. For this reason, the electrode facing portion LF is also referred to as an effective portion.

[0038] <End gap part> The end gap portion is a portion where the first internal electrode layer 10a and the second internal electrode layer 10b do not face each other in the stacking direction T. Specifically, in the stacking direction T, a portion where the first internal electrode layer 10a is arranged but the second internal electrode layer 10b is not arranged is the first end gap portion EG1. Similarly, a portion where the second internal electrode layer 10b is arranged but the first internal electrode layer 10a is not arranged is the second end gap portion EG2.

[0039] The first end gap EG1 corresponds to the portion where the first extension electrode portion 12a is arranged, and the second end gap EG2 corresponds to the portion where the second extension electrode portion 12b is arranged. The first end gap EG1 functions as an extension electrode to the first end face E1 of the first internal electrode layer 10a, and the second end gap EG2 functions as an extension electrode to the second end face E2 of the second internal electrode layer 10b. The end gap EG is a section in the length direction L, and is therefore also called an L gap.

[0040] The length of the end gap portion EG in the longitudinal direction L can be set to, for example, 5 μm or more and 30 μm or less.

[0041] The specific configuration of the internal electrode layer 10 and the like can be changed in various ways. For example, the shape of the first opposing electrode portion 11a of the first internal electrode layer 10a is not particularly limited, but is preferably rectangular. However, the corners may be rounded or may be formed at an angle. That is, the corners may be tapered. Also, the corners may be tapered, with an inclination toward one of the edges of the first opposing electrode portion 11a.

[0042] Similarly, the shape of the second opposing electrode portion 11b of the second internal electrode layer 10b is not particularly limited, but is preferably rectangular. However, the corners may be rounded or may be formed at an angle. That is, the corners may be tapered. Alternatively, the second opposing electrode portion 11b may be tapered, with an inclination toward one of its edges.

[0043] Similarly, the shape of the first extension electrode portion 12a of the first internal electrode layer 10a is not particularly limited, but is preferably rectangular. However, the corners may be rounded or may be formed at an angle. That is, the corners may be tapered. Alternatively, the first extension electrode portion 12a may be tapered, with an inclination toward one of its edges.

[0044] Similarly, the shape of the second extension electrode portion 12b of the second internal electrode layer 10b is not particularly limited, but is preferably rectangular. However, the corners may be rounded or may be formed at an angle. That is, the corners may be tapered. Alternatively, the second extension electrode portion 12b may be tapered, with an inclination toward one of its edges.

[0045] The width of the first opposing electrode portion 11a of the first internal electrode layer 10a and the width of the first extraction electrode portion 12a of the first internal electrode layer 10a may be formed to be the same width, or one of them may be formed to be narrower in width.

[0046] The width of the second opposing electrode portion 11b of the second internal electrode layer 10b and the width of the second extraction electrode portion 12b of the second internal electrode layer 10b may be formed to be the same width, or one of them may be formed to be narrower in width.

[0047] The first extraction electrode portion 12a of the first internal electrode layer 10a may be curved toward the center of the first end face E1 of the laminate 2.

[0048] The second extraction electrode portion 12b of the second internal electrode layer 10b may be curved toward the center of the second end face E2 of the laminate 2.

[0049] The distance between the internal electrode layer 10 closest to the first main surface M1 and the internal electrode layer 10 closest to the second main surface M2 among the internal electrode layers 10 drawn out to each end face E may be shorter than the distance between the opposing electrode portion 11 closest to the first main surface M1 and the opposing electrode portion 11 closest to the second main surface M2.

[0050] In the multilayer ceramic capacitor 1 of this embodiment, capacitance is formed by opposing electrode portions 11 of the internal electrode layers 10 facing each other via the dielectric layer 4, and the characteristics of the capacitor are thereby realized. In order to increase the capacitance of the capacitor, it is necessary to increase the surface area of ​​the internal electrode layers 10. Therefore, it is preferable that the coverage of the LW surface of the internal electrode layers 10 is 90% or more. The coverage of the LW surface is defined as the ratio of the area remaining after subtracting the area of ​​voids from the area inside the edge of the internal electrode layer 10 when viewing the internal electrode layer 10 from the LW surface.

[0051] The higher the coverage of the LW surface, the higher the capacitance of the capacitor. However, when the coverage of the LW surface is low, the dielectric layers 4 are bonded together through gaps, which increases the bonding strength between the layers and makes delamination less likely to occur.

[0052] Furthermore, it is preferable that the internal electrode layers 10 have a uniform thickness, but the thickness at the edge in the width direction W may be greater than the thickness at the center in the width direction W.

[0053] <Step layer> Furthermore, a step layer may be disposed in the L gap, i.e., the end gap portion EG. The step layer is a dielectric layer 4 that is additionally disposed in the end gap portion EG to reduce the difference in length in the stacking direction T between the end gap portion EG and the electrode facing portion LF. The step layer may be disposed so that the internal electrode layer 10 covers a portion of the step layer. Alternatively, conversely, the step layer may be disposed so that the internal electrode layer 10 covers a portion of the step layer. The step layer preferably has the same thickness as the internal electrode layer 10. Furthermore, the step layer preferably has the same components as the dielectric layer 4. However, the components of the dielectric layer 4 are not limited thereto.

[0054] <Dummy electrode layer> A dummy electrode layer may be disposed in the L gap. The dummy electrode layer may be disposed in at least one of the inner layer portion IL and the outer layer portion OL. Here, the outer layer portion OL includes a first outer layer portion OL1 and a second outer layer portion OL2. When a dummy electrode layer is disposed in the outer layer portion OL, the dummy electrode layer is preferably disposed on a portion corresponding to a position obtained by translating the L gap in the stacking direction T. In other words, the dummy electrode layer is preferably disposed at a position corresponding to the L gap in the length direction L of the outer layer portion OL.

[0055] The dummy electrode layers may include a first dummy electrode layer and a second dummy electrode layer. The first dummy electrode layer preferably has a thickness similar to the sum of the thicknesses of the first internal electrode layers 10a. In other words, the first dummy electrode layer preferably has a thickness similar to the thickness of the first internal electrode layer 10a multiplied by the number of first internal electrode layers 10a. The first dummy electrode layer may be one or more layers, as long as it has a thickness similar to the sum of the thicknesses of the first internal electrode layers 10a.

[0056] The second dummy electrode layer is similar to the first dummy electrode layer. That is, the second dummy electrode layer preferably has a thickness similar to the sum of the thicknesses of the second internal electrode layers 10b. That is, the second dummy electrode layer preferably has a thickness similar to the thickness of the second internal electrode layer 10b multiplied by the number of second internal electrode layers 10b. The second dummy electrode layer may be one or more layers, as long as it has a thickness similar to the sum of the thicknesses of the second internal electrode layers 10b.

[0057] <External electrode> The external electrodes 20 include a first external electrode 20a and a second external electrode 20b. <First external electrode> The first external electrode 20a is an external electrode 20 arranged on the first end face E1 of the laminate 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a.

[0058] <Second external electrode> The second external electrode 20b is an external electrode 20 arranged on the second end face E2 of the laminate 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.

[0059] <External electrodes on each side> The external electrode 20 extends from the end face E to parts of the two main faces M and to parts of the two side faces S. The part of the external electrode 20 that is arranged on the end face E is referred to as an end face external electrode 25. The part of the external electrode 20 that is arranged on parts of the main faces M is referred to as a main face external electrode 26. The part of the external electrode 20 that is arranged on parts of the side faces S is referred to as a side face external electrode 27.

[0060] Specifically, the portion of the first external electrode 20a that is arranged on the first end face E1 is referred to as the first end face external electrode 25a. The portion of the first external electrode 20a that is arranged on a part of the first main face M1 or a part of the second main face M2 is referred to as the first main face external electrode 26a. The portion of the first external electrode 20a that is arranged on a part of the first side face S1 or a part of the second side face S2 is referred to as the first side face external electrode 27a.

[0061] Similarly to the first external electrode 20a, the portion of the second external electrode 20b that is arranged on the second end face E2 is referred to as a second end face external electrode 25b. The portion of the second external electrode 20b that is arranged on a part of the first main face M1 or a part of the second main face M2 is referred to as a second main face external electrode 26b. The portion of the second external electrode 20b that is arranged on a part of the first side face S1 or a part of the second side face S2 is referred to as a second side face external electrode 27b.

[0062] <Layer structure of external electrodes> The layer structure of the external electrode 20 will be described with reference to Figures 4 and 5. The external electrode 20 includes three layers: a base electrode layer 21, an inner plating layer 23, and a top plating layer 24. These layers are arranged in this order from the end face E of the laminate 2: base electrode layer 21, inner plating layer 23, top plating layer 24. Specifically, the first external electrode 20a includes a first base electrode layer 21a, a first inner plating layer 23a, and a first top plating layer 24a. Similarly, the second external electrode 20b includes a second base electrode layer 21b, a second inner plating layer 23b, and a second top plating layer 24b.

[0063] <Base electrode layer> The first base electrode layer 21a is disposed on and covers the first end face E1 of the laminate 2. The first base electrode layer 21a may extend from the first end face E1 to a portion of the first main face M1, a portion of the second main face M2, a portion of the first side face S1, and a portion of the second side face S2.

[0064] Similarly, the second base electrode layer 21b is disposed on and covers the second end face E2 of the laminate 2. The second base electrode layer 21b may extend from the second end face E2 to a portion of the first main face M1, a portion of the second main face M2, a portion of the first side face S1, and a portion of the second side face S2.

[0065] The first underlying electrode layer 21a and the second underlying electrode layer 21b include at least one selected from a baked layer, a conductive resin layer, a thin film layer, a direct plating layer, and the like.

[0066] <Baked layer> The baking layer contains a glass component and a metal. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer may be a multi-layered layer. The baking layer is formed by applying a conductive paste containing a glass component and a metal to the laminate 2 and then baking it. This baking, i.e., firing, may be performed simultaneously with the firing of the internal electrode layers 10, or may be fired separately after the firing of the internal electrode layers 10.

[0067] The thicknesses of the first baked layer and the second baked layer at the center in the stacking direction T of the first base electrode layer 21a located on the first end face E1 and the second base electrode layer 21b located on the second end face E2 are preferably, for example, 0.1 μm or more and 200 μm or less.

[0068] When a baking layer is provided on the first principal surface M1 and the second principal surface M2, and the first side surface S1 and the second side surface S2, it is preferable that the thickness of the baking layer at the center of the longitudinal direction of the base electrode layer 21 on each surface is, for example, 0.1 μm or more and 200 μm or less.

[0069] <Conductive resin layer> Next, a case where the first underlying electrode layer 21a and the second underlying electrode layer 21b include a conductive resin layer will be described.

[0070] The conductive resin layer contains a thermosetting resin and a metal. Therefore, the conductive resin layer is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if a ceramic electronic component such as the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the capacitor.

[0071] The metal contained in the conductive resin layer can be Ag, Cu, or an alloy thereof. Alternatively, a metal powder with an Ag coating on its surface can be used. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu or Ni as the metal powder. Alternatively, Cu with an oxidation prevention treatment can be used. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it does not oxidize and has high resistance. The reason for using Ag-coated metal is that it reduces the amount of Ag used while still taking advantage of the above-mentioned properties of Ag, making it possible to use a cheaper base metal.

[0072] The metal is preferably contained in an amount of 35 vol% or more and 75 vol% or less relative to the volume of the entire conductive resin. The shape of the metal contained in the conductive resin layer is not particularly limited. The shape of the metal, in other words, the shape of the conductive filler, may be spherical or flat. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the metal, for example, the conductive filler, can be, for example, about 0.3 μm or more and 10 μm or less.

[0073] Here, the metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers forms an electrical path inside the conductive resin layer. The metal contained in the conductive resin layer can be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0074] The resin used in the conductive resin layer can be, for example, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin contained in the conductive resin layer is preferably contained in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin. Furthermore, the conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0075] The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the laminate 2. The conductive resin layer may also be a multi-layer structure.

[0076] The thicknesses of the first conductive resin layer and the second conductive resin layer at the center in the stacking direction T of the first base electrode layer 21a located on the first end face E1 and the second base electrode layer 21b located on the second end face E2 are preferably, for example, approximately 10 μm or more and 200 μm or less.

[0077] When a conductive resin layer is provided on the first principal surface M1 and the second principal surface M2, and the first side surface S1 and the second side surface S2, the thickness of the conductive resin layer at the center of the length direction of the base electrode layer 21 on each surface is preferably, for example, 5 μm or more and 50 μm or less.

[0078] <Thin film layer> Next, when the first base electrode layer 21a and the second base electrode layer 21b include a thin film layer, the thin film layer can be formed by a thin film formation method such as a sputtering method or a vapor deposition method, and can be a layer of 1 μm or less on which metal particles are deposited.

[0079] <Direct plating layer> The external electrode 20 may include a direct plating layer. The direct plating layer is a plating layer formed directly on the surface of the laminate 2. That is, the multilayer ceramic capacitor 1 may have a structure including a direct plating layer electrically connected to the first internal electrode layer 10a or the second internal electrode layer 10b. When forming a direct plating layer, a catalyst may be disposed on the surface of the laminate 2 as a pretreatment, and then the direct plating layer may be formed.

[0080] The direct plating layer preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such metal. For example, when the first internal electrode layer 10a and the second internal electrode layer 10b are formed using Ni, the direct plating layer is preferably formed using Cu, which has good bonding properties with Ni. The thickness of each direct plating layer is preferably 1.0 μm or more and 15 μm or less. Furthermore, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99% by volume or more.

[0081] The plating layer on the base electrode layer 21 may be one layer or multiple layers. When the plating layer is two layers, it is preferable that the order from bottom to top is a Ni plating layer and a Sn plating layer. When the plating layer is three layers, it is preferable that the order from bottom to top is a Sn plating layer, a Ni plating layer, and a Sn plating layer. Of these, a two-layer structure of Ni plating and Sn plating is preferable. Below, a case where the plating layer is two layers, an inner plating layer 23 and a surface plating layer 24, will be described.

[0082] <Inner plating layer> The inner plating layer 23 is disposed on the base electrode layer 21 and covers at least a portion of the base electrode layer 21 .

[0083] <Surface plating layer> The surface plating layer 24 is disposed on the inner plating layer 23 and covers at least a portion of the inner plating layer 23.

[0084] The plating layers, including the inner plating layer 23 and the surface plating layer 24, preferably contain at least one selected from metals such as Cu, Ni, Ag, Pd, Au, and Sn, and alloys such as Ag-Pd alloys. Among these, the inner plating layer 23 is preferably a Ni plating layer, and the surface plating layer 24 is preferably a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting a ceramic electronic component. The Sn plating layer can improve the wettability of solder when mounting a ceramic electronic component, facilitating mounting. Using a Sn plating layer as the surface plating layer 24 can improve the wettability of solder to the external electrode 20. The thickness of each plating layer is preferably 1.0 μm or more and 15 μm or less.

[0085] <Internal structure of laminate (WT cross section)> The internal structure of the laminate 2, particularly the internal structure from the second end face E2, will be described with reference to FIG. 5. FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II. The laminate 2 has an electrode facing portion WF where the internal electrode layers 10 face each other, and a side gap portion SG in the width direction W. The side gap portion SG includes a first side gap SG1 and a second side gap SG2. The first side gap SG1 and the second side gap SG2 are arranged to sandwich the electrode facing portion WF. The first side gap SG1 is located between the electrode facing portion WF and the first side face S1, and the second side gap SG2 is located between the electrode facing portion WF and the second side face S2.

[0086] Specifically, the first side gap SG1 is located between the end of the internal electrode layer 10 on the first side surface S1 side and the first side surface S1, and the second side gap SG2 is located between the end of the internal electrode layer 10 on the second side surface S2 side and the second side surface S2. The first side gap SG1 and the second side gap SG2 do not include the internal electrode layer 10, but include only the dielectric layer 4. The first side gap SG1 and the second side gap SG2 function as protective layers for the internal electrode layer 10. The side gap SG is a section in the width direction W, and is therefore also called a W gap.

[0087] The length of the side gap portion SG in the width direction W can be set to, for example, 5 μm or more and 50 μm or less.

[0088] <Size of multilayer ceramic capacitor> The size of the multilayer ceramic capacitor 1 is not particularly limited. The size of the multilayer ceramic capacitor 1 can be, for example, as follows. That is, the dimension in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, is defined as dimension L. The dimension L is preferably 0.2 mm or more and 6.5 mm or less. The dimension in the stacking direction T of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, is defined as dimension T. The dimension T is preferably 0.1 mm or more and 6.5 mm or less. Furthermore, the dimension in the width direction W of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, is defined as dimension W. The dimension W is preferably 0.1 mm or more and 5.5 mm or less. The lengths of each part of the laminate 2 and the external electrodes 20 can be measured using a micrometer or an optical microscope.

[0089] In this embodiment, the multilayer ceramic capacitor 1 is a two-terminal capacitor.

[0090] <Corner> The multilayer ceramic capacitor 1 of this embodiment is characterized by the corners of the capacitor main portion 3. This will be described with reference to Figs. 6 and 7. Fig. 6(a) is a cross-sectional view taken along line III-III in Fig. 2, and Fig. 6(b) is a view corresponding to the cross-sectional view taken along line III-III in Fig. 2 of a conventional multilayer ceramic capacitor. Fig. 7 is a view corresponding to the cross-sectional view taken along line III-III in Fig. 2 of another embodiment of the present invention.

[0091] In the multilayer ceramic capacitor 1 of this embodiment, the capacitor main portion 3 has curved corners C, which are portions where the main surface M and the main portion side surface SS intersect.

[0092] <Definition of corners> In the capacitor main portion 3, the corner where the first main surface M1 and the first main-portion side surface SS1 intersect is referred to as corner C1, and the corner where the second main surface M2 and the first main-portion side surface SS1 intersect is referred to as corner C2. Similarly, in the capacitor main portion 3, the corner where the first main surface M1 and the second main-portion side surface SS2 intersect is referred to as corner C3, and the corner where the second main surface M2 and the second main-portion side surface SS2 intersect is referred to as corner C4.

[0093] <Corner curvature> In the multilayer ceramic capacitor 1 of this embodiment, the corners C are curved. As shown in FIG. 6(b), in a conventional multilayer ceramic capacitor 1, the corners C are bent at approximately right angles when viewed from the longitudinal direction L of the capacitor main portion 3, in other words, in the WT cross section. In contrast, in the multilayer ceramic capacitor 1 of this embodiment, the corners C are curved, as shown in FIG. 6(a). Specifically, the corner C1 is curved across the first main surface M1 and the first main-portion side surface SS1. The same is true for the other corners C. The corner C2 is curved across the second main surface M2 and the first main-portion side surface SS1. The corner C3 is curved across the first main surface M1 and the second main-portion side surface SS2. The corner C4 is curved across the second main surface M2 and the second main-portion side surface SS2.

[0094] <Insulating covering> The insulating portion 8 covers this curved corner C. That is, as shown in FIG. 6(a), the insulating portion 8 covers the corner C when viewed from the longitudinal direction L of the capacitor main portion 3, in other words, in the WT cross section.

[0095] The second corner C2 will be taken as an example. The outer edge of the second corner C2 does not pass through point P3, which is the point where the second main surface M2 and the first main portion side surface SS1 intersect. This is because the second corner C2 is curved due to the absence of the outer dielectric layer 5 in the vicinity of point P3.

[0096] A point on the first main portion side surface SS1 closer to the first main surface M1 than point P3 is designated as point P2. A point on the second main portion side surface M2 closer to the second main portion side surface SS2 than point P3 is designated as point P4. The second corner C2 is curved in such a way that points P2 and P4 are connected by a curve.

[0097] The first insulating portion 8a is also disposed in the area surrounded by points P2, P3, and P4, so that the second corner C2 is covered by the first insulating portion 8a from point P2 to point P4.

[0098] The same applies to the corners other than the first corner C1, i.e., the second corner C2, the third corner C3, and the fourth corner C4. As described above, the first insulating portion 8a covers the first corner C1 and the second corner C2, and the second insulating portion 8b covers the third corner C3 and the fourth corner C4.

[0099] <Continuous coating> When the capacitor main part 3 is viewed in its longitudinal direction L, the insulating part 8 continuously covers the corner C. In particular, the insulating part 8 starts from the end point on the main part side surface SS of the corner C and continuously covers the corner C from that starting point. This will be explained using the second corner C2 as an example. As shown in FIG. 6(a), at the second corner C2, the first insulating part 8a continuously covers the second corner C2 from point P2 to point P4 without separating from the capacitor main part 3.

[0100] Here, point P2 is the end point of the second corner C2 on the first main side surface SS1. Therefore, when the laminate 2 is viewed from its longitudinal direction L, it can be said that the first insulating portion 8a continuously covers the second corner C2 from the first main side surface SS1. The same is true for corners C other than the second corner C2.

[0101] As described above, when the capacitor main part 3 is viewed from its longitudinal direction L, the first insulating part 8a continuously covers the first corner C1 and the second corner C2, and similarly, continuously covers the second insulating part 8b, the third corner C3 and the fourth corner C4.

[0102] <Coverage> Furthermore, when the capacitor main body 3 is viewed in the longitudinal direction L, the insulating portion 8 covers 50% or more of the corner C, starting from the upper end point of the corner C on the main-portion side surface SS and following the shape of the corner C. The second corner C2 will be described as an example. As shown in FIG. 6(a), at the second corner C2, the first insulating portion 8a continuously covers the second corner C2 from point P2 to point P4 without separating from the capacitor main body 3. Point P2 is the upper end point of the first main-portion side surface SS1 at the second corner C2. Therefore, when the laminate 2 is viewed in the longitudinal direction L, the first insulating portion 8a covers 50% or more of the second corner C2, starting from point P2, which is the upper end point of the first main-portion side surface SS1, and following the shape of the second corner C2. The same applies to corners C other than the second corner C2.

[0103] As described above, when viewed from the longitudinal direction L of the capacitor main part 3, the first insulating part 8a covers more than 50% of the first corner part C1 and the second corner part C2 from the end points on the first main part side surface SS1 of the first corner part C1 and the second corner part C2, along the shapes of the first corner part C1 and the second corner part C2, and similarly, the second insulating part 8b covers more than 50% of the third corner part C3 and the fourth corner part C4 from the end points on the second main part side surface SS2 of the third corner part C3 and the fourth corner part C4, along the shapes of the third corner part C3 and the fourth corner part C4.

[0104] <Surface roughness> Next, the roughness of the corner C will be described. In the multilayer ceramic capacitor 1 of this embodiment, the roughness of the corner C is greater than the roughness of the insulating portion 8 located on the corner C. In other words, the roughness of the corner C is greater than the roughness of the corner of the laminate 2 corresponding to the corner C. This will be explained below.

[0105] <Outer corner> In the first insulating portion 8a, the corner where the first main surface M1 and the first side surface S1 intersect is referred to as the first outer corner K1. Furthermore, in the first insulating portion 8a, the corner where the second main surface M2 and the first side surface S1 intersect is referred to as the second outer corner K2. Similarly, in the second insulating portion 8b, the corner where the first main surface M1 and the second side surface S2 intersect is referred to as the third outer corner K3. Furthermore, in the second insulating portion 8b, the corner where the second main surface M2 and the second side surface S2 intersect is referred to as the third outer corner K4. As described above, the first side surface S1 is the surface of the first insulating portion 8a opposite to the surface that contacts the first main portion side surface SS1. Furthermore, the second side surface S2 is the surface of the second insulating portion 8b opposite to the surface that contacts the second main portion side surface SS2.

[0106] In the multilayer ceramic capacitor 1 of this embodiment, the roughness of the first corner C1 is greater than the roughness of the first outer corner K1. Similarly, the roughness of the second corner C2 is greater than the roughness of the second outer corner K2, the roughness of the third corner C3 is greater than the roughness of the third outer corner K3, and the roughness of the fourth corner C4 is greater than the roughness of the fourth outer corner K4.

[0107] By increasing the roughness of the corners C in this manner, the anchoring effect of the surface shape of the corners C can increase the adhesive strength between the capacitor main part 3 and the insulating part 8. This makes it possible to prevent or suppress peeling.

[0108] The roughness of the corners C is preferably 0.05 μm or more and less than 1.00 μm. If the roughness is less than 0.05 μm, the anchoring effect is likely to be insufficient. If the roughness is 1.00 μm or more, the surface irregularities become too large, preventing sufficient adhesion between the capacitor main part 3 and the insulating part 8, which may result in air entrapment or peeling.

[0109] <Method of measuring surface roughness> The surface roughness can be measured as follows. Specifically, the 1 / 2 WT cross section of the laminate 2 is observed using an SEM. The laminate 2 and the insulating portion 8 are then binarized, and the roughness of the corner C of the capacitor main portion 3 and the outer corner K of the laminate 2 are measured. Note that the outer corner K of the laminate 2 and the outer corner K of the insulating portion 8 have the same meaning and indicate the same position. More specifically, the roughness was measured using a Keyence digital microscope and image analysis software based on the outlines of the corner C of the capacitor main portion 3 and the outer corner K of the laminate 2. The roughness measured using this image analysis software is the surface roughness Sa in accordance with the ISO-25178 standard.

[0110] <Other corner shapes> Other shapes of the corners C will be described. FIG. 7 is a cross-sectional view corresponding to the line III-III in FIG. 2 according to another embodiment of the present invention. In the other embodiment shown in FIG. 7, the corners C are provided with protrusions V protruding in the width direction W. Specifically, as shown in FIG. 7, in the first outer layer portion OL1, a first protrusion V1 protruding toward the first insulating portion 8a is disposed at the corner C1, and a third protrusion V3 protruding toward the second insulating portion 8b is disposed at the corner C3. Similarly, in the second outer layer portion OL2, a second protrusion V2 protruding toward the first insulating portion 8a is disposed at the corner C2, and a fourth protrusion V4 protruding toward the second insulating portion 8b is disposed at the corner C4.

[0111] The second corner C2 will be used as an example. In Fig. 7, the apex of the second protrusion V2 disposed at the second corner C2, in the direction toward the first insulating portion 8a, is indicated by point P5. As shown in Fig. 7, point P5, which is the apex of the second protrusion V2, protrudes from the first main-portion side surface SS1 of the capacitor main portion 3 toward the first side surface S1 of the laminate 2. A length D5 by which point P5, which is the apex of the second protrusion V2, protrudes from the first main-portion side surface SS1 of the capacitor main portion 3 toward the first side surface S1 of the laminate 2 can be, for example, 0.5 µm or more and 10.0 µm or less.

[0112] Next, the position of the protrusion V in the stacking direction T will be described. In FIG. 7, the thickness of the second outer layer portion OL2 in the stacking direction T is indicated by D1. Line L1 in FIG. 7 indicates a position in the second outer layer portion OL2 that is 10% of the thickness of the second outer layer portion OL2 in the stacking direction T from the second main surface M2. In other words, D1:D2=100:10. Line L2 in FIG. 7 indicates a position in the second outer layer portion OL2 that is 60% of the thickness of the second outer layer portion OL2 in the stacking direction T from the second main surface M2. In other words, D1:D3=100:60.

[0113] As shown in FIG. 7, point P5, which is the vertex of the second protrusion V2, is located in the range from line L1 to line L2 in the stacking direction T of the second outer layer portion OL2. That is, point P5, which is the vertex of the second protrusion V2, is located at a position that is 10% to 60% of the thickness of the second outer layer portion OL2 in the stacking direction T from the second main surface M2. The arrangement of the second protrusion V2 is similar for the protrusions V other than the second protrusion V2. As described above, the protrusion V is located at a position that is 10% to 60% of the thickness of the laminate 2 of the outer layer portion OL in the stacking direction T from the first main surface M1 or the second main surface M2. The position of the protrusion V is the position of the vertex of the protrusion V in the width direction W.

[0114] <Other shapes of convex parts> The shape of the protrusion V can be modified in various ways. An example is shown in FIG. 8. FIG. 8 is a diagram showing another type of protrusion V. FIG. 8 is a diagram corresponding to region R in FIG. 7. In the protrusion V4 shown in FIG. 7, the protrusion V4 is formed so as to extend over the entire area in the stacking direction T of the outer dielectric layer 5. In other words, the edge surface of the outer dielectric layer 5 does not include a straight line portion parallel to the second main portion side surface SS2. In contrast, the protrusion V4 shown in FIG. 8 has a flat portion V4F between the protrusion V4 and the inner layer portion IL in the stacking direction T. This flat portion V4F is a straight line portion parallel to the second main portion side surface SS2 on the edge surface of the outer dielectric layer 5.

[0115] 8, the protrusion V4 can improve the adhesion between the capacitor main part 3 and the second insulating part 8b at the boundary between the second outer layer part OL2 and the inner layer part IL on the second main part side surface SS2, thereby further preventing delamination between the second outer layer part OL2 and the inner layer part IL and preventing moisture and other substances from penetrating between the second outer layer part OL2 and the inner layer part IL.

[0116] <Length direction shape of the convex part> Next, the shape of the protrusion V in the longitudinal direction L will be described with reference to Figs. 9 and 10. Fig. 9 is a perspective view showing a part of the capacitor main part 3. Fig. 10 is a perspective view showing a part of the capacitor main part 3 in another form. More specifically, Figs. 9 and 10 are partial perspective views of the capacitor main part 3, showing up to a part of the length of the capacitor main part 3 in the longitudinal direction L, for the capacitor main part 3 included in the region R in Fig. 7. The protrusion V shown in Fig. 9 and the protrusion V shown in Fig. 10 have different values ​​of D5, which is the height of the protrusion V, in the longitudinal direction L.

[0117] 9 has a constant height D5 in the length direction L. That is, the protrusions V are formed continuously in the length direction L.

[0118] However, the protrusions V do not need to be formed continuously in the length direction L as shown in Fig. 9. It is also possible to have a configuration in which the height D5 of the protrusions V varies in the length direction L, resulting in the presence of multiple peaks. In other words, the protrusions V can be formed in an uneven or discontinuous configuration in the length direction L. Furthermore, in a discontinuous configuration, the peaks may be arranged at regular intervals or at irregular intervals.

[0119] FIG. 10 shows an example of a configuration in which multiple peaks exist. Point P5 in FIG. 10 indicates the point in the length direction L where D5 is maximum. That is, point P5 indicates the position of the peak of the peak. In contrast, point B1 in FIG. 10 indicates the point in the length direction L where D5 is minimum. That is, point B1 indicates the position of the valley between the peaks. As shown in FIG. 10, the protrusion V can be formed so that points P5 and B1 are repeated multiple times in the length direction L. This makes it possible to realize a protrusion V in which multiple peaks exist in the length direction L.

[0120] Furthermore, the protrusion V is not in contact with either the first internal electrode layer 10a or the second internal electrode layer 10b. The second protrusion V2 will be used as an example. In FIG. 7, the boundary between the first outer layer portion OL1 and the internal layer portion IL on the first main portion side surface SS1 is indicated by point P1. As shown in FIG. 7, the second protrusion V2 does not extend beyond point P1 and does not exist within the range of the internal layer portion IL. Therefore, the second protrusion V2 is not in contact with either the first internal electrode layer 10a or the second internal electrode layer 10b. The same applies to the protrusions V other than the second protrusion V2. As described above, the protrusion V is not in contact with either the first internal electrode layer 10a or the second internal electrode layer 10b. In other words, the protrusion V is not joined to the internal electrode layer 10.

[0121] The protrusions V can be protrusions separate from the protrusions caused by the roughness on the corners C. That is, they can be protrusions that are discontinuous with the unevenness of the corners C. Or, the protrusions V can be protrusions that are continuous with the unevenness of the corners C. That is, the protrusions V can be protrusions that extend from the corners C. Furthermore, it is preferable that the width of the protrusions of the protrusions V is wider than the width of the protrusions caused by the roughness of the corners C. Here, the width of the protrusions and protrusions refers to the width in the WT cross section.

[0122] Furthermore, it is preferable that the material forming the protrusions V contains the same main component as that of the dielectric layer 4.

[0123] By arranging the protrusions V as described above, when moisture penetrates from the interface between the laminate 2 and the insulating portion 8, the protrusions V can prevent the moisture from penetrating into the effective portion.

[0124] <Insulation section> The insulating portion will now be described. The thickness of the insulating portion 8 is preferably 10 μm or more and 50 μm or less. If the insulating portion 8 is 10 μm or less in thickness, it will not be able to sufficiently cover the interface exposed on the main portion side surface SS of the capacitor main portion 3. This may result in a decrease in moisture resistance reliability. On the other hand, if the insulating portion 8 is 50 μm or more in thickness, the dimensions of the laminate 2 will become too large. This will reduce the degree of freedom in mounting the multilayer ceramic capacitor 1.

[0125] Furthermore, the insulating part 8 may be a single layer or a double layer. When the insulating part 8 is a double layer, the total thickness of the two layers may be 10 μm or more and 50 μm or less, or the thickness of each layer may be 10 μm or more and 50 μm or less. By making the insulating part 8 a double layer, moisture resistance can be further improved.

[0126] In the above description, the first to fourth corners C are uniform. However, the first to fourth corners C may not be uniform, and for example, each corner C may have a different shape.

[0127] <Method of manufacturing multilayer ceramic electronic components> Next, a method for manufacturing a multilayer ceramic electronic component will be described using the multilayer ceramic capacitor 1 as an example. In the following description, the method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be mainly described with a focus on characteristic aspects.

[0128] <Making laminated blocks> A conductive paste for the dielectric sheets and the internal electrode layers is prepared. The conductive paste for the dielectric sheets and the internal electrode layers contains a binder and a solvent. Known organic binders and organic solvents can be used as the binder and solvent. The conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheets, for example, by screen printing or gravure printing, to form the internal electrode layer pattern. A predetermined number of dielectric sheets for the outer layers, each having no internal electrode layer pattern printed thereon, are stacked on top of these, and a predetermined number of other dielectric sheets for the outer layers are stacked on top of these to produce a laminated sheet. The laminated sheets are pressed in the stacking direction using means such as a hydrostatic press to produce a laminated block.

[0129] <Fabrication of stacked chips> The laminated block is cut to a predetermined size to cut out laminated chips. The laminated chips become the capacitor main section 3 when fired. Hereinafter, the capacitor main section 3 before firing may be referred to as the capacitor main section precursor. After cutting out the laminated chips, the corners of the laminated chips are rounded by barrel polishing or the like. In this process, convex portions are formed around the corners by changing the barrel polishing time, rotation speed, or both.

[0130] <Corner processing> When rounding the corners of a laminated chip, the surface of the corners can be roughened by sanding with sandpaper or by sandblasting, etc., so that the corners have the desired roughness. When using sandpaper, the surface of the corners can be made rougher by using sandpaper with a coarser roughness. The desired roughness can also be achieved by changing the amount of pressure applied by the sandpaper. When using sandblasting, the desired roughness can be achieved by controlling the strength or time of spraying, or both. Note that the method for roughening the corners to have the desired roughness is not limited to the above-mentioned method, and various methods can be used.

[0131] Furthermore, when rounding the corners of the laminated chip, for example, by changing the amount of pressure applied by sandpaper, it is possible to form the convex portion V of the desired shape. However, the method for forming the convex portion V is not limited to this. For example, the convex portion V can also be formed by depositing the scraped material.

[0132] <Formation of insulating part> After the corners are processed, insulating portions 8 are formed on each of the two main side surfaces SS of the precursor of the capacitor main portion 3 having the desired corner shape. The insulating portions 8 may be formed by punching an insulating sheet into the main side surfaces SS, or by forming the insulating portions 8 on the main side surfaces SS by a dipping method.

[0133] When the insulating portion 8 is formed by a punching method using an insulating sheet, the desired hardness is given to the elastic body used in punching, and the amount of pressing is adjusted, so that the insulating portion 8 can be formed to cover from the main portion side surface SS to any position of the corner.

[0134] When the insulating portion 8 is formed by the dipping method, the insulating portion can be formed into a desired shape by changing the pressure applied during dipping, the amount of insulating paste, or both.

[0135] <Firing> Next, the laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric layers 4 and the internal electrode layers 10, but is preferably 900°C or higher and 1400°C or lower. Note that the insulating section 8 may be formed after firing the laminated chip, or the insulating section 8 may be formed before firing, and the laminated chip provided with the insulating section 8 may then be fired.

[0136] Before or after the firing, it is preferable to round the outer corners K of the laminate 2, in other words, the outer corners K of the insulating portion 8. At this time, the outer corners K can also be roughened to a predetermined roughness. The method of rounding or roughening the surface can be the same as the method used to process the corners of the laminated chip described above.

[0137] <External electrode> Next, the formation of the external electrodes 20 will be described. <When the base electrode layer is a baked layer> First, a conductive paste that will become the base electrode layer 21 is applied to both end faces E of the laminate 2 to form the base electrode layer 21. When forming a baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer 21. The baking temperature at this time is preferably 700°C or higher and 900°C or lower. Thereafter, if necessary, plating is performed on the surface of the baked layer.

[0138] <When a conductive resin layer is provided> When the base electrode layer 21 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or may be formed directly on the laminate 2 without forming a baking layer. The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate 2, and then performing a heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form a conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. In addition, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0139] <When a thin film layer is provided> When the base electrode layer 21 is formed as a thin film layer, it can be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 21 formed as a thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0140] <When forming a plating layer directly> A plating layer may be provided directly on the exposed portions of the internal electrode layers 10 of the laminate 2. In this case, it can be formed by the following method. That is, a plating process is performed on the first end face E1 and the second end face E2 of the laminate 2, and a plating film is formed directly on the exposed portions of the internal electrode layers 10. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. As a plating method, it is preferable to use barrel plating. Furthermore, if necessary, an upper layer plating electrode, which is usually formed on the surface of a lower layer plating electrode, may be formed in the same manner.

[0141] Thereafter, a plating layer is formed on the surface of the base electrode layer, the surface of the conductive resin layer, or the surface of the direct plating layer. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating. In this manner, the multilayer ceramic capacitor 1 is obtained.

[0142] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0143] For example, the method for forming the external electrodes 20 is not limited to the above-described method. For example, Ni may be screen-printed on the two end faces E of the laminate 2. Then, the two end faces E are dipped in Cu to form a Cu layer on the Ni. Then, Ni and Sn plating may be applied to form the external electrodes 20.

[0144] The above explanation has focused on the intersection of two surfaces of the laminate 2 or the capacitor main part 3. However, the curvature of the corners and the predetermined roughness of the corners are not limited to the intersection of two surfaces. Alternatively, the intersection of three surfaces of the laminate 2 or the capacitor main part 3 can also be similarly curved, have a roughened surface, or both.

[0145] <1> a plurality of dielectric layers stacked together; a first main surface and a second main surface facing each other in the stacking direction; A first main portion side surface and a second main portion side surface facing each other in a width direction perpendicular to the stacking direction; a first end surface and a second end surface facing each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer alternately stacked with the plurality of dielectric layers and exposed to the first end face, the first main side face, and the second main side face; a capacitor main body including second internal electrode layers alternately stacked with the plurality of dielectric layers and exposed to the second end face, the first main body side face, and the second main body side face; a first insulating portion disposed on a first main portion side surface of the capacitor main portion; a second insulating portion disposed on a second main portion side surface of the capacitor main portion; a first external electrode provided so as to extend from the first end face to the first main surface, the second main surface, the surface of the first insulating portion, and the surface of the second insulating portion; a second external electrode provided so as to extend from the second end face to the first main surface, the second main surface, the surface of the first insulating portion, and the surface of the second insulating portion; the capacitor main portion has a first corner portion curved across the first main surface and the first main portion side surface of the capacitor main portion, a second corner portion curved across the second main surface and the first main portion side surface, a third corner portion curved across the first main surface and the second main portion side surface, and a fourth corner portion curved across the second main surface and the second main portion side surface, the first insulating portion covers the first corner portion and the second corner portion; the second insulating portion covers the third corner portion and the fourth corner portion, a surface of the first insulating portion opposite to a surface in contact with the first main portion side surface is defined as a first side surface of the laminate; a surface of the second insulating portion opposite to a surface in contact with the second main portion side surface is defined as a second side surface of the laminate; the first insulating portion has a first outer corner where the first main surface and the first side surface intersect, and a second outer corner where the second main surface and the first side surface intersect, the second insulating portion has a third outer corner where the first main surface and the second side surface intersect, and a fourth outer corner where the second main surface and the second side surface intersect, the roughness of the first corner is greater than the roughness of the first outer corner; the roughness of the second corner is greater than the roughness of the second outer corner; the roughness of the third corner is greater than the roughness of the third outer corner; The roughness of the fourth corner is greater than the roughness of the fourth outer corner. Multilayer ceramic capacitor.

[0146] This configuration makes it possible to provide a multilayer ceramic capacitor that is small and has a large capacity, while suppressing a decrease in moisture resistance. This is because the roughened surface of the corners tends to strengthen the adhesion between the insulating parts and the corners.

[0147] <2> the surface roughness of the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion is 0.05 μm or more and 1.00 μm or less; <1> The multilayer ceramic capacitor according to claim 1.

[0148] <3> The capacitor main body includes: an inner layer portion formed by alternately stacking the first inner electrode layers, the dielectric layers, and the second inner electrode layers; a first outer layer portion located on the first main surface side of the inner layer portion in the stacking direction and made of the dielectric layer; a second outer layer portion made of the dielectric layer and located on the second main surface side of the inner layer portion in the stacking direction, a first convex portion protruding toward the first insulating portion and a third convex portion protruding toward the second insulating portion are arranged in the first outer layer portion at a position from the first main surface that is 10% to 60% of the thickness of the first outer layer portion in the stacking direction, a second convex portion protruding toward the first insulating portion and a fourth convex portion protruding toward the second insulating portion are arranged in the second outer layer portion at a position from the second main surface that is 10% to 60% of the thickness of the second outer layer portion in the stacking direction. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0149] This configuration can further prevent moisture and the like from penetrating into the inner layer portion, because the protrusions can further prevent water from penetrating from the outer layer portion to the inner layer portion.

[0150] <4> the first convex portion, the second convex portion, the third convex portion, and the fourth convex portion are not in contact with either the first internal electrode layer or the second internal electrode layer; <3> The multilayer ceramic capacitor according to claim 1.

[0151] This configuration can further prevent moisture and the like from penetrating into the inner layer portion, because it makes it difficult for inclusions to be present between the internal electrode and the insulating portion, and strengthens the adhesion between the inner layer portion and the insulating portion.

[0152] <5> The thickness of the first insulating portion and the second insulating portion in the width direction is 10.0 μm or more and 50.0 μm or less. <1> from <4> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes.

[0153] <6> When viewed from the longitudinal direction of the capacitor main body, the first insulating portion continuously covers the first corner portion and the second corner portion, the second insulating portion continuously covers the third corner portion and the fourth corner portion. <1> from <5> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes.

[0154] This configuration can further prevent moisture and the like from penetrating into the inner layer portion, because the penetration of moisture and the like into the inner layer portion is prevented on both sides in the stacking direction.

[0155] <7> When viewed from the longitudinal direction of the capacitor main body the first insulating portion covers 50% or more of the first corner portion and the second corner portion from end points on the first main portion side surface of the first corner portion and the second corner portion along the shapes of the first corner portion and the second corner portion; the second insulating portion covers 50% or more of the third corner portion and the fourth corner portion from end points on the second main portion side surface of the third corner portion and the fourth corner portion along the shapes of the third corner portion and the fourth corner portion; <1> from <6> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes. [Explanation of symbols]

[0156] 1. Multilayer ceramic capacitors 2. Laminate 3 Main capacitor part 4 Dielectric Layer 5. Outer dielectric layer 6 Inner dielectric layer 8 Insulation 10 Internal electrode layer 11 Counter electrode section 12 Extraction electrode 20 External electrode 21 Base electrode layer 23 Inner plating layer 24 Surface plating layer 25 Edge external electrode 26 Main surface external electrode 27 Side external electrode IL Inner Layer OL outer layer LF electrode opposing part EG end gap WF electrode facing part SG Side gap part C Corner K Outer corner V convex part M main surface E End face S side SS Main section side T Stacking direction L lengthwise W width direction

Claims

1. a plurality of dielectric layers stacked together; a first main surface and a second main surface facing each other in a stacking direction; a first main portion side surface and a second main portion side surface facing each other in a width direction perpendicular to the stacking direction; a first end surface and a second end surface facing each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer that is alternately stacked with the plurality of dielectric layers and exposed to the first end face, the first main side face, and the second main side face; second internal electrode layers alternately stacked with the plurality of dielectric layers and exposed at the second end face, the first main side face, and the second main side face; a capacitor main body including: a first insulating portion disposed on a first main portion side surface of the capacitor main portion; a second insulating portion disposed on a second main portion side surface of the capacitor main portion; a first external electrode provided so as to extend from the first end face to the first main surface, the second main surface, a surface of the first insulating portion, and a surface of the second insulating portion; a second external electrode provided so as to extend from the second end face to the first main surface, the second main surface, a surface of the first insulating portion, and a surface of the second insulating portion; the capacitor main portion has a first corner portion curved across the first main surface and the first main portion side surface of the capacitor main portion, a second corner portion curved across the second main surface and the first main portion side surface, a third corner portion curved across the first main surface and the second main portion side surface, and a fourth corner portion curved across the second main surface and the second main portion side surface, the first insulating portion covers the first corner portion and the second corner portion; the second insulating portion covers the third corner portion and the fourth corner portion, a surface of the first insulating portion opposite to a surface in contact with the first main portion side surface is defined as a first side surface of the laminate; a surface of the second insulating portion opposite to a surface in contact with the second main portion side surface is defined as a second side surface of the laminate; the first insulating portion has a first outer corner where the first main surface and the first side surface intersect, and a second outer corner where the second main surface and the first side surface intersect, the second insulating portion has a third outer corner where the first main surface and the second side surface intersect, and a fourth outer corner where the second main surface and the second side surface intersect, the roughness of the first corner is greater than the roughness of the first outer corner; the roughness of the second corner is greater than the roughness of the second outer corner; the roughness of the third corner is greater than the roughness of the third outer corner; the roughness of the fourth corner is greater than the roughness of the fourth outer corner; Multilayer ceramic capacitor.

2. the surface roughness of the first corner portion, the second corner portion, the third corner portion, and the fourth corner portion is 0.05 μm or more and 1.00 μm or less; The multilayer ceramic capacitor according to claim 1 .

3. The capacitor main body includes: an inner layer portion formed by alternately stacking the first inner electrode layers, the dielectric layers, and the second inner electrode layers; a first outer layer portion located on the first main surface side of the inner layer portion in the stacking direction and made of the dielectric layer; a second outer layer portion made of the dielectric layer and located on the second main surface side of the inner layer portion in the stacking direction, a first convex portion protruding toward the first insulating portion and a third convex portion protruding toward the second insulating portion are arranged in the first outer layer portion at a position from the first main surface that is 10% to 60% of a thickness of the first outer layer portion in the stacking direction, a second convex portion protruding toward the first insulating portion and a fourth convex portion protruding toward the second insulating portion are arranged in the second outer layer portion at a position from the second main surface that is 10% to 60% of the thickness of the second outer layer portion in the stacking direction, 3. The multilayer ceramic capacitor according to claim 1.

4. the first convex portion, the second convex portion, the third convex portion, and the fourth convex portion are not in contact with either the first internal electrode layer or the second internal electrode layer; The multilayer ceramic capacitor according to claim 3 .

5. The thickness of the first insulating portion and the second insulating portion in the width direction is 10.0 μm or more and 50.0 μm or less.

3. The multilayer ceramic capacitor according to claim 1.

6. When viewed from the longitudinal direction of the capacitor main body, the first insulating portion continuously covers the first corner portion and the second corner portion; the second insulating portion continuously covers the third corner portion and the fourth corner portion; 3. The multilayer ceramic capacitor according to claim 1.

7. When viewed from the longitudinal direction of the capacitor main body the first insulating portion covers 50% or more of the first corner portion and the second corner portion from end points on the first main portion side surface of the first corner portion and the second corner portion along the shapes of the first corner portion and the second corner portion; the second insulating portion covers 50% or more of the third corner portion and the fourth corner portion from end points on the second main portion side surface of the third corner portion and the fourth corner portion along the shapes of the third corner portion and the fourth corner portion, 3. The multilayer ceramic capacitor according to claim 1.

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