Neuromorphic device, electronic system and driving method thereof

Abstract

To provide a neuromorphic device, electronic system, and a driving method thereof.SOLUTION: A neuromorphic device provided herein comprises a first resistor line RL1 having a plurality of resistors R11-R13 that are connected in series, a second resistor line RL2 having a plurality of resistors R14-R16 that are connected in series, one or more current sources configured to control current I1, I2 flowing through each of the first resistor line and the second resistor line at a respective current level, a first capacitor C1 electrically connected to the first resistor line, and a second capacitor C2 electrically connected to the second resistor line.SELECTED DRAWING: Figure 12A

Description

[Technical Field]

[0001] The present invention relates to a neuromorphic device, an electronic system, and a driving method thereof. [Background technology]

[0002] Neural network processing in a neural network device involves a multiply-accumulate (MAC) operation, which repeats multiplication and addition. At a specific node in a neural network, a calculation is performed in which the node value of a previous layer is multiplied by the weight mapped to it, and then an appropriate activation function is applied. To perform this calculation, a memory access operation is performed in which appropriate inputs and weights are loaded at desired times, and a MAC calculation is performed in which the loaded inputs and weights are multiplied and added. Instead of processing neural networks using commonly known digital computers, various methods have been attempted to more efficiently perform neural network processing, such as MAC calculations, using other hardware architectures. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a neuromorphic device and an electronic system including the same, which have improved reliability and power efficiency of analog calculations. The technical problem to be solved by the present invention is not limited to the above-mentioned technical problem, and other technical problems may be inferred from the following examples. [Means for solving the problem]

[0004] According to one aspect, a neuromorphic device includes a first resistor line including a plurality of resistors connected in series, a second resistor line including a plurality of resistors connected in series, one or more current sources capable of controlling the current flowing through each of the first resistor line and the second resistor line by a predetermined current value, a first capacitor electrically connected to the first resistor line, and a second capacitor electrically connected to the second resistor line.

[0005] The neuromorphic device further includes a switch that can be switched to connect the first capacitor and the second capacitor in parallel.

[0006] The neuromorphic device further includes a voltage measuring device that measures a potential difference between both ends of the first and second capacitors when the first and second capacitors are connected in parallel.

[0007] The neuromorphic device includes a plurality of current sources coupled to the first resistor line and the second resistor line, respectively.

[0008] The neuromorphic device includes a current source commonly coupled to the first resistor line and the second resistor line.

[0009] The neuromorphic device further includes a controller that applies an input and a weight to the resistor.

[0010] In the neuromorphic device, the one or more current sources control the current flowing through the first resistor line and the current flowing through the second resistor line with the same current value.

[0011] The neuromorphic device further includes a controller that applies inputs and weights to the resistors, the controller independently controlling the inputs applied to the resistors included in the first resistor line and the inputs applied to the resistors included in the second resistor line.

[0012] In the neuromorphic device, the first capacitor and the second capacitor have the same capacitance.

[0013] The neuromorphic device further includes a first switch disposed between the first capacitor and the first resistor line, and a second switch disposed between the second capacitor and the second resistor line.

[0014] In the neuromorphic device, each of the resistors includes a magnetic memory element having a plurality of resistance values.

[0015] In the neuromorphic device, one end of the first capacitor and one end of the second capacitor are electrically connected.

[0016] According to another aspect, a method for driving a neuromorphic device includes applying a current having a predetermined current value to a first resistor line including a plurality of resistors connected in series and a second resistor line including a plurality of resistors connected in series; sampling a first voltage of the first resistor line using a first capacitor connected to the first resistor line and a second voltage of the second resistor line using a second capacitor connected to the second resistor line; and measuring voltages across the first and second capacitors connected in parallel by switching one end of the first capacitor and one end of the second capacitor to be connected in parallel.

[0017] The method for driving a neuromorphic device further includes calculating, from the measured voltage, the sum of products of the inputs and weights applied to the resistors of the first and second resistor lines.

[0018] The method for driving a neuromorphic device further includes applying a resistance value to a variable resistor included in each of the resistors.

[0019] In the method for driving a neuromorphic device, the sampling step includes sampling the first voltage and then sampling the second voltage.

[0020] According to yet another aspect, a neuromorphic device includes a resistor line in which a plurality of resistors are connected in series, and a current source that applies a current to the resistor line, each of the resistors including at least two variable resistors connected in parallel and a switch connected in series with each of the variable resistors.

[0021] In the neuromorphic device, each of the resistors includes a pair of variable resistors, each of which is a variable resistance element having a first or second resistance value, and when one of the pair of variable resistors has the first resistance value, the other variable resistor has the second resistance value.

[0022] The neuromorphic device further includes a first weight line and a second weight line electrically connected to both ends of the variable resistor.

[0023] The neuromorphic device further includes a voltage measuring device that measures the voltage on the resistor line.

[0024] The neuromorphic device further includes a controller that applies an input and a weight to the resistor, and the sum of the input and the weight applied to the resistor is calculated from the voltage measured by the voltage measuring device.

[0025] According to yet another aspect, a method for driving a neuromorphic device includes the steps of applying a weight and an input to each resistor including at least two variable resistors connected in parallel and a switch connected in series with each of the variable resistors; applying a current to a resistor line to which the resistors are connected in series; and calculating the sum of products of the inputs and the weights applied to the resistors from voltages generated in the resistor lines by the applied current.

[0026] In the method for driving a neuromorphic device, each of the resistors includes a pair of variable resistors, and the step of applying a weight and an input to each of the resistors includes applying the weight and the input so that the pair of variable resistors included in each of the resistors are set to different resistance values.

[0027] In the method for driving a neuromorphic device, the step of applying the current applies the current by closing at least one of the switches included in each of the resistors so that the current flows through any one of the variable resistors included in each of the resistors.

[0028] According to yet another aspect, an electronic system includes a neural network device including a neuromorphic device; and a central processing unit (CPU) having a processor core and controlling the function of the neural network device, wherein the neuromorphic device includes: a first resistor line including a plurality of resistors connected in series; a second resistor line including a plurality of resistors connected in series; one or more current sources capable of controlling currents flowing through each of the first resistor line and the second resistor line at a predetermined current value; a first capacitor electrically connected to the first resistor line; and a second capacitor electrically connected to the second resistor line.

[0029] The electronic system further includes a switch that the neuromorphic device can switch to connect the first capacitor and the second capacitor in parallel.

[0030] The electronic system further includes a voltage measuring device that measures a potential difference across the first and second capacitors when the first and second capacitors are connected in parallel.

[0031] According to yet another aspect, an electronic system includes a neural network device including a neuromorphic device; and a central processing unit (CPU) having a processor core and controlling the function of the neural network device, the neuromorphic device including a resistor line in which a plurality of resistors are connected in series, and a current source that applies current to the resistor line, each of the resistors including at least two variable resistors connected in parallel and a switch connected in series with each of the variable resistors.

[0032] In the electronic system, each of the resistors includes a pair of variable resistors, each of which is a variable resistance element having a first or second resistance value, and when one of the pair of variable resistors has the first resistance value, the other variable resistor has the second resistance value.

[0033] The electronic system further includes a first weight line and a second weight line that the neuromorphic device electrically connects across the variable resistor.

[0034] The electronic system further includes a voltage measuring device for measuring the voltage of the resistor line by the neuromorphic device. [Effects of the Invention]

[0035] According to an embodiment of the present invention, the reliability of a neuromorphic device can be improved. According to an embodiment, the power efficiency of a neural network device and an electronic system including a neuromorphic device can be improved by using a capacitor to expand the range of operations that can be performed in an analog circuit domain. [Brief explanation of the drawings]

[0036] [Figure 1] 1 is a diagram illustrating a biological neuron and its operation. [Figure 2] 1 is a diagram illustrating an example of a neural network. [Figure 3A]1 is a diagram illustrating an example of a neuromorphic device. [Figure 3B] 1 is a diagram illustrating an example of a neuromorphic device. [Figure 4] 3B is a diagram illustrating the structure and operation of a voltage measuring device applied to the neuromorphic device of FIG. 3A. [Figure 5A] 3B is a diagram illustrating the structure and operation of a resistor applied to the neuromorphic device of FIG. 3A. [Figure 5B] 3B is a diagram illustrating the structure and operation of a resistor applied to the neuromorphic device of FIG. 3A. [Figure 5C] 3B is a diagram illustrating the structure and operation of a resistor applied to the neuromorphic device of FIG. 3A. [Figure 6] 3B is a diagram illustrating the structure and operation for setting weights on resistors of the neuromorphic device of FIG. 3A. [Figure 7] 3B is a diagram illustrating the flow of current when input and current are applied to the neuromorphic device of FIG. 3A. [Figure 8A] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device in which the same input is applied to two rows of resistor lines. [Figure 8B] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device in which the same input is applied to two rows of resistor lines. [Figure 9] 8C is a diagram for explaining the operation of the neuromorphic device of FIG. 8B when a current is applied to the device. [Figure 10A] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device that calculates the sum of products of inputs applied to two rows of resistor lines and weights. [Figure 10B] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device that calculates the sum of products of inputs applied to two rows of resistor lines and weights. [Figure 11]8C is a diagram for explaining the operation of the neuromorphic device of FIG. 8B when a current is applied to the device. [Figure 12A] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device that calculates, in the analog domain, the sum of products of inputs applied to two rows of resistor lines and weights. [Figure 12B] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device that calculates, in the analog domain, the sum of products of inputs applied to two rows of resistor lines and weights. [Figure 13A] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device that calculates, in the analog domain, the sum of products of inputs applied to two rows of resistor lines and weights. [Figure 13B] 1 is a diagram illustrating an example of the structure and operation of a neuromorphic device that calculates, in the analog domain, the sum of products of inputs applied to two rows of resistor lines and weights. [Figure 14] FIG. 1 is a chip block diagram of a neuromorphic device according to an example. [Figure 15] FIG. 1 is a block diagram illustrating an electronic system according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0037] Various examples of the present document will now be described with reference to the accompanying drawings. The examples and terms used therein are not intended to limit the technology described in the present document to a specific embodiment, but should be understood to include various modifications, equivalents, and / or alternatives of the examples. In describing the drawings, similar reference numerals may be used for similar elements. The singular includes the plural unless the context clearly dictates otherwise. In the various examples of the present document, expressions such as "A or B" or "A and / or B" include all possible combinations of the listed items. Expressions such as "first," "second," and the like can modify the elements in question, regardless of order or importance, and are used only to distinguish one element from other elements, not to limit the elements in question.

[0038] In the description of the embodiments, when a part is said to be connected to another part, this includes not only a direct connection but also a connection via another component. Furthermore, when a part is said to "comprise" a component, it does not mean that the other component is excluded, but that the part may further include the other component, unless otherwise specified. On the other hand, the term "comprise" should not be interpreted as including any of the multiple components or multiple steps described in the specification.

[0039] The embodiments described below relate to the technical field of neuromorphic devices (e.g., neuromorphic processors), and detailed descriptions of matters that are well known to those skilled in the art will be omitted.

[0040] Unlike conventional digital computers that use a common data bus to transmit and receive information, neuromorphic devices have analog circuits for processing multiplication and addition operations, and related embodiments will be described with reference to the following drawings.

[0041] The following description of the embodiments should not be construed as limiting the scope of the invention, and any content that can be easily inferred by a person skilled in the art should be construed as falling within the scope of the present specification. Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings for illustrative purposes only.

[0042] FIG. 1 is a diagram illustrating a biological neuron and its operation.

[0043] Referring to Figure 1, a biological neuron 10 refers to a cell present in the human nervous system and is one of the fundamental biological computational entities. The human brain contains approximately 100 billion biological neurons and approximately 100 trillion interconnections between them.

[0044] A biological neuron 10 is a single cell that includes a cell body containing a nucleus and various organelles, including mitochondria, numerous dendrites that emanate from the cell body, and an axon that traverses the cell body with many branching extensions.

[0045] Generally, axons transmit signals from one neuron to another, and dendrites receive signals from another neuron. For example, when different neurons are connected to each other, a signal transmitted through one neuron's axon is received by the dendrites of the other neuron. Signals are transmitted between neurons through specialized connections called synapses, and multiple neurons are connected to each other to form a neural network. Neurons that secrete neurotransmitters through synapses are called presynaptic neurons, and neurons that receive information transmitted through neurotransmitters are called postsynaptic neurons.

[0046] The human brain can learn and memorize a huge amount of information by transmitting and processing various signals through a neural network formed by interconnecting such a large number of neurons. Various attempts have been made to develop a computer device that can efficiently process a huge amount of information by replicating such a biological neural network.

[0047] FIG. 2 is a diagram for explaining an example of a neural network.

[0048] Referring to FIG. 2, an example of an artificial neural network (i.e., neural network 20) ​​that mimics the above-mentioned biological neural network is shown. The neural network 20 is an example of a deep neural network (DNN). For convenience of explanation, the neural network 20 is illustrated as including two hidden layers, but may include multiple hidden layers. Also, in FIG. 2, the neural network 20 is illustrated as including a separate input layer 21 for receiving input data, but the input data may be directly input to the hidden layer.

[0049] In the neural network 20, artificial nodes in layers other than the output layer are connected to artificial nodes in the next layer through links for transmitting output signals. Through these links, the artificial nodes receive the output of activation functions related to the weighted inputs of the artificial nodes included in the previous layer. The weighted inputs are the inputs (node ​​values) of the artificial nodes multiplied by weights, where the inputs correspond to axon values ​​and the weights correspond to synaptic weights. The weights are referred to as parameters of the neural network 20. Activation functions include sigmoid, hyperbolic tangent (tanh), and ReLU (rectified linear unit), and nonlinearity can be formed in the neural network 20 depending on the activation function.

[0050] The output of any one node 22 included in such a neural network 20 can be expressed as Equation 1 below.

[0051]

number

[0052] 3A and 3B are diagrams for explaining an example of a neuromorphic device.

[0053] Here, FIG. 3A is a diagram for explaining the architecture of a neuromorphic device according to one embodiment, and FIG. 3B is a diagram illustrating an example of a neural network requiring calculations performed by the neuromorphic device of FIG. 3A.

[0054] Referring to FIG. 3A, the neuromorphic device 100 includes a plurality of resistors R 11 , R 12 , R 13 , resistor R 11 , R 12 , R 13 a current source 130 providing a current I applied to the line, and a total voltage V T1 The voltage measuring device 150 may measure the overall voltage V T1 is the resistance of each resistor R included in the resistor line 11 , R 12 , R13 Potential difference between both ends V 11 , V 12 , V 13 The number of resistors connected in series is not particularly limited, but is preferably 64 to 256. For the sake of convenience, the number of resistors connected in series is three. 11 , R 12 , R 13 A structure in which the following are connected in series will be described as an example.

[0055] 3B, a neural network having three nodes in the first layer 170 and two nodes in the second layer 190 is illustrated. The first layer 170 can be either the input layer or the hidden layer of FIG. 2. The second layer 190 receives a value obtained by multiplying the output value of the first layer 170 by a weight, inputs the resultant value into an activation function, and has the resulting value as a node value, which is provided as an input to the next layer. Specifically, the first node a1 of the second layer 190 performs three multiplications of the output value of the first layer 170 by the weight corresponding to each link, as shown in Equation 2, and an addition operation to sum up the resulting values. Here, for the sake of convenience, details related to the activation function will be omitted.

[0056] Formula 2 a1= x1·w 11 + x2·w 21 + x3·w 31 The neuromorphic device 100 shown in FIG. 3A is a device used to calculate Equation 2. Referring to FIG. 3A, the first to third resistors R 11 , R 12 , R 13 may have different resistance values ​​relative to the current source 130. 11 denotes a first resistor corresponding to a first node in the first layer 170, and similarly, R 12 and R 13 170 respectively refer to a second resistor corresponding to a second node in the first layer 170 and a third resistor corresponding to a third node in the first layer 170.

[0057] Resistor R for current source 130 11 , R 12 , R 13 The resistance value of each resistor R 11 , R 12 , R 13 The inputs x1, x2, x3 and weight w are applied to 11 , w 21 , w 31 where input "x1" refers to the output value or node value of the first node (first layer 170) and the first resistor R 11 Similarly, input "x2" and input "x3" refer to the inputs or node values ​​of the second and third nodes, respectively, and are connected to the second resistor R 12 and the third resistor R 13 The weight "w 11 In ", the left "1" refers to the first node of the first layer 170, and the right "1" refers to the first node of the second layer 190. 11 ” is the weight for the link between the first node of the first layer 170 and the first node of the second layer 190, and the first resistor R 11 Similarly, the weight w 21 and weight w 31 are the second resistor R 12 and the third resistor R 13 This means the weight applied to

[0058] Resistor R for current source 130 11 , R 12 , R 13 The resistance value of each resistor is R 11 , R 12 , R 13 The inputs x1, x2, x3 and weight w are applied to each 11 , w 21 , w 31 A method for calculating the sum of products of inputs and weights by setting the weights to have a value that represents the value obtained by multiplying the inputs by the weights will be described.

[0059] The inputs x1, x2, x3 have values ​​of 1 or -1, and the weights w 11 , w 21 , w 31 Assume that the input value is also 1 or −1. The input value of 1 or −1 means that the node value of the first layer 170 or the resistor R 11 , R 12 , R 13 The weight w means that the input applied to 11 , w 21 , w 31 is 1 or −1, the weights or resistors R assigned to the links between the nodes in the first layer 170 and the nodes in the second layer 190 are 11 , R 12 , R 13 The weight applied to each is either -1 or 1. 11 , w 21 , w 31 is a value determined through learning, or a value modified according to conditions such as the structure of the neural network and the type of input.

[0060] Such inputs x1, x2, x3 and weights w 11 , w 21 , w 31 The product of R and R has a value of 1 or -1. 11 , R 12 , R 13 can be configured to have two different resistance values, i.e., one resistance value is set to correspond to when the product of the input and the weight is 1, and the other resistance value is set to correspond to when the product of the input and the weight is −1. As such a resistor, various elements that can change the resistance value, such as a phase change element or a magnetic tunnel junction (MTJ) element, can be used.

[0061] If the product of the input and the weight is "1", the resistor R 11 , R 12 , R 13The resistance value of each resistor is 20 Ω. When the product of the input and the weight is "-1", the resistor R 11 , R 12 , R 13 Let's take the example of a resistor value of 5Ω. If the first resistor R 11 Weight w 11 If is 1 and 1 is applied to input x1, then input x1 and weight w 11 The product of this and is 1. Therefore, the first resistor R 11 is set to have a resistance of 20 Ω relative to the current source 130. Alternatively, if the first resistor R 11 Weight w 11 is -1 and 1 is applied to input x1, then input x1 and weight w 11 The product of this and is -1. Therefore, the first resistor R 11 is set to have a resistance of 5 Ω relative to the current source 130. Such inputs x1, x2, x3 and weight w 11 , w 21 , w 31 and resistor R 11 , R 12 , R 13 The relationship between the resistance and the capacitance is summarized in Table 1.

[0062] [Table 1] Below, the first to third resistors R 11 , R 12 , R 13 Inputs x1, x2, x3 and weight w for 11 , w 21 , w 31 If is as in Table 2, then the method by which the neuromorphic device 100 operates will be described.

[0063] [Table 2] 1st resistor R 11 Well, weight w11 is set to 1, and 1 is applied as input x1, so input x1 and weight w 11 The product of this is 1·1=1. Therefore, referring to Table 1, the first resistor R 11 The resistance of the second resistor R 12 Well, weight w 21 is set to -1, and 1 is applied as input x2, so input x2 and weight w 21 The product of this is 1·-1=-1. This means that the second resistor R 12 The resistance of the third resistor R 13 Well, weight w 31 is set to -1, and -1 is applied as input x3, so input x3 and weight w 31 The product of this is -1·-1=1. This means that the third resistor R 13 The resistance for the current source 130 is determined to be 20 Ω.

[0064] Inputs x1, x2, x3 and weight w 11 , w 21 , w 31 By each resistor R 11 , R 12 , R 13 Once the resistance value for the current source 130 is determined, the resistor R 11 , R 12 , R 13 A current of a specific value (for example, 1 A) is passed through the line in which the resistors R are connected in series, and a voltage meter 150 is used to measure the potential difference generated by the current. When a current of 1 A is passed, the voltage of each resistor R is measured according to Ohm's law (V=I*R). 11 , R 12 , R 13 A potential difference corresponding to the resistance value occurs between both ends of the resistor. At this time, the overall voltage of the resistor line, that is, the third resistor R 13 and the bottom of the first resistor R 11 potential difference V T1 By measuring the resistance of each resistor R 11 , R 12 , R 13The total potential difference between the resistors R and R is known. Also, the magnitude of the current (for example, 1 A) is known, so that the current flowing through each resistor R in series is known. 11 , R 12 , R 13 The sum of the resistance values ​​set in each resistor R 11 , R 12 , R 13 The sum of the products of the inputs and weights applied to the resistors is known. That is, the total voltage V T1 The total resistance can be calculated from the measured value by Ohm's law (V=IR), and the total resistance is calculated by the resistance of the resistors R connected in series. 11 , R 12 , R 13 The sum of the resistance values ​​of each resistor is the same. 11 , R 12 , R 13 Since each represents the product of the input and the weight applied to it, the total potential difference is calculated by the resistor R 11 , R 12 , R 13 The sum of the products of the inputs and weights applied to each is obtained. The relationship between the total voltage and the sum of the products of the inputs and weights is summarized in Table 3 below.

[0065] [Table 3] If the total voltage due to 1A of current is 45V, then referring to Table 3, the sum of the products of the input and weight is 1. Or, if another weight and input are applied and the measured total voltage is 15V, then the sum of the products is found to be -3, even if the applied input and weight are unknown. 11 , R 12 , R 13 The relationship between the input, weight, current, and voltage for each is summarized in Table 4.

[0066] [Table 4] FIG. 4 is a diagram illustrating the structure and operation of a voltage measuring device applied to the neuromorphic device of FIG. 3A.

[0067] 4, the voltage measuring device 150 detects the resistor R 11 , R 12 , R 13 A method for calculating the sum of the products of the inputs and weights applied to each of the inputs will now be described by way of example.

[0068] The voltage measurer 150 includes a reference voltage generator 151 and a comparator 153, and is driven in a manner of comparing whether a voltage to be measured is higher or lower than the reference voltage to find a section to which the measured voltage belongs. The voltage measurer 150 may be embodied as an analog-to-digital converter (ADC) or a multi-level sense amplifier (MLSA), but is not limited thereto.

[0069] Specifically, the voltage measuring device 150 of Fig. 4 comprises a reference voltage generator 151 that provides three reference voltages (e.g., 22.5V, 37.5V, and 52.5V) and three comparators 153 that output the results of comparing the reference voltages with the measured voltages. However, the reference voltages are merely arbitrary values ​​for the sake of convenience, and the reference voltages are not limited thereto and may be set to other values. The total voltage V applied to the resistor line T1 To measure the total voltage V T1 4 is applied to the other input terminal of each comparator 153, and different reference voltages (e.g., 22.5V, 37.5V, 52.5V) provided by the reference voltage generator 151 are applied to the other input terminal of each comparator 153. By using the comparator 153 of FIG. T1 The corresponding section can be divided into four parts. Specifically, the total voltage V T1 ≥ 52.5V, a second section where 52.5V > VT1 ≥ 37.5V, a third section where 37.5V > VT1 ≥ 22.5V, and a fourth section where 22.5V > VT1.

[0070] Overall voltage V T1 Based on the measurement result of the voltage measuring device 150, it is determined to which section the output of the voltage measuring device 150 belongs, and the sum of the products of the corresponding input and the weight is output. For example, when the measured total voltage V T1 If it is in the first section, the result is 3 and the measured total voltage V T1 If the voltage falls within the second section, the result is 1. This is summarized in Table 5. The voltage range for each section depends on the magnitude of the applied current and the resistance of the resistor. Therefore, the voltage range for each section varies depending on the applied current and resistance.

[0071] The measured overall voltage V T1 is 45V, the measured overall voltage V T1 belongs to the second section, so referring to Table 5, the voltage measuring device 150 outputs a result value of 1. The result value 1 is 11 , R 12 , R 13 The output value of the voltage measurer 150 is the sum of the products of the inputs and weights applied to each. The output value of the voltage measurer 150 is a digital value and also a binary number. For example, if the output value of the voltage measurer 150 is 3, the binary number "11" is output. Alternatively, the output value may be a binary number including a separate sign bit indicating the sign.

[0072] [Table 5] 5A to 5C are diagrams illustrating the structure and operation of a resistor applied to the neuromorphic device of FIG. 3A.

[0073] The structure of a resistor will be described with reference to Figure 5A. The resistive memory cell of Figure 5A may include a pair of variable resistors Ra and Rb, each of which is formed by magnetic tunnel junction (MTJ) elements connected in parallel, and a pair of transistors Sa and Sb connected in series to the variable resistors Ra and Rb, respectively. The variable resistor embodied as a magnetic tunnel junction (MTJ) has a resistance value that varies depending on the magnitude and direction of the applied current (or voltage), and may have non-volatile characteristics in which the resistance value is maintained even when the applied current (or voltage) is cut off.

[0074] The magnetic tunnel junction (MTJ) element may include a pinned layer L3, a free layer L1, and a tunnel layer L2 therebetween. The magnetization direction of the pinned layer L3 is fixed, and the magnetization direction of the free layer L1 may be the same as or different from the magnetization direction of the pinned layer L3 depending on the conditions. To fix the magnetization direction of the pinned layer L3, layers for forming, for example, an antiferromagnetic layer and / or a synthetic antiferromagnetic layer may be further provided.

[0075] The magnetization direction of the free layer L1 can be changed by electrical / magnetic factors provided externally and / or internally of the resistive memory cell. The free layer L1 may include a material having a changeable magnetization direction, such as a ferromagnetic material. Examples of the free layer L1 include CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O 12 and / or combinations thereof.

[0076] The tunnel layer L2 has a thickness less than the spin diffusion length and may include a non-magnetic material such as magnesium (Mg), titanium (Ti), aluminum (Al), magnesium-zinc (MgZn) and magnesium-boron (MgB) oxides, titanium (Ti), vanadium (V) and / or combinations thereof.

[0077] The pinned layer L3 may have its magnetization direction fixed by an antiferromagnetic layer. The pinned layer L3 may be made of a ferromagnetic material, such as CoFeB, FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, or Y3Fe5O 12 and / or combinations thereof.

[0078] As described above, the magnetic tunnel junction (MTJ) element may further include an antiferromagnetic layer and / or a synthetic antiferromagnetic layer to fix the magnetization direction of the pinned layer L3. The antiferromagnetic layer may be made of an antiferromagnetic material, such as PtMn, IrMn, MnO, MnS, MnTe, MnF2, or FeC. l2 , FeO, CoC l2 , CoO, NiC l2 The composite antiferromagnetic layer may include Cu, Ru, Ir, and / or a combination thereof. The composite antiferromagnetic layer may include a spacer including Cu, Ru, Ir, and / or a combination thereof, and a pinned layer having a strong magnetic anisotropy. The pinned layer may include an alloy or multilayer of a ferromagnetic material such as Co, Ni, or Fe and an antiferromagnetic material such as Pt, Pd, Cr, or Ir.

[0079] 5B and 5C show the magnetization directions of a magnetic tunnel junction (MTJ) element according to the data stored in the resistor of FIG. 5A.

[0080] The resistance of the magnetic tunnel junction (MTJ) element is changed by the magnetization direction of the free layer L1. The strength of the write current for changing the magnetization direction of the free layer L1 is much larger than the strength of the drive current. Once the magnetization direction of the free layer L1 is determined so that the magnetic tunnel junction (MTJ) element has a specific resistance, that direction can be determined by supplying a write current. Then, the drive current (or read current) provided to use (read) the resistance of the magnetic tunnel junction (MTJ) element is much smaller than the write current so as not to change the predetermined magnetization direction of the free layer L1.

[0081] FIG. 5B illustrates a state in which the magnetization directions of the free layer L1 and the pinned layer L3 of the magnetic tunnel junction (MTJ) element are parallel. When the magnetization directions are parallel, the magnetic tunnel junction (MTJ) element may have a low resistance, for example, a resistance of 5 Ω. FIG. 5C illustrates a state in which the magnetization directions of the free layer L1 and the pinned layer L3 of the magnetic tunnel junction (MTJ) element are anti-parallel. When the magnetization directions are anti-parallel, the magnetic tunnel junction (MTJ) element may have a high resistance, for example, a resistance of 20 Ω.

[0082] FIG. 6 is a diagram illustrating the structure and operation for setting weights on resistors of the neuromorphic device of FIG. 3A.

[0083] Hereinafter, with reference to FIG. 6, a method for applying weights and inputs to resistors included in the neuromorphic device shown in FIG. 3A will be described in detail.

[0084] Referring to Figure 6, each resistor R 11 , R 12 , R 13may have a structure including a pair of variable resistors connected in parallel and a pair of switches connected in series with each variable resistor. For convenience of explanation, the variable resistor element in FIG. 6 is illustrated as having a resistance value of 20Ω or 5Ω depending on the direction of the voltage applied across both ends. Specifically, the variable resistor R 11a , R 11b , R12a , R 12b , R 13a , R 13b is set to have a resistance of 20 Ω when a potential higher than a certain level is applied to the upper part (first stage) than to the lower part (second stage), and is set to have a resistance of 5 Ω when a potential higher than a certain level is applied to the lower part (second stage) than to the upper part (first stage). For example, referring to FIG. 6, the first resistor R 11 The first variable resistor R 11a If +100V is applied to both ends of R 11a is set to 20 Ω, and similarly, the first resistor R 11 The first variable resistor R 11a If -100V is applied across R 11 is set to 5 Ω.

[0085] In this embodiment, a pair of variable resistors included in one resistor are set to have complementary values ​​that are different from each other. For example, if the first variable resistor R11a is set to 20 Ω, the second variable resistor R 11b is set to 5 Ω, and the first variable resistor R 11a When set to 5Ω, the second variable resistor R 11b is set to 20 Ω.

[0086] First variable resistor R 11a The first resistor R 11 It is also determined by the weight value applied to the first resistor R 11 Weight w applied to 11 , w 21 , w 31 If is 1 or -1, the first resistor R 11 When the weight applied to the first variable resistor R 11ais set to have a resistance of 20 Ω. 11b is the first variable resistor R 11a Since the second variable resistor R 11b is set to 5 Ω. Similarly, the first resistor R 11 Weight w applied to 11 When is -1, the first variable resistor R 11a The second variable resistor R is set to have 5 Ω. 11b is the first variable resistor R 11a and can be set to 20 Ω complementary to

[0087] 2nd resistor R 12 and the third resistor R 13 Also, the first resistor R 11 Similarly, when the applied weight is 1, the first variable resistor R 21 , R 31 has a resistance of 20 Ω, and the second variable resistor R 22 , R 32 is set to have a resistance of 5 Ω. When the applied weight is −1, the first variable resistor R 21 , R 31 has a resistance of 5 Ω, and the second variable resistor R 22 , R 32 may be set to have a resistance of 20 Ω.

[0088] A pair of switches included in one resistor are connected to each resistor R 11 , R 12 , R 13 The first switch S is designed to operate in a complementary manner depending on the inputs x1, x2, and x3 applied to the first switch S. 11a , S 12a , S 13a When the second switch S is closed, 11b , S 12b , S 13b is opened, and the first switch S 11a , S 12a , S 13a When the second switch S is opened, 11b , S 12b , S 13bSuch a switch can be implemented in various ways using, but not limited to, a metal oxide semiconductor field effect transistor (MOSFET) and a simple circuit, so a detailed description of the structure of the switches operating in a complementary manner will be omitted here.

[0089] Which switch is closed / open depends on each resistor R 11 , R 12 , R 13 It is also determined by the inputs x1, x2, and x3 applied to each resistor R 11 , R 12 , R 13 The input applied to the first switch S can be either 1 or -1. When the input is 1, the first switch S 11a , S 12a , S 13a is closed, and the second switch S 11b , S 12b , S 13b is configured to be open. Similarly, resistor R 11 , R 12 , R 13 When the input applied to the first switch S is -1, 11a , S 12a , S 13a is opened, and the second switch S 11b , S 12b , S 13b may be configured to be closed.

[0090] In other words, the first resistor R 11 When the input of the first variable resistor R 11a The first switch S 11a is closed, and the second switch S 11b The circuit is designed so that the first resistor R 11 When the input x1 to 11b The second switch S 11b is closed, and the first switch S 11a The circuit is designed so that the second resistor R 12and the third resistor R 13 The first resistor R 11 Similarly, when the applied inputs x2 and x3 are 1, the first switch S 12a , S 13a is closed, and the second switch S 12b , S 13b is open, and when the applied inputs x2 and x3 are -1, the first switch S 12a , S 13a is opened, and the second switch S 12b , S 13b may be configured to be closed.

[0091] Meanwhile, the circuit structure illustrated in Fig. 6 corresponds to a partial circuit design provided within the neuromorphic device 100. Therefore, the neuromorphic device 100 includes several circuit structures described in Fig. 6, and each circuit structure may be implemented in the neuromorphic device 100 so as to be connected and combined with each other.

[0092] FIG. 7 is a diagram illustrating the flow of current when an input and a current are applied to the neuromorphic device of FIG. 3A.

[0093] 6 and 7, the inputs x1, x2, x3 and the weight w 11 , w 21 , w 31 We will now explain the process of calculating the sum of products.

[0094] First, the weight to be applied to each resistor is set. Referring to the example in Table 4, the first resistor R 11 Weight w applied to 11 is 1, the second resistor R 12 Weight w applied to 21 is -1, the third resistor R 13 Weight w applied to 31 is -1.

[0095] 1st resistor R 11 Weight w applied to 11 is 1, so as mentioned above, the first resistor R11 The first variable resistor R 11a is set to 20 Ω, and the second variable resistor R 11b must be set to 5 Ω. If the first variable resistor R 11a is 5Ω, and the second variable resistor R 11b If the variable resistor R is set to 20 Ω, the resistance value needs to be changed. 11a , R 11b To set and check the resistance value of the resistor, a first wait line WL1 and a second wait line WL2 are provided on the side of the resistor line. 11a , S R1 , S R12 is closed, and a potential 100 V higher than that of the second wait line WL2 is applied to the first wait line WL1, the first variable resistor R 11a A voltage V1+100V is applied across the first variable resistor R 11a is set to 20 Ω. The switches for setting the weight and the voltage / current are driven by a separate weight controller. Similarly, the switch S 11b , S R1 , S R12 is closed, and a potential 100 V lower than that of the second wait line WL2 is applied to the first wait line WL1, the second variable resistor R 11b A voltage V1-100V is applied across the second variable resistor R 11b is set to 5 Ω.

[0096] A further step can then be taken to check whether the variable resistance setting of the resistor is correct. For example, switch S 11a , S R1 , S R12 is closed, and the second wait line WL2 is grounded. A specific current (test current) is passed through the first wait line WL1, and the voltage generated in the first wait line WL1 is measured. 11a Similarly, the resistance value set in the switch S 11b , S R1 , S R12is closed, and the second wait line WL2 is grounded, a test current is passed through the first wait line WL1, and the voltage generated in the first wait line WL1 is measured. 11b The resistance value can be confirmed.

[0097] 1st resistor R 11 Weight w 11 Once the setting is complete, the second resistor R 12 Weight w 21 is set. The second resistor R 12 Weight w applied to 21 is -1, so the second resistor R 12 The first variable resistor R 12a is set to 5 Ω, and the second variable resistor R 12b must be set to 20 Ω. If the first variable resistor R 12a is 20Ω, and the second variable resistor R 12b If the resistor is set to 5 Ω, the setting of the variable resistor needs to be changed. The way to change the resistance of the variable resistor is to change the first resistor R 11 Since it is similar to the second resistor R, detailed description will be omitted. 12 When testing the weight setting, the first weight line WL1 is grounded, a test current is passed through the second weight line WL2, and the voltage of the second resistor line WL2 is measured. 12 Weight w 21 Once the setting is complete, the third resistor R 13 Weight w 31 Set the third resistor R 13 Weight w applied to 31 is -1, so the third resistor R 13 The first variable resistor R 13a is set to 5 Ω, and the second variable resistor R 13b The resistance of the resistors mentioned above should be 20Ω. The setting method is similar to that of the first resistor, so a detailed explanation will be omitted. The resistance values ​​of the resistors mentioned above are summarized in Table 6.

[0098] [Table 6] Each resistor R 11 , R 12 , R 13 Weight w 11 , w 21 , w 31 Once the settings are complete, apply inputs x1, x2, and x3. Referring to FIG. 6, the first resistor R 11 Since the input x1 to 11a is closed and the second switch S 11b Similarly, the second resistor R 12 Since the input x2 to the first switch S 12a is closed and the second switch S 12b is open. Also, the third resistor R 13 Since the input x3 to 13a is opened and the second switch S 13b is closed.

[0099] Each resistor R 11 , R 12 , R 13 Weight w 11 , w 21 , w 31 After the inputs x1, x2, and x3 are applied, a constant current, for example, 1 A, is applied to the resistor line through the current source 130. As shown in FIG. 7, the applied current flows through the first resistor R 11 The first variable resistor R 11a , second resistor R 12 The first variable resistor R 12a , third resistor R 13 The second variable resistor R 13b Then, the total voltage generated in the resistor line by the current is measured. According to Ohm's law, the total voltage can be calculated using Equation 3. Here, the resistance and voltage drop due to the switch and conductors are very small and can be ignored.

[0100] Equation 3 V T1 = I1*R 11a + I1*R 12a+ I1*R 13b In Equation 3, I1 is 1A and R 11a , R 12a , and R 13b are 20Ω, 5Ω, and 20Ω, respectively, so V T1 The total voltage V is calculated as 45V. T1 Measure the resistance and refer to Table 5. It is found that the resistance falls into the second section, and the sum of the products of the input and the weight applied to the resistor line is 1.

[0101] 8A and 8B are diagrams for explaining an example of the structure and operation of a neuromorphic device in which the same input is applied to two rows of resistor lines.

[0102] Hereinafter, with reference to FIGS. 8A and 8B, the structure and operation method of a neuromorphic device that performs an operation on inputs and weights applied to two nodes will be described as an example.

[0103] 8A exemplarily illustrates a neural network having three nodes in the first layer 170 and two nodes in the second layer 190. The first node a1 in the second layer 190 receives inputs x1, x2, and x3 from the first layer 170 and their respective weights w as shown in Equation 2. 11 , w 21 , w 31 Similarly, at the second node a2 of the second layer 190, as shown in Equation 4, the inputs x1, x2, and x3 from the first layer 170 and their respective weights w 12 , w 22 , w 32 Three multiplication operations may be performed to multiply the values ​​by 1 and 2, and an addition operation may be performed to add up the results of the multiplication operations.

[0104] Equation 4 a2= x1·w 12 + x2·w 22 + x3·w 32 The method of operating the neuromorphic device used for the calculations performed in the first node a1 has been described in detail above, so a repeated description will be omitted here.

[0105] Referring to FIG. 8B, two rows of resistor lines RL1 and RL2 are disclosed. The first resistor line RL1 performs the required operation at the first node a1, and the second resistor line RL2 performs the required operation at the second node a2. As shown, resistors arranged in the same row are configured to receive the same input. For example, the first resistor R 11 and the first resistor R of the second resistor line RL2. 21 Although the weights applied to the first and second resistor lines RL1 and RL2 may be different, the same input may be applied to the second and first resistor lines RL1 and RL2. The voltage meter 150 may be disposed separately for each resistor line, or a single voltage meter may be disposed to measure the voltages of the first and second resistor lines RL1 and RL2 with a time lag. FIG. 8B shows an example in which a single voltage meter 150 is used. Although FIG. 8B shows an example in which separate current sources 131 and 133 are disposed for the first and second resistor lines RL1 and RL2, the present invention is not limited thereto, and a structure in which a single current source sequentially applies current to the first and second resistor lines RL1 and RL2 may also be used.

[0106] FIG. 9 is a diagram for explaining the operation of the neuromorphic device of FIG. 8B when a current is applied to it.

[0107] The operation of the neuromorphic device shown in FIG. 8B will now be described with reference to FIG. 9. For convenience of explanation, the inputs x1, x2, x3 and weight w associated with the first resistor line RL1 will be described. 11 , w 21 , w 31 are the same as Table 2. The inputs x1, x2, and x3 associated with the second resistor line RL2 are common to the inputs of the first resistor line RL1, and the weight w 12 , w 22 , w 32 Ha, w 12 = -1, w 22 = -1, w32 = 1.

[0108] First, weights are set for the first resistor line RL1 and the second resistor line RL2. The setting of the variable resistor included in the first resistor line RL1 has already been described and is shown in Table 6. The setting method of the variable resistor included in the second resistor line RL2 is the same as described above and is summarized in Table 7. [Table 7]

[0109] When the weight setting is completed for the first resistor line RL1 and the second resistor line RL2, the inputs x1, x2, and x3 are applied to the first resistor line RL1 and the second resistor line RL2 simultaneously or sequentially. The inputs x1, x2, and x3 are applied by driving the switches included in the first resistor line RL1 and the second resistor line RL2, and the switches S 21a , S 21b , S 22a , S 22b , S 23a , S 23b The driving method of the second resistor line RL2 is the same as that described above. 21a , S 22a , S 23b When the three switches are closed, 21b , S 22b , S 23a 9, since the inputs x1, x2, and x3 applied to the first resistor line RL1 and the second resistor line RL2 are the same, it can be seen that the current paths of the first resistor line RL1 and the second resistor line RL2 are the same.

[0110] When inputs x1, x2, and x3 are applied, currents are applied to the first and second resistor lines RL1 and RL2, and the overall voltage is measured at the top ends of the resistor lines RL1 and RL2. The currents I1 and I2 applied to the first and second resistor lines RL1 and RL2 may be the same or different, but in the example described below, the same current, 1 A, is applied.

[0111] As described above, the total voltage generated in the first resistor line RL1 by a 1A current is 45V, and the total voltage in the second resistor line RL2 is 15V. Referring to Table 3, the voltage measuring device 150 measures the inputs x1, x2, x3 and weight w applied to the second resistor line RL2. 12 , w 22 , w 32 The output is -3, which is the sum of the products of the two. The voltages for each resistor due to the input, weight, and current source for the second resistor line RL2 are summarized in Table 8.

[0112] [Table 8] 10A and 10B are diagrams for explaining an example of the structure and operation of a neuromorphic device that calculates the sum of products of weights and inputs applied to two rows of resistor lines.

[0113] Hereinafter, with reference to Figures 10A and 10B, a neuromorphic device and a driving method that can be used even when the number of applied inputs exceeds the number of resistors included in one resistor line will be described.

[0114] 10A, a neural network having six nodes in the first layer 270 and two nodes in the second layer 290 is illustrated. The first node a1 in the second layer 290 receives inputs x1, x2, x3, x4, x5, and x6 from the first layer 270 and their respective weights w as shown in Equation 5. 11 ,w 21 ,w31 ,w 41 ,w 51 ,w 61 Six multiplication operations for multiplying the values ​​and an addition operation for adding up the multiplication results can be performed.

[0115] Equation 5 a1 = x1·w11 + x2·w21 + x3·w31 + x4·w41 + x5·w51 + x6·w61 10B exemplarily illustrates the structure of a neuromorphic device utilized for the computation performed at the first node a1. Referring to FIG. 10B, the neuromorphic device includes two series-connected resistor lines RL1 and RL2, current sources 231 and 233 that provide currents applied to the resistor lines RL1 and RL2, and a voltage meter 250 that measures the voltage applied across the series-connected resistor lines RL1 and RL2. The difference between FIG. 10B and the embodiment illustrated in FIG. 8B is that the inputs applied to the resistors arranged in the same row are independent of each other. For example, the first resistor R of the first resistor line RL1 is 11 The input x1 and the first resistor R of the second resistor line RL2 are applied to 14 Since the inputs x1 and x4 are independent of each other, different values ​​are applied to each resistor R. That is, when the first input x1 is 1, the fourth input x4 is -1. 11 , R 14 To apply such independent inputs, the resistor R included in the first resistor line RL1 11 , R 12 , R 13 an input line (not shown; for example, a gate line of a switch connected in series with a variable resistor) for applying an input to the second resistor line RL2; 14 , R 15 , R 16 The input lines for applying the inputs to the weights are configured to be independently controlled. The application of the inputs is also controlled by a separate controller (not shown). Here, the controller for controlling the inputs and the controller for controlling the application of the weights may be embodied as separate devices or as a single device.

[0116] The number of multiplication operations required at the first node a1 of the second layer 290 shown in Figure 10A is six, but the number of resistors included in one resistor line is three. Therefore, if multiple multiplication operations cannot be processed with one resistor line, a structure such as that shown in Figure 10B can be used.

[0117] In describing the embodiments of Figures 10A and 10B, we will exemplarily describe a case where the number of required multiplication operations is the same as the number of resistors included in the two resistor lines, and for the sake of explanation, we will assume that the values ​​required for the operations performed at the first node a1 are as shown in Table 9 below.

[0118] [Table 9] The calculation of Equation 5 performed at the first node a1 can be separated into an operation performed on the first resistor line RL1 as shown in Equation 6 and an operation performed on the second resistor line RL2 as shown in Equation 7. The final result value can be obtained by adding up the results of each calculation.

[0119] Equation 6 First resistor line RL1:x1·w 11 + x2·w 21 + x3·w 31 Formula 7 Second resistor line RL2: x4·w 41 + x5·w 51 + x6·w 61 To perform the calculation, a weight for each resistor is set, an input is applied, and then a current is applied to each resistor line. The current I1 supplied to the first resistor line RL1 and the current I2 supplied to the second resistor line RL2 may be the same or different. For example, the first current I1 of the first resistor line RL1 is 1 A, and the second current I2 of the second resistor line RL2 is 2 A. While FIG. 10B illustrates an example in which separate current sources 231 and 233 apply current to the first resistor line RL1 and the second resistor line RL2, respectively, the present invention is not limited thereto, and a single current source may apply current to each resistor line with a time delay.

[0120] FIG. 11 is a diagram for explaining the operation of the neuromorphic device of FIG. 8B when a current is applied to it.

[0121] Referring to FIG. 11, since the input values ​​applied to the resistors included in the first resistor line RL1 and the second resistor line RL2 are different, the paths of the currents flowing through the resistor lines are also different.

[0122] When the values ​​calculated through the first resistor line RL1 and the second resistor line RL2 are summarized, Equation 6 is set to be the same as Equation 2, so the results shown for the first resistor line RL1 are as shown in Table 4. When the results for the second resistor line RL2 are summarized in the same manner, they are as shown in Table 10.

[0123] [Table 10] As such, the total voltage measured at the upper terminal of the second resistor line RL2 corresponds to 30 V, which corresponds to Section 4 in Table 11 showing the results by section for a current of 2 A. Therefore, the result of Equation 7 is −3.

[0124] [Table 11] As a result, the values ​​corresponding to the calculation results of Equation 6 and Equation 7 are found, and it is found that the result value of Equation 5, which is the result of the operation performed at the first node a1 of the second layer 290, is −2, which is the sum of the result value of Equation 6 and the result value of Equation 7. The calculation of adding up the result values ​​of Equation 6 and Equation 7 is performed in the digital circuit domain, but is not limited to this.

[0125] 8A to 11, for the sake of convenience, three resistors are included in one resistor line and two resistor lines are included. However, the number of resistors included in one line and the number of resistor lines used for the operation may be changed. For example, if the number of multiplication operations required at a certain node is greater than the number of resistors included in one resistor line, the multiplication operations are performed using two or more resistor lines, as in the embodiment described in FIGS. 10A to 11.

[0126] As the number of inputs processed by a neuromorphic device increases while the number of resistors included in the neuromorphic device is limited, situations often arise where a structure such as that described in FIGS. 10A through 11 must be utilized. In particular, when measuring the overall voltage after applying current to a resistor line in which resistors are connected in series, the maximum voltage applied to the resistor line increases as the number of rows receiving inputs increases, i.e., the number of resistors connected in series increases. However, since the maximum voltage applied to the resistor line cannot exceed the power supply voltage of the current source, the number of resistors that can be connected in series is limited. Furthermore, as the number of resistors connected in series increases, noise also increases, resulting in reliability issues. Therefore, when more inputs than the number of resistors connected in series are applied, simultaneous calculations cannot be performed using a single resistor line. Therefore, it is preferable to adopt a method in which the input is distributed and applied to multiple resistor lines, or the input is distributed and applied to a single resistor line with a time lag, and then partial calculations are performed, and the calculation results are then summed.

[0127] 12A and 12B are diagrams for explaining an example of the structure and operation of a neuromorphic device that calculates, in the analog domain, the sum of products of inputs applied to two rows of resistor lines and weights.

[0128] Hereinafter, with reference to FIGS. 12A and 12B, it will be described how the summation of the results of Equation 6 and Equation 7 in the above embodiment is performed in the analog circuit domain.

[0129] 10B, the device illustrated in FIG. 12A further includes a first capacitor C1 electrically connected to the first resistor line RL1 and a second capacitor C2 electrically connected to the second resistor line RL2, and includes a voltage measuring device 350 configured to measure the voltage across the first and second capacitors C1 and C2. The first capacitor C1 and the second capacitor C2 may have the same capacitance. The capacitance may have a value of, for example, 0.1 fF to 100 fF.

[0130] 12A and 12B, the inputs and weights are as shown in Table 9. It is assumed that the first current I1 and the second current I2 are equal to 1 A. As described above, separate current sources are provided to supply current to each resistor line, but this is not limiting, and one current source may supply current to each resistor line sequentially. The inputs, weights, and voltages for the first resistor line RL1 are as shown in Table 4, and the inputs, weights, and voltages for the second resistor line RL2 are as shown in Table 12.

[0131] [Table 12] Hereinafter, a method for performing the sum of products of inputs and weights applied to resistors included in different resistor lines in an analog circuit domain will be described through the embodiments of FIGS. 12A and 12B.

[0132] First, a weight and an input are applied to each resistor, and a current of the same magnitude is applied to each resistor line, and the voltages generated at the upper ends of each resistor line are sampled by different capacitors.

[0133] Specifically, the total voltage V of the first resistor line RL1 T1 is sampled by the first capacitor C1 and the total voltage V of the second resistor line RL2 T2 is sampled by the second capacitor C2. One end of the first capacitor C1 is electrically connected to the upper terminal of the first resistor line RL1, and the total voltage V T1 Similarly, one end of the second capacitor C2 is electrically connected to the upper terminal of the second resistor line RL2, and the overall voltage V T2 The voltage at one end of the second capacitor C2, which is equal to the voltage at one end of the second capacitor C2, can be sampled.

[0134] As shown in FIG. 12A, during sampling, the first capacitor C1 must be electrically connected to the upper terminal of the first resistor line RL1. Therefore, a first capacitor switch S is disposed between the first capacitor C1 and the first resistor line RL1. c1 is in a closed state, and the second capacitor C2 must be electrically connected to the upper end of the second resistor line RL2. Therefore, the second capacitor switch S disposed between the second capacitor C2 and the second resistor line RL2 is C2 The inter-capacitor switch S C12 is in an open state. This state in which the first capacitor C1 and the second capacitor C2 are electrically connected to the first resistor line RL1 and the second resistor line RL2, respectively, to sample the voltage is referred to as the "first state." The upper terminals of the first capacitor C1 and the second capacitor C2 are grounded. Therefore, in the first state, the total voltage V of the first resistor line RL1 is T1The voltage across the first capacitor C1 is equal to the total voltage V of the first resistor line RL1. T1 and the total voltage V of the second resistor line RL2 T2 The voltage across the second capacitor C2 is equal to the total voltage V across the second resistor line RL2. T2 This is the same as Q = CV, so the charge Q stored in the first capacitor C1 is 11 is C*V T1 Similarly, the charge amount Q 12 is C*V T2 This becomes:

[0135] After sampling, as shown in FIG. 12B, the first capacitor switch S c1 and the second capacitor switch S C2 is opened and switch S C12 is closed. This state in which the capacitors C1 and C2 are connected in parallel, i.e., the voltages at one end of the capacitors C1 and C2 are kept the same (grounded) and the other end of the capacitors C1 and C2 are electrically connected and floating, is called the "second state." In the second state, the charge stored in the capacitors C1 and C2 does not move to the outside, so the charge amount is conserved, and as the charge moves between the capacitors C1 and C2, a specific voltage is formed at the floating terminal. This voltage is called the sum voltage Vx. In the second state, the charge amount Q stored in the first capacitor C1 is 21 is C*Vx, the charge Q stored in the second capacitor C2 22 will be C*Vx.

[0136] Thereafter, the voltage measuring device 350 measures the voltage across the first capacitor C1 and the second capacitor C2.

[0137] Using the law of conservation of charge, the total voltage V of the first resistor line RL1 can be calculated from the measured voltages across the first capacitor C1 and the second capacitor C2 as shown in Equation 8. T1 and the total voltage V of the second resistor line RL2 T2The current is 1 A, and the calculation result of Equation 5 can be obtained from this value.

[0138] Formula 8 1st state: Q 11 =C*V T1 , Q 12 =C*V T2 Second state: Q 21 =C*Vx, Q 22 =C*Vx Charge conservation:Q 11 +Q 12 = Q 21 +Q 22 V T1 +V T2 = 2*Vx Combined voltage V x The relationship between the output value of the calculation result of Equation 5 and the output value is summarized in Table 13.

[0139] [Table 13] Combined voltage V x is 30V, the voltage measuring device 350 can output −2, which is the sum of the products of the inputs and weights applied to the resistors included in the first resistor line RL1 and the second resistor line RL2, respectively.

[0140] 12A and 12B illustrate that even when multiple resistor lines are used because the number of inputs exceeds the number of resistors included in the resistor lines, the calculation is performed in the analog domain using capacitors. For convenience of explanation, FIG. 12A exemplarily illustrates a structure in which the sum of products of inputs applied to two rows of resistor lines and weights is calculated in the analog domain. However, this embodiment is not limited thereto and is equally applicable to neuromorphic devices having three or more rows of resistor lines, e.g., five rows, ten rows, etc. Capacitors electrically connected to each resistor line sample the voltage of each resistor line, and the sampled voltages can be measured in a summed form after the capacitors are connected in parallel.

[0141] 12A has been described as a structure for calculating the sum of products of inputs and weights applied to all resistor lines, but the present invention is not limited thereto and may be implemented such that only some resistor lines that require summation are connected to capacitors to selectively perform the calculation. Also, while FIG. 12A has been described as a structure in which only one capacitor is connected to a resistor line, multiple capacitors (e.g., four) may be connected to one resistor line in consideration of various factors such as capacitance and element placement.

[0142] 12A and 12B illustrate an example in which the upper terminals of capacitors C1 and C2 are grounded and the lower terminals of capacitors C1 and C2 are floating in the second state. However, the voltage in the second state can be measured by connecting capacitors in parallel in various ways, as will be described with reference to FIGS. 13A and 13B.

[0143] 13A and 13B are diagrams for explaining an example of the structure and operation of a neuromorphic device that calculates, in the analog domain, the sum of products of inputs applied to two rows of resistor lines and weights.

[0144] Referring to FIG. 13A, in the first state, the common voltage switch S CM and the first and second capacitor switches S C1 , S C2 By closing the resistor, the upper terminals of the first and second capacitors C1 and C2 are connected to a common voltage V CM , whereby the first and second capacitors C1 and C2 are supplied with the first and second voltages V T1 , V T2 is sampled.

[0145] Referring to FIG. 13B, in the second state, the common voltage switch S CM By opening the first and second capacitors C1 and C2, the upper terminals of the first and second capacitor switches S C1 , S C2 Open the switch S C1V , S C2V By closing the resistor, the lower terminals of the first and second capacitors C1 and C2 are connected to the second voltage V Y In the second state, by measuring the potential difference between the upper and lower terminals of the first and second capacitors C1 and C2, the sum of the products of the inputs applied to the two resistor lines RL1 and RL2 and the weights can be obtained in the analog circuit domain.

[0146] The intervention of digital calculations increases the frequency of ADC (Analog to Digital Converter) use, which increases the quantization error generated by the ADC and reduces power efficiency. Therefore, as mentioned above, more efficient calculations can be achieved by using a neuromorphic device that can calculate the sum of products of inputs applied to multiple resistor lines and weights in the analog circuit domain.

[0147] FIG. 14 is a chip block diagram of a neuromorphic device according to one embodiment.

[0148] 14, a hardware configuration of a neuromorphic device according to an exemplary embodiment is illustrated. The neuromorphic device 500 includes a resistor array 510, a controller 520, a row decoder 530, a column decoder 540, a wait driver 550, a current source controller 560, a voltage measurement unit 580, and a data buffer 570. The neuromorphic device 500 illustrated in FIG. 14 illustrates components related to this embodiment. However, the neuromorphic device 500 is not limited thereto, and may further include other general-purpose components in addition to the components illustrated in FIG. 14.

[0149] The controller 520 can decode commands necessary to drive and operate the neuromorphic device 500. For example, the controller 520 decodes commands such as setting weights, checking weight settings, applying inputs, measuring voltages, etc., and transmits signals to components necessary to carry out these commands.

[0150] The resistor array 510 may be, for example, an array of resistors configured with the variable resistors and switches described above, where the variable resistors may be magnetic tunnel junction (MTJ) elements having magnetic materials.

[0151] The row decoder 530 may receive a row address and an input signal and apply an input value to the resistor array 510. The row decoder 530 may include a digital-to-analog converter (DAC) and may apply a driving voltage to a switch connected in series with a variable resistor based on the input value. The row decoder 530 may also change the resistance value of a variable resistor included in a resistor in the resistor array 510, and may apply a driving voltage to an associated switch to select a target variable resistor during wait setting.

[0152] The column decoder 540 receives a column address and a wait setting signal and applies a voltage / current to a variable resistor. The column decoder 540 can select a resistor line for which voltage measurement is required and a wait line connected to a resistor for which wait setting is required.

[0153] When setting a wait, the wait driver 550 can transmit wait data to a resistor selected by the row decoder 530 and the column decoder 540. The wait driver 550 can set a wait and check the set wait by driving a wait line connected to the column decoder 540 based on data received from the data buffer 570. The wait driver 550 may include a current source that applies a check current to the wait line to check whether a desired resistance value is set in the variable resistor.

[0154] The current source controller 560 receives signals from the controller 520 to drive the current source to apply current to the resistor line.

[0155] The voltage measuring device 580 may measure the voltage of the resistor line or a capacitor connected to one end of the resistor line and store the measured value in an external memory (not shown). The voltage measuring device 580 may include an ADC that outputs the measured value as a digital value.

[0156] FIG. 15 is a block diagram illustrating an electronic system according to an example.

[0157] 15, electronic system 800 may analyze input data and extract useful information using a neural network device 830 including a neuromorphic device, and may make a situational decision based on the extracted information or control the configuration of an electronic device in which electronic system 800 is installed. For example, electronic system 800 may be applied to a drone, a robotic device such as an Advanced Driver Assistance System (ADAS), a smart TV, a smartphone, a medical device, a mobile device, a video display device, a measuring device, an IoT device, and the like, and may also be installed in various other types of electronic devices.

[0158] The electronic system 800 may include a CPU 810, a RAM 820, a memory 840, a sensor module 850, and a communication module (Tx / Rx module) 860 in addition to the neural network device 830. The electronic system 800 may further include an input / output module, a security module, a power control device, etc. Some of the hardware components of the electronic system 800 are mounted on a semiconductor chip. The neural network device 830 may be an on-chip implementation of the neuromorphic device described above with reference to the drawings, or may be a device that includes the neuromorphic device described above with reference to the drawings as a part thereof.

[0159] The CPU 810 controls the overall operation of the electronic system 800. The CPU 810 may include one processor core (single core) or multiple processor cores (multi-core). The CPU 810 processes or executes programs and / or data stored in the memory 840. The CPU 810 controls the functions of the neural network device 830 by executing programs stored in the memory 840. The functions of the CPU 810 may be implemented by a graphic processing unit (GPU), an application processor (AP), etc.

[0160] The RAM 820 can temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 840 are temporarily stored in the RAM 820 under the control of the CPU 810 or boot code. The RAM 820 may also be implemented by a memory device such as a dynamic RAM (DRAM) or a static RAM (SRAM).

[0161] The neural network device 830 may perform neural network operations based on received input data and generate an information signal based on the results of the operations. The neural network device 830 may include the neuromorphic device described above with reference to the drawings. The neural network may include, but is not limited to, a convolution neural network (CNN), a recurrent neural network (RNN), a deep belief network, a restricted Boltzmann machine, etc. The neural network device 830 may correspond to a hardware accelerator dedicated to the neural network.

[0162] The information signal may include various types of recognition signals such as a voice recognition signal, an object recognition signal, a video recognition signal, and a biometric information recognition signal. For example, the neural network device 830 may receive frame data included in a video stream as input data and generate a recognition signal for an object included in an image represented by the frame data. Depending on the type or function of the electronic device in which the electronic system 800 is installed, the neural network device 830 may receive various types of input data and generate a recognition signal based on the input data.

[0163] The memory 840 serves as a storage location for data and can store an operating system (OS), various programs, and various data. The memory 840 may include volatile memory or nonvolatile memory. Nonvolatile memory includes read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable and programmable read-only memory (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Volatile memory includes dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FeRAM). Memory 840 may include, for example, a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), an extreme digital (xD), or a Memory Stick.

[0164] The sensor module 850 may collect information about the surroundings of an electronic device in which the electronic system 800 is installed. The sensor module 850 may sense or receive signals (e.g., video signals, audio signals, magnetic signals, biosignals, touch signals, etc.) from outside the electronic device and convert the sensed or received signals into data. To this end, the sensor module 850 may be any of various types of sensing devices, such as a microphone, an imaging device, an image sensor, a LIDAR (light detection and ranging) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, or a touch sensor.

[0165] The sensor module 850 may provide the converted data as input data to the neural network device 830. For example, the sensor module 850 may include an image sensor, capture an external environment of the electronic device to generate a video stream, and sequentially provide successive data frames of the video stream as input data to the neural network device 830. However, the sensor module 850 is not limited thereto, and may provide various types of data to the neural network device 830.

[0166] The communication module 860 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 860 may include a communication interface connectable to a wired local area network (LAN), a wireless local area network (WLAN) such as Wi-Fi (Wireless Fidelity), a wireless personal area network (WPAN) such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio-frequency identification (RFID), power line communication (PLC), or a mobile cellular network such as 3rd generation (3G), 4th generation (4G), long term evolution (LTE), or 5th generation (5G).

[0167] The electronic system 800 may further include a processor, a memory device for storing and executing program data, permanent storage such as a disk drive, a communication port for communicating with external devices, and user interface devices such as a touch panel, keys, buttons, etc. A method embodied by a software module or an algorithm may be stored on a computer-readable recording medium as computer-readable code or program instructions executable on a processor.

[0168] The above-described embodiments are merely illustrative and are not intended to limit the scope of the present invention in any way. For the sake of brevity, descriptions of well-known electronic configurations, control systems, software, and other functional aspects have been omitted. Furthermore, wire connections or connecting members between components shown in the drawings are illustrative of functional connections and / or physical or circuit connections, and may be embodied in an actual device by alternative or additional functional, physical, or circuit connections.

[0169] Those skilled in the art will understand that the embodiments can be embodied in various modified forms without departing from the essential characteristics described above. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not the above description, and all variations within the scope of the claims should be construed as being included in the embodiments.

Claims

1. a first resistor line including a plurality of resistors connected in series; a second resistor line including a plurality of resistors connected in series; one or more current sources capable of controlling currents flowing through the first resistor line and the second resistor line at predetermined current values; a first capacitor electrically connected to the first resistor line; a second capacitor electrically connected to the second resistor line; each of the plurality of resistors in the first resistor line and the second resistor line has a resistance value that is variably set according to an applied input and a weight; the first capacitor and the second capacitor have the same capacitance; A neuromorphic device that obtains the sum of products of inputs and weights applied to multiple resistors in the first resistor line and the second resistor line by sampling a first voltage generated in the first resistor line using the first capacitor and sampling a second voltage generated in the second resistor line using the second capacitor, then switching the first capacitor and the second capacitor to a state where they are connected in parallel, and measuring the combined voltage generated across the first capacitor and the second capacitor connected in parallel.

2. The neuromorphic device of claim 1 , further comprising a switch that can be switched so that the first capacitor and the second capacitor are connected in parallel.

3. The neuromorphic device of claim 2 , further comprising a voltage measuring device that measures a potential difference across the first and second capacitors when the first and second capacitors are connected in parallel.

4. The neuromorphic device comprises:

4. The neuromorphic device of claim 1, further comprising a plurality of current sources coupled to the first resistor line and the second resistor line, respectively.

5. The neuromorphic device comprises:

4. The neuromorphic device of claim 1, further comprising a current source commonly coupled to the first resistor line and the second resistor line.

6. The neuromorphic device of any one of claims 1 to 5, further comprising a controller that applies an input and a weight to the resistor.

7. A neuromorphic device according to any one of claims 1 to 6, wherein the one or more current sources control the current flowing through the first resistor line and the current flowing through the second resistor line to the same current value.

8. a controller that applies an input and a weight to the resistor; A neuromorphic device according to any one of claims 1 to 3, wherein the controller independently controls an input applied to the resistor included in the first resistor line and an input applied to the resistor included in the second resistor line.

9. a first switch disposed between the first capacitor and the first resistor line; The neuromorphic device of any one of claims 1 to 8, further comprising: a second switch disposed between the second capacitor and the second resistor line.

10. A neuromorphic device according to any one of claims 1 to 9, wherein each of the resistors comprises a magnetic memory element having a plurality of resistance values.

11. The neuromorphic device of any one of claims 1 to 10, wherein one end of the first capacitor and one end of the second capacitor are electrically connected.

12. A method for driving a neuromorphic device, comprising: applying a current having a predetermined current value to a first resistor line including a plurality of resistors connected in series and a second resistor line including a plurality of resistors connected in series, each of the plurality of resistors in the first resistor line and the second resistor line having a resistance value that is variably set according to an applied input and a weight; sampling a first voltage of the first resistor line using a first capacitor coupled to the first resistor line and a second voltage of the second resistor line using a second capacitor coupled to the second resistor line, the first capacitor and the second capacitor having the same capacitance; measuring a sum voltage generated across both ends of the parallel-connected first and second capacitors by switching one end of the first capacitor and one end of the second capacitor to be connected in parallel; determining a sum of products of weights and inputs applied to the plurality of resistors in the first resistor line and the second resistor line based on the summed voltage; A method for driving a neuromorphic device, comprising:

13. A method for driving a neuromorphic device as described in claim 12, further comprising a step of calculating the sum of products of the inputs and weights applied to the multiple resistors of the first and second resistor lines using a predetermined correspondence between the measured combined voltage and the sum of products in the step of calculating the sum of products.

14. The method of claim 12 , further comprising applying a resistance value to a variable resistor included in each of the resistors.

15. The sampling step includes: The method for driving a neuromorphic device according to claim 12 , further comprising sampling the first voltage and then sampling the second voltage.

16. a neural network device including a neuromorphic device; a central processing unit having a processor core and controlling the function of the neural network device; The neuromorphic device comprises: a first resistor line including a plurality of resistors connected in series; a second resistor line including a plurality of resistors connected in series; one or more current sources capable of controlling currents flowing through the first resistor line and the second resistor line at predetermined current values; a first capacitor electrically connected to the first resistor line; a second capacitor electrically connected to the second resistor line; each of the plurality of resistors in the first resistor line and the second resistor line has a resistance value that is variably set according to an applied input and a weight; the first capacitor and the second capacitor have the same capacitance; an electronic system that samples a first voltage generated in the first resistor line using the first capacitor, samples a second voltage generated in the second resistor line using the second capacitor, switches the first capacitor and the second capacitor to a state where they are connected in parallel, and measures a sum of products of inputs and weights applied to multiple resistors in the first resistor line and the second resistor line.

17. The neuromorphic device comprises: The electronic system of claim 16 , further comprising a switch that can be switched to connect the first capacitor and the second capacitor in parallel.

18. The neuromorphic device comprises: The electronic system of claim 16 , further comprising a voltage measuring device that measures a potential difference across the first and second capacitors when the first and second capacitors are connected in parallel.

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