Data communication circuit

Abstract

A data communication circuit according to one embodiment of the present disclosure is a data communication circuit that performs data communication between a first data processing unit and a second data processing unit, and includes a transmission path that transmits data from the first data processing unit to the second data processing unit using a CDR method, and a control unit that controls data communication, wherein the control unit controls the circuit to transition to an operating state that causes a signal transition on the transmission path when there is data to be transmitted from the first data processing unit to the second data processing unit, based on a resting state in which no signal transition occurs on the transmission path.

Description

[Technical Field]

[0001] The present disclosure relates to data communication circuits. [Background technology]

[0002] For example, the Clock and Data Recovery (CDR) method is used as a method for high-speed data communication between LSIs, etc. The CDR method receives a signal on a transmission line where the clock is superimposed on the data, and separates the clock from the data, and is used in USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface), etc.

[0003] In the CDR method, during initial operation (training operation), the transmitter sends a training pattern, and the receiver receives the training pattern and adjusts the timing for receiving data. After that, the transmitter transmits data at the same timing as the training operation, and the receiver receives data based on the adjusted timing. As long as the transmitter continues to send data at the same timing as the training operation, the receiver can correctly receive the data from the transmitter. This is called the locked state.

[0004] For some reason, such as noise, the timing of transmission from the transmitter may deviate from the training operation. When data is being communicated at high speed, this timing deviation means that the receiver cannot receive the data immediately. In other words, the lock is lost. When the lock is lost, some kind of recovery process, such as restarting the training, is required.

[0005] In the CDR system, to prevent timing deviations, the data to be transmitted is coded so that it does not take on the same value continuously for a predetermined period of time or more, and a clock signal for synchronization is embedded in this data (see, for example, Patent Document 1). In other words, in the CDR system, a signal with a certain degree of variation is always transmitted even during periods when no data is being transmitted. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 5235190 Summary of the Invention [Problem to be solved by the invention]

[0007] By constantly generating signal changes in the transmission path, the timing during training can be easily maintained, and training can be avoided for a relatively long period of time. However, signal changes consume power, and this power consumption cannot be ignored, especially since the CDR method is generally used at high speeds.

[0008] The present disclosure has been made in light of the above-mentioned circumstances, and aims to provide a data communication circuit that can reduce power consumption in CDR-based data communication. [Means for solving the problem]

[0009] A data communication circuit according to one embodiment of the present disclosure is a data communication circuit that performs data communication between a first data processing unit and a second data processing unit, and includes a transmission path that transmits data from the first data processing unit to the second data processing unit using a CDR method, and a control unit that controls data communication, wherein the control unit controls the circuit to transition to an operating state that causes a signal transition on the transmission path when there is data to be transmitted from the first data processing unit to the second data processing unit, based on a resting state in which no signal transition occurs on the transmission path. [Effects of the Invention]

[0010] The data communication circuit of the present disclosure can reduce power consumption in data communication using the CDR method. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a circuit configuration diagram of a data communication circuit according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram showing how data communication is performed in the data communication circuit of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] [Description of the embodiments of the present disclosure] (1) A data communication circuit according to one embodiment of the present disclosure is a data communication circuit that performs data communication between a first data processing unit and a second data processing unit, and includes a transmission path that transmits data from the first data processing unit to the second data processing unit using a CDR method, and a control unit that controls data communication, wherein the control unit controls the transmission path to transition to an operating state that causes a signal transition on the transmission path when there is data to be transmitted from the first data processing unit to the second data processing unit, based on a resting state in which no signal transition occurs on the transmission path.

[0013] In the data communication circuit, the control unit normally maintains a pause state in which no signal transition occurs on the transmission path, and performs control to cause a signal transition on the transmission path when there is data to be transmitted from the first data processing unit to the second data processing unit. Therefore, unnecessary signal transitions can be reduced, thereby reducing power consumption.

[0014] (2) In the data communication circuit of (1), the control unit may store parameters for reproducing clock timing information, and when transitioning from the sleep state to the operating state, reproduce the clock timing information based on the parameters. By reproducing the clock timing information based on the parameters when transitioning from the sleep state to the operating state in this way, timing is more easily maintained, and retraining can be avoided for a relatively long period of time.

[0015] (3) In the data communication circuit of (2), the parameters may include a transmission voltage level and a transmission emphasis level of the first data processing unit, and an equalization level and a sampling timing of the second data processing unit. By including these timing information in the parameters, the timing can be easily maintained.

[0016] (4) In the data communication circuit of any one of (1) to (3), the control unit may perform a refresh operation to forcibly and temporarily generate a signal transition on the transmission path when the pause state is maintained for a predetermined period of time. By performing the refresh operation in this manner, it is possible to more reliably prevent timing deviations from occurring.

[0017] [Details of the embodiments of the present disclosure] A data communication circuit according to an embodiment of the present disclosure will be described below.

[0018] The data communication circuit 1 shown in FIG. 1 is a data communication circuit that performs data communication between a first data processing unit 10 and a second data processing unit 20.

[0019] The first data processing unit 10 and the second data processing unit 20 are preferably mounted on separate semiconductor devices X1 and X2, respectively. Examples of the semiconductor devices X1 and X2 include large-scale integrated circuits (LSIs). The mounting location is not limited to semiconductor devices, as long as the components are capable of performing data communication between components. Furthermore, there is nothing preventing the use of the devices for data communication within a single component, for example, within a semiconductor integrated circuit.

[0020] The data communication circuit 1 is particularly suitable for use in high-speed data communication. The lower limit of the data rate of the data communication circuit 1 is preferably 1 Gbps, more preferably 5 Gbps, and even more preferably 50 Gbps. On the other hand, the upper limit of the data rate of the data communication circuit 1 is not particularly limited, but is practically 100 Gbps.

[0021] The data communication circuit 1 includes a transmission path 30 and a control unit 40.

[0022] <Transmission path> The transmission path 30 transmits data from the first data processing unit 10 to the second data processing unit 20 in the CDR format.

[0023] In the data communication circuit 1 shown in FIG. 1, the transmission path 30 is composed of two signal lines (a first signal line 31 and a second signal line 32), and data is transmitted via these two signal lines using differential signals. Specifically, currents of opposite phases flow through the first signal line 31 (positive side) and the second signal line 32 (negative side), and a signal is transmitted using the potential difference between the two. In this case, even if the same external noise is applied to the positive and negative first signal line 31 and second signal line 32, the noise is canceled out because the potential difference between the signal lines is detected, making it less likely to malfunction. In this way, using differential signals in the transmission path 30 can increase resistance to external noise.

[0024] <Data processing section> The first data processing unit 10 has an output buffer 11 that drives the transmission path 30 , and the second data processing unit 20 has an input buffer 21 that receives a signal from the transmission path 30 .

[0025] The output buffer 11 generates a signal of data to be transmitted from the first data processing unit 10 to the second data processing unit 20 and its inverted signal, and applies these signals as voltages to a first signal line 31 as the positive side and a second signal line 32 as the negative side, respectively. As a result, the signal is transmitted from the first data processing unit 10 to the second data processing unit 20 via the transmission path 30.

[0026] On the other hand, the input buffer 21 receives a signal transmitted from the first data processing unit 10. Since the signal is transmitted through two signal lines, a first signal line 31 on the positive side and a second signal line 32 on the negative side, the signal is reproduced by taking the potential difference between these signal lines.

[0027] <Control unit> The control unit 40 controls data communication. The control unit 40 is composed of a first control unit 41 arranged in the first data processing unit 10 and a second control unit 42 arranged in the second data processing unit 20. The first control unit 41 controls data to be output to the output buffer 11. The second control unit 42 controls data input by the input buffer 21.

[0028] The operation of the control unit 40 will be described below with reference to the timing chart of FIG.

[0029] (training) First, the control unit 40 performs a training operation T before performing data communication. In the training operation T, training data is sent from the output buffer 11 of the first data processing unit 10 to the second data processing unit 20, and the reception timing of the input buffer 21 of the second data processing unit 20 is determined for transmission at a high data rate. By determining the reception timing of the second data processing unit 20 in this manner, when the first control unit 41 transmits data from the output buffer 11 of the first data processing unit 10 at a high data rate, the second control unit 42 can receive the data at the input buffer 21 of the second data processing unit 20 without the need for a clock signal that synchronizes the output buffer 11 and input buffer 21.

[0030] At this time, the control unit 40 stores parameters 50 for reproducing the timing information of the clock. The parameters 50 preferably include the transmission voltage level and transmission emphasis level of the first data processing unit 10, as well as the equalization level and sampling timing of the second data processing unit 20. By including this timing information in the parameters 50, it is possible to easily maintain the timing in the operating state S2, which will be described later.

[0031] The transmission voltage level and transmission emphasis level of the first data processing unit 10 may be stored in the first data processing unit 10 as first parameters 51, and the equalization level and sampling timing of the second data processing unit 20 may be stored in the second data processing unit 20 as second parameters 52. Storing the parameters 50 in the processing unit to be used in this manner allows the parameters 50 to be used efficiently.

[0032] 1, it is preferable that the transmission voltage level and transmission emphasis level stored in the first data processing unit 10 have copies thereof stored in the second data processing unit 20, and that the equalization level and sampling timing stored in the second data processing unit 20 have copies thereof stored in the first data processing unit 10. By storing copies in this manner, all parameters can be referenced within each data processing unit. For example, by having the first data processing unit 10 reference the parameters of the second data processing unit 20, it becomes possible to complete the training operation T in a short time when training is required again, for example.

[0033] If clock timing generation is performed by a PLL (Phase-Locked Loop) or a DLL (Delay-Locked Loop), the timing parameters of the synchronized PLL or DLL may be stored and used in addition to or instead of the above parameters.

[0034] (Hibernate) When the training operation T is completed, the control unit 40 enters a sleep state S1 in which, in principle, no signal transition occurs on the transmission path 30. The data communication circuit 1 operates based on this sleep state S1. In other words, when other operations are completed, the control unit 40 basically enters the sleep state S1. However, this does not prevent the control unit 40 from, for example, transitioning from the training operation T to the operating state S2 without passing through the sleep state S1.

[0035] (Operating state) When there is data to be transmitted from the first data processing unit 10 to the second data processing unit 20, the control unit 40 performs control to transition to an operating state S2 in which a signal transition occurs on the transmission path 30.

[0036] When transitioning from the sleep state S1 to the operating state S2, the control unit 40 recreates the clock timing information based on the parameter 50. That is, the first control unit 41 reads the first parameter 51, and in the example shown in FIG. 2, sets the transmission voltage level and transmission emphasis level of the first data processing unit 10 to the read parameter values. Similarly, the second control unit 42 reads the second parameter 52, and in the example shown in FIG. 2, sets the equalization level and sampling timing of the second data processing unit 20 to the read parameter values. By recreating the clock timing information based on the parameter 50 in this way when transitioning from the sleep state S1 to the operating state S2, timing is more easily maintained, and retraining can be avoided for a relatively long period of time.

[0037] Thereafter, the control unit 40 transmits data from the first data processing unit 10 to the second data processing unit 20. When the data transmission is completed, the control unit 40 transitions to the sleep state S1.

[0038] (Refresh operation) When the pause state S1 is maintained for a predetermined period P, the control unit 40 performs control to perform a refresh operation S3 that forcibly and temporarily generates a signal transition on the transmission path 30. By performing the refresh operation S3 in this manner, it is possible to more reliably prevent timing deviations from occurring.

[0039] The lower limit of the predetermined period P is preferably 1 μs, and more preferably 5 μs. On the other hand, the upper limit of the predetermined period P is preferably 1000 μs, and more preferably 500 μs. If the predetermined period P is less than the lower limit, the power reduction effect of the data communication circuit 1 may be insufficient. Conversely, if the predetermined period P exceeds the upper limit, timing deviations may be more likely to occur.

[0040] The lower limit of the duration D of the refresh operation S3 is preferably 1 ns, more preferably 5 ns. On the other hand, the upper limit of the duration D is preferably 10 ns, more preferably 5 ns. If the duration D is less than the lower limit, timing deviations may be more likely to occur. Conversely, if the duration D exceeds the upper limit, the power reduction effect of the data communication circuit 1 may be insufficient.

[0041] The refresh pattern used in the refresh operation S3 is not particularly limited, but preferably has a high frequency of signal transitions, and for example, a pattern in which 0101 is repeated at the minimum time interval (data transmission bit rate) can be adopted.

[0042] When the refresh operation S3 is completed, the control unit 40 transitions to the sleep state S1.

[0043] (Retraining) Note that, for some unavoidable reason, for example, if the transmission timing of data sent from the output buffer 11 of the first data processing unit 10 deviates from the timing established in the training operation T, the input buffer 21 of the second data processing unit 20 may not be able to receive the data. In such a case, recovery can be achieved by, for example, performing the training operation T again to readjust the timing.

[0044] <Advantages> In the data communication circuit 1, the control unit 40 normally maintains a sleep state S1 in which no signal transition occurs on the transmission path 30, and performs control to cause a signal transition on the transmission path 30 when there is data to be transmitted from the first data processing unit 10 to the second data processing unit 20. Therefore, unnecessary signal transitions can be reduced, and power consumption can be reduced.

[0045] [Other embodiments] The above-described embodiments do not limit the configuration of the present disclosure. Therefore, the above-described embodiments may include omissions, substitutions, or additions of components based on the description in this specification and common general technical knowledge, and all of these should be construed as belonging to the scope of the present disclosure.

[0046] In the above embodiment, the data communication circuit for one-way communication has been described, but the data communication circuit may be used for two-way communication. In this case, the data communication circuit may be used for both directions, or may be used for only one of the two directions.

[0047] In the above embodiment, the transmission line is a single line, but a bus-like configuration in which multiple transmission lines are arranged may also be adopted. In this case, the multiple transmission lines may be controlled by a single control unit, or a control unit may be provided for each transmission line and controlled independently.

[0048] When there are multiple transmission paths using the CDR method, the data communication circuit may be used for all of the transmission paths, but it is also possible to configure some of the transmission paths without using the data communication circuit. For example, when data communication is performed frequently and it is difficult to put the data communication circuit into a pause state even if the data communication circuit is used, a configuration in which data communication is performed at all times as in the past may be adopted.

[0049] In the above embodiment, a case was described in which the control unit stores parameters for reproducing the timing information of the clock, but it is not an essential configuration for the control unit to store parameters for reproducing the timing information of the clock.

[0050] In the above embodiment, the case where the control unit performs the refresh operation has been described, but the refresh operation is not an essential configuration, and the present disclosure also intends to include a data communication circuit in which the control unit does not perform the refresh operation. For example, in a system in which it is known that the interval between data communications will not exceed a predetermined time, it is easy to maintain timing without performing the refresh operation. [Industrial Applicability]

[0051] The data communication circuit of the present disclosure can reduce power consumption in data communication using the CDR method. [Explanation of symbols]

[0052] 1 Data communication circuit 10 First data processing section 11 Output Buffer 20 Second Data Processing Section 21 Input Buffer 30 Transmission Line 31 First signal line 32 Second signal line 40 Control Unit 41 First Control Section 42 Second Control Section 50 parameters 51 First parameter 52 Second Parameter X1, X2 semiconductor devices T Training Movement S1 Hibernation S2 operating state S3 Refresh Operation P predetermined period D. Duration

Claims

1. A data communication circuit for performing data communication between a first data processing unit and a second data processing unit, a transmission path for transmitting data from the first data processing unit to the second data processing unit in a CDR system; a control unit for controlling data communication; Equipped with The transmission path is composed of two signal lines, and data is transmitted as a differential signal via the two signal lines; Clock timing is generated using a PLL or DLL. the control unit performs control to transition to an operating state in which a signal transition is caused on the transmission line when there is data to be transmitted from the first data processing unit to the second data processing unit, based on a pause state in which no signal transition is caused on the transmission line; and storing parameters for reproducing the timing information of the clock; A data communication circuit wherein said parameter is the timing of said PLL or DLL after synchronization.

2. A data communication circuit for performing data communication between a first data processing unit and a second data processing unit, a transmission path for transmitting data from the first data processing unit to the second data processing unit in a CDR system; a control unit for controlling data communication; Equipped with the control unit performs control to transition to an operating state in which a signal transition is caused on the transmission line when there is data to be transmitted from the first data processing unit to the second data processing unit, based on a pause state in which no signal transition is caused on the transmission line; and storing parameters for reproducing the timing information of the clock; When transitioning from the sleep state to the operating state, clock timing information is reproduced based on the parameters; The data communication circuit, wherein the parameters include a transmission voltage level and a transmission emphasis level of the first data processing unit, and an equalization level and a sampling timing of the second data processing unit.

3. A data communication circuit for performing data communication between a first data processing unit and a second data processing unit, a transmission path for transmitting data from the first data processing unit to the second data processing unit in a CDR system; a control unit for controlling data communication; Equipped with the control unit performs control to transition to an operating state in which a signal transition is caused on the transmission line when there is data to be transmitted from the first data processing unit to the second data processing unit, based on a pause state in which no signal transition is caused on the transmission line; and The data communication circuit wherein the control unit performs control so as to perform a refresh operation that forcibly and temporarily generates a signal transition on the transmission path when the pause state is maintained for a predetermined period of time.

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