Capacitor, electric circuit, circuit board, electronic device, and power storage device

Abstract

A capacitor 1a is provided with a first electrode layer 11, a second electrode layer 12, and an antiferroelectric layer 20. The antiferroelectric layer 20 is disposed between the first electrode layer 11 and the second electrode layer 12 in a thickness direction of the first electrode layer 11. The antiferroelectric layer 20 has varying thicknesses at a plurality of locations.

Description

[Technical Field]

[0001] The present disclosure relates to a capacitor, an electric circuit, a circuit board, an electronic device, and an electricity storage device. [Background technology]

[0002] Conventionally, capacitors using an antiferroelectric material in the dielectric layer are known.

[0003] For example, Patent Document 1 discloses a capacitor using an antiferroelectric material made of a metal oxide containing HfO2, suggesting that metal oxides containing HfO2 may exhibit antiferroelectricity. Patent Document 1 also describes an example in which part of the Hf in the HfO2 contained in the metal oxide of the dielectric layer of a capacitor is substituted with an element such as Bi. In this example, the relative permittivity of the dielectric layer fluctuates between 20 and 90 depending on the field strength when an external electric field of 0 MV / cm to 2 MV / cm is applied (see Figures 5 and 6). In addition, the relative permittivity of the dielectric layer can reach its maximum value in the field strength range of 0.5 MV / cm to 1.5 MV / cm.

[0004] Patent Document 2 describes a multilayer ceramic capacitor that includes a first capacitor unit made of a first material and a second capacitor unit made of a second material different from the first material. It describes that the first material exhibits ferroelectric properties and the second material exhibits antiferroelectric properties. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 208340 [Patent Document 2] Special Publication No. 2013-518400 Summary of the Invention [Problem to be solved by the invention]

[0006] The techniques described in Patent Documents 1 and 2 need to be reconsidered from the viewpoint of ease of designing products equipped with the capacitor. Therefore, the present disclosure provides a capacitor that uses an antiferroelectric material and is advantageous from the viewpoint of ease of product design. [Means for solving the problem]

[0007] The capacitor of the present disclosure comprises: a first electrode layer; A second electrode layer; an antiferroelectric layer disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, the first electrode layer covers the antiferroelectric layer on the inner side of the outermost portion of the first electrode layer in a plan view, the second electrode layer covers the antiferroelectric layer on the inner side of the outermost portion of the second electrode layer in a plan view, The antiferroelectric layer has different thicknesses at a plurality of locations. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a capacitor that uses an antiferroelectric material and is advantageous in terms of ease of product design. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1A is a plan view of a capacitor according to one embodiment of the present disclosure. [Figure 1B] FIG. 1B is a cross-sectional view of the capacitor taken along line IB-IB in FIG. [Figure 2A] FIG. 2A is a diagram schematically illustrating an example of an electric circuit according to the present disclosure. [Figure 2B] FIG. 2B is a diagram schematically illustrating an example of a circuit board according to the present disclosure. [Figure 2C] FIG. 2C is a diagram schematically illustrating an example of an electronic device according to the present disclosure. [Figure 2D] FIG. 2D is a diagram schematically illustrating an example of an electricity storage device according to the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view of a capacitor according to another embodiment of the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view of a capacitor according to yet another embodiment of the present disclosure. [Figure 5A] FIG. 5A is a plan view of a capacitor according to yet another embodiment of the present disclosure. [Figure 5B] FIG. 5B is a cross-sectional view of the capacitor taken along line VB-VB in FIG. 5A. [Figure 6A] FIG. 6A is a plan view of a capacitor according to yet another embodiment of the present disclosure. [Figure 6B] FIG. 6B is a cross-sectional view of the capacitor taken along line VIB-VIB in FIG. 6A. [Figure 7A] FIG. 7A is a plan view of a capacitor according to yet another embodiment of the present disclosure. [Figure 7B] FIG. 7B is a cross-sectional view of the capacitor taken along line VIIB-VIIB in FIG. 7A. [Figure 8] FIG. 8 is a graph showing the relationship between the polarization moment and the magnitude of the voltage between the electrodes of the capacitors according to the example and the comparative example. [Figure 9] FIG. 9 is a graph showing the relationship between the slope ΔP of the graph shown in FIG. 8 and the magnitude of the voltage. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Findings that formed the basis of this disclosure) An antiferroelectric is a material in which two sublattices in a crystal exhibit spontaneous polarization in opposite directions, which cancel each other out, resulting in zero spontaneous polarization for the entire crystal. As described in Patent Document 1, the dielectric constant of an antiferroelectric changes depending on the applied electric field strength. The capacitor described in Patent Document 1 is a parallel-plate type, and the thickness of the dielectric layer is understood to be constant in-plane. When a parallel-plate capacitor is constructed using an antiferroelectric, the change in the amount of charge stored in the capacitor relative to a change in voltage may be significantly different in a specific voltage range from that in other voltage ranges. This is because the dielectric constant of an antiferroelectric changes depending on the electric field strength applied to the antiferroelectric. These antiferroelectric characteristics are advantageous in terms of increasing the capacitance of the capacitor. However, the present inventors have newly discovered that some measures may be necessary to address these antiferroelectric characteristics in order to facilitate the design of products that include capacitors.

[0011] For example, if a capacitor using an antiferroelectric material is incorporated into an electric circuit without any special measures, the amount of charge stored in the capacitor may vary greatly depending on the drive voltage of the electric circuit. Therefore, it may become necessary to select an appropriate antiferroelectric composition and film thickness for each drive voltage. Furthermore, such characteristics of a capacitor using an antiferroelectric material may affect the selection of other devices in the electric circuit, making the design of the electric circuit more complicated and cumbersome.

[0012] In view of these circumstances, the present inventors have conducted extensive research into how to address the above-described characteristics of antiferroelectrics in capacitors using antiferroelectrics from the viewpoint of ease of product design. As a result, they have newly discovered that a capacitor advantageous from the viewpoint of ease of product design can be obtained by providing an antiferroelectric layer in a capacitor with a specific structure, and have devised the capacitor of the present disclosure.

[0013] (Summary of one aspect of the present disclosure) The capacitor according to the first aspect of the present disclosure comprises: a first electrode layer; A second electrode layer; an antiferroelectric layer disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, the first electrode layer covers the antiferroelectric layer on the inner side of the outermost portion of the first electrode layer in a plan view, the second electrode layer covers the antiferroelectric layer on the inner side of the outermost portion of the second electrode layer in a plan view, The antiferroelectric layer has different thicknesses at a plurality of locations.

[0014] According to the first aspect, the antiferroelectric layer has different thicknesses at multiple locations, so that when a voltage is applied between the first electrode layer and the second electrode layer, the electric field strength applied to the antiferroelectric layer varies at multiple locations. As a result, despite the antiferroelectric's characteristic of changing its relative permittivity depending on the applied electric field strength, the average rate of change, which is the ratio of the amount of change in the amount of charge stored in the capacitor to a constant amount of voltage change, is unlikely to fluctuate significantly over a wide voltage range. Therefore, the capacitor according to the first aspect is advantageous from the perspective of ease of product design. Furthermore, since the first electrode layer and the second electrode layer cover the antiferroelectric layer as described above, the capacitance of the capacitor is likely to be large. In addition, the thickness of the antiferroelectric layer can be easily adjusted over a wide range.

[0015] In a second aspect of the present disclosure, for example, in the capacitor according to the first aspect, the antiferroelectric layer may have a thickness of 10 nanometers (nm) to 1 micrometer (μm). According to the second aspect, insulation failure is prevented, and the capacitance of the capacitor is less likely to decrease.

[0016] In a third aspect of the present disclosure, for example, in the capacitor according to the first or second aspect, the ratio of the maximum thickness of the antiferroelectric layer to the minimum thickness of the antiferroelectric layer may be greater than 1 and less than 10. According to the third aspect, the average rate of change is more reliably less likely to fluctuate significantly over a wide voltage range. In addition, the capacitance of the capacitor is less likely to decrease.

[0017] In a fourth aspect of the present disclosure, for example, in the capacitor according to any one of the first to third aspects, the maximum thickness of the antiferroelectric layer may be 500 nm or less. According to the fourth aspect, the capacitance of the capacitor is likely to be large. In addition, the thickness of the capacitor is likely to be small.

[0018] In a fifth aspect of the present disclosure, for example, in the capacitor according to any one of the first to fourth aspects, the antiferroelectric layer may have a thickness smaller than that of the first electrode layer. According to the fifth aspect, the capacitance of the capacitor is likely to be large. In addition, the thickness of the capacitor is likely to be small.

[0019] In a sixth aspect of the present disclosure, for example, in the capacitor according to any one of the first to fifth aspects, the antiferroelectric layer may have a thickness smaller than that of the second electrode layer. According to the sixth aspect, the capacitance of the capacitor is likely to be large. In addition, the thickness of the capacitor is likely to be small.

[0020] In a seventh aspect of the present disclosure, for example, in the capacitor according to any one of the first to sixth aspects, the antiferroelectric layer may have a thickness that varies continuously or stepwise in a specific direction in the plane. According to the seventh aspect, the thickness of the antiferroelectric layer can take various values, so that the average rate of change is more reliably less likely to fluctuate significantly over a wide voltage range.

[0021] In an eighth aspect of the present disclosure, for example, in the capacitor according to the seventh aspect, the antiferroelectric layer may have a thickness that changes continuously or stepwise from one end to the other end in a specific in-plane direction. According to the eighth aspect, the thickness of the antiferroelectric layer can take on various values ​​from one end to the other end in the specific in-plane direction, so that the average rate of change is more reliably less likely to fluctuate significantly over a wide voltage range.

[0022] In a ninth aspect of the present disclosure, for example, in the capacitor according to any one of the first to eighth aspects, the antiferroelectric layer may include a first region having a minimum thickness and a predetermined area in a planar view, and a second region having a maximum thickness and a predetermined area in a planar view. Additionally, the ratio of the area of ​​the second region in a planar view to the area of ​​the first region in a planar view may be greater than 1 and less than 10. According to the ninth aspect, when a voltage is applied between the first electrode layer and the second electrode layer, the spatial distribution of the electric field strength applied to the antiferroelectric layer is likely to be in a desired state. As a result, the average rate of change is more reliably less likely to fluctuate significantly over a wide voltage range.

[0023] In a tenth aspect of the present disclosure, for example, the capacitor according to any one of the first to ninth aspects may include a connection portion formed between a pair of regions having different thicknesses, the connection portion having a step corresponding to the difference in thickness between the pair of regions. According to the tenth aspect, the connection portion is small in the antiferroelectric layer, making it easy to make the pair of regions large. Also, it is easy to fabricate the antiferroelectric layer.

[0024] In an eleventh aspect of the present disclosure, for example, in a capacitor according to any one of the first to tenth aspects, the antiferroelectric layer may be formed between a pair of regions having different thicknesses and may include a connecting portion having a thickness that varies continuously or stepwise from one of the pair of regions to the other of the pair of regions. According to the eleventh aspect, discontinuities are unlikely to occur in the second electrode layer above the pair of regions. In addition, poor adhesion between the antiferroelectric layer and the second electrode layer is easily prevented. As a result, the capacitor is likely to have high reliability.

[0025] In a twelfth aspect of the present disclosure, for example, in the capacitor according to any one of the first to eleventh aspects, the antiferroelectric layer may include a plurality of specific regions having a specific thickness and a predetermined area in a planar view. In addition, the plurality of specific regions may be arranged apart from each other when the antiferroelectric layer is viewed in a planar view from the second electrode layer side. According to the twelfth aspect, the locations where a load is applied to the antiferroelectric layer are likely to be dispersed, and the capacitor is likely to have high robustness.

[0026] According to a thirteenth aspect of the present disclosure, for example, in the capacitor according to the twelfth aspect, the plurality of specific regions may be regularly arranged when the antiferroelectric layer is viewed from the second electrode layer side in a plan view, which makes it easier for the capacitor to have high robustness with more certainty.

[0027] According to a fourteenth aspect of the present disclosure, for example, in the capacitor according to the twelfth or thirteenth aspect, the plurality of specific regions may be formed as a plurality of strips extending parallel to each other when the antiferroelectric layer is viewed in plan from the second electrode layer side, which makes it easier for the capacitor to have high robustness with more certainty.

[0028] According to a fifteenth aspect of the present disclosure, for example, in the capacitor according to the twelfth or thirteenth aspect, the plurality of specific regions may be circular or rectangular when the antiferroelectric layer is viewed from the second electrode layer side in a plan view. According to the fifteenth aspect, the capacitor is likely to have high robustness more reliably.

[0029] According to a sixteenth aspect of the present disclosure, for example, in the capacitor according to any one of the first to fifteenth aspects, the antiferroelectric layer may contain a metal oxide having at least one of hafnium and zirconium, which makes it easier for the capacitor to have a desired capacitance.

[0030] According to a seventeenth aspect of the present disclosure, for example, the capacitor according to any one of the first to sixteenth aspects may further include a support, and the first electrode layer may be disposed between the support and the antiferroelectric layer in the thickness direction of the first electrode layer. According to the seventeenth aspect, the support can support a stack including the first electrode layer, the antiferroelectric layer, and the second electrode layer, which tends to increase the mechanical strength of the capacitor.

[0031] According to an eighteenth aspect of the present disclosure, for example, in the capacitor according to any one of the seventeenth aspects, the support may not have a void at a position corresponding to the antiferroelectric layer in plan view, which tends to further increase the mechanical strength of the capacitor.

[0032] An electric circuit according to a 19th aspect of the present disclosure includes the capacitor according to any one of the 1st to 18th aspects. According to the 19th aspect, the electric circuit can be easily designed.

[0033] A circuit board according to a twentieth aspect of the present disclosure includes the capacitor according to any one of aspects 1 to 18. According to the twentieth aspect, the circuit board can be easily designed.

[0034] An electronic device according to a 21st aspect of the present disclosure includes the capacitor according to any one of the 1st to 18th aspects. According to the 21st aspect, the electronic device is easy to design.

[0035] An electricity storage device according to a 22nd aspect of the present disclosure includes the capacitor according to any one of the 1st to 18th aspects. According to the 22nd aspect, the electricity storage device can be easily designed.

[0036] (Embodiment) Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments. In the following description, terms indicating specific directions and positions (e.g., "upper," "lower," "left," "right," and other terms containing these terms) will be used as necessary. However, the use of these terms is intended to facilitate understanding of the invention with reference to the drawings, and the meanings of these terms do not limit the technical scope of the present disclosure.

[0037] 1A and 1B are a plan view and a cross-sectional view, respectively, illustrating a capacitor 1a according to an embodiment of the present disclosure. As shown in FIGS. 1A and 1B, the capacitor 1a includes a first electrode layer 11, a second electrode layer 12, and an antiferroelectric layer 20. The antiferroelectric layer 20 is disposed between the first electrode layer 11 and the second electrode layer 12 in the thickness direction of the first electrode layer 11. The first electrode layer 11 covers the antiferroelectric layer 20 on the inner side of the outermost portion 11e of the first electrode layer 11 in a planar view. In addition, the second electrode layer 12 covers the antiferroelectric layer 20 on the inner side of the outermost portion 12e of the second electrode layer 12 in a planar view. Each of the first electrode layer 11 and the second electrode layer 12 is, for example, a layer having no openings or gaps in a planar view. This configuration facilitates the increase in capacitance of the capacitor 1a. Additionally, the thickness of the antiferroelectric layer 20 can be easily adjusted over a wide range. The antiferroelectric layer 20 has different thicknesses at multiple locations. When a voltage is applied between the first electrode layer 11 and the second electrode layer 12, the electric field strength applied to the antiferroelectric layer 20 varies at multiple locations. In other words, the electric field strength applied to the antiferroelectric layer 20 can take on a variety of values. As a result, although the capacitor 1a includes the antiferroelectric layer 20 as a dielectric layer, the average rate of change, which is the ratio of the amount of change in the amount of charge stored in the capacitor 1a to a constant amount of voltage change, is unlikely to fluctuate significantly over a wide voltage range. For this reason, the capacitor 1a is advantageous from the perspective of ease of product design.

[0038] The thickness of the antiferroelectric layer 20 is not limited to a specific value. The thickness of the antiferroelectric layer 20 is, for example, 10 nm or more and 1 μm or less. For example, the thickness of the antiferroelectric layer 20 falls within this range throughout the entire antiferroelectric layer 20. When the thickness of the antiferroelectric layer 20 is 10 nm or more, pinholes are less likely to occur in the antiferroelectric layer 20, and insulation defects can be prevented. The capacitance of the capacitor is inversely proportional to the thickness of the dielectric layer. When the thickness of the antiferroelectric layer 20 is 1 μm or less, the capacitance of the capacitor 1 a is less likely to decrease. The thickness of the antiferroelectric layer 20 can be determined, for example, by observing a cross section of the capacitor 1 a perpendicular to the main surface of the first electrode layer 11 with an electron microscope.

[0039] The ratio of the maximum thickness of the antiferroelectric layer 20 to the minimum thickness of the antiferroelectric layer 20 is not limited to a specific value. The value of the ratio is, for example, greater than 1 and less than 10. This more reliably prevents the average rate of change from fluctuating significantly over a wide voltage range. In addition, the capacitance of the capacitor 1a is less likely to decrease. The ratio of the maximum thickness of the antiferroelectric layer 20 to the minimum thickness of the antiferroelectric layer 20 may be 1.1 or more, 1.2 or more, 1.5 or more, or even 2 or more. The ratio of the maximum thickness of the antiferroelectric layer 20 to the minimum thickness of the antiferroelectric layer 20 may be 9 or less, 8 or less, 7 or less, 6 or less, or 5 or less.

[0040] The maximum thickness of the antiferroelectric layer 20 may be less than 1 μm, and preferably 500 nm or less. This tends to increase the capacitance of the capacitor 1a. In addition, it tends to reduce the thickness of the capacitor 1a. The maximum thickness of the antiferroelectric layer 20 may be 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, or 20 nm or less.

[0041] The relationship between the thickness of the antiferroelectric layer 20 and the thickness of the first electrode layer 11 is not limited to a specific relationship. The antiferroelectric layer 20 has a thickness smaller than that of the first electrode layer 11, for example. With such a configuration, the capacitance of the capacitor 1a tends to be large. In addition, the thickness of the capacitor 1a tends to be small. The antiferroelectric layer 20 may have a thickness equal to or greater than that of the first electrode layer 11.

[0042] The relationship between the thickness of the antiferroelectric layer 20 and the thickness of the second electrode layer 12 is not limited to a specific relationship. The antiferroelectric layer 20 has a thickness smaller than that of the second electrode layer 12, for example. With such a configuration, the capacitance of the capacitor 1a tends to be large. In addition, the thickness of the capacitor 1a tends to be small. The antiferroelectric layer 20 may have a thickness equal to or greater than that of the second electrode layer 12.

[0043] 1A and 1B, the antiferroelectric layer 20 has, for example, a first region 21 and a second region 22. The first region 21 and the second region 22 have different thicknesses. The first region 21 has, for example, the smallest thickness in the antiferroelectric layer 20 and a predetermined area in a plan view. For example, the thickness of the first region 21 is constant or can be considered to be constant throughout the entire first region 21. For example, when thickness data at 10 or more randomly selected locations in the target region show a difference between the maximum value and the average value and a difference between the average value and the minimum value that is 10% or less of the average value, the thickness of the target region can be considered to be constant. The second region 22 has, for example, the largest thickness in the antiferroelectric layer 20 and a predetermined area in a plan view. For example, the thickness of the second region 22 is constant or can be considered to be constant throughout the entire second region 22. The ratio of the area of ​​the second region 22 in a plan view to the area of ​​the first region 21 in a plan view is not limited to a specific value. The ratio is, for example, greater than 1 and less than 10. In this case, when a voltage is applied between the first electrode layer 11 and the second electrode layer 12, the spatial distribution of the electric field intensity applied to the antiferroelectric layer 20 is likely to be in a desired state. As a result, the average rate of change is more reliably less likely to fluctuate significantly over a wide voltage range. The ratio of the area of ​​the second region 22 in a planar view to the area of ​​the first region 21 in a planar view may be 1.5 or more, 2 or more, or 3 or more. The ratio of the area of ​​the second region 22 in a planar view to the area of ​​the first region 21 in a planar view may be 9 or less, 8 or less, or 7 or less.

[0044] 1B , the antiferroelectric layer 20 includes, for example, a connection portion 25. The connection portion 25 is formed between the first region 21 and the second region 22. The connection portion 25 forms, for example, a step corresponding to the difference in thickness between the first region 21 and the second region 22. With such a configuration, the connection portion 25 in the antiferroelectric layer 20 is likely to be small, and the area of ​​the first region 21 or the second region 22 is likely to be large.

[0045] The antiferroelectric material contained in the antiferroelectric layer 20 is not limited to a specific material as long as it has antiferroelectric properties. The antiferroelectric layer 20 typically has a uniform composition and phase throughout. The antiferroelectric layer 20 includes, for example, a metal oxide having at least one of hafnium and zirconium. Thereby, the capacitor 1a is likely to have a desired capacitance. Examples of metal oxides having at least one of hafnium and zirconium are oxides having a fluorite structure such as HfO2, ZrO2, Hf Zr x O2. x is a value satisfying the condition 0 < x < 1. The metal oxide may be an oxide in which a part of Hf in HfO2 or Hf 1-x Zr x O2 is substituted with Si or Al. The metal oxide may be an oxide in which a part of Zr in ZrO2 or Hf 1-x Zr x O2 is substituted with Y, Ti, Sn, or Ce. The antiferroelectric material contained in the antiferroelectric layer 20 may be another metal oxide having a fluorite structure or an oxide having a perovskite structure. Examples of oxides having a perovskite structure are PbZr y Ti 1-y O3, NaNbO3, and AgNbO3. y is a value satisfying the condition 0 < y < 1.

[0046] <00,00244>As shown in FIG. 1B, the first electrode layer 11, for example, contacts the antiferroelectric layer 20. The thickness of the first electrode layer 11 is not limited to a specific value. The thickness of the first electrode layer 11 is, for example, 100 nm or more. Thereby, the internal resistance of the capacitor 1a is likely to be low. The thickness of the first electrode layer 11 is, for example, 500 nm or less. Thereby, the capacitance density of the entire capacitor 1a is likely to be large.

[0047] The material of the first electrode layer 11 is not limited to a specific material. The material of the first electrode layer 11 may be a metal such as Pt, Au, Al, Ta, or Zr. The material of the first electrode layer 11 may be a conductive nitride such as TiN or TaN, or a conductive oxide such as indium tin oxide (ITO), antimony tin oxide (ATO), or ZnO. When the process of forming the antiferroelectric layer 20 on the first electrode layer 11 is performed in an oxidizing atmosphere, the material of the first electrode layer 11 is preferably Pt, Au, ITO, or ZnO. When the process of forming the antiferroelectric layer 20 on the first electrode layer 11 is performed in a reducing atmosphere, the material of the first electrode layer 11 is preferably Pt, Au, Al, Ta, Zr, TiN, or TaN.

[0048] 1B, the second electrode layer 12, for example, contacts the antiferroelectric layer 20. The second electrode layer 12 contacts both the first region 21 and the second region 22. In addition, the second electrode layer 12 contacts the connection portion 25.

[0049] The thickness of the second electrode layer 12 is not limited to a specific value. The thickness of the second electrode layer 12 is, for example, 100 nm or more. In this case, the internal resistance of the capacitor 1a tends to be low. The thickness of the second electrode layer 12 is, for example, 500 nm or less. In this case, the capacitance density of the entire capacitor 1a tends to be high.

[0050] The material of the second electrode layer 12 is not limited to a specific material. The material of the second electrode layer 12 may be a metal such as Pt, Au, Al, Ta, or Zr. The material of the second electrode layer 12 may be a conductive nitride such as TiN or TaN, or a conductive oxide such as ITO, ATO, or ZnO. After the second electrode layer 12 is formed, an annealing treatment may be performed to crystallize the material that will form the antiferroelectric layer 20. When the annealing treatment creates an oxidizing atmosphere around the second electrode layer 12 due to the gas supplied around the second electrode layer 12, the material of the second electrode layer 12 is preferably Pt, Au, ITO, or ZnO. When the annealing treatment creates a reducing atmosphere around the second electrode layer 12, the material of the second electrode layer 12 is preferably Pt, Au, Al, Ta, Zr, TiN, or TaN.

[0051] As shown in FIG. 1B , the capacitor 1a further includes, for example, a support 30. The first electrode layer 11 is disposed between the support 30 and the antiferroelectric layer 20 in the thickness direction of the first electrode layer 11. The support 30 can support a stack including the first electrode layer 11, the antiferroelectric layer 20, and the second electrode layer 12, which tends to increase the mechanical strength of the capacitor 1a. The support 30 can be used, for example, as a base material for forming the first electrode layer 11. In the capacitor 1a, the support 30 may be omitted.

[0052] The support 30 may be a conductor, a semiconductor, or an insulator. When the support 30 is a conductor, the support 30 and the first electrode layer 11 may be integrated together. In this case, the thickness of the first electrode layer 11 may be greater than 500 nm.

[0053] The thickness of the support 30 is not limited to a particular value, and is, for example, 5 μm or more and 1 mm or less.

[0054] The support 30 does not have a void in a plan view at a position corresponding to the antiferroelectric layer 20. With such a configuration, the mechanical strength of the capacitor 1a tends to be increased.

[0055] In the capacitor 1a, when a voltage is applied between the first electrode layer 11 and the second electrode layer 12, a potential difference is generated in the antiferroelectric layer 20. The magnitude of the potential difference generated in the first region 21 is the same as that in the second region 22. On the other hand, the electric field strength is the potential difference per unit thickness of the dielectric layer, and has a dimension of V / m. Since the first region 21 and the second region 22 have different thicknesses, the electric field strengths in the first region 21 and the second region 22 are different from each other. Since the relative dielectric constant of the antiferroelectric varies depending on the electric field strength, even if the first region 21 and the second region 22 are formed of the same type of antiferroelectric, the relative dielectrics in the first region 21 and the second region 22 may have different relative dielectric constants from each other.

[0056] The dielectric constant of many antiferroelectric materials tends to increase with increasing electric field strength and then slightly decrease with further increase in electric field strength. As a result, the applied voltages at which the dielectric constant is maximized are different between the first region 21 and the second region 22. Therefore, even if the ratio of the change in dielectric constant to a given voltage change is large in one of the first region 21 and the second region 22, the ratio of the change in dielectric constant to a given voltage change is likely to be small in the other of the first region 21 and the second region 22. This prevents the ratio of the change in dielectric constant to a given voltage change from fluctuating significantly across a given voltage range throughout the entire antiferroelectric layer 20. As a result, compared to capacitors with a constant antiferroelectric layer thickness, the average rate of change of the capacitor 1a, which is the ratio of the change in the amount of charge stored in the capacitor to a given voltage change, is less likely to fluctuate significantly across a wide voltage range. This makes the capacitor 1a advantageous in terms of ease of designing products such as electrical circuits.

[0057] As shown in FIG. 2A , for example, an electric circuit 3 including a capacitor 1a can be provided. The electric circuit 3 is not limited to a specific circuit as long as it includes a capacitor 1a. The electric circuit 3 may be an active circuit or a passive circuit. The electric circuit 3 may be a discharge circuit, a smoothing circuit, a decoupling circuit, or a coupling circuit. Since the electric circuit 3 includes a capacitor 1a, the design of the electric circuit 3 is easy.

[0058] 2B, for example, a circuit board 5 including a capacitor 1a can be provided. Since the circuit board 5 includes the capacitor 1a, the design of the circuit board 5 is easy. For example, an electric circuit 3 including the capacitor 1a is formed on the circuit board 5.

[0059] As shown in Fig. 2C, for example, an electronic device 7 including a capacitor 1a can be provided. Because the electronic device 7 includes the capacitor 1a, the design of the electronic device 7 is easy. For example, the electronic device 7 includes a circuit board 5 including the capacitor 1a. The electronic device 7 is, for example, an information terminal such as a smartphone or a tablet PC.

[0060] As shown in FIG. 2D , for example, an electricity storage device 9 including a capacitor 1a can be provided. Because the electricity storage device 9 includes the capacitor 1a, the electricity storage device 9 can be easily designed. Using the electricity storage device 9, for example, an electricity storage system 50 can be provided. The electricity storage system 50 includes the electricity storage device 9 and a power generation device 2. In the electricity storage system 50, electricity generated by the power generation device 2 is stored in the electricity storage device 9. The power generation device 2 is, for example, a device for solar power generation or wind power generation. The electricity storage device 9 is, for example, a device including a lithium-ion battery or a lead-acid battery.

[0061] An example of a method for manufacturing the capacitor 1a will be described. First, a first electrode layer 11 is formed on the main surface of the support 30. For example, a vacuum process, plating, or coating can be used to form the first electrode layer 11. Examples of vacuum processes include DC sputtering, RF magnetron sputtering, pulsed laser deposition (PLD), atomic layer deposition (ALD), and chemical vapor deposition (CVD). The support 30 may be made of a metal foil such as aluminum foil or copper foil, and the support 30 and the first electrode layer 11 may be integrally formed. As an example, a TiN thin film serving as the first electrode layer 11 may be formed by RF magnetron sputtering on the main surface of a Si substrate serving as the support 30.

[0062] Next, the antiferroelectric layer 20 is formed on the first electrode layer 11. The vacuum process exemplified as the method for forming the first electrode layer 11 can be applied to the formation of the antiferroelectric layer 20. The antiferroelectric layer 20 may also be formed by a wet process such as dip coating, spin coating, or die coating using a Chemical Solution Deposition (CSD) method. For example, the antiferroelectric layer 20 may be formed by RF magnetron sputtering using Hf 0.48 Zr 0.48 Si 0.04 Examples of suitable methods include forming an O2 thin film. The first region 21 is formed by inserting a metal mask directly above the location where the first region 21 is to be formed while depositing the material that will form the antiferroelectric layer 20 by, for example, RF magnetron sputtering. The metal mask can be inserted at a predetermined position on a line connecting the sputtering target and the deposit of the material that will form the antiferroelectric layer 20. As a result, in the region covered with the metal mask, the deposition of the material that will form the antiferroelectric layer 20 stops, and the first region 21 having a small thickness is formed. On the other hand, in the region not covered with the metal mask, the deposition of the material that will form the antiferroelectric layer 20 continues, and the second region 22 having a large thickness is formed. Hf 0.48 Zr 0.48 Si 0.04 The O2 thin film can be formed under conditions that result in an amorphous structure.0.48 Zr 0.48 Si 0.04 O2 thin film exhibits paraelectricity and does not exhibit antiferroelectricity. Therefore, the amorphous structure of Hf 0.48 Zr 0.48 Si 0.04 Rapid Thermal Anneal (RTA) treatment was performed on the O2 thin film, and Hf 0.48 Zr 0.48 Si 0.04 The O2 thin film is crystallized into the tetragonal phase. 0.48 Zr 0.48 Si 0.04 The O2 thin film exhibits antiferroelectricity, and an antiferroelectric layer 20 is obtained.

[0063] Next, the second electrode layer 12 is formed on the antiferroelectric layer 20. To form the second electrode layer 12, a vacuum process, plating, or coating can be applied, as in the case of forming the first electrode layer 11. One example is to form an Au electrode, which is the second electrode layer 12, by vacuum deposition.

[0064] In the capacitor 1a, the antiferroelectric layer 20 includes, for example, two regions having different thicknesses as described above. The antiferroelectric layer 20 may also include three or more regions having different thicknesses.

[0065] 3 is a cross-sectional view showing a capacitor 1b according to another embodiment of the present disclosure. Capacitor 1b has the same configuration as capacitor 1a, except for portions that will be specifically described. Components of capacitor 1b that are the same as or correspond to components of capacitor 1a are denoted by the same reference numerals, and detailed description thereof will be omitted. The description of capacitor 1a also applies to capacitor 1b, unless technically inconsistent.

[0066] 3, in the capacitor 1b, the antiferroelectric layer 20 has a thickness that changes continuously in a specific direction in the plane. This allows the thickness of the antiferroelectric layer 20 to take on a variety of values, making it more reliable that the average rate of change does not fluctuate significantly over a wide voltage range. The antiferroelectric layer 20 may have a thickness that changes stepwise in a specific direction in the plane.

[0067] 3 , the antiferroelectric layer 20 includes a connection portion 25. The connection portion 25 is formed between the first region 21 and the second region 22. The connection portion 25 has a thickness that changes continuously from the first region 21 to the second region 22. The connection portion 25 has a thickness that changes monotonically between the first region 21 and the second region 22, for example. The connection portion 25 may have a thickness that changes stepwise from the first region 21 to the second region 22.

[0068] The connecting portion 25 has a thickness that increases continuously from the first region 21 toward the second region 22. The surface of the connecting portion 25 is inclined at a predetermined angle with respect to the main surface of the first electrode layer 11 that is in contact with the antiferroelectric layer 20. The angle is, for example, not less than 30° and not more than 60°.

[0069] An example of a method for forming such a connection portion 25 will be described. When forming the antiferroelectric layer 20 by RF magnetron sputtering, a metal mask is placed over the region where the first region 21 is to be formed during thin-film deposition. Thereafter, the material for the antiferroelectric layer 20 is prevented from depositing in the region where the first region 21 is to be formed. Then, the metal mask is moved at a constant speed toward the space above the region where the second region 22 is to be formed by a distance corresponding to the connection portion 25 until the deposition of the material for the antiferroelectric layer 20 in the region where the second region 22 is to be formed is completed. Alternatively, the metal mask inserted between the sputtering target and the first electrode layer 11 is positioned away from the region where the antiferroelectric layer 20 is to be formed. This allows particles repelled from the sputtering target to flow behind the metal mask, forming the connection portion 25. Forming the connection portion 25 in this manner makes it difficult for discontinuities to occur in the second electrode layer 12 above the first region 21 and the second region 22. Additionally, poor adhesion between the antiferroelectric layer 20 and the second electrode layer 12 is easily prevented. As a result, capacitor 1b tends to have high reliability.

[0070] 4 is a cross-sectional view showing a capacitor 1c according to yet another example of an embodiment of the present disclosure. Capacitor 1c has the same configuration as capacitor 1a, except for portions that will be particularly described. Components of capacitor 1c that are the same as or correspond to components of capacitor 1a are given the same reference numerals, and detailed description thereof will be omitted. The description of capacitor 1a also applies to capacitor 1c, unless technically inconsistent.

[0071] As shown in FIG. 4, in the capacitor 1c, the antiferroelectric layer 20 has a thickness that changes continuously in a specific direction within the plane.

[0072] The antiferroelectric layer 20 has a thickness that changes continuously from one end to the other end in a specific in-plane direction, for example. With this configuration, the thickness of the antiferroelectric layer 20 can take on various values ​​from one end to the other end in a specific in-plane direction of the antiferroelectric layer 20. This makes it more certain that the average rate of change does not fluctuate significantly over a wide voltage range. The antiferroelectric layer 20 may have a thickness that changes stepwise from one end to the other end in a specific in-plane direction.

[0073] The antiferroelectric layer 20 has, for example, a thickness that continuously increases from one end to the other end in a specific in-plane direction. The antiferroelectric layer 20 has, for example, a thickness that continuously increases from one end to the other end in a specific in-plane direction. The antiferroelectric layer 20 has, for example, a thickness that monotonically changes from one end to the other end in a specific in-plane direction. The antiferroelectric layer 20 has, for example, a thickness that monotonically increases from one end to the other end in a specific in-plane direction. The antiferroelectric layer 20 is formed, for example, so that the ratio of the amount of change in thickness to the amount of change in distance between one end and the other end in a specific in-plane direction is constant.

[0074] An example of a method for forming such an antiferroelectric layer 20 will be described. When forming the antiferroelectric layer 20 by RF magnetron sputtering, a material for the antiferroelectric layer 20 is deposited to a predetermined thickness. Then, a metal mask is moved at a constant speed from left to right in FIG. 4 while the film is being formed. The material for the antiferroelectric layer 20 is not deposited in the area covered by the metal mask. Therefore, the thickness of the antiferroelectric layer 20 is small on the left side of FIG. 4 and large on the right side of FIG. 4 where the antiferroelectric layer 20 is covered by the metal mask for a shorter period of time. This allows the antiferroelectric layer 20 to be formed so that the ratio of the change in thickness to the change in distance between one end and the other end in a specific in-plane direction is constant. Alternatively, the antiferroelectric layer 20 can be formed by performing sputtering while the first electrode layer 11 is tilted relative to the sputtering target rather than being parallel to it. In this case, the thickness of the antiferroelectric layer 20 tends to be large in regions on the first electrode layer 11 that are close to the target, and tends to be small in regions on the first electrode layer 11 that are close to the target. The antiferroelectric layer 20 formed in this manner can be considered to include a large number of minute regions having different thicknesses, and the thickness of the antiferroelectric layer 20 can take on a variety of values.

[0075] FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, of a capacitor 1d according to yet another example of an embodiment of the present disclosure. FIGS. 6A and 6B are a plan view and a cross-sectional view, respectively, of a capacitor 1e according to yet another example of an embodiment of the present disclosure. FIGS. 7A and 7B are a plan view and a cross-sectional view, respectively, of a capacitor 1f according to yet another example of an embodiment of the present disclosure. Capacitors 1d, 1e, and 1f are each configured similarly to capacitor 1a, except for portions that are particularly described. Components of capacitors 1d, 1e, and 1f that are the same as or correspond to components of capacitor 1a are designated by the same reference numerals, and detailed description thereof will be omitted. The description of capacitor 1a also applies to capacitors 1d, 1e, and 1f, unless technically inconsistent.

[0076] As shown in FIGS. 5A, 5B, 6A, 6B, 7A, and 7B, in each of the capacitors 1d, 1e, and 1f, the antiferroelectric layer 20 includes a plurality of specific regions 23. The specific regions 23 have a specific thickness. In other words, the thickness of the antiferroelectric layer 20 in the plurality of specific regions 23 is the same. Alternatively, the thickness of the antiferroelectric layer 20 in the plurality of specific regions 23 can be considered to be the same. For example, when the difference between the maximum and minimum average values ​​of thicknesses measured at 10 or more randomly selected locations in each specific region 23 is 10% or less of the minimum value, the thickness of the antiferroelectric layer 20 in the plurality of specific regions 23 can be considered to be the same. The plurality of specific regions 23 are arranged apart from each other when the antiferroelectric layer 20 is viewed from the second electrode layer 12 side in a plan view. With this configuration, for example, the locations to which a load is applied on the antiferroelectric layer 20 are likely to be dispersed. Therefore, when the capacitor 1d is used to form a stacked structure or a wound structure, the capacitor 1d is likely to have high robustness. The specific regions 23 protrude in the thickness direction of the antiferroelectric layer 20, for example.

[0077] As shown in Figures 5A, 5B, 6A, 6B, 7A, and 7B, in each of capacitors 1d, 1e, and 1f, the multiple specific regions 23 are regularly arranged when the antiferroelectric layer 20 is viewed in plan from the second electrode layer 12 side. With this configuration, capacitor 1d is more likely to have high robustness. In the cross sections of Figures 5B, 6B, and 7B, the thickness of the antiferroelectric layer 20 varies periodically. Capacitors 1d, 1e, and 1f may each be modified so that the multiple specific regions 23 are irregularly arranged when the antiferroelectric layer 20 is viewed in plan from the second electrode layer 12 side.

[0078] As shown in FIG. 5A, in the capacitor 1d, the multiple specific regions 23 are formed as multiple strips extending parallel to each other when the antiferroelectric layer 20 is viewed from the second electrode layer 12 side. With this configuration, the total area of ​​the multiple specific regions 23 in the planar view is likely to be large, and the capacitor 1d is likely to have higher robustness more reliably. The antiferroelectric layer 20 further includes, for example, multiple bottom regions 24. As shown in FIG. 5B, the thickness of the antiferroelectric layer 20 in each bottom region 24 is smaller than the thickness of the antiferroelectric layer 20 in the specific region 23. The multiple bottom regions 24 are formed as multiple strips extending parallel to each other. In the antiferroelectric layer 20, the specific regions 23 and the bottom regions 24 are alternately arranged.

[0079] As shown in FIG. 6A, in capacitor 1e, the multiple specific regions 23 are rectangular when the antiferroelectric layer 20 is viewed from the second electrode layer 12 side in a planar view. On the other hand, as shown in FIG. 7A, in capacitor 1f, the multiple specific regions 23 are circular when the antiferroelectric layer 20 is viewed from the second electrode layer 12 side in a planar view. These configurations make it easier for the capacitor to have high robustness more reliably. In addition, it is easy to adjust the total area of ​​the multiple specific regions 23 in a planar view, and to adjust the capacitance characteristics of the capacitor.

[0080] In each of the capacitors 1e and 1f, the antiferroelectric layer 20 further includes, for example, a bottom region 24. The thickness of the antiferroelectric layer 20 in the bottom region 24 is smaller than the thickness of the antiferroelectric layer 20 in the specific region 23. The bottom region 24 is adjacent to each of the multiple specific regions 23 when the antiferroelectric layer 20 is viewed in plan from the second electrode layer 12 side, and extends continuously within the plane of the antiferroelectric layer 20.

[0081] The multiple specific regions 23 may have a polygonal shape other than a rectangle when the antiferroelectric layer 20 is viewed in a plane from the second electrode layer 12 side, may have an elliptical shape, may have a figure shape having both curved and straight lines, or may have an irregular shape.

[0082] 5B, 6B, and 7B, for example, the surfaces of capacitors 1d, 1e, and 1f on the side of the second electrode layer 12 have irregularities. These irregularities are due to the shape of the antiferroelectric layer 20. Capacitors 1d, 1e, and 1f may be modified so that the surfaces on the side of the second electrode layer 12 are flat. [Example]

[0083] The present disclosure will be described in more detail below based on examples, although the present disclosure is not limited to the following examples.

[0084] [Example] A 300 nm thick TiN thin film was formed on the (100) surface of the Si substrate by RF magnetron sputtering to obtain a first electrode layer. Next, an amorphous thin film was formed on the first electrode layer by RF magnetron sputtering. The composition of this amorphous thin film was Hf 0.48 Zr 0.48 Si 0.04 O2 and exhibited paraelectric properties. In the deposition of this amorphous thin film, a metal mask was inserted between the sputtering target and the first electrode layer. The metal mask was moved in two stages during the RF sputtering process, and the area masked by the metal mask was changed in two stages. This resulted in the deposition of an amorphous thin film having three regions with different thicknesses: Region A, Region B, and Region C. The area of ​​Region A in plan view was 1 mm 2 The thickness of the amorphous thin film in region A was 10 nm. The area of ​​region B in plan view was 1 mm. 2 The thickness of the amorphous thin film in region B was 15 nm. The area of ​​region C in plan view was 2 mm 2 The thickness of the amorphous thin film in region C was 20 nm. The Si substrate on which the first electrode layer and the amorphous thin film were formed was subjected to RTA treatment in which it was heated in a nitrogen atmosphere at 700°C for 30 seconds. 0.48 Zr 0.48 Si 0.04The oxide with a composition of O2 changed from an amorphous state to a tetragonal crystalline structure exhibiting antiferroelectricity. This resulted in the formation of an antiferroelectric layer on the first electrode layer. A 100 nm-thick Au thin film was then formed on the antiferroelectric layer by vacuum deposition to obtain a second electrode layer. In this way, a capacitor according to the example was fabricated, equipped with an antiferroelectric layer containing three regions of different thicknesses.

[0085] [Comparative Example] A capacitor according to a comparative example was fabricated in the same manner as in the example, except that a metal mask was not inserted between the sputtering target and the first electrode layer in the deposition of the amorphous thin film. In the capacitor according to the comparative example, the area of ​​the antiferroelectric layer in a plan view was 4 mm. 2 This area was the same as the total area of ​​regions A, B, and C in the plan view of the antiferroelectric layer of the capacitor according to the example. In the capacitor according to the comparative example, the thickness of the antiferroelectric layer was 15 nm.

[0086] [evaluation] Polarization-Electric field measurements were performed on the capacitors according to the examples and comparative examples using a ferroelectric tester Premier II manufactured by Radiant Technology, Inc. Based on the measurement results, a graph was obtained showing the relationship between the polarization moment of each capacitor and the magnitude of the voltage applied between the first electrode layer and the second electrode layer.

[0087] FIG. 8 is a graph showing the relationship between the polarization moment of the capacitor and the magnitude of the voltage applied between the first electrode layer and the second electrode layer. FIG. 9 is a graph showing the relationship between the slope ΔP of the graph shown in FIG. 8 and the magnitude of the voltage applied between the first electrode layer and the second electrode layer. In FIG. 8, the vertical axis represents the polarization moment of the capacitor, and the horizontal axis represents the magnitude of the voltage applied between the first electrode layer and the second electrode layer. In FIG. 9, the vertical axis represents the slope of the graph shown in FIG. 8, and the horizontal axis represents the magnitude of the voltage applied between the first electrode layer and the second electrode layer.

[0088] 8 and 9, the slope ΔP of the graph shown in Fig. 8 for the capacitor according to the example does not vary significantly within a specific voltage range when the voltage applied between the first electrode layer and the second electrode layer varies between 0 V and 4 V. In other words, for the capacitor according to the example, the ratio of the change in polarization moment to a constant change in voltage applied between the first electrode layer and the second electrode layer does not vary significantly within the range of 0 V to 4 V.

[0089] Specifically, ΔP of the capacitor according to the example increases from 0.28 to 0.55 in the range from 0 V to 4 V and remains roughly constant in the range from 2.5 V to 4 V. On the other hand, in the capacitor according to the comparative example, the polarization moment increases exponentially as the voltage applied between the first electrode layer and the second electrode layer changes between 2.5 V and 4 V. Therefore, as shown in FIG. 9 , the slope of the graph shown in FIG. 8 for the capacitor according to the comparative example increases sharply in the voltage range from 3 V to 4 V. For the capacitor according to the example, the ΔP value fluctuates by only about 0.2 in the range from 2 V to 2.5 V and remains roughly constant in the range from 2.5 V to 4 V. On the other hand, for the capacitor according to the comparative example, the ΔP value fluctuates by about 0.5 in the range from 3 V to 4 V.

[0090] It is understood that in the capacitors according to the examples, the ratio of the change in polarization moment to a constant change in voltage applied between the electrodes is less likely to fluctuate significantly over a wide voltage range, compared to the capacitors according to the comparative examples. It is understood that in a capacitor having an antiferroelectric layer, the antiferroelectric layer has different thicknesses at multiple locations, making it possible to bring the relationship between the voltage between the electrodes of the capacitor and the amount of charge stored in the capacitor closer to a direct proportional relationship. [Industrial Applicability]

[0091] The capacitor of the present disclosure has a suppressed change in the dielectric constant throughout the antiferroelectric layer, which simplifies the design of the electrical circuit when incorporating the capacitor into the electrical circuit. Therefore, the capacitor of the present disclosure can be used in electronic devices such as smartphones and tablet terminals, electric vehicles including hybrid vehicles and plug-in hybrid vehicles, and energy storage systems combined with power generation devices such as solar cells and wind power generators.

Claims

1. a first electrode layer; A second electrode layer; an antiferroelectric layer disposed between the first electrode layer and the second electrode layer in a thickness direction of the first electrode layer, the first electrode layer covers the antiferroelectric layer on the inner side of the outermost portion of the first electrode layer in a plan view, the second electrode layer covers the antiferroelectric layer on the inner side of the outermost portion of the second electrode layer in a plan view, the antiferroelectric layer has different thicknesses at a plurality of locations; Capacitor.

2. The capacitor of claim 1 , wherein the antiferroelectric layer has a thickness of at least 10 nanometers and at most 1 micrometer.

3. 3. The capacitor according to claim 1, wherein a ratio of a maximum thickness of the antiferroelectric layer to a minimum thickness of the antiferroelectric layer is greater than 1 and less than 10.

4. 4. The capacitor according to claim 1, wherein the maximum thickness of the antiferroelectric layer is 500 nanometers or less.

5. The capacitor according to claim 1 , wherein the antiferroelectric layer has a thickness smaller than a thickness of the first electrode layer.

6. The capacitor according to claim 1 , wherein the antiferroelectric layer has a thickness smaller than a thickness of the second electrode layer.

7. The capacitor according to claim 1 , wherein the antiferroelectric layer has a thickness that changes continuously or stepwise in a specific direction in the plane.

8. 8. The capacitor according to claim 7, wherein the antiferroelectric layer has a thickness that changes continuously or stepwise from one end to the other end in a specific direction within the plane.

9. the antiferroelectric layer includes a first region having a minimum thickness and a predetermined area in a plan view, and a second region having a maximum thickness and a predetermined area in a plan view; a ratio of an area of ​​the second region in a plan view to an area of ​​the first region in a plan view is greater than 1 and less than 10; The capacitor according to any one of claims 1 to 8.

10. 10. The capacitor according to claim 1, wherein the antiferroelectric layer is formed between a pair of regions having different thicknesses and includes a connection portion having a step corresponding to the difference in thickness between the pair of regions.

11. 11. The capacitor according to claim 1, wherein the antiferroelectric layer is formed between a pair of regions having different thicknesses and includes a connection portion having a thickness that changes continuously or stepwise from one of the pair of regions to the other of the pair of regions.

12. the antiferroelectric layer includes a plurality of specific regions each having a specific thickness and a specific area in a plan view, the plurality of specific regions are arranged apart from one another when the antiferroelectric layer is viewed in plan from the second electrode layer side; The capacitor according to any one of claims 1 to 11.

13. The capacitor according to claim 12 , wherein the plurality of specific regions are regularly arranged when the antiferroelectric layer is viewed from the second electrode layer side in plan view.

14. The capacitor according to claim 12 or 13, wherein the plurality of specific regions are formed in the shape of a plurality of strips extending parallel to each other when the antiferroelectric layer is viewed in plan from the second electrode layer side.

15. The capacitor according to claim 12 or 13, wherein the plurality of specific regions are circular or rectangular when the antiferroelectric layer is viewed from the second electrode layer side in a plan view.

16. The capacitor of claim 1 , wherein the antiferroelectric layer includes a metal oxide having at least one of hafnium and zirconium.

17. Further comprising a support; the first electrode layer is disposed between the support and the antiferroelectric layer in a thickness direction of the first electrode layer; 17. The capacitor of claim 1.

18. The capacitor according to claim 17 , wherein the support has no void at a position corresponding to the antiferroelectric layer in a plan view.

19. An electric circuit comprising a capacitor according to any one of claims 1 to 18.

20. A circuit board comprising the capacitor according to any one of claims 1 to 18.

21. An electronic device comprising the capacitor according to any one of claims 1 to 18.

22. An electricity storage device comprising the capacitor according to any one of claims 1 to 18.

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