Integration techniques for micromachined pMUT arrays and electronics using thermocompression, eutectic, and solder bonding

Abstract

To provide methods of integrating piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) by using thermocompression or eutectic / solder bonding.SOLUTION: The present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, where the first substrate and the second substrate are bonded together using thermocompression, where any set of individual pMUTs of the pMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a single pMUT array and the second substrate comprising a single electrical circuit, where the first substrate and the second substrate are bonded together using eutectic or solder bonding, where any set of individual pMUTs of the pMUT array is addressable.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 62 / 671,361, filed May 14, 2018, which is incorporated by reference herein in its entirety. [Background technology]

[0002] Piezoelectric micromachined ultrasonic transducer (pMUT) arrays can provide advantages in ultrasound imaging due to their efficiency in converting between the electrical and acoustic energy domains. Specifically, pMUTs can provide significant advantages in imaging using drives of ≦10 V, thereby enabling direct connection to modern electronic nodes without intermediate electronics. By eliminating high-voltage drives and directly coupling circuitry to pMUT arrays, several advantages can be realized: reduction of expensive and bulky wiring, reduced noise, and reduced overall system cost, power, and / or size. Summary of the Invention

[0003] The present disclosure provides a method for integrating a micromachined piezoelectric micromachined ultrasonic transducer (pMUT) array with an application specific integrated circuit (ASIC) using thermocompression, eutectic or solder bonding.

[0004] The use of thermocompression bonding, eutectic bonding, or solder bonding can provide advantages for integration such as heterogeneous integration, low temperature, low resistance, high density, high yield interconnects, excellent adhesion performance, wafer-to-wafer, die-to-wafer, or die-to-die bonding, and environmental control between parts.

[0005] In one aspect, the present disclosure provides a device including a first substrate and a second substrate, the first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) array, and the second substrate including at least one electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression bonding, and wherein any set of one or more individual pMUTs of the at least one pMUT array is addressable.

[0006] In some embodiments, the pMUT array is configured to perform ultrasound imaging. In some embodiments, the at least one electrical circuit comprises an application specific integrated circuit (ASIC). In some embodiments, the bonding comprises wafer-to-wafer bonding. In some embodiments, the bonding comprises die-to-wafer bonding. In some embodiments, the die-to-wafer bonding uses an intermediate handle substrate and a temporary bonding layer. In some embodiments, the bonding comprises (a) temporarily bonding a wafer of the first substrate or the second substrate to a handle substrate using a temporary bonding layer; (b) dicing the wafer onto the handle substrate; and (c) bonding the diced wafer to another wafer of the first substrate or the second substrate using thermocompression bonding. In some embodiments, the bonding comprises die-to-die bonding. In some embodiments, thermocompression bonding is performed at a temperature of about 350°C or less. In some embodiments, thermocompression bonding is performed at a temperature of about 300°C or less. In some embodiments, the thermocompression bonding forms a hermetically sealed cavity configured to controllably maintain a gas species and pressure. In some embodiments, thermocompression bonding involves joining together two metals of the same type selected from the group consisting of gold (Au), copper (Cu) and aluminum (Al).

[0007] In another aspect, the present disclosure provides a method for manufacturing an integrated device, the method including: (a) obtaining a first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) array; (b) obtaining a second substrate including at least one electrical circuit; and (c) bonding the first substrate and the second substrate together using thermocompression bonding, wherein any set of one or more individual pMUTs of the at least one pMUT array is addressable.

[0008] In some embodiments, the pMUT array is configured to perform ultrasound imaging. In some embodiments, the at least one electrical circuit comprises an application specific integrated circuit (ASIC). In some embodiments, the bonding comprises wafer-to-wafer bonding. In some embodiments, the bonding comprises die-to-wafer bonding. In some embodiments, the die-to-wafer bonding uses an intermediate handle substrate and a temporary bonding layer. In some embodiments, the bonding comprises (a) temporarily bonding a wafer of the first substrate or the second substrate to a handle substrate using a temporary bonding layer; (b) dicing the wafer onto the handle substrate; and (c) bonding the diced wafer to another wafer of the first substrate or the second substrate using thermocompression bonding. In some embodiments, the bonding comprises die-to-die bonding. In some embodiments, thermocompression bonding is performed at a temperature of about 350°C or less. In some embodiments, thermocompression bonding is performed at a temperature of about 300°C or less. In some embodiments, the thermocompression bonding forms a hermetically sealed cavity configured to controllably maintain a gas species and pressure. In some embodiments, thermocompression bonding involves joining together two metals of the same type selected from the group consisting of gold (Au), copper (Cu) and aluminum (Al).

[0009] In another aspect, the present disclosure provides an apparatus including a first substrate and a second substrate, the first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) array, and the second substrate including at least one electrical circuit, wherein the first substrate and the second substrate are bonded together using a eutectic bond or a solder bond, and wherein any set of one or more individual pMUTs of the at least one pMUT array is addressable.

[0010] In some embodiments, the pMUT array is configured to perform ultrasound imaging. In some embodiments, the at least one electrical circuit comprises an application specific integrated circuit (ASIC). In some embodiments, the bonding comprises wafer-to-wafer bonding. In some embodiments, the bonding comprises die-to-wafer bonding. In some embodiments, the die-to-wafer bonding uses an intermediate handle substrate and a temporary bonding layer. In some embodiments, the bonding comprises: (a) temporarily bonding a wafer of the first substrate or the second substrate to a handle substrate using a temporary bonding layer; (b) dicing the wafer onto the handle substrate; and (c) bonding the diced wafer to another wafer of the first substrate or the second substrate using eutectic bonding or solder bonding. In some embodiments, the bonding comprises die-to-die bonding. In some embodiments, the eutectic bonding or solder bonding is performed at a temperature of about 350°C or less. In some embodiments, the eutectic bonding or solder bonding is performed at a temperature of about 300°C or less. In some embodiments, the eutectic or solder bond forms a hermetically sealed cavity configured to controllably maintain gas species and pressure. In some embodiments, one or both of the first and second substrates includes at least one feature for restricting the flow of melt in the eutectic or solder bond. In some embodiments, the eutectic or solder bond comprises a eutectic bond. In some embodiments, the eutectic bond comprises joining together a plurality of dissimilar metals selected from the group consisting of aluminum (Al), gold (Au), copper (Cu), germanium (Ge), indium (In), silicon (Si), and tin (Sn). In some embodiments, the plurality of dissimilar metals comprises Au-Si, Al-Ge, Au-Sn, Cu-Sn, or Au-In. In some embodiments, the eutectic or solder bond comprises a solder bond. In some embodiments, the solder joint comprises a joint using a solder alloy, the solder alloy comprising a plurality of different metals selected from the group consisting of silver (Ag), gold (Au), chromium (Cr), copper (Cu), germanium (Ge), indium (In), manganese (Mn), lead (Pb), silicon (Si), tin (Sn), and zinc (Zn).In some embodiments, the plurality of different metals comprises Au—Sn.

[0011] In another aspect, the present disclosure provides a method for manufacturing an integrated device, the method including: (a) obtaining a first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) array; (b) obtaining a second substrate including at least one electrical circuit; and (c) bonding the first substrate and the second substrate together using eutectic or solder bonding, wherein any set of one or more individual pMUTs in the at least one pMUT array is addressable.

[0012] In some embodiments, the pMUT array is configured to perform ultrasound imaging. In some embodiments, the at least one electrical circuit comprises an application specific integrated circuit (ASIC). In some embodiments, the bonding comprises wafer-to-wafer bonding. In some embodiments, the bonding comprises die-to-wafer bonding. In some embodiments, the die-to-wafer bonding uses an intermediate handle substrate and a temporary bonding layer. In some embodiments, the bonding comprises: (a) temporarily bonding a wafer of the first substrate or the second substrate to a handle substrate using a temporary bonding layer; (b) dicing the wafer onto the handle substrate; and (c) bonding the diced wafer to another wafer of the first substrate or the second substrate using eutectic bonding or solder bonding. In some embodiments, the bonding comprises die-to-die bonding. In some embodiments, the eutectic bonding or solder bonding is performed at a temperature of about 350°C or less. In some embodiments, the eutectic bonding or solder bonding is performed at a temperature of about 300°C or less. In some embodiments, the eutectic or solder bond forms a hermetically sealed cavity configured to controllably maintain gas species and pressure. In some embodiments, one or both of the first and second substrates includes at least one feature to restrict the flow of melt in the eutectic or solder bond. In some embodiments, the eutectic or solder bond comprises a eutectic bond. In some embodiments, the eutectic bond comprises joining a plurality of dissimilar metals selected from the group consisting of aluminum (Al), gold (Au), copper (Cu), germanium (Ge), indium (In), silicon (Si), and tin (Sn). In some embodiments, the plurality of dissimilar metals comprises Au-Si, Al-Ge, Au-Sn, Cu-Sn, or Au-In. In some embodiments, the eutectic or solder bond comprises a solder bond. In some embodiments, the solder joint comprises a joint using a solder alloy, the solder alloy comprising a plurality of different metals selected from the group consisting of silver (Ag), gold (Au), chromium (Cr), copper (Cu), germanium (Ge), indium (In), manganese (Mn), lead (Pb), silicon (Si), tin (Sn), and zinc (Zn).In some embodiments, the plurality of different metals comprises Au—Sn.

[0013] Further aspects and advantages of the present disclosure will become readily apparent to those skilled in the art from the following detailed description. This description shows and describes only exemplary embodiments of the present disclosure. As will be understood, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0014] Incorporation by Reference All publications, patents, and patent applications mentioned herein are incorporated by reference to the same extent as if each individual publication, patent, and patent application was specifically and individually indicated to be incorporated by reference. To the extent that a publication, patent, or patent application incorporated by reference conflicts with a disclosure contained herein, the present specification is intended to supersede and / or take precedence over any such conflicting text. [Brief explanation of the drawings]

[0015] The novel features of the invention are set forth with particularity in the appended claims. A better understanding of the features and advantages of the invention will be obtained by reference to the following detailed description which sets forth illustrative embodiments, in which the principles of the invention are utilized and in which the accompanying drawings (also "FIG" and "FIG") show: [Figure 1A] FIG. 1A shows a "junction zone" according to a disclosed embodiment; [Figure 1B] FIG. 1B shows a "junction zone" according to a disclosed embodiment; [Figure 1C] FIG. 1C shows a "junction zone" according to a disclosed embodiment; [Figure 2-1]FIG. 2A illustrates ASIC planarization for thermocompression or eutectic / solder bonding according to disclosed embodiments; FIG. 2B illustrates ASIC planarization for thermocompression or eutectic / solder bonding according to disclosed embodiments; FIG. 2C illustrates ASIC planarization for thermocompression or eutectic / solder bonding according to disclosed embodiments; [Figure 2-2] FIG. 2D illustrates ASIC planarization for thermocompression or eutectic / solder bonding according to disclosed embodiments; FIG. 2E illustrates ASIC planarization for thermocompression or eutectic / solder bonding according to disclosed embodiments; [Figure 3] FIG. 3A illustrates ASIC preparation for thermo-compression bonding according to disclosed embodiments; FIG. 3B illustrates ASIC preparation for thermo-compression bonding according to disclosed embodiments; FIG. 3C illustrates ASIC preparation for thermo-compression bonding according to disclosed embodiments; [Figure 4] FIG. 4A shows a pMUT array wafer preparation for thermocompression bonding and eutectic / solder bonding according to a disclosed embodiment; FIG. 4B shows a pMUT array wafer preparation for thermocompression bonding and eutectic / solder bonding according to a disclosed embodiment; FIG. 4C shows a pMUT array wafer preparation for thermocompression bonding and eutectic / solder bonding according to a disclosed embodiment; [Figure 5] FIG. 5A illustrates thermo-compression wafer-to-wafer bonding of a pMUT array and an ASIC according to disclosed embodiments; FIG. 5B illustrates thermo-compression wafer-to-wafer bonding of a pMUT array and an ASIC according to disclosed embodiments; [Figure 6] FIG. 6A illustrates singulation of a wafer of pMUTs and ASICs bonded using thermo-compression bonding, according to disclosed embodiments; FIG. 6B illustrates singulation of a wafer of pMUTs and ASICs bonded using thermo-compression bonding, according to disclosed embodiments; [Figure 7] FIG. 7A shows ASIC preparation for eutectic / solder bonding according to disclosed embodiments; FIG. 7B shows ASIC preparation for eutectic / solder bonding according to disclosed embodiments; FIG. 7C shows ASIC preparation for eutectic / solder bonding according to disclosed embodiments; [Figure 8]FIG. 8A illustrates a eutectic / solder wafer-to-wafer bond between a pMUT array and an ASIC according to a disclosed embodiment; FIG. 8B illustrates a eutectic / solder wafer-to-wafer bond between a pMUT array and an ASIC according to a disclosed embodiment; [Figure 9] FIG. 9A illustrates the singulation of a wafer of pMUTs and ASICs bonded by eutectic / solder bonding according to a disclosed embodiment; FIG. 9B illustrates the singulation of a wafer of pMUTs and ASICs bonded by eutectic / solder bonding according to a disclosed embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Piezoelectric micromachined ultrasonic transducer (pMUT) arrays can provide advantages in ultrasound imaging due to their efficiency in converting between the electrical and acoustic energy domains. Specifically, pMUTs can provide significant advantages in imaging using drives of ≦10 V, thereby enabling direct connection to modern electronic nodes without intermediate electronics. By eliminating high-voltage drives and directly coupling circuitry to pMUT arrays, several advantages can be realized: reduction of expensive and bulky wiring, reduced noise, and reduced overall system cost, power, and / or size.

[0017] Piezoelectric materials and devices can face challenges due to their Curie temperature (Tc). The Tc of a piezoelectric material can vary depending on the specific material, but generally falls within a range between 80°C and 400°C. At temperatures below the Tc of a piezoelectric material, the material can exhibit ferroelectric properties, meaning that the piezoelectric material has asymmetry in its unit cell. Such asymmetry can cause the charge component ions to separate, creating dipoles (e.g., a center of positive charge can be displaced from a center of negative charge). The dipoles can form regions where the dipoles all point in the same direction. Generally, each crystal can have multiple regions, each with a dipole moment at 180 degrees or 90 degrees relative to adjacent regions. Regions separated by crystal boundaries can assume any relative orientation. Poling can essentially align the dipoles of regions within a crystal and of different crystals in a single direction.

[0018] At temperatures above the Curie temperature (Tc) of a piezoelectric material, the piezoelectric material may have dielectric properties, meaning that the piezoelectric material loses its piezoelectric effect. This can result from a phase change in the unit cell of the piezoelectric material from an asymmetric unit cell with respect to charge to a symmetric unit cell. In other words, at temperatures below Tc, the unit cell has a dipole moment; whereas, at temperatures above Tc, the unit cell does not have a dipole moment. For example, lead zirconate titanate (Pb[Zr x Ti 1-x ]O3, PZT) is a piezoelectric material that can change phase from a rhombohedral and tetragonal unit cell, which has a dipole moment, to a cubic unit cell, which has no dipole moment, when subjected to a temperature change from below Tc to above Tc.

[0019] In such situations, the piezoelectric effect of the material may be restored by returning the piezoelectric material to a temperature below Tc. However, films of piezoelectric material may become dipolarized, thereby reducing their effectiveness as piezoelectric materials. In other words, instead of the ferroelectric regions of the piezoelectric material being essentially aligned in the same direction, the ferroelectric regions may be randomly aligned or only partially aligned. Poling the piezoelectric material may be necessary to restore the piezoelectric material to its optimal performance. Furthermore, repeated or prolonged exposure of piezoelectric materials to temperatures above Tc may lead to degradation of their piezoelectric performance.

[0020] Recognizing the need for improved methods for the integration of piezoelectric devices, the present disclosure provides a method for integrating micromachined piezoelectric micromachined ultrasonic transducer (pMUT) arrays with application specific integrated circuits (ASICs) using thermocompression bonding, eutectic bonding, or solder bonding at the wafer level.

[0021] Thermocompression bonding is also sometimes called diffusion bonding, pressure bonding, and solid-state or thermocompression welding. Thermocompression bonding may involve contacting two similar metals and applying pressure and heat. Atoms then exchange between the metals through intermolecular diffusion, thereby forming a stable bond. For thermocompression bonding, appropriate metals can be selected, such as high-diffusion metals like gold (Au), copper (Cu), and aluminum (Al). Each metal may require a different temperature for thermocompression bonding. For example, Cu and Al generally require thermocompression bonding temperatures above 350°C, while Au-Au thermocompression bonding can be performed at temperatures as low as 260°C. Thermocompression bonding using Cu and Al may also require additional preparation to eliminate interface chemistry; on the other hand, Au is more inert and may not require as much surface preparation for thermocompression bonding.

[0022] Thermocompression bonding advantageously avoids the challenges associated with the occurrence of "squeezing" because no liquid is generated during the process, and the bonding liquid can be transported away from the bonding site by capillary action. Thus, bonds formed by thermocompression bonding are sufficiently stable to reheating and may essentially not change shape with changes in temperature unless the melting point of the metal is reached.

[0023] Eutectic bonding can refer to the process of bringing two dissimilar materials into contact and applying pressure and heat to the two materials. Consider two materials, material 1 and material 2, whose melting temperatures are T m1 and T m2 Assuming that, then T m1 <T m2 As a result, thermodynamically, any mixture of two materials will have a temperature of T m2 The eutectic temperature Te can be defined as the lowest temperature of the two material systems. The eutectic temperature is lower than the other two melting points, i.e., Te <T m1 <T m2 During eutectic bonding, the temperature may be raised to a point slightly above Te. A molten alloy may be produced, which may have properties based on the temperature of the bond. The eutectic bonding process may continue until a stable alloy mixture is achieved at the bonding temperature. The eutectic bond may be prone to squeezing and may change properties if the temperature is allowed to reach or exceed the bonding temperature. Common material systems used in eutectic bonding include Au-Si, Al-Ge, Au-Sn, Cu-Sn, and Au-In. For example, Au-Sn, Cu-Sn, and Au-In may have eutectic temperatures below 300°C.

[0024] Solder joining can refer to the process of placing a low-fusible alloy between two surfaces and heating it to form a bond. Typical solder alloys can contain two or more of the following materials: silver (Ag), gold (Au), chromium (Cr), copper (Cu), germanium (Ge), indium (In), manganese (Mn), lead (Pb), silicon (Si), tin (Sn), and zinc (Zn). Solder alloys can be configured to melt at eutectic or non-eutectic temperatures. Therefore, eutectic bonding can be considered a subset of solder joining. Solder alloys may be selected to be suitable for temperatures below 300°C. During solder joining, a liquid forms, and the joint may become more susceptible to squeezing. During squeezing, the solder joint may backflow if the temperature approaches the alloy melting temperature, thereby making the joint more unstable. Typical solder joints may contain Au-Sn, which can form a eutectic bond with the correct alloy ratios.

[0025] In this disclosure, eutectic and solder joints may be referred to as "eutectic / solder joints." Eutectic / solder joints may advantageously require less force and lower temperatures compared to thermocompression bonds. However, both eutectic and solder joints are subject to challenges from compression and may produce less stable joints than thermocompression bonds.

[0026] The use of thermocompression bonding, eutectic bonding, or solder bonding can provide advantages for integration including heterogeneous integration, low temperature, low resistance, high density, high yield interconnects, excellent adhesion performance, wafer-to-wafer, die-to-wafer, or die-to-die bonding, and environmental control between parts, and high temperature stability.

[0027] For example, the use of thermocompression bonding, eutectic bonding, or solder bonding to perform the integration of electronics with micromachined pMUT arrays may enable heterogeneous integration by bonding and interconnecting two single dies fabricated using different process technologies. Using the methods of the present disclosure, various electronics may be integrated into microelectromechanical systems (MEMS) components.

[0028] As another example, the use of thermocompression bonding, eutectic bonding, or solder bonding to integrate electronics with micromachined pMUT arrays may be performed at low temperatures. For example, gold-gold (Au-Au) thermocompression bonding may be performed at temperatures below 300°C. Most solder alloys have melting temperatures at or below about 300°C. Specifically, performing the integration of electronics with pMUT arrays at low temperatures may advantageously maintain the reliability of the pMUT arrays.

[0029] As another example, the use of thermocompression, eutectic, or solder joints to integrate the micromachined pMUT array with the electronics may provide low resistance. To reduce noise and parasitic power, an interconnect method with a low resistance of less than about 1 ohm (Ω) may be selected. Thermocompression, eutectic, and solder joints all typically utilize metals or metal-based alloys (e.g., Au—Si), thereby creating an integrated structure with interconnect resistances much lower than 1 ohm (Ω).

[0030] As another example, the use of thermocompression, eutectic, or solder bonding to integrate micromachined pMUT arrays with electronics may provide high-density and high-yield interconnects. Thermocompression, eutectic, and solder bonding all maintain interconnect pitches of less than 100 microns (μm), thus enabling the interconnection of dense arrays of devices with electronics, such as may be necessary to fabricate transducer arrays formed for ultrasound imaging. The density of interconnects using thermocompression bonding may be primarily limited by control of interconnect height based on plating and / or sputter stacking. The yield of interconnects using thermocompression bonding may similarly be limited by control of interconnect height based on plating. If the interconnect height is controlled, the interconnect yield may be dominated by defect density. The density of interconnects using eutectic / solder bonding may be primarily limited by squeezing, and control must include squeezing. Such control may affect the design and performance of the bonded devices.

[0031] As another example, the use of thermocompression, eutectic, or solder joints to perform the integration of micromachined pMUT arrays with electronics may provide superior adhesive performance. Because thermocompression, eutectic, and solder joints are metal-based, each of the joints has the potential to be hermetic with high mechanical stability.

[0032] As another example, the use of thermocompression bonding, eutectic bonding, or solder bonding to perform the integration of micromachined pMUT arrays and electronics may enable a variety of bonding types, including wafer-to-wafer bonding, die-to-wafer bonding, and die-to-die bonding. For example, die-to-wafer bonding or die-to-die bonding may be performed to allow bonding of known-good die only for higher yields, while wafer-to-wafer bonding may be performed with higher throughput and lower cost.

[0033] As another example, the use of thermocompression, eutectic, or solder bonding to effect the integration of micromachined pMUT arrays and electronics may allow for environmental control between parts. For example, thermocompression, eutectic, and solder bonding may all allow for the construction of closed cavities where the cavity environment can be controlled in terms of gas species and pressure. For example, gas species and pressure may be adjusted for optimal imager performance.

[0034] As another example, the use of thermocompression, eutectic, or solder bonding to integrate micromachined pMUT arrays with electronics may provide high-temperature stability. Because thermocompression bonding may rely on solid-state diffusion of atoms across the bonding interface without the formation of a liquid, thermocompression bonding may be particularly insensitive to high temperatures and pressures. As a result, thermocompression bonds may be further subjected to one or many temperature excursions up to and above the bonding temperature without substantially altering the thermocompression bond. Indeed, thermocompression bonds can remain stable up to the melting temperature of the bonding materials (e.g., 1064°C for Au-Au thermocompression bonding). Eutectic and solder bonding may leave unreacted material, and subsequent temperature excursions may result in changes to the eutectic / solder bond. Therefore, thermocompression bonding may be a preferred bonding method if the system can tolerate the process conditions (e.g., temperature and pressure) required to perform thermocompression bonding.

[0035] The present disclosure provides methods for bonding piezoelectric micromachined ultrasonic transducer (pMUT) arrays to electronics (e.g., application-specific integrated circuits (ASICs)) using thermocompression bonding, eutectic bonding, or solder bonding to form a dense array of conductive bonds. These techniques may be described in embodiments involving wafer-to-wafer bonding methods. Wafer-to-wafer bonding offers the advantage of providing the ability to rapidly bond large numbers of components while minimizing extra steps, thereby resulting in higher batch processing throughput and lower cost of integration. Such production advantages can be significant for high volume and / or low cost. Wafer-to-wafer bonding can also present the following potential challenges: 1) combined yield of pMUT array wafers and ASIC wafers; 2) alignment tolerances within the substrates; and 3) the need to design pMUT wafers and ASIC wafers so that the die sizes precisely match, resulting in wasted wafer area.

[0036] In other embodiments, integration methods using thermocompression bonding, eutectic bonding, and solder bonding may be applicable to die-to-wafer bonding and die-to-die bonding. Die-to-wafer bonding using thermocompression or eutectic / solder bonding offers the advantage of providing the ability to bond known-good die (KGD), thereby reducing or eliminating challenges associated with yield synthesis between the ASIC die and the pMUT die. This can be accomplished by placing only the KGD pMUT die on a handle wafer above the KGD ASIC die. Die-to-wafer bonding using thermocompression or eutectic / solder bonding can present potential challenges, such as the need for precise handling of the thinned die when attaching it to the handle wafer and the need for precision pick-and-place equipment for this process. Such constraints can limit the throughput of the die-to-wafer bonding method, thereby increasing manufacturing costs.

[0037] Die-to-die bonding using thermocompression or eutectic / solder bonding may offer the advantage of providing the capability to bond ASIC die and pMUT die of different sizes. Furthermore, similar to die-to-wafer bonding using thermocompression or eutectic / solder bonding, die-to-die bonding using thermocompression or eutectic / solder bonding may offer the advantage of providing the capability to bond only known-good die (KGD), thereby reducing or eliminating issues associated with yield synthesis between ASIC die and pMUT die. This can be accomplished by integrally bonding only KGD ASIC die and KGD pMUT die.

[0038] Die-to-die bonding using thermocompression or eutectic / solder bonding can present potential challenges due to the need for precise handling of the thinned die during bonding and the need for die-to-die bonding equipment for this process. Furthermore, only pairs of ASIC die and pMUT die can be bonded at a time. Such constraints can limit the throughput of die-to-die bonding methods using thermocompression or eutectic / solder bonding, thereby increasing manufacturing costs.

[0039] The integration technique may be selected from among wafer-to-wafer bonding, die-to-wafer bonding, and die-to-die bonding using thermocompression or eutectic / solder bonding based at least in part on factors including specific cost targets, area limitations, and yield of a given integration process.

[0040] Through the implementation of the disclosed methods, a pMUT (piezoelectric micromachined ultrasonic transducer) array can be bonded to an ASIC (application-specific integrated circuit) using thermo-compression bonding or eutectic / solder bonding to form a dense array of conductive bonds, according to various embodiments. In some embodiments, bonding may include wafer-to-wafer bonding using thermo-compression bonding. In some embodiments, bonding may include wafer-to-wafer bonding using eutectic / solder bonding. In some embodiments, bonding may include die-to-wafer bonding using thermo-compression bonding. In some embodiments, bonding may include die-to-wafer bonding using eutectic / solder bonding. In some embodiments, bonding may include die-to-die bonding using thermo-compression bonding. In some embodiments, bonding may include die-to-die bonding using eutectic / solder bonding. As shown in FIG. 6B , the end result of the bonding process may involve a pMUT die (201) bonded to an ASIC die (101) using one or more sets of conductive bonds (302).

[0041] In one aspect, a method for manufacturing an integrated device may include obtaining a first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) device. The pMUT device may be configured to perform ultrasound imaging (e.g., using one or more pMUT transducer arrays). The method for manufacturing the integrated device may include obtaining a second substrate including at least one electrical circuit. The electrical circuit may include an application specific integrated circuit (ASIC). The method for manufacturing the integrated device may include integrally bonding the first substrate and the second substrate using thermocompression bonding, wherein any set of one or more individual pMUTs of the at least one pMUT array is addressable.

[0042] In another aspect, a method for manufacturing an integrated device may include obtaining a first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) device. The pMUT device may be configured to perform ultrasound imaging (e.g., using one or more pMUT transducer arrays). The method for manufacturing the integrated device may include obtaining a second substrate including at least one electrical circuit. The electrical circuit may include an application specific integrated circuit (ASIC). The method for manufacturing the integrated device may include integrally bonding the first substrate and the second substrate using eutectic or solder bonding, wherein any set of one or more individual pMUTs of the at least one pMUT array is addressable.

[0043] Thermocompression bonding, eutectic bonding, or solder bonding may involve integrally joining a first substrate and a second substrate using a set of one or more conductive bonding posts. The conductive bonding posts may comprise an intermetallic compound. The conductive bonding posts may have heights of at least about 1,000 μm, at least about 500 μm, at least about 100 μm, at least about 90 μm, at least about 80 μm, at least about 70 μm, at least about 60 μm, at least about 50 μm, at least about 40 μm, at least about 30 μm, at least about 20 μm, at least about 10 μm, at least about 5 μm, at least about 4 μm, at least about 3 μm, at least about 2 μm, or at least about 1 μm, and increments therein. The conductive bonding posts may have lateral dimensions between about 10 μm and about 100 μm. For example, the conductive junction posts may have lateral dimensions of at least about 1,000 μm, at least about 500 μm, at least about 100 μm, at least about 90 μm, at least about 80 μm, at least about 70 μm, at least about 60 μm, at least about 50 μm, at least about 40 μm, at least about 30 μm, at least about 20 μm, at least about 10 μm, at least about 5 μm, at least about 4 μm, at least about 3 μm, at least about 2 μm, or at least about 1 μm, and increments thereof.

[0044] Thermocompression bonding, eutectic bonding, or solder bonding may involve joining the first and second substrates together using a set of one or more conductive receiver pads or posts. The conductive receiver pads or posts may have heights of at least about 1,000 μm, at least about 500 μm, at least about 100 μm, at least about 90 μm, at least about 80 μm, at least about 70 μm, at least about 60 μm, at least about 50 μm, at least about 40 μm, at least about 30 μm, at least about 20 μm, at least about 10 μm, at least about 5 μm, at least about 4 μm, at least about 3 μm, at least about 2 μm, or at least about 1 μm, and increments therein. The conductive receiver pads or posts may have lateral dimensions between about 10 μm and about 100 μm. For example, the conductive receiver pads or posts may have lateral dimensions of at least about 1,000 μm, at least about 500 μm, at least about 100 μm, at least about 90 μm, at least about 80 μm, at least about 70 μm, at least about 60 μm, at least about 50 μm, at least about 40 μm, at least about 30 μm, at least about 20 μm, at least about 10 μm, at least about 5 μm, at least about 4 μm, at least about 3 μm, at least about 2 μm or at least about 1 μm, and increments thereof.

[0045] Thermocompression bonding, eutectic bonding, or solder bonding may be performed at temperatures of about 400°C or less, about 390°C or less, about 380°C or less, about 370°C or less, about 360°C or less, about 350°C or less, about 340°C or less, about 330°C or less, about 320°C or less, about 310°C or less, about 300°C or less, about 290°C or less, about 280°C or less, about 270°C or less, about 260°C or less, about 250°C or less, about 240°C or less, about 230°C or less, about 220°C or less, about 210°C or less, or about 200°C or less, and increments therebetween.

[0046] 1A, 1B, and 1C illustrate a "bonding zone" according to disclosed embodiments. Thermocompression bonding, eutectic bonding, and solder bonding may require only relatively small variations in the height of the "bonding zone." The bonding zone can be defined as a volume with a top surface defined by the plane imprinted by the bonding point of the top wafer and a bottom surface defined by the plane imprinted by the bonding point of the bottom wafer. For example, consider the typical case illustrated in FIG. 1A. Here, the top bonding fixture (290) and bottom bonding fixture (190) are assumed to be perfectly planar, and the pMUT wafer (200) and ASIC wafer (110) have negligible (or zero) total thickness variation (TTV). Furthermore, the conductive bonding posts (312) and conductive receiver pads / posts (311) are assumed to be uniform in thickness. In this case, the bonding zone (320) is represented as a cylinder the diameter of the wafer, with no thickness variation. This is an ideal (or perfect) bonding zone. It is noted that in this example the actual thickness of the bond zone is inconsequential and is arbitrarily defined by the choice of coordinate system.

[0047] Two major sources of bond zone thickness variation can include the overall thickness variation (TTV) of the incoming wafer and variations in the height of the bond posts. For example, an ASIC wafer with a TTV (111) is shown in Figure 1B. In other cases, the bond fixtures (190 and 290) are assumed to be perfectly horizontal, the pMUT wafer (200) has no TTV, and the bond posts (311 and 312) are assumed to be perfectly uniform. In this case, a non-ideal bond zone (321) is created. Similarly, as shown in Figure 1C, if the conductive receiver pads / posts are not uniform in height (313), and all other components are assumed to be perfectly horizontal, have zero TTV, and are uniform in height, an inconsistent bond zone (322) can similarly result.

[0048] Specifications for allowable or acceptable thickness variations on the bond zone can be difficult to define because such bond zone thickness variations can depend on many factors, including bonding equipment, pressure, temperature, wafer TTV, bonding material ductility, contact size, wafer and material compliance, etc. Bond zone thickness variations can be more significant for integration methods that use thermo-compression bonding, which may require intimate contact of solid surfaces. Application of good bonding force can overcome some local bond zone thickness variations, but is often limited to a few hundred nanometers or less.

[0049] A eutectic or solder joint may be tolerant or tolerate thickness variations on the bond zone because a liquid or conformal paste may be created during the bonding process. The liquid or conformal paste may deform to overcome a higher degree of local bond zone thickness variation to produce a solid bond. Tolerant or acceptable local bond zone thickness variation is difficult to define but may be approximately 1 micron overall.

[0050] Given the relatively strict requirements regarding tolerance for thickness variations in the junction zone, one or both of the incident wafers may be planarized. The planarization process is illustrated in Figures 2A, 2B, 2C, 2D, and 2E for an ASIC wafer (100). In this representative example, the ASIC wafer (100) has an incident TTV represented by the top metal (101). The source of the TTV can arise not only from the physical top metal of the ASIC wafer, but also from wafer TTV and film variations. However, for illustrative purposes, in this example, the top metal (101) may represent all of the various TTV components. To planarize the wafer, a thick dielectric material (102), such as TEOS, is deposited on top of the wafer, as shown in Figure 2B. From Figure 2B to Figure 2C, the top surface undergoes chemical-mechanical polishing (CMP) to reduce local thickness variations and create a planar top surface (which may be planar with respect to incident height variations). Contacts may then be opened in the thick dielectric material (102) and connecting conductors (103) deposited and patterned to result in the structure shown in Figure 2D. The connecting conductors (103) may provide a flat surface on the contact side for a good quality thermocompression, eutectic or solder bond, as shown in Figure 2E.

[0051] Additionally, this form of planarization can also be applied to the pMUT wafer (200). However, by doing so, the mechanical dynamics of the pMUT array may be altered. Adding such planarization will be apparent to those skilled in the art of microfabrication after consideration of Figures 2A, 2B, 2C, 2D, and 2E. Careful design of the pMUT wafer (200) and / or the ASIC wafer (100) can eliminate the need for planarization. For illustrative purposes, the pMUT wafer (200) may be assumed to be a design that does not require planarization, while the ASIC wafer (100) may be assumed to be a design that does require planarization.

[0052] After sufficient planarization of the incident wafers to allow wafer-to-wafer bonding, the planarized incident wafers may be bonded together using thermocompression bonding or eutectic / solder bonding, as described in the following embodiments.

[0053] Wafer-to-wafer bonding using thermocompression bonding In embodiments, integration of the pMUT array wafer and the ASIC wafer may include wafer-to-wafer bonding using thermocompression bonding. Figures 3A, 3B, and 3C illustrate ASIC preparation for thermocompression bonding, according to disclosed embodiments. As shown in the cross-sectional views of Figures 3A through 3B, a set of one or more conductive contact posts (300) are deposited and patterned on the ASIC stack of Figure 2D, which includes the ASIC wafer (100), top metal (101), planarized thick dielectric material (102), and connecting conductors (103). Deposition and patterning of the conductive contact posts (300) can be performed by a deposition and etch-back process, or can be plated using a mold such as a photosensitive resist ("photoresist").

[0054] The conductive bonding posts (300) can be formed using any configuration of materials so long as 1) the posts are conductive (e.g., made from one or more conductive materials) and 2) the top surface includes the target thermocompression material to be bonded. For example, for gold-gold (Au-Au) thermocompression bonding, the conductive bonding posts (300) may be formed from a gold alloy, or may include a copper (Cu) base with gold attached, or a nickel (Ni) base with gold attached and an external gold cap. The conductive bonding posts (300) can have any suitable height and array configuration. After the conductive bonding posts (300) are formed, the substrate can be thinned as needed, as shown in the cross-sectional views of Figures 3B-3C. For example, a backside thinning process can be used to thin the backside of the ASIC wafer (100) to the desired thickness.

[0055] 4A, 4B, and 4C illustrate a pMUT array wafer preparation for thermocompression bonding and eutectic / solder bonding according to disclosed embodiments. As shown in the cross-sectional views of FIGS. 4A through 4B, a set of one or more conductive receiver pads or pillars (301) are deposited and patterned on the pMUT wafer (200) containing the pMUT array, or plated using a mold such as photoresist. The conductive receiver pads or pillars (301) can be formed as the pMUT wafer is fabricated.

[0056] Similar to the conductive bond pillars (300) on the ASIC wafer, the conductive receiver pads or pillars (301) can be formed using any configuration of materials, so long as 1) the pillars are conductive (e.g., made from one or more conductive materials) and 2) the top surface includes the target thermocompression material to be bonded. For example, for gold-gold (Au-Au) thermocompression bonding, the conductive receiver pads or pillars (301) may be formed from a gold alloy, or may include a copper (Cu) base with gold attached, or a nickel (Ni) base with gold attached and an external gold cap. The conductive receiver pads or pillars (301) can have any suitable height and array configuration. After the conductive receiver pads or pillars (301) are formed, the substrate can be thinned as needed, as shown in the cross-sectional views of Figures 4B-4C. For example, a backside thinning process can be used to thin the backside of the pMUT wafer (200) to the desired thickness.

[0057] Figures 5A and 5B illustrate thermocompression wafer-to-wafer bonding of a pMUT array and an ASIC according to disclosed embodiments. After forming conductive contact posts (300) on the ASIC wafer (100) and conductive receiver posts or pads (301) on the pMUT wafer (200), the pMUT wafer (200) is inverted and aligned with the ASIC wafer stack (100, 101, 102, 103, and 300), or vice versa, as shown in the cross-sectional views of Figures 5A and 5B. The two wafers are aligned together, and the manufacturing atmosphere conditions (e.g., gas, temperature, and / or pressure) are adjusted as needed to bring the wafers into contact. Pressure is applied to the contacting wafers to form sufficient intimate contact to promote bonding. As shown in the cross-sectional views of Figures 5A and 5B, the wafers are brought to an appropriate temperature for the conductive bond posts (300) and conductive receiver pads or posts (301) to form a solid conductive bond (302) using a thermocompression bonding process. After a solid conductive bond is formed between the two wafers, the wafer stack can be further processed as needed. For example, the pMUT wafer (200) can be further thinned, if desired. For example, a backside thinning process may be used to thin the backside of the pMUT wafer (200) to a desired thickness.

[0058] 6A and 6B illustrate the singulation of pMUT and ASIC wafers bonded using thermo-compression bonding, according to disclosed embodiments. After a solid conductive bond is formed between the two wafers, the wafers are sequentially singulated. By way of example, FIG. 6A illustrates the pMUT wafer (200) of FIG. 5B being singulated to produce a plurality of pMUT dice (201). Subsequently, in FIGS. 6A-6B, the ASIC wafer (100) is singulated to produce a plurality of ASIC dice (101), thereby completing the wafer-to-wafer bonding method using thermo-compression bonding and achieving the desired bonding configuration.

[0059] In some embodiments, thermocompression bonding involves joining two metals of the same type selected from the group consisting of gold (Au), copper (Cu), and aluminum (Al).

[0060] It will be appreciated that one skilled in the art can use alternatives to metal construction for bonding. In the case of Au-Au thermocompression bonding, the process temperature can be reduced to below 300°C, thereby making the bonding process compatible with many piezoelectric materials, such as pMUT arrays.

[0061] Wafer-to-wafer bonding using eutectic or solder bonding In embodiments, integration of the pMUT array wafer and the ASIC wafer may include wafer-to-wafer bonding using eutectic or solder bonding. Figures 7A, 7B, and 7C illustrate ASIC preparation for eutectic / solder bonding, according to disclosed embodiments. As shown in the cross-sectional views of Figures 7A-7B, a set of one or more conductive contact posts (303) with solder is deposited and patterned on the ASIC stack of Figure 2D, which includes the ASIC wafer (100), top metal (101), planarized thick dielectric material (102), and connecting conductors (103). Deposition and patterning of the conductive contact posts (303) can be performed by a deposition and etch-back process, or can be plated using a mold such as photoresist. Alternatively, for larger conductive contact posts (303), screen printing can be used to deposit and pattern the conductive contact posts (303).

[0062] The soldered conductive joint posts (303) can be formed using any configuration of materials so long as 1) the posts are conductive (e.g., made from one or more conductive materials) and 2) the top surface contains the target solder material being used. For example, for gold-tin (Au-Sn) solder, the soldered conductive joint posts (303) may include a gold (Au) base with a thinner layer of tin (Sn) attached, or a copper (Cu) base with thin layers of gold (Au) and tin (Sn) attached (e.g., single or multiple layers of each). The soldered conductive joint posts (303) can have any suitable height and array configuration. After the soldered conductive joint posts (303) are formed, the substrate can be thinned as needed, as shown in the cross-sectional views of Figures 7B-7C. For example, a backside thinning process can be used to thin the backside of the ASIC wafer (100) to the desired thickness.

[0063] The pMUT array wafer can be prepared for eutectic / solder bonding in a manner similar to that used for thermocompression bonding. As shown in the cross-sectional views of Figures 4A-4B, a set of one or more conductive receiver pads or pillars (301) are deposited and patterned on the pMUT wafer (200) containing the pMUT array, or plated using a mold such as photoresist. After the conductive receiver pads or pillars (301) are formed, the substrate can be thinned as needed, as shown in the cross-sectional views of Figures 4B-4C. For example, a backside thinning process may be used to thin the backside of the pMUT wafer (200) to the desired thickness.

[0064] For eutectic / solder bonding, the conductive receiver pad or pillar (301) can be formed using any configuration of materials, such that: 1) the pillar is conductive (e.g., made from one or more conductive materials). The conductive receiver pad or pillar (301) can include, for example, gold (Au), copper (Cu), nickel (Ni), or aluminum (Al). Alternatively, the conductive receiver pad or pillar (301) can include a conductive material, such as a semiconductor, for example, polysilicon (poly-Si) or polygermanium (poly-Ge). Optionally, solder can be added to the top of the conductive receiver pad / pillar (301).

[0065] Figures 8A and 8B illustrate eutectic / solder wafer-to-wafer bonding of a pMUT array to an ASIC according to disclosed embodiments. After forming conductive contact posts (300) on the ASIC wafer (100) and conductive receiver posts or pads (301) on the pMUT wafer (200), the pMUT wafer (200) is inverted and aligned to the ASIC wafer stack (100, 101, 102, 103, and 303), or vice versa, as shown in the cross-sectional views of Figures 8A and 8B. The two wafers are aligned together, and the manufacturing atmosphere conditions (e.g., gas, temperature, and / or pressure) are adjusted as needed to bring the wafers into contact. Pressure is applied to the contacting wafers to form sufficient intimate contact to promote bonding. As shown in the cross-sectional views of Figures 8A and 8B, the wafers are brought to a suitable temperature for the soldered conductive bond posts (303) and conductive receiver pads or posts (301) to form a solid conductive bond (304) using a eutectic / solder process. In the case of a eutectic / solder bond, the conductive bond (304) can be formed from a specific set of materials with an alloy material to form a central bond. One or both of the pMUT wafer (200) and the ASIC wafer stack (100, 101, 102, 103, and 303) may include features to limit the flow of melt in the eutectic or solder bond. After a solid conductive bond is formed between the two wafers, the wafer stack can be further processed as needed. For example, the pMUT wafer (200) can be further thinned as desired. For example, a backside thinning process may be used to thin the backside of the pMUT wafer (200) to a desired thickness.

[0066] 9A and 9B illustrate the singulation of pMUT and ASIC wafers bonded by eutectic / solder bonding, according to disclosed embodiments. After a solid conductive bond is formed between the two wafers, the wafers are sequentially singulated. By way of example, FIG. 9A illustrates the pMUT wafer (200) of FIG. 8B being singulated to produce a plurality of pMUT dice (201). Subsequently, in FIGS. 9A-9B, the ASIC wafer (100) is singulated to produce a plurality of ASIC dice (101), thereby completing the wafer-to-wafer bonding method using eutectic / solder bonding and achieving the desired bonding configuration.

[0067] During the eutectic / solder bonding process, the eutectic / solder material may form a liquid or malleable paste. At this point, the eutectic / solder material may squeeze out, causing shorts or other problems. To suppress such squeezing, features can be added to the ASIC and / or pMUT wafers; for example, shallow grooves or additional trace metal around each bond post can be used (not shown). This improves yield and allows for smaller pitch patterns.

[0068] In some embodiments, the eutectic bond comprises joining a plurality of dissimilar metals selected from the group consisting of aluminum (Al), gold (Au), copper (Cu), germanium (Ge), indium (In), silicon (Si), and tin (Sn). For example, the plurality of dissimilar metals may comprise Au-Si, Al-Ge, Au-Sn, Cu-Sn, or Au-In.

[0069] In some embodiments, the solder joint comprises a joint using a solder alloy. For example, the solder alloy may comprise a plurality of different metals selected from the group consisting of silver (Ag), gold (Au), chromium (Cr), copper (Cu), germanium (Ge), indium (In), manganese (Mn), lead (Pb), silicon (Si), tin (Sn), and zinc (Zn). For example, the plurality of different metals may comprise Au-Sn.

[0070] It will be recognized that one skilled in the art can use alternatives to the specific arrangement of conductive bond posts and eutectic / solder material. As long as the eutectic / solder material is located at the bond interface, the alternative may not be critical. For example, the eutectic / solder material may be applied to the pMUT wafer instead of the ASIC wafer. Alternatively, the eutectic / solder material may be applied to both the pMUT wafer and the ASIC wafer.

[0071] Die-to-wafer bonding using thermocompression or eutectic / solder bonding In embodiments, integrating the pMUT array wafer with the ASIC wafer may include die-to-wafer bonding using thermo-compression or eutectic / solder bonding. The die-to-wafer bonding may include bonding multiple pMUT dice to an individual ASIC wafer using thermo-compression or eutectic / solder bonding. Alternatively, the die-to-wafer bonding may include bonding multiple ASIC dice to an individual pMUT wafer using thermo-compression or eutectic / solder bonding.

[0072] Die-to-wafer bonding using thermocompression or eutectic / solder bonding may involve preparing an ASIC wafer (100) as described in Figures 3A, 3B, and 3C. One or more sets of conductive contact posts (300) may be deposited and patterned on the ASIC stack of Figure 2D, which includes the ASIC wafer (100), top metal (101), planarized thick dielectric material (102), and connecting conductors (103). Deposition and patterning of the conductive contact posts (300) may be performed by a deposition and etch-back process, or may be plated using a mold such as photoresist. After the conductive contact posts (300) are formed, the ASIC wafer (100) may be thinned as needed.

[0073] The pMUT wafer (200) of Figure 4C may be singulated to produce a plurality of individual pMUT dice, which may be arranged on a handle substrate using a temporary bonding layer, in an arrangement that may mirror the arrangement of the ASIC dice (101) on the ASIC wafer (100).

[0074] The ASIC wafer (100) with handle substrate and temporary bonding layer and the plurality of pMUT dice are aligned together, and if necessary, the manufacturing atmosphere conditions (e.g., gas, temperature, and / or pressure) are adjusted and the wafers are brought into contact. Pressure is applied to the contacting wafers to form sufficient intimate contact to promote bonding. The wafers are brought to an appropriate temperature for the conductive bonding posts (300) and conductive receiver pads or posts (301) to form solid conductive bonds (300) using thermocompression or eutectic / solder bonding.

[0075] After a solid conductive bond is formed between the two wafers, the handle substrate and temporary bonding layer are removed. The wafer stack can then be further processed as needed. For example, either or both of the pMUT die or the ASIC wafer (100) can be further thinned, as desired. After a solid conductive bond is formed between the two wafers, the ASIC wafer (100) is singulated to produce a plurality of ASIC dice, thereby completing the bonding process and achieving the desired bonding configuration. As shown in FIG. 6B, the end result of the bonding process can involve a pMUT die (201) bonded to an ASIC die (101) using one or more sets of conductive bonds (302).

[0076] Die-to-wafer bonding offers the advantage of providing the ability to bond only known-good die (KGD), thereby reducing or eliminating the challenges associated with yield synthesis between the ASIC die and the pMUT die. This can be done by placing only the KGD pMUT die on a handle wafer above the KGD ASIC die.

[0077] Die-to-wafer bonding using thermocompression or eutectic / solder bonding can present potential challenges due to the need for precise handling of the thinned die when attaching it to the handle wafer and the need for precision pick-and-place equipment for this process. Such constraints can limit the throughput of the method for die-to-wafer bonding, thereby increasing manufacturing costs.

[0078] Die-to-die bonding using thermocompression or eutectic / solder bonding In embodiments, integrating the pMUT array wafer with the ASIC wafer may include die-to-die bonding using thermocompression or eutectic / solder bonding. Die-to-wafer bonding using thermocompression or eutectic / solder bonding may include bonding multiple pMUT dice to multiple ASIC dice. Die-to-wafer bonding using thermocompression or eutectic / solder bonding may include preparing an ASIC wafer (100) as described in Figures 3A, 3B, and 3C. One or more sets of conductive contact posts (300) may be deposited and patterned on the ASIC stack of Figure 2D, including the ASIC wafer (100), top metal (101), planarized thick dielectric material (102), and connecting conductors (103). Deposition and patterning of the conductive contact posts (300) may be performed by a deposition and etch-back process, or may be plated using a mold such as photoresist. After the conductive contact posts (300) are formed, the ASIC wafer (100) can be thinned.

[0079] Die-to-die bonding using thermocompression or eutectic / solder bonding may involve preparing a pMUT wafer (200) as illustrated in Figures 4A, 4B, and 4C. One or more sets of conductive receiver pads or pillars (301) are deposited and patterned on the pMUT wafer (200) or plated using a mold such as photoresist. The conductive receiver pads or pillars (301) can have any suitable height and array configuration. The conductive receiver pads or pillars (301) can be formed as the pMUT wafer is fabricated. After the conductive receiver pads or pillars (301) are formed, the substrate can be thinned as needed, as shown in the cross-sectional views of Figures 4B through 4C. For example, a backside thinning process may be used to thin the backside of the pMUT wafer (200) to a desired thickness.

[0080] After the conductive bond pillars are formed on the ASIC wafer and the conductive receiver pads or pillars are formed on the pMUT wafer, the ASIC wafer and the pMUT wafer may be individually singulated to produce a plurality of ASIC dies, each with a conductive bond pillar, and a plurality of pMUT dies with a conductive receiver pad or pillar. After the ASIC wafer and the pMUT wafer are singulated, the plurality of ASIC dies and the plurality of pMUT dies are aligned together, and the manufacturing atmosphere conditions (e.g., gas, temperature, and / or pressure) are adjusted as necessary to bring the dies into contact. Pressure is applied to the contacting ASIC dies and pMUT dies to form sufficient intimate contact to promote bonding. The ASIC dies and pMUT dies are brought to an appropriate temperature so that the conductive bond pillars (300) and the conductive receiver pads or pillars (301) form solid conductive bonds (300) using thermocompression or eutectic / solder bonding, thereby completing the die-to-die bond and achieving the desired bond configuration. As shown in FIG. 6B, the end result of the bonding process may involve a pMUT die (201) bonded to an ASIC die (101) using one or more sets of conductive bonds (302).

[0081] Die-to-die bonding using thermocompression or eutectic / solder bonding may offer the advantage of providing the capability to bond ASIC die and pMUT die of different sizes. Furthermore, similar to die-to-wafer bonding using thermocompression or eutectic / solder bonding, die-to-die bonding using thermocompression or eutectic / solder bonding may offer the advantage of providing the capability to bond only known-good die (KGD), thereby reducing or eliminating the challenges associated with yield bonding between ASIC die and pMUT die. This can be accomplished by bonding only KGD ASIC die and KGD pMUT die.

[0082] Die-to-die bonding using thermocompression or eutectic / solder bonding can present potential challenges due to the need for precise handling of the thinned die during bonding and the need for die-to-die bonding equipment for this process. Furthermore, only pairs of ASIC and pMUT dice can be bonded at a time. Such constraints can limit the throughput of die-to-die bonding methods using thermocompression or eutectic / solder bonding, thereby increasing manufacturing costs.

[0083] While preferred embodiments of the present invention have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. It is not intended that the present invention be limited by the specific examples provided herein. While the present invention has been described in conjunction with the above specification, the descriptions and drawings of the embodiments herein should not be construed as limiting. Numerous variations, changes, and substitutions will occur to those skilled in the art without departing from the invention. Furthermore, it will be understood that all aspects of the present invention are not limited to the specific depictions, configurations, or relative proportions set forth herein, which are subject to a variety of conditions and variables. It will be understood that various alternatives to the embodiments of the invention may be utilized in practicing the invention described herein. Accordingly, it is contemplated that the present invention also covers any such alternatives, modifications, variations, or equivalents. The following claims define the scope of the invention, and it is intended that methods and structures within the scope of the claims, and their equivalents, be covered thereby.

Claims

1. a device including a first substrate and a second substrate; the first substrate includes at least one piezoelectric micromachined ultrasonic transducer (pMUT) array; the second substrate includes at least one electrical circuit; the first substrate and the second substrate are joined using a eutectic bond or a solder bond; Any set of one or more individual piezoelectric micromachined ultrasonic transducers (pMUTs) of the at least one piezoelectric micromachined ultrasonic transducer (pMUT) array is addressable; In the apparatus, the eutectic bond or the solder bond forms a hermetically sealed cavity, the cavity being configured to controllably maintain a gas species and pressure. Device.

2. The apparatus of claim 1 , wherein the piezoelectric micromachined ultrasonic transducer (pMUT) array is configured to perform ultrasound imaging.

3. The apparatus of claim 1 , wherein the at least one electrical circuit comprises an application specific integrated circuit (ASIC).

4. The apparatus of claim 1 , wherein the bonding comprises wafer-to-wafer bonding.

5. The apparatus of claim 1 , wherein the bonding comprises a die-to-wafer bond.

6. The apparatus of claim 5 , wherein the die-to-wafer bonding uses an intermediate handle substrate and a temporary bonding layer.

7. The joining is a) temporarily bonding the first substrate or the second substrate wafer to a handle substrate using a temporary bonding layer; b) dicing the wafer onto the handle substrate; c) bonding the diced wafer to another wafer of the first substrate or the second substrate using eutectic or solder bonding; The apparatus of claim 1 , comprising:

8. The apparatus of claim 1 , wherein the bond comprises a die-to-die bond.

9. 10. The apparatus of claim 1, wherein the eutectic or solder bonding is performed at a temperature of 350°C or less.

10. 10. The apparatus of claim 9, wherein the eutectic or solder bonding is performed at a temperature of 300°C or less.

11. 10. The apparatus of claim 9, wherein one or both of the first substrate and the second substrate includes at least one feature for restricting the flow of melt of a eutectic or solder joint.

12. The apparatus of claim 9 , wherein the eutectic bond or the solder bond comprises a eutectic bond.

13. 13. The apparatus of claim 12, wherein the eutectic bond comprises joining together a plurality of dissimilar metals selected from the group consisting of aluminum (Al), gold (Au), copper (Cu), germanium (Ge), indium (In), silicon (Si), and tin (Sn).

14. 14. The apparatus of claim 13, wherein the plurality of different metals comprises Au-Si, Al-Ge, Au-Sn, Cu-Sn, or Au-In.

15. The apparatus of claim 9 , wherein the eutectic bond or the solder bond comprises a solder bond.

16. 16. The apparatus of claim 15, wherein the solder joint comprises a joint using a solder alloy, the solder alloy comprising a plurality of different metals selected from the group consisting of silver (Ag), gold (Au), chromium (Cr), copper (Cu), germanium (Ge), indium (In), manganese (Mn), lead (Pb), silicon (Si), tin (Sn), and zinc (Zn).

17. The apparatus of claim 16, wherein the plurality of different metals comprises Au—Sn.

18. 1. A method of manufacturing an integrated device, comprising: a) obtaining a first substrate including at least one piezoelectric micromachined ultrasonic transducer (pMUT) array; b) obtaining a second substrate including at least one electrical circuit; c) bonding the first substrate and the second substrate using eutectic or solder bonding, wherein any set of one or more individual piezoelectric micromachined ultrasonic transducers (pMUTs) of the at least one piezoelectric micromachined ultrasonic transducer (pMUT) array is addressable; In a method comprising: the eutectic bond or the solder bond forms a hermetically sealed cavity, the cavity configured to controllably maintain a gas species and pressure. method.

19. 20. The method of claim 18, wherein the piezoelectric micromachined ultrasonic transducer (pMUT) array is configured to perform ultrasound imaging.

20. 20. The method of claim 18, wherein the at least one electrical circuit comprises an application specific integrated circuit (ASIC).

21. The method of claim 18 , wherein the bonding comprises wafer-to-wafer bonding.

22. The method of claim 18 , wherein the bonding comprises die-to-wafer bonding.

23. 23. The method of claim 22, wherein the die-to-wafer bonding uses an intermediate handle substrate and a temporary bonding layer.

24. The joining is a) temporarily bonding the first substrate or the second substrate wafer to a handle substrate using a temporary bonding layer; b) dicing the wafer onto the handle substrate; c) bonding the diced wafer to another wafer of the first substrate or the second substrate using eutectic or solder bonding; 20. The method of claim 18, comprising:

25. The method of claim 18 , wherein the bonding comprises die-to-die bonding.

26. 20. The method of claim 18, wherein the eutectic or solder bonding is performed at a temperature of 350°C or less.

27. 27. The method of claim 26, wherein the eutectic or solder bonding is performed at a temperature of 300°C or less.

28. 20. The method of claim 18, wherein either one or both of the first substrate and the second substrate includes at least one feature for restricting the flow of melt of a eutectic or solder joint.

29. 27. The method of claim 26, wherein the eutectic bond or the solder bond comprises a eutectic bond.

30. 30. The method of claim 29, wherein the eutectic bonding comprises bonding together a plurality of dissimilar metals selected from the group consisting of aluminum (Al), gold (Au), copper (Cu), germanium (Ge), indium (In), silicon (Si), and tin (Sn).

31. 31. The method of claim 30, wherein the plurality of different metals comprises Au-Si, Al-Ge, Au-Sn, Cu-Sn, or Au-In.

32. 27. The method of claim 26, wherein the eutectic bond or the solder bond comprises a solder bond.

33. 33. The method of claim 32, wherein the solder joint comprises a joint using a solder alloy, the solder alloy comprising a plurality of different metals selected from the group consisting of silver (Ag), gold (Au), chromium (Cr), copper (Cu), germanium (Ge), indium (In), manganese (Mn), lead (Pb), silicon (Si), tin (Sn), and zinc (Zn).

34. 34. The method of claim 33, wherein the plurality of different metals comprises Au-Sn.

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