Integral loop

Abstract

To provide an integration circuit having less power consumption.SOLUTION: A feedback rate correction capacitor CR is provided between two input terminals of a difference type amplification circuit 15, and is connected at the time of a sampling and hold mode. By controlling a separation at the time of an integration mode, a feedback rate in the sample and holding mode and the integration mode can be set to an almost same level, and an unnecessary power consumption does not flow in the integration mode because a phase margin in the integration mode is not required to be increased.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an integrating circuit. [Background technology]

[0002] In a delta-sigma analog-to-digital converter, an integrator circuit is used that has the function of sampling and holding the difference in input voltages and integrating them.

[0003] FIG. 5 is a circuit diagram showing a conventional integrating circuit. The conventional integrating circuit 40 includes switch circuits 41, 42, and 43, a differential amplifier circuit 44, capacitors C1 and C2, and capacitors C3 and C4.

[0004] The conventional integrator circuit 40 operates as follows to integrate the difference between the input voltages Vi1 and Vi2.

[0005] First, clock signals Φs1 and Φs2 go high, and clock signal Φint goes low. Capacitor C1 has input voltage Vi1 applied to one end and a predetermined voltage Vdd / 2 applied to the other end. Capacitor C2 has input voltage Vi2 applied to one end and a predetermined voltage Vdd / 2 applied to the other end. After this, clock signal Φs2 goes low, causing input voltages Vi1 and Vi2 to be sampled by capacitors C1 and C2. This operating mode is the sample and hold mode.

[0006] Next, the clock signal Φs1 goes low and the clock signal Φint goes high. A predetermined voltage Vdd / 2 is applied to one end of capacitor C1, and the other end is connected to capacitor C3 via switch circuit 43. A predetermined voltage Vdd / 2 is applied to one end of capacitor C2, and the other end is connected to capacitor C4 via switch circuit 43. That is, the charge sampled on capacitor C1 is transferred to capacitor C3, and the charge sampled on capacitor C2 is transferred to capacitor C4. Therefore, input voltages Vi1 and Vi2 are integrated and output as output voltages Vo1 and Vo2. After this, when the clock signal Φint goes low, the input terminals of the differential amplifier circuit 44 are disconnected from capacitors C1 and C2, and a voltage corresponding to the charge integrated in the integrating capacitor is held and output as an integrated voltage. This operating mode is the integration mode.

[0007] The conventional integrating circuit 40 is provided with a differential amplifier circuit 44 that has a short settling time, and thus can improve integration accuracy even when operated at a high frequency (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-81568 Summary of the Invention [Problem to be solved by the invention]

[0009] In a delta-sigma analog-to-digital converter, the current consumption of the integrating circuit accounts for most of the current consumption. Therefore, there is a demand for reducing the current consumption of the integrating circuit in a delta-sigma analog-to-digital converter.

[0010] In the conventional integrator circuit 40, the feedback factor of the differential amplifier circuit 44 differs between the two operating modes. In the sample and hold mode, the capacitors C1 and C2 are disconnected from the differential amplifier circuit 44, so the feedback factor is large. In the integration mode, the capacitors C1 and C2 are connected to the input terminals of the differential amplifier circuit 44, so the feedback factor is small. In other words, the phase margin of the differential amplifier circuit 44 is smaller in the sample and hold mode.

[0011] Therefore, the differential amplifier circuit 44 needs to have a sufficient phase margin in the sample and hold mode, and the margin will be too large in the integral mode. If the phase margin of the differential amplifier circuit 44 is increased, the current consumption will increase. In other words, if the phase margin of the differential amplifier circuit 44 is increased to match the sample and hold mode, the current consumption will increase unnecessarily in the integral mode, which is a problem.

[0012] The present invention has been made in view of the above-mentioned problems, and has an object to reduce the current consumption of an integrating circuit. [Means for solving the problem]

[0013] An integrator circuit according to one aspect of the present invention comprises: an input selector switch that selects and outputs a first and second input signal and a first predetermined voltage; first and second capacitors, each having one end connected to the output terminal of the input selector switch; a first charge transfer switch having one end connected to the other end of the first capacitor; a second charge transfer switch having one end connected to the other end of the second capacitor; a sampling switch having one end connected to the other ends of the first and second charge transfer switches and the other end connected to a second predetermined voltage; a differential amplifier circuit having a first input terminal connected to the other end of the first charge transfer switch, a second input terminal connected to the other end of the second charge transfer switch, and first and second output terminals; and a feedback factor correction circuit provided between the first input terminal and the second input terminal of the differential amplifier circuit, the feedback factor correction circuit being composed of a feedback factor correction switch and a feedback factor correction capacitor. [Effects of the Invention]

[0014] According to the integration circuit of the present invention, a feedback factor correction capacitor CR is provided between the two input terminals of differential amplifier circuit 15, and is controlled so that it is connected in sample and hold mode and disconnected in integration mode. Therefore, by making the feedback factors of differential amplifier circuit 15 approximately the same in the two operating modes, it is possible to reduce the current consumption of differential amplifier circuit 15. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a circuit diagram showing an integrating circuit according to the present embodiment. [Figure 2] 4 is a timing chart of clock signals that control each switch of the integrating circuit of the present embodiment. [Figure 3] FIG. 10 is a circuit diagram illustrating another example of the integrating circuit of the present embodiment. [Figure 4] FIG. 10 is a circuit diagram illustrating another example of the integrating circuit of the present embodiment. [Figure 5] FIG. 1 is a circuit diagram showing a conventional integrating circuit. DETAILED DESCRIPTION OF THE INVENTION

[0016] The integrating circuit of the present invention will be described below with reference to the drawings. For the sake of simplicity, only the circuits necessary for the operation of the present invention are shown, and detailed descriptions of other circuits and operations are omitted.

[0017] FIG. 1 is a circuit diagram of the integrating circuit of this embodiment. The integrating circuit 10 of this embodiment includes sampling capacitors C1 and C2 that sample input voltages Vi1 and Vi2, an input changeover switch circuit 11 that switches between the input voltages Vi1 and Vi2 and predetermined voltages Vd1 and Vd2 and inputs them to the capacitors C1 and C2, a sampling switch circuit 12 that biases the other ends of the capacitors C1 and C2 to a predetermined voltage Vaicm, a charge transfer switch circuit 13 that transfers the charges sampled in the capacitors C1 and C2 to the capacitors C3 and C4, a differential amplifier circuit 15 and integrating capacitors C3 and C4 for implementing the integrating operation, and a feedback factor correction capacitor CR and feedback factor correction switch circuit 14 connected between the two input terminals of the differential amplifier circuit 15.

[0018] The predetermined voltage Vaicm is a voltage within the range of the common-mode input voltage of the differential amplifier circuit 15 (for example, half the voltage of the power supply voltage Vdd), and may be the same voltage or different voltages for the capacitors C1 and C2.

[0019] FIG. 2 is a timing chart of clock signals that control the switches of the integrating circuit of this embodiment. Switch circuit 11 operates to switch the output voltage in response to clock signal Φs1. Switch circuit 12 is turned on and off in response to clock signal Φs2. Switch circuit 13 is turned on and off in response to clock signal Φint. Switch circuit 14 is turned on and off in response to clock signal ΦR.

[0020] The integrating circuit 10 of this embodiment operates as follows to integrate the difference between the input voltages Vi1 and Vi2.

[0021] First, clock signals Φs1 and Φs2 go high, and clock signal Φint goes low. Capacitor C1 has input voltage Vi1 applied to one end and a predetermined voltage Vaicm applied to the other end. Capacitor C2 has input voltage Vi2 applied to one end and a predetermined voltage Vaicm applied to the other end. After this, clock signal Φs2 goes low, causing capacitors C1 and C2 to sample input voltages Vi1 and Vi2 with respect to the predetermined voltage Vaicm. This operating mode is the sample and hold mode.

[0022] At this time, switch circuit 13 is off, and capacitors C1 and C2 are disconnected from the input terminals of differential amplifier circuit 15. Therefore, the feedback ratio to the input terminals of differential amplifier circuit 15 as viewed from the output terminals is greater than when switch circuit 13 is on.

[0023] Here, by setting the clock signal ΦR to a high level, the switch circuit 14 is turned on, and the feedback factor correction capacitor CR is connected between the two input terminals of the differential amplifier circuit 15. If the capacitance value of capacitors C3 and C4 is C3 and the capacitance value of capacitor CR is CR, the feedback factor of the sample and hold mode of the differential amplifier circuit 15 is approximately C3 / (C3+2CR). Therefore, it can be seen that the feedback factor of the differential amplifier circuit 15 is reduced by connecting the capacitor CR.

[0024] Next, the clock signals Φs1 and ΦR are set to low level. An input voltage Vd1 is applied to one end of capacitor C1, and the other end is connected to the non-inverting input terminal + of differential amplifier circuit 15. An input voltage Vd2 is applied to one end of capacitor C2, and the other end is connected to the inverting input terminal - of differential amplifier circuit 15. Furthermore, switch circuit 14 is turned off, and capacitor CR is disconnected from the two input terminals of differential amplifier circuit 15. Therefore, the charge sampled in capacitors C1 and C2 is transferred to capacitors C3 and C4, and input voltages Vi1 and Vi2 are integrated. This operating mode is the integration mode. If the capacitance value of capacitors C1 and C2 is C1, the feedback ratio of differential amplifier circuit 15 in integration mode is approximately C3 / (C3+C1).

[0025] Here, by setting the capacitance value CR of capacitor CR to C1 / 2, the feedback factor of differential amplifier circuit 15 in sample and hold mode can be made approximately the same as the feedback factor in integration mode. As a result, differential amplifier circuit 15 does not need to increase the phase margin in integration mode to match the sample and hold mode, and unnecessary current consumption in integration mode does not occur. Furthermore, since the voltage across capacitor CR becomes the virtual ground of differential amplifier circuit 15, the voltages at the two input terminals of differential amplifier circuit 15 fluctuate little before and after connecting capacitor CR. Therefore, the stable operation of integration circuit 10 is not impaired even if capacitor CR is provided.

[0026] FIG. 3 is a circuit diagram showing another example of the integrating circuit of this embodiment. The integrator circuit 10 in Figure 3 has a configuration in which the capacitor CR is two capacitors connected in parallel. As an integrated circuit device, capacitors have differences in parasitic capacitance between their two terminals. Therefore, when the capacitor CR is connected between the two input terminals of the differential amplifier circuit 15, differences in the feedback ratio may occur. To avoid this, the polarity of the two capacitors is reversed and they are connected in parallel, thereby matching the characteristics such as the parasitic capacitance between the two terminals of the capacitors. By matching the feedback ratio between the two terminals of the differential amplifier circuit 15, it is possible to avoid deterioration in the operational stability of the differential amplifier circuit 15.

[0027] FIG. 4 is a circuit diagram showing another example of the integrating circuit of this embodiment. The integrating circuit 10 in FIG. 4 has a configuration in which the capacitor CR is connected to two separate input terminals of the differential amplifier circuit 15 and a predetermined voltage input terminal.

[0028] As explained above, the integrator circuit 10 of the present invention provides a feedback factor correction capacitor CR between the two input terminals of the differential amplifier circuit 15, and controls the capacitor to be connected in the sample and hold mode and disconnected in the integration mode, thereby making it possible to maintain approximately the same feedback factor in both modes. Therefore, the differential amplifier circuit 15 does not need to increase the phase margin in the integration mode to match the sample and hold mode, and unnecessary current consumption does not occur in the integration mode. In other words, the integrator circuit 10 of the present invention can reduce current consumption.

[0029] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the present invention. For example, the predetermined voltages Vd1 and Vd2 and Vaicm may be equal voltages, such as the voltage of the GND terminal. [Explanation of symbols]

[0030] 10: Integral circuit 11: Input selector switch circuit 12: Sampling switch circuit 13: Charge transfer switch circuit 14: Feedback rate correction switch circuit 15: Differential amplifier circuit C1, C2: Sampling capacitors C3, C4: Integration capacitors CR: Feedback factor correction capacitor

Claims

1. an input changeover switch that switches between first and second input signals and first and second predetermined voltages and outputs the selected voltage; first and second capacitors, one end of each of which is connected to the output terminal of the input selector switch; a first charge transfer switch having one end connected to the other end of the first capacitor; a second charge transfer switch having one end connected to the other end of the second capacitor; a sampling switch having one end connected to one end of each of the first and second charge transfer switches and having the other end to which a third predetermined voltage is applied; a differential amplifier circuit including a first input terminal connected to the other end of the first charge transfer switch, a second input terminal connected to the other end of the second charge transfer switch, and first and second output terminals; a feedback factor correction circuit configured by connecting a feedback factor correction capacitor between a first input terminal and a second input terminal of the differential amplifier circuit via a feedback factor correction switch; An integrating circuit comprising:

2. the integrator circuit has a sample and hold mode in which the input selector switch outputs the first and second input signals, the sampling switch is turned on, and the first and second charge transfer switches are turned off, and an integration mode in which the input selector switch outputs the first and second predetermined voltages, the sampling switch is turned off, and the first and second charge transfer switches are turned on; The feedback factor correction switch is turned on in the sample and hold mode.

2. The integrator circuit according to claim 1 .

3. The feedback factor correction capacitor has both ends connected to the first input terminal and the second input terminal of the differential amplifier circuit.

3. The integrating circuit according to claim 1, wherein:

4. The feedback factor correction capacitor is a first feedback factor correction capacitor having one end connected to the first input terminal of the differential amplifier circuit and the other end connected to the third predetermined voltage via the feedback factor correction switch; a second feedback factor correction capacitor having one end connected to the second input terminal of the differential amplifier circuit and the other end connected to the third predetermined voltage via the feedback factor correction switch; 3. The integrating circuit according to claim 1, wherein:

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