Instruction dispatch routing

Abstract

A method for routing instruction dispatch includes receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order different from the first rotation order is associated with non-priority instructions; selecting one issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

Description

[Technical Field]

[0001] The present invention relates generally to computer technology, and more particularly to methods, processors, and systems for routing instruction dispatches. [Background technology]

[0002] Processor cores with multiple issue queues driving multiple execution units typically utilize a mechanism to distribute dispatched instructions across these issue queues. Conventional processor cores typically accomplish this by distributing instructions sequentially in order. That is, they dispatch instructions by starting with one issue queue and rotating through the issue queues, assigning one instruction to each issue queue in order. However, this conventional technique can result in performance degradation. For example, there is usually information about which issue queues are full, and these queues are rotated out. However, waiting until an issue queue is overfull before reacting is undesirable from a performance perspective. For performance purposes, it is desirable to give each issue queue an equal amount of work, and because all instructions are not equivalent in terms of the resources they use, it is not as simple as evenly distributing the number of instructions across each issue queue. Summary of the Invention

[0003] Aspects of the present disclosure may include a method, a processor, and a system for routing instruction dispatches. In one aspect, the method includes receiving an instruction for dispatch to one of a plurality of issue queues, determining a priority status of the instruction, selecting a rotation order based on the priority status, where a first rotation order is associated with priority instructions and a second rotation order different from the first rotation order is associated with non-prioritized instructions, selecting one issue queue from the plurality of issue queues based on the selected rotation order, and dispatching the instruction to the selected issue queue.

[0004] In another aspect, a method includes receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; dispatching each of the one or more instructions designated as resource-intensive to a respective one of a plurality of issue queues according to a first rotation order; and dispatching each of the one or more instructions designated as non-resource-intensive to a respective one of the plurality of issue queues according to a second rotation order that is opposite to the first rotation order.

[0005] In another aspect, a processor includes an instruction fetch unit, a dispatch unit communicatively connected to the instruction fetch unit, and a plurality of issue queues communicatively connected to the dispatch unit. The dispatch unit is configured to receive the plurality of instructions from the instruction fetch unit, determine an individual priority status for each of the plurality of instructions, and select a rotation order for each of the plurality of instructions based on the individual priority status. A first rotation order is associated with the prioritized instructions, and a second rotation order different from the first rotation order is associated with the non-prioritized instructions. The dispatch unit is further configured to select a respective issue queue of the plurality of issue queues for each of the plurality of instructions based on the respective selected rotation order, and dispatch each of the plurality of instructions to the respective selected issue queue.

[0006] In another aspect, a computer system includes a memory configured to store program code and a processor communicatively coupled to the memory and configured to execute the program code. The processor includes an instruction fetch unit, a dispatch unit communicatively coupled to the instruction fetch unit, and a plurality of issue queues communicatively coupled to the dispatch unit. The dispatch unit is configured to receive a plurality of instructions in a cycle. The plurality of instructions includes one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive. The dispatch unit is configured to dispatch each of the one or more instructions designated as resource-intensive to a respective one of the plurality of issue queues according to a first rotation order and to dispatch each of the one or more instructions designated as non-resource-intensive to a respective one of the plurality of issue queues according to a second rotation order that is opposite to the first rotation order.

[0007] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.

[0008] It should be understood that the drawings depict exemplary embodiments only and therefore should not be considered limiting in scope, and that exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a high-level block diagram illustrating one embodiment of an exemplary computer system. [Figure 2] FIG. 1 is a high-level block diagram of one embodiment of an exemplary processor core. [Figure 3] FIG. 3 is a partial diagram of one embodiment of the processor core of FIG. 2. [Figure 4] FIG. 3 is a partial diagram of one embodiment of the processor core of FIG. 2. [Figure 5] 1 is a flow chart illustrating one embodiment of an exemplary method for dispatching instructions. [Figure 6] 10 is a flow chart illustrating another embodiment of an exemplary method for dispatching instructions. [Figure 7] 10 is a flow chart illustrating another embodiment of an exemplary method for dispatching instructions. DETAILED DESCRIPTION OF THE INVENTION

[0010] According to common practice, the various illustrated features are not drawn to scale but are drawn to emphasize specific features relevant to the illustrated embodiments.

[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which there is shown by way of illustration specific illustrative embodiments. It is to be understood, however, that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Furthermore, the methods presented in the drawings and specification should not be construed as limiting the order in which individual steps may be performed. Accordingly, the following detailed description is not to be taken in a limiting sense.

[0012] An embodiment is described below.

[0013] FIG. 1 is a high-level block diagram illustrating one embodiment of an exemplary computer system 10. Computer system 10 includes one or more processors 12 connected to various additional components, such as system memory 14, input / output (I / O) 16, and storage 18, via one or more communication paths 20 implemented, for example, using one or more buses, networks, interconnects, etc. Each processor 12 may include one or more processor cores 22 and local storage 24, including, for example, internal system memory and / or one or more levels of cache memory. While each processor 12 may be configured identically in some embodiments, other embodiments may utilize differently configured processors together. Furthermore, in multi-core processor implementations, each core 22 may be configured identically or differently from other cores 22 within the same processor 12. It should be appreciated that the embodiments described herein may be utilized in a variety of system configurations, including uni-processor and / or multi-processor configurations, as well as single-core and / or multi-core configurations. Furthermore, the embodiments described herein may be utilized in various types of special purpose processors, such as graphics processors, network processors, co-processors, service processors, embedded processors, and the like.

[0014] In some embodiments, system memory 14 may include random access memory (RAM), representing the system's primary volatile storage. Furthermore, while some embodiments may support a single system memory 14, in other embodiments, memory is distributed across multiple nodes, with one or more processors 12 implemented in each node, and with non-uniform memory access between portions of memory on the same or different nodes within the system. Nodes may also be arranged in various hierarchical structures, such as different cabinets, racks, cards, slots, etc., and interconnected via a high-speed network.

[0015] System 10 also includes various input / output (I / O) interfaces and devices 16, which may vary depending on the type of system. For example, in some systems, I / O 16 may include adapters and / or interfaces to one or more external networks, such as private networks, public networks, wired networks, and wireless networks. Additionally, in single-user systems such as desktop computers, laptop computers, tablets, and mobile devices, I / O 16 may also include user input devices, such as a mouse, keyboard, touchscreen, microphone, and imaging device, for receiving user input, and a graphical display and / or audio playback device for displaying information. System 10 may also include a storage subsystem 18, which may include non-removable mass storage drives, such as solid-state disk drives and hard disk drives, as well as removable drives, such as flash drives and optical drives, that may be used to retrieve program code and / or data stored on computer-readable media, such as optical disks.

[0016] Exemplary program code 28 is illustrated, for example, in memory 24, and this code may represent various types of instructions that may be executed by core 22 of processor 12, including, for example, user-level applications, operating systems, firmware, middleware, device drivers, virtualization program code, etc. It should be appreciated that program code 28 may also at times be stored in other computer-readable media, including various types of both non-volatile and volatile memory, such as cache memory, system memory, external storage, removable media, etc.

[0017] While the system of FIG. 1 is used to provide an illustration of a system in which embodiments described herein may be implemented, it will be understood that the depicted architecture is not limiting and is intended to provide an example of a suitable computer system in which the various techniques disclosed herein may be applied.

[0018] It should further be appreciated that the techniques described herein may be implemented within a circuit arrangement generally representing a physical device or system (e.g., one or more integrated circuit devices / chips, cards, boards, components, systems, etc.) incorporating hardware and, in some cases, software configured to implement such techniques. Additionally, it should be appreciated that implementations utilizing the techniques described herein may be distributed, at least in part, in the form of a program product that defines a circuit arrangement and includes logic definition code stored on a computer-readable medium, and that the present invention applies equally regardless of the particular type of computer-readable medium used to actually execute the distribution. Logic definition program code may include, for example, a synthesizable form, such as that described in a general-purpose gate netlist, a hardware description language such as Verilog or VHDL, a lower-level, physical description language such as GDSII, or other types of program code capable of defining, at various levels of detail, the functionality and / or layout of a circuit arrangement to be manufactured. Examples of computer-readable media include, but are not limited to, non-transitory, physical, recordable types of media such as volatile and non-volatile memory devices, floppy disks, hard disk drives, CD-ROMs, and DVDs (among others).

[0019] Further details of processor core 22 are shown and described with respect to FIG. 2. In one example, the processor is a superscalar processor that retrieves instructions from a memory (e.g., system memory 14 of FIG. 1) and loads these instructions into the processor's instruction sequencing logic (ISL) 204. Instruction sequencing logic 204 includes, for example, a level 1 instruction cache (L1 I-cache) 206, a fetch-decode unit 208, an instruction queue 210, and a dispatch unit 212. In one example, instructions are loaded into L1 I-cache 206 of ISL 204 and retained in L1 I-cache 206 until the instructions are needed or, if the instructions are no longer needed, until they are replaced. Instructions are retrieved from L1 I-cache 206 and, in one example, grouped into instruction groups and decoded by fetch-decode unit 208 (also referred to herein as instruction fetch unit 208). After decoding the current instruction, the current instruction is loaded into instruction queue 210. Dispatch unit 212 dispatches the instruction from instruction queue 210 to one of a plurality of issue queues 222-1...222-N (collectively referred to herein as issue queues 222), where N is the total number of issue queues. In this example, processor core 22 includes four issue queues 222. However, it should be understood that in other embodiments, more or fewer than four issue queues 222 may be used.

[0020] The issue queue 222 issues the current instruction to one of the execution units 224-1..224-M (collectively referred to herein as execution units 224), respectively, where M is the total number of execution units. The issue queue 222 may include, for example, floating-point type instructions, fixed-point type instructions, or load / store instructions, or a combination thereof. However, it should be appreciated that any number and type of instructions may be used. For example, instruction types include, but are not limited to, fixed-point arithmetic, matrix multiply-accumulate (MMA), vector scalar unit (VSU), and load / store (LS) instructions. In this example, the processor core 22 includes eight execution units 224 for executing instructions received from the issue queue 222. However, it should be understood that in other embodiments, more or fewer than eight execution units 224 may be used. Each of the execution units 224 may be implemented or configured to execute one or more types of instructions. For example, execution units 224 may include, but are not limited to, a matrix multiply-accumulate (MMA), a vector scalar unit (VSU), and a load / store (LS) unit.

[0021] For example, in one exemplary embodiment, each of the issue queues 222 is associated with a separate vector-scalar unit (e.g., execution units 224-1, 224-3, 224-4, and 224-6). Also in this example, the two issue queues 222 drive one load / store unit for a total of two load / store units per core (e.g., execution units 224-2 and 224-5). Similarly, the two issue queues drive one matrix multiply-accumulate unit for a total of two MMA units per core (e.g., execution units 224-7 and 227-M). Additionally, in the exemplary embodiment of FIG. 2, the processor core 22 can be split into two when operating in what is referred to as simultaneous multithreading (SMT) 4 mode. In SMT4 mode, core 22 is configured to handle two threads per side, e.g., using two issue queues, one load / store unit, and one MMA unit per side. In SMT4 mode, each side routes four instructions to up to two issue queues in the even and odd half slices, for a total of four half slices per side. In Figure 2, the sides are labeled superslice 0 and superslice 1. When operating in a mode referred to as SMT2 mode, or a mode referred to as single-threaded (ST) mode, core 22 is unified (i.e., not divided into superslices or sides) and dispatches eight instructions to one of the four issue queues in the even or odd half slice, for a total of eight half slices.

[0022] Each issue queue 222 is also referred to herein as a slice. Additionally, each issue queue 222 has two slots, referred to herein as even and odd half-slices, discussed in more detail below. In SMT2 mode, all instructions (e.g., eight instructions) in each cycle are allocated to one of four issue queues 222 in either the even or odd slice, for a total of eight half-slices. In SMT4 mode, each side or super slice routes half of the instructions (e.g., four instructions) per cycle to up to two issue queues in the even and odd slices, for a total of four half-slices per side or super slice.

[0023] A processor core with multiple issue queues driving multiple execution units utilizes a mechanism to distribute dispatched instructions among these issue queues. Conventional processor cores typically accomplish this by distributing instructions sequentially in order. That is, they dispatch instructions by starting with one issue queue and rotating through the issue queues, assigning one instruction to each issue queue in order. However, this conventional technique can result in performance degradation. For example, there is usually information about which issue queues are full, and these queues are rotated out. However, waiting until an issue queue is overfull before reacting is undesirable from a performance perspective. For performance purposes, it is desirable to give each issue queue an equal amount of work, and because all instructions are not equivalent in terms of the resources they use, it is not as simple as evenly distributing the number of instructions among each issue queue.

[0024] If instructions are simply dispatched sequentially, as in conventional systems, a situation can arise in which all of the same instruction type, such as VSU or MMA instructions, are sent to the same issue queue that feeds only one VSU or MMA unit, and therefore work is not distributed to execute in parallel. For example, if every fourth instruction is a VSU instruction and the instructions are simply dispatched sequentially, all VSU instructions will be dispatched to the same issue queue and therefore the same VSU execution unit. This creates a local bottleneck on completion from one VSU, delaying the execution of the overall workload.

[0025] In the embodiments described herein, dispatch unit 212 is configured to overcome the performance problems of conventional processor cores by implementing a novel dispatching technique that is efficient and fast to execute. In particular, the circuits of a processor core execute at very high frequencies. Therefore, the dispatching technique implemented in dispatch unit 212 is configured to be buildable into high-performance circuits, enabling dispatch unit 212 to quickly determine or select an issue queue 222 for a given instruction. This allows the dispatch unit to balance the weight or load on each issue queue 222 approximately equally, while also performing such routing quickly enough to avoid becoming a performance bottleneck given the high execution rates of the circuits within processor core 22.

[0026] At a higher level, dispatch unit 212 is configured to implement two different and distinct rotation orders. One rotation order is associated with instruction types designated as preferred / optimal instruction types, and the other rotation order is associated with instruction types designated as non-preferred / non-optimal instruction types. In some embodiments, the selection of the preferred / optimal instruction type may be based on the type of instruction that is likely to clog the issue queue (e.g., it may be determined based on the length of the instruction pipeline, particularly with respect to data dependencies). In some embodiments, the instruction type designated as preferred may be selected in advance. Furthermore, in some embodiments, only one instruction type (e.g., MMA, VSU, or L / S) is designated as the preferred instruction. In other embodiments, more than one instruction type may be designated as the preferred instruction.

[0027] By way of example, in some embodiments, eight instructions are received from the instruction fetch unit 208 per cycle. In some such embodiments, priority instructions are marked in an eight-bit vector sent from the instruction fetch unit 208, where, for example, a one represents an optimal or prioritized instruction and a zero represents a non-optimal or non-prioritized instruction. As described in further detail below, the dispatch unit 212 is configured to store or track the issue queue number for the next rotational dispatch for each type of instruction. For example, in some embodiments, a two-bit latch is used for four types of instructions to track the issue queue number for the next rotational dispatch of that type of instruction. Furthermore, in some embodiments, a switch may be used to statically choose which types of instructions are designated as optimal / prioritized.

[0028] Additionally, in some embodiments, the instruction type designated as the priority instruction can change dynamically from cycle to cycle, rather than remaining a statically assigned type in advance. In some such embodiments, the instruction fetch unit 208 sends instructions of the prioritized type to the dispatch unit 212. For example, in some such embodiments, a hierarchy of instruction type priorities is used to assign a priority instruction type for a given cycle based on the instruction type in that cycle. By way of example, in one such embodiment, MMA instructions have the highest priority, followed by VSU instructions, then L / S instructions, and then fixed-point arithmetic. Thus, in such an embodiment, if one or more MMA instructions are present in a given cycle, the MMA instructions are assigned the priority instruction type, and the VSU, L / S, and fixed-point arithmetic instructions are considered non-priority instructions. However, if no MMA instructions are present in a given cycle and one or more VSU instructions are present in that cycle, the VSU instructions are assigned the priority instruction type for that cycle, and so on. This dynamic selection of the preferred instruction type may, in some embodiments, be performed in the instruction fetch unit 208 and communicated to the dispatch unit 212. In some embodiments, a switch may be used to turn on / off the dynamic changing of the preferred instruction type, as well as other functions to indicate the selected preferred instruction type, force rotation, etc., as discussed in more detail below.

[0029] Additionally, in some other embodiments involving dynamically designating an instruction type as preferred, the dispatch unit 212, the instruction fetch unit 208, or another unit within the processor core is configured to observe the workload for a rolling window (e.g., 20 cycles) of prior cycles. Based on the observed workload for the prior cycle, an instruction type is selected as the preferred instruction type for the next cycle. For example, in some such embodiments, if an MMA instruction type was observed in any of the last 20 cycles, the MMA instruction type may be selected as the preferred instruction type for the next cycle. If an MMA instruction type was not observed in the last 20 cycles, a different instruction type (e.g., VSU) may be selected as the preferred instruction type for the next cycle. Thus, rather than switching every instruction cycle, the instruction type considered to be the preferred instruction type is periodically switched less frequently (e.g., after 10 or 20 cycles, depending on the size of the rolling window).

[0030] Given a designated priority instruction type for a given cycle, dispatch unit 212 is configured to dispatch any priority instructions according to a first rotation order associated with the priority instructions and to dispatch any other instructions in the cycle according to a second rotation order associated with non-priority instructions that differs from the first rotation order. Each of the first and second rotation orders defines a respective direction of rotation through issue queue 222, as well as an amount by which to adjust the rotation, as described in further detail below with respect to Figures 3 and 4. In some embodiments, dispatch unit 212 may be comprised of various logic gates to determine where to dispatch instructions based on various received bits and switches, as described herein.

[0031] FIG. 3 is a partial diagram of one embodiment of processor core 22, depicting only dispatch unit 212 and issue queue 222. In particular, FIG. 3 illustrates one embodiment of dispatching instructions to issue queue 222 in a single cycle. In the example shown in FIG. 3, the cycle includes eight instructions (labeled i0 through i7) received at dispatch unit 212 from instruction fetch unit 208. In this example, instructions i0 and i1 have instruction types designated as priority instruction types for this cycle. Instructions i2 through i7 have instruction types designated as non-priority instructions for this example. In some embodiments, dispatch unit 212 is configured to determine the instruction type of each instruction in the cycle based on information sent from instruction fetch unit 208. For example, instruction fetch unit 208 can set one or more bits sent with the decoded instructions. In other embodiments, dispatch unit 212 determines the instruction type of each instruction using a different technique.

[0032] In this embodiment, the architecture of processor core 22 dispatches instructions sequentially from i0 to i7. That is, before instruction i1 can be dispatched, instruction i0 must first be dispatched, and so on. In this example, instructions i0 and i1 are designated as priority instructions, so a first rotation order is selected to dispatch instructions i0 and i1, while a second rotation order is selected to dispatch instructions i2 through i7. The first and second rotation orders can be described in terms of slice and half-slice numbers. For example, issue queues 222-1, 222-2, 222-3, and 222-N are also referred to as slice 0 (S0), slice 1 (S1), slice 2 (S2), and slice 3 (S3), respectively. Additionally, as discussed above, each issue queue has two slots or half-slices. These slots or half-slices are labeled 0, 1, 2, 3, 4, 5, 6, and 7, respectively. Each issue queue has an even half-slices (0, 2, 4, or 6) and an odd half-slices (1, 3, 5, or 7).

[0033] In this embodiment, the first rotation order specifies a slice order of 0-2-1-3. Thus, the first rotation order starts with slice 0 (issue queue 222-1) for the first priority instruction, rotates to slice 2 (issue queue 222-3) for the next priority instruction, then rotates to slice 1 (issue queue 222-2) for the next priority instruction, and then rotates to slice 3 (issue queue 222-N) for the next priority instruction. If there are five or more priority instructions, the first rotation order starts over with slice 0. The second rotation order for non-priority instructions specifies a slice order of 3-1-2-0 in this example. Thus, the second rotation order starts with slice 3 (issue queue 222-N) for the first non-priority instruction, rotates to slice 1 (issue queue 222-2) for the next non-priority instruction, then rotates to slice 2 (issue queue 222-3) for the next non-priority instruction, and then rotates to slice 0 (issue queue 222-1) for the next non-priority instruction. If there are five or more non-priority instructions, the second rotation order starts over with slice 3.

[0034] As can be seen, the first and second rotation orders each define a starting point and a rotation direction and amount (e.g., rotate two slices to the right, rotate one slice to the left, etc.) for each rotation. Notably, the starting point, rotation direction, and rotation amount defined by the second rotation order are essentially opposite to the starting point, rotation direction, and rotation amount defined by the first rotation order. Additionally, in this example, the dispatch unit is configured to first select an even half-slice per slice in a given cycle, and then select an odd half-slice per slice. For example, the first instruction dispatched to slice 0 (issue queue 222-1), whether prioritized or non-prioritized, is dispatched to half-slice or slot 0. Similarly, the first time an instruction is dispatched to another slice, whether prioritized or non-prioritized, the instruction is dispatched to an even half-slice (e.g., 2, 4, or 6). The next time an instruction, whether prioritized or non-prioritized, is dispatched to slice 0 (or one of the other slices), the subsequent instruction will be dispatched to an odd-numbered half-slice (i.e., 1, 3, 5, or 7).

[0035] Thus, dispatch unit 212 is configured to track or store, in both the first and second rotation orders, the point at which dispatch unit 212 is located relative to each subsequent instruction, as well as whether it uses an even or odd half-slice for that slice. Additionally, in some embodiments, dispatch unit 212 stores the point across cycles in both the first and second rotation orders. That is, rather than resetting the first and second rotation orders at the beginning of each cycle, dispatch unit 212 stores the point at which dispatch unit 212 is located at the end and beginning of each cycle in each of the first and second rotation orders. For example, if, at the end of a given cycle, the dispatch unit dispatches a priority instruction to slice 2, then in a subsequent cycle the next priority instruction is sent to slice 1 using the example rotation discussed above. Additionally, in some embodiments, dispatch unit 212 tracks the last half-slice used in each cycle across cycles, as mentioned above. For example, dispatch unit 212 may track whether the last instruction sent to slice 1 was for an odd half-slice or an even half-slice, so that the next subsequent instruction sent to slice 1, whether in the same cycle or a subsequent cycle, will be sent to another half-slice in slice 1.

[0036] Further, in addition to tracking the last issue queue used for the prioritized and non-prioritized rotation orders, in some embodiments, dispatch unit 212 is configured to track the last issue queue used for each instruction type. Thus, in an embodiment in which four different instruction types are present, for example, dispatch unit 212 is configured to track the last issue queue used for each of the four different instruction types. In an embodiment with dynamic selection of the priority instruction type, for example, at the beginning of each instruction cycle, dispatch unit 212 adjusts the start of the priority rotation order based on the last issue queue used for the instruction type selected as the priority instruction type for that instruction cycle. In particular, dispatch unit 212 sets the first or starting issue queue in the priority rotation order for that instruction cycle as the next issue queue in the priority rotation order after the last issue queue used for the priority instruction type. Next, the non-prioritized rotation order is adjusted to be the opposite of the priority rotation order. In other words, the starting issue queue for the non-prioritized issue queue is the opposite of the starting issue queue for the priority rotation order.

[0037] In some embodiments, dispatch unit 212 utilizes a two-bit encoded or four-bit decoded value to track which issue queue to use next for each of the first and second rotation orders. For example, the next rotation number can be selected from a previous rotation state latch, which can be expanded into a four-bit orthogonal signal rotated one bit to the right after every priority instruction. An opposite four-bit orthogonal signal is used for non-priority instructions, which rotate one bit to the left after every non-priority instruction. In this way, each instruction is examined in turn, with priority instructions receiving the optimal rotation while non-priority instructions are rotated in the opposite direction starting from the last selection of a priority instruction. In this way, dispatch unit 212 can track where it is currently in each of the first and second rotation orders.

[0038] Thus, through the use of two separate rotation orders for prioritized and non-prioritized instructions and the storage of the most recently used half-slice, dispatch unit 212 can ensure a more even distribution of workload across issue queue 222 than conventional processor cores. For example, in a conventional processor, if a more resource-intensive instruction occurs every fourth instruction, these more resource-intensive instructions would be dispatched to the same queue, imbalancing the workload distributed across the execution load and resulting in reduced performance. In contrast, in the same situation using embodiments described herein, the more resource-intensive instructions can be labeled as prioritized instructions and dispatched differently from non-prioritized instructions. Thus, in embodiments using the rotation orders described herein, the more resource-intensive instructions (as well as less resource-intensive instructions) are distributed more evenly across the issue queue, resulting in improved performance for the execution unit compared to conventional processors.

[0039] For example, in the embodiment shown in FIG. 3, instructions i0 and i1 are designated as priority instructions (e.g., more resource-intensive instructions), e.g., based on instruction type. Therefore, instructions i0 and i1 are dispatched according to a first rotation order. In this particular example, instruction i0 is dispatched to slice 0 (issue queue 222-1). Because it is the first instruction dispatched to slice 0, instruction i0 is sent to half slice 0. Instruction i1 is then dispatched to slice 2 (issue queue 222-3). Again, because it is the first instruction for slice 2, instruction i1 is sent to even half slice 4. Instructions i2-i7 are designated as non-priority instructions (e.g., less resource-intensive compared to the priority instructions) and therefore are dispatched according to a second rotation order. In particular, instruction i2 is dispatched to slice 3 (issue queue 222-N). Because it is the first instruction dispatched to slice 3, instruction i2 is sent to half slice 6. Instruction i3 is the first instruction dispatched to slice 1, so it is sent to even half-slice 3 in slice 1 (issue queue 222-1). Instruction i4 is the second instruction dispatched to slice 2, so it is dispatched to odd half-slice 5 in slice 2 (issue queue 222-3). Instruction i5 is the second instruction dispatched to slice 0, so it is dispatched to odd half-slice 1 in slice 0. The second rotation order then starts over, starting with slice 3, and dispatch unit 212 dispatches instruction i6 to odd half-slice 7 in slice 3, followed by instruction i7 to odd half-slice 3 in slice 1.

[0040] In the next cycle, if instructions i0 and i1 are still priority instructions, instruction i0 will be dispatched to slice 1, and instruction i1 will be dispatched to slice 3. Therefore, as can be seen, priority instructions are dispatched to different issue queues and evenly distributed throughout issue queue 222 for more parallel execution. Additionally, the example rotation order allows support for both 4-way and 2-way rotation. For example, the example processor core 22 has two MMA execution units. Therefore, the rotation of MMA instructions is a 2-way rotation. However, in the example of FIG. 2, there are four VSU execution units, so the rotation of VSU instructions is a 4-way rotation. However, as described above, the first and second rotation orders are configured to shift or rotate between super slice 0 (SS0) and super slice 1 (SS1), respectively. Therefore, 4-way rotation supports 2-way rotation, in the sense that instructions alternate between the two super slices. Furthermore, the embodiments described herein support SMT4, SMT2, and ST modes, as discussed above. In particular, by ensuring that each rotation or switch alternates superslices, the first and second rotation orders can support embodiments with one or two superslices. In this manner, the embodiments described herein are capable of supporting SMT4, SMT2, and ST modes.

[0041] Furthermore, in SMT4 mode, processor core 22 is split into two, so that only two issue queues are possible for each side. That is, multiple issue queues are divided into two groups that operate independently of each other. Each of the two groups can have a separate primary rotation order for priority / resource-intensive instructions and a separate secondary rotation order for non-priority / non-resource-intensive instructions. Additionally, in some embodiments, instructions are split between the two sides. For example, instructions i0-i3 can be dispatched to super slice 0, and instructions i4-i7 can be dispatched to super slice 1. This can be indicated by a single bit, but information is tracked in both half cores for each group of possible instruction types (e.g., up to four instruction types). Thus, in some such embodiments, eight total instruction types are tracked: four types in super slice 0 and four types in super slice 1. For each super slice or half core, a one-bit signal is passed for optimal / prioritized instruction type rotation and a separate one-bit signal for non-optimal / non-prioritized instruction rotation. Non-optimal rotation begins as the opposite of the starting value for optimal rotation. Each of the four instructions on a side is rotated sequentially using either the optimal or non-optimal rotation signal, and the appropriate signal is inverted for each case of that type of instruction in each super slice. Thus, in some embodiments, each super slice can have a different priority instruction type (e.g., MMA for super slice 0 and VSU for super slice 1).

[0042] Furthermore, in some embodiments, dispatch unit 212 is configured to take into account busy issue queues. For example, in the embodiment of FIG. 3, there are eight instructions and four issue queues, each with two half-slices. Some issue queues may be busy. If there are no busy issue queues, dispatching an instruction is a simple choice between one of the two rotation orders. If there are some busy issue queues, in some embodiments, dispatch unit 212 has a sequential dependency on the oldest instruction in a group of eight instructions. For example, in some embodiments, to conserve cycle time, dispatch unit 212 chooses to schedule only four instructions if there are some busy issue queues 222, but otherwise it is an eight-instruction dependency chain. Additionally, in some embodiments, if the issue queue pointed to by the rotation vector / rotation order is busy, subsequent queues in the rotation are checked, one after the other. If all remaining issue queues are busy, in some embodiments, this instruction and all newer instructions in the group are not dispatched. Handling of busy issue queues / slices 222 may depend on the operating mode. For example, in some embodiments operating in SMT2 mode or ST mode, if one or more slices are busy, dispatch unit 212 may be configured to dispatch instructions in pairs rather than individually, and to dispatch less than all of the instructions for a cycle (e.g., four rather than eight). In some embodiments operating in SMT4 mode, if one or more slices are busy, dispatch unit 212 may be configured to dispatch any instruction to any half-slice per super-slice, prioritizing even half-slices first.

[0043] Furthermore, in some other embodiments, the dispatch unit 212 is configured to force the rotation order if the issue queue pointed to by the rotation vector / rotation order is busy, rather than checking the next issue queue in the rotation. In some such embodiments, a switch is used to force rotation depending on the instruction type. For example, if the force rotation switch is set high, only the selected issue queue pointed to by the rotation vector / rotation order is checked for busyness. If the indicated issue queue is not available, the dispatch unit 212 stalls until the indicated issue queue is available. In some implementations, the selection to force rotation depends on the instruction type, as mentioned above. For example, in some implementations, the MMA instruction is always selected to turn on the force rotation signal, but none of the other instruction types are selected to turn on the force rotation signal. Some instructions, such as the MMA instruction, may be relatively long-running, so performance may be improved by waiting for the indicated issue queue rather than issuing a long-running instruction to a different issue queue early. Additionally, in some embodiments, a programmable time limit is used to limit the amount of time that dispatch unit 212 waits for a busy issue queue to become available. The programmable time limit, in some embodiments, can be measured, for example, in cycles or as actual elapsed time. In such embodiments using a programmable time limit, if the time limit is reached and the indicated issue queue is still busy, dispatch unit 212 moves on to the next issue queue in the rotation order.

[0044] It should be understood that the exemplary first and second rotation orders discussed above with respect to FIG. 3 are provided by way of example only, and that other rotation orders may be used in other embodiments. For example, in another embodiment, the first rotation order specifies a slice order of 1-3-0-2, and the second rotation order specifies a slice order of 2-0-3-1. Additionally, in some embodiments, the dispatch unit 212 is configured to first dispatch instructions to the odd half-slices of each issue queue 222, then to the even half-slices. Furthermore, in still other embodiments, the dispatch unit 212 may be configured to reset one or both of the first rotation order and the second rotation order for each cycle. It should be further understood that the number of prioritized and non-prioritized instructions and the order of prioritized and non-prioritized instructions discussed herein are provided by way of example only, and that the number and order of prioritized and non-prioritized instructions may vary for each cycle and embodiment. In particular, it should be understood that all of the prioritized instructions are not necessarily consecutive or the first instructions in a cycle.

[0045] Additionally, in some embodiments, dispatch unit 212 is configured to route paired instructions, as discussed with respect to FIG. 4. In particular, in the example shown in FIG. 4, instructions i0 and i1 are paired instructions. As used herein, paired instructions are instructions that are executed by the same execution unit. As such, dispatch unit 212 is configured to dispatch paired instructions to the same issue queue 222. Additionally, in this example, instructions i0, i1, and i2 are designated as non-priority instructions, and instructions i3-i7 are designated as priority instructions. None of instructions i2-i7 are paired instructions. However, dispatch unit 212 is configured in this example to adapt the dispatching of instructions i0-i7 to take paired instructions i0 and i1 into account. In particular, dispatch unit 212 is configured to dispatch all of instructions i0-i7 as pairs, even though only instructions i0 and i1 are considered paired instructions.

[0046] For example, in this embodiment, instructions i0 and i1 are paired, non-prioritized instructions. Therefore, instructions i0 and i1 are dispatched according to a second routing order associated with non-prioritized instructions. In the example of FIG. 4 , the second routing instructions start in slice 3. Therefore, instruction i0 is dispatched to even half-slice 6 of slice 3, and instruction i1 is dispatched to odd half-slice 7 of slice 3. Instructions i2 and i3 are also dispatched together as a pair. In this example, instruction i2 is non-prioritized, and instruction i3 is a priority instruction. Therefore, in this example, instructions i2 and i3 are dispatched using a first routing order associated with priority instructions. Therefore, instruction i2 is dispatched to even half-slice 0 of slice 0, and instruction i3 is dispatched to odd half-slice 1 of slice 0. However, in other embodiments, if one of the two instructions dispatched as a pair is a non-prioritized instruction, the pair of instructions may be dispatched according to a second routing order associated with the non-prioritized instruction. In such an embodiment, for example, instruction i2 is dispatched to even half-slice 2 of slice 1, and instruction i3 is dispatched to odd half-slice 3 of slice 1.

[0047] Instructions i4 and i5 are priority instructions and are dispatched according to the first routing order. Thus, in this example, instruction i4 is dispatched to even half-slice 4 of slice 2, and instruction i5 is dispatched to odd half-slice 5 of slice 2. Finally, instructions i6 and i7 are priority instructions and are dispatched as a pair according to the first routing order. In this example, instruction i6 is dispatched to even half-slice 2 of slice 1, and instruction i7 is dispatched to odd half-slice 3 of slice 1. Thus, the paired mode shown in FIG. 4 for dispatching instructions is similar to the separate mode of FIG. 3 in that it uses two separate routing orders for priority and / or non-prioritized instructions. However, in contrast to FIG. 3, instructions are not routed individually to one of the slices, but rather as pairs to the even and odd half-slices of the same slice, alternating between the even and odd half-slices, as described above.

[0048] 5 is a flow chart illustrating one embodiment of an example method 500 for dispatching instructions. Method 500 may be performed by a dispatch unit of a processor core, such as dispatch unit 212 discussed above. It should be understood that the order of actions in example method 500 is provided for illustrative purposes, and that the method may be performed in a different order in other embodiments. Likewise, it should be understood that in other embodiments, some actions may be omitted or additional actions may be included.

[0049] At 502, an instruction is received for dispatch to one of a plurality of issue queues. For example, in each cycle, multiple instructions may be received from an instruction fetch unit, as described above. One or more of the instructions in each instruction cycle may be designated as priority or best instructions. As discussed above, priority or best instructions are instructions that are designated as resource-intensive. Thus, instruction types that are not designated as resource-intensive for a given instruction cycle are designated as non-priority or non-resource-intensive instructions.

[0050] At 504, the priority status of the instruction is determined. This designation or priority status may be based on the instruction type of the instruction, as discussed above. In addition, in some embodiments, the priority status of each instruction may be indicated by a bit in a vector received from the instruction fetch unit, as discussed above. Furthermore, as discussed above, the instruction types designated as priority or resource-intensive may be determined dynamically, such as by the instruction fetch unit, on a cycle-by-cycle basis. In addition, the instruction types designated as priority or resource-intensive may be determined based on historical data of instruction types dispatched in prior cycles, as discussed above. It should be understood that the designation of resource-intensive or non-resource-intensive refers to the relative resource needs of the instruction type in a given instruction cycle. For example, in one instruction cycle, a VSU instruction type may be designated as a priority or resource-intensive instruction type compared to a fixed-point arithmetic instruction in the same instruction cycle. However, in another instruction cycle, the VSU instruction may be designated as non-resource-intensive compared to an MMA instruction designated as resource-intensive for that instruction cycle. Thus, the designations of resource intensive and non-resource intensive are not absolute designations of the specific amount of resources required, but rather relative designations of the likely resource needs relative to other instructions in an instruction cycle based on the particular instruction type.

[0051] At 506, a rotation order is selected based on the priority status. In particular, as discussed above, a first rotation order is associated with priority instructions, and a second rotation order, different from the first rotation order, is associated with non-priority instructions. The second rotation order can be the opposite of the first rotation order. For example, as discussed above, the dispatch unit can track the last rotation or issue queue used for each instruction type. For example, the last rotation or issue queue used for VSU instructions can be issue queue 222-2 (slice S1) in example FIG. 3, and the VSU instruction is selected as the priority instruction type for the current instruction cycle. Thus, at the start of the current instruction cycle, the first rotation order associated with priority instructions is advanced to start in the next rotation or issue queue after the last rotation used for VSU instructions according to the first rotation order. For example, if the last rotation used for the current priority instruction type was slice S1 (issue queue 222-2), then the first rotation order for the current instruction cycle is advanced to start at slice S3 (issue queue 222-N) according to the example rotation order discussed above with respect to FIG. 3 . Thus, the first rotation order for this instruction cycle follows a slice order of 3-0-2-1. At the start of the current instruction cycle, a second rotation order for non-priority instruction types is selected to be the opposite of the first rotation order. Thus, in the example described here, the second rotation order follows a slice order of 1-2-0-3. During an instruction cycle, each instruction is routed according to one of the two rotation orders, as discussed above. After each individual instruction, only the rotation order corresponding to the individual instruction is updated. For example, if during an instruction cycle, a given instruction is routed according to the first rotation order, only the first rotation order is updated. Similarly, during an instruction cycle, if a given instruction is routed according to the second rotation order, only the second rotation order is updated.

[0052] At 508, one issue queue of the plurality of issue queues is selected based on the selected rotation order, as discussed above. Additionally, as discussed above, in some embodiments, each issue queue has two slots. In such embodiments, selecting an issue queue includes selecting an issue queue and a slot based on the selected rotation order. At 510, the instruction is dispatched to the selected issue queue. Method 500 then returns to 502 for the next instruction in the instruction cycle. In some embodiments, dispatching the instruction to the selected issue queue includes determining that the selected issue queue is busy and, in response to determining that the selected issue queue is busy, waiting for the selected issue queue to become available, e.g., as described with respect to the exemplary embodiment of FIG. 7. In other embodiments, dispatching the instruction to the selected issue queue includes, in response to determining that the selected issue queue is busy, selecting a next issue queue based on the selected rotation order and dispatching the instruction to the next issue queue, e.g., as described with respect to the exemplary embodiment of FIG. 6.

[0053] 6 is a flow chart depicting another embodiment of an example method 600 for dispatching instructions. Method 600 may be performed by a dispatch unit of a processor core, such as dispatch unit 612 discussed above. It should be understood that the order of actions in example method 600 is provided for illustrative purposes, and that the method may be performed in a different order in other embodiments. Likewise, it should be understood that in other embodiments, some actions may be omitted or additional actions may be included.

[0054] At 602, an instruction is received for dispatch to one of a plurality of issue queues. For example, in each cycle, multiple instructions may be received from the instruction fetch unit, as described above. One or more of the instructions in each cycle may be designated as priority or best instructions. As discussed above, priority or best instructions are instructions designated as resource-intensive. At 604, a priority status of the instruction is determined. This designation or priority status may be based on the instruction type of the instruction, as discussed above. Additionally, in some embodiments, the priority status of each instruction may be indicated by a bit in a vector received from the instruction fetch unit, as discussed above. Furthermore, as discussed above, the instruction type designated as priority or resource-intensive may be dynamically determined, such as by the instruction fetch unit, on a cycle-by-cycle basis. Additionally, the instruction type designated as priority or resource-intensive may be determined based on historical data of instruction types dispatched in prior cycles, as discussed above.

[0055] At 606, a rotation order is selected based on the priority status. In particular, as discussed above, a first rotation order is associated with priority instructions, and a second rotation order, different from the first rotation order, is associated with non-priority instructions. The second rotation order can be the opposite of the first rotation order. For example, as discussed above, the dispatch unit can track the last rotation or issue queue used for each instruction type. For example, the last rotation or issue queue used for MMA instructions can be issue queue 222-3 (slice S2) in example FIG. 3, and MMA instructions are selected as the priority instruction type for the current instruction cycle. Thus, at the start of the current instruction cycle, the first rotation order associated with priority instructions is advanced to start in the next rotation or issue queue after the last rotation used for MMA instructions according to the first rotation order. For example, if the last rotation used for the current priority instruction type was slice S2 (issue queue 222-3), then the first rotation order for the current instruction cycle is advanced to start at slice S1 (issue queue 222-2) according to the example rotation order discussed above with respect to FIG. 3 . Thus, the first rotation order for this instruction cycle follows a slice order of 1-3-0-2. At the start of the current instruction cycle, a second rotation order for non-priority instruction types is selected to be the opposite of the first rotation order. Thus, in the example described here, the second rotation order follows a slice order of 2-0-3-1. During an instruction cycle, each instruction is routed according to one of the two rotation orders, as discussed above. After each individual instruction, only the rotation order corresponding to the individual instruction is updated. For example, if during an instruction cycle, a given instruction is routed according to the first rotation order, only the first rotation order is updated. Similarly, during an instruction cycle, if a given instruction is routed according to the second rotation order, only the second rotation order is updated.

[0056] At 608, an issue queue of the plurality of issue queues is selected based on the selected rotation order, as discussed above. Additionally, as discussed above, in some embodiments, each issue queue has two slots. In such embodiments, selecting an issue queue includes selecting an issue queue and a slot based on the selected rotation order. At 610, it is determined whether the selected issue queue is busy or unavailable. If the selected issue queue is not busy, the instruction is dispatched to the selected issue queue at 612.

[0057] In some embodiments, if the selected issue queue is busy, then at block 614 it is determined whether there are more issue queues to check. In other words, at block 614 it is determined whether all of the issue queues have already been checked to determine whether there are available issue queues. If there are no more issue queues to check, then in some embodiments, method 600 stops dispatching instructions for that instruction cycle at block 616. If there are one or more issue queues to check, then method 600 returns to block 608 and selects the next issue queue in the rotation order selected at block 608. If the next issue queue in the selected rotation is not busy at block 610, then the instruction is dispatched to the next issue queue at block 612, and method 600 returns to 602 for the next instruction in the cycle.

[0058] 7 is a flow chart illustrating another embodiment of an example method 600 for dispatching instructions. Method 700 may be performed by a dispatch unit of a processor core, such as dispatch unit 712 discussed above. It should be understood that the order of actions in example method 700 is provided for illustrative purposes, and that the method may be performed in a different order in other embodiments. Likewise, it should be understood that in other embodiments, some actions may be omitted or additional actions may be included.

[0059] At 702, an instruction is received for dispatch to one of a plurality of issue queues. For example, in each cycle, multiple instructions may be received from the instruction fetch unit, as described above. One or more of the instructions in each instruction cycle may be designated as priority or best instructions. As discussed above, priority or best instructions are instructions designated as resource-intensive. At 704, a priority status of the instruction is determined. This designation or priority status may be based on the instruction type of the instruction, as discussed above. Additionally, in some embodiments, the priority status of each instruction may be indicated by a bit in a vector received from the instruction fetch unit, as discussed above. Furthermore, as discussed above, the instruction type designated as priority or resource-intensive may be dynamically determined, such as by the instruction fetch unit, on a cycle-by-cycle basis. Additionally, the instruction type designated as priority or resource-intensive may be determined based on historical data of instruction types dispatched in prior cycles, as discussed above.

[0060] At 706, a rotation order is selected based on the priority status. In particular, as discussed above, a first rotation order is associated with priority instructions, and a second rotation order, different from the first rotation order, is associated with non-priority instructions. The second rotation order can be the opposite of the first rotation order. For example, as discussed above, the dispatch unit can track the last rotation or issue queue used for each instruction type. For example, the last rotation or issue queue used for L / S instructions can be issue queue 222-1 (slice S0) in example FIG. 3, and L / S instructions are selected as the priority instruction type for the current instruction cycle. Thus, at the start of the current instruction cycle, the first rotation order associated with priority instructions is advanced to start in the next rotation or issue queue after the last rotation used for L / S instructions according to the first rotation order. For example, if the last rotation used for the current priority instruction type was slice S0 (issue queue 222-1), then the first rotation order for the current instruction cycle is advanced to start at slice S2 (issue queue 222-3) according to the example rotation order discussed above with respect to FIG. 3 . Thus, the first rotation order for this instruction cycle follows a slice order of 2-1-3-0. At the start of the current instruction cycle, a second rotation order for non-priority instruction types is selected to be the opposite of the first rotation order. Thus, in the example described here, the second rotation order follows a slice order of 0-3-1-2. During an instruction cycle, each instruction is routed according to one of the two rotation orders, as discussed above. After each individual instruction, only the rotation order corresponding to the individual instruction is updated. For example, if during an instruction cycle, a given instruction is routed according to the first rotation order, only the first rotation order is updated. Similarly, during an instruction cycle, if a given instruction is routed according to the second rotation order, only the second rotation order is updated.

[0061] At 708, an issue queue of the plurality of issue queues is selected based on the selected rotation order, as discussed above. Additionally, as discussed above, in some embodiments, each issue queue has two slots. In such embodiments, selecting an issue queue includes selecting an issue queue and a slot based on the selected rotation order. At 710, it is determined whether the selected issue queue is busy or unavailable. If the selected issue queue is not busy, the instruction is dispatched to the selected issue queue at 712.

[0062] If the selected issue queue is busy, then at block 714, it is determined whether forced rotation is on for the given instruction type. For example, as discussed above, a bit may be set to indicate that rotation should be forced for the given instruction type. If forced rotation is on at block 714, then at block 716, the dispatch unit waits until the selected issue queue becomes available. As discussed above, in some embodiments, a time limit may be applied to limit the amount of time the dispatch unit waits for the selected issue queue. Once the selected issue queue becomes available, the instruction is dispatched to the selected issue queue at block 712. If forced rotation is turned off for the given instruction type at block 714, then method 700 returns to block 708, where the next issue queue in the selected rotation order is selected, and then method 700 proceeds to block 710 to determine whether the next issue queue in the rotation is busy. If the next issue queue is not busy, then the instruction is dispatched to the next issue queue at block 714. The method 700 then returns to 702 for the next instruction in the instruction cycle.

[0063] Thus, through the techniques described herein, in a cycle, each of a plurality of instructions is dispatched using one of two different rotation orders based on the priority status of the individual instructions. In particular, each of one or more instructions designated as resource-intensive or prioritized is dispatched to a respective one of a plurality of issue queues according to a first rotation order, and each of one or more instructions designated as non-resource-intensive or non-prioritized is dispatched to a respective one of a plurality of issue queues according to a second rotation order. As discussed herein, dispatching instructions using two different rotation orders for prioritized and non-prioritized instructions improves the processor core's ability to distribute workload evenly across issue queues and execution units, thereby improving performance compared to conventional processors and systems.

[0064] Illustrative Embodiments Example 1 includes a method including receiving an instruction to dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order different from the first rotation order is associated with non-priority instructions; selecting one issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

[0065] Example 2 includes the method of example 1, wherein determining the priority status of the instruction includes checking a bit corresponding to the instruction in a vector received from the instruction fetch unit.

[0066] Example 3 includes the method of example 1 or 2, wherein determining the priority status of the instructions is based on an instruction type of the instructions, one instruction type is designated as preferred and at least one instruction type is designated as non-preferred, the first rotation order is adjusted to start at the next issue queue in the first rotation order after the last used issue queue for the instruction type designated as preferred, and the second rotation order is adjusted to be opposite to the first rotation order.

[0067] Example 4 includes the method of example 3, in which the instruction types designated as preferred are dynamically determined on a cycle-by-cycle basis.

[0068] Example 5 includes the method of example 3 or 4, wherein the instruction type designated as preferred is determined based on historical data of instruction types dispatched in prior cycles.

[0069] Example 6 includes the method of any one of examples 1 to 5, wherein each issue queue has two slots, and selecting an issue queue includes selecting the issue queue and the slots based on a selected rotation order.

[0070] Example 7 includes the method of any one of Examples 1 to 6, wherein dispatching the instruction to the selected issue queue further includes determining that the selected issue queue is busy, and in response to determining that the selected issue queue is busy, waiting until the selected issue queue becomes available.

[0071] Example 8 includes the method of any one of Examples 1 to 7, where dispatching instructions to the selected issue queue further includes determining that the selected issue queue is busy, and in response to determining that the selected issue queue is busy, selecting a next issue queue based on the selected rotation order, and dispatching instructions to the next issue queue.

[0072] Example 9 includes a method that includes receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; dispatching each of the one or more instructions designated as resource-intensive to a respective one of a plurality of issue queues according to a first rotation order; and dispatching each of the one or more instructions designated as non-resource-intensive to a respective one of the plurality of issue queues according to a second rotation order that is opposite to the first rotation order.

[0073] Example 10 includes the method of Example 9, further including tracking the position in the first rotation order and the position in the second rotation order for use in subsequent cycles.

[0074] Example 11 includes the method of example 9 or 10, wherein the plurality of issue queues are divided into a first group and a second group that operates independently of the first group, and each of the first group and the second group is associated with both an individual first rotation order for resource-intensive instructions and an individual second rotation order for non-resource-intensive instructions.

[0075] Example 12 includes the method of any one of examples 9 to 11, wherein at least two of the plurality of instructions are paired instructions, the method further including pairing each of the unpaired instructions with another unpaired instruction, wherein dispatching each of the one or more instructions designated as resource-intensive includes dispatching each of the one or more instructions designated as resource-intensive with another instruction of the plurality of instructions according to a first rotation order, and wherein dispatching each of the one or more instructions designated as non-resource-intensive includes pairing each of the one or more instructions designated as non-resource-intensive with another non-resource-intensive instruction according to a second rotation order.

[0076] Example 13 includes a processor comprising an instruction fetch unit, a dispatch unit communicatively coupled to the instruction fetch unit, and a plurality of issue queues communicatively coupled to the dispatch unit, wherein the dispatch unit is configured to: receive the plurality of instructions from the instruction fetch unit, determine an individual priority status for each of the plurality of instructions, select a rotation order for each of the plurality of instructions based on the individual priority status, wherein a first rotation order is associated with prioritized instructions and a second rotation order different from the first rotation order is associated with non-prioritized instructions, select a respective issue queue of the plurality of issue queues for each of the plurality of instructions based on the respective selected rotation order, and dispatch each of the plurality of instructions to the respective selected issue queue.

[0077] Example 14 includes the processor of Example 13, wherein the dispatch unit is configured to determine a priority status for each of the plurality of instructions by checking a bit corresponding to each instruction in the vector received from the instruction fetch unit.

[0078] Example 15 includes the processor of example 13 or 14, wherein the instruction fetch unit is configured to determine an individual priority status for each instruction based on the individual instruction type of each instruction.

[0079] Example 16 includes a processor described in any one of Examples 13 to 15, wherein the instruction fetch unit is configured to dynamically determine the instruction types designated as preferred on a cycle-by-cycle basis.

[0080] Example 17 includes a processor described in any one of Examples 13 to 16, wherein the instruction fetch unit is configured to determine the instruction type designated as preferred based on historical data of instruction types dispatched in previous cycles.

[0081] Example 18 includes the processor of any one of Examples 13 to 17, wherein each issue queue of the plurality of issue queues has two slots, and wherein selecting an individual issue queue of the plurality of issue queues for each of the plurality of instructions includes selecting the individual issue queue and slot based on the individual selected rotation order.

[0082] Example 19 includes the processor of any one of Examples 13 to 18, wherein the dispatch unit is further configured to determine that, for a given one of the plurality of instructions, a respective selected issue queue is busy and wait to dispatch the given one of the plurality of instructions until the respective selected issue queue becomes available.

[0083] Example 20 includes the processor of any one of Examples 13 to 19, wherein the dispatch unit is further configured to: determine, for a given one of the plurality of instructions, that the respective selected issue queue is busy; and, in response to determining that the respective selected issue queue is busy, select a next issue queue based on the respective selected rotation order; and dispatch the given one of the plurality of instructions to the next issue queue.

[0084] Example 21 includes a computer system comprising: a memory configured to store program code; and a processor communicatively coupled to the memory and configured to execute the program code. The processor comprises an instruction fetch unit, a dispatch unit communicatively coupled to the instruction fetch unit, and a plurality of issue queues communicatively coupled to the dispatch unit. The dispatch unit is configured to receive a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive, dispatch each of the one or more instructions designated as resource-intensive to a respective one of the plurality of issue queues according to a first rotation order, and dispatch each of the one or more instructions designated as non-resource-intensive to a respective one of the plurality of issue queues according to a second rotation order that is opposite to the first rotation order.

[0085] Example 22 includes the computer system of example 21, wherein the dispatch unit is further configured to track the position in the first rotation order and the position in the second rotation order for use in subsequent cycles.

[0086] Example 23 includes the computer system of example 21 or 22, wherein the multiple issue queues are divided into a first group and a second group that operates independently of the first group, and each of the first group and the second group is associated with both an individual first rotation order for resource-intensive instructions and an individual second rotation order for non-resource-intensive instructions.

[0087] Example 24 includes the computer system of any one of Examples 21 to 23, wherein at least two of the plurality of instructions are paired instructions, and the dispatch unit is further configured to dispatch the plurality of instructions in pairs such that each of one or more instructions designated as resource-intensive is dispatched with another instruction of the plurality of instructions according to a first rotation order, and such that each of one or more instructions designated as non-resource-intensive that are paired with another instruction designated as non-resource-intensive is dispatched according to a second rotation order.

[0088] Example 25 includes a computer system described in any one of Examples 21 to 24, wherein the instruction fetch unit is configured to dynamically determine the instruction types designated as resource intensive on a cycle-by-cycle basis.

[0089] While specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. It is manifestly intended, therefore, that this invention be limited only by the claims and equivalents thereof.

Claims

1. A method of processing a program comprising: receiving, by a processor, an instruction to be dispatched to one of a plurality of issue queues; determining, by a processor, a priority status of said instruction; selecting, by a processor, a rotation order based on the priority status, wherein a first rotation order is associated with prioritized instructions and a second rotation order different from the first rotation order is associated with non-prioritized instructions; selecting, by a processor, an issue queue from the plurality of issue queues based on the selected rotation order; dispatching, by a processor, the instruction to the selected issue queue; A method comprising:

2. 2. The method of claim 1, wherein determining the priority status of the instruction comprises checking a bit corresponding to the instruction in a vector received from an instruction fetch unit.

3. determining the priority status of the instruction based on an instruction type of the instruction; one instruction type is designated as preferred and at least one instruction type is designated as non-preferred; the first rotation order is adjusted to start at the next issue queue in the first rotation order after the last used issue queue for the instruction type designated as preferred; The method of claim 1 , wherein the second rotation order is adjusted to be opposite to the first rotation order.

4. 4. The method of claim 3, wherein the instruction types designated as preferred are determined dynamically on a cycle-by-cycle basis.

5. 4. The method of claim 3, wherein the instruction types designated as preferred are determined based on historical data of instruction types dispatched in prior cycles.

6. Each issue queue has two slots, The method of claim 1 , wherein selecting the issue queue comprises selecting the issue queue and slot based on the selected rotation order.

7. Dispatching the instruction to the selected issue queue determining that the selected issue queue is busy; in response to determining that the selected issue queue is busy, waiting until the selected issue queue becomes available; The method of claim 1 further comprising:

8. Dispatching the instruction to the selected issue queue determining that the selected issue queue is busy; responsive to determining that the selected issue queue is busy, selecting a next issue queue based on the selected rotation order; dispatching the instruction to the next issue queue; The method of claim 1 further comprising:

9. receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive, the resource-intensive instructions being priority instructions and the non-resource-intensive instructions being non-priority instructions; dispatching each of the one or more instructions designated as resource intensive to a respective one of a plurality of issue queues according to the first rotation order; dispatching each of the one or more instructions designated as non-resource intensive to a respective one of the plurality of issue queues according to the second rotation order, the second rotation order being opposite to the first rotation order; The method of claim 1 , comprising:

10. 10. The method of claim 9, further comprising tracking a position in the first rotation order and a position in the second rotation order for use in subsequent cycles.

11. the plurality of issue queues are divided into a first group and a second group that operates independently of the first group; 10. The method of claim 9, wherein each of the first group and the second group is associated with both a respective first rotation order for resource-intensive instructions and a respective second rotation order for non-resource-intensive instructions.

12. at least two of the plurality of instructions are paired instructions; the method further comprising pairing each unpaired instruction with another unpaired instruction; dispatching each of the one or more instructions designated as resource-intensive includes dispatching each of the one or more instructions designated as resource-intensive with another instruction of the plurality of instructions in accordance with the first rotation order; 10. The method of claim 9, wherein dispatching each of the one or more instructions designated as non-resource intensive comprises pairing each of the one or more instructions designated as non-resource intensive with another non-resource intensive instruction and dispatching it according to the second rotation order.

13. A method of receiving, by a processor, a plurality of instructions in a single cycle, the plurality of instructions including one or more instructions designated as resource intensive and one or more instructions designated as non-resource intensive; dispatching, by the processor, each of the one or more instructions designated as resource-intensive to a respective one of a plurality of issue queues according to a first rotation order; dispatching, by the processor, each of the one or more instructions designated as non-resource intensive to a respective one of the plurality of issue queues according to a second rotation order that is opposite to the first rotation order; A method comprising:

14. 14. The method of claim 13, further comprising tracking a position in the first rotation order and a position in the second rotation order for use in subsequent cycles.

15. the plurality of issue queues are divided into a first group and a second group that operates independently of the first group; 14. The method of claim 13, wherein each of the first group and the second group is associated with both a respective first rotation order for resource-intensive instructions and a respective second rotation order for non-resource-intensive instructions.

16. at least two of the plurality of instructions are paired instructions; the method further comprising pairing each unpaired instruction with another unpaired instruction; dispatching each of the one or more instructions designated as resource-intensive includes dispatching each of the one or more instructions designated as resource-intensive with another instruction of the plurality of instructions in accordance with the first rotation order; 14. The method of claim 13, wherein dispatching each of the one or more instructions designated as non-resource intensive comprises pairing each of the one or more instructions designated as non-resource intensive with another non-resource intensive instruction and dispatching it according to the second rotation order.

17. an instruction fetch unit; a dispatch unit communicatively connected to the instruction fetch unit; a plurality of issue queues communicatively connected to the dispatch unit; wherein the dispatch unit receiving a plurality of instructions from the instruction fetch unit; determining an individual priority status for each of the plurality of instructions; selecting a rotation order for each of the plurality of instructions based on the individual priority status, wherein a first rotation order is associated with prioritized instructions and a second rotation order different from the first rotation order is associated with non-prioritized instructions; selecting a respective issue queue of the plurality of issue queues for each of the plurality of instructions based on the respective selected rotation order; dispatching each of the plurality of instructions to the respective selected issue queue; a processor configured to:

18. 18. The processor of claim 17, wherein the dispatch unit is configured to determine the priority status of each of the plurality of instructions by checking a bit corresponding to each instruction in a vector received from the instruction fetch unit.

19. 18. The processor of claim 17, wherein the instruction fetch unit is configured to determine the individual priority status of each instruction based on each instruction's individual instruction type.

20. 20. The processor of claim 19, wherein the instruction fetch unit is configured to dynamically determine on a cycle-by-cycle basis which instruction types are designated as preferred.

21. 20. The processor of claim 19, wherein the instruction fetch unit is configured to determine the instruction types designated as preferred based on historical data of instruction types dispatched in prior cycles.

22. each issue queue of the plurality of issue queues having two slots; 18. The processor of claim 17, wherein selecting the respective issue queue of the plurality of issue queues for each of the plurality of instructions comprises selecting the respective issue queue and slot based on the respective selected rotation order.

23. 18. The processor of claim 17, wherein the dispatch unit is further configured to: determine, for a given one of the plurality of instructions, that the respective selected issue queue is busy; and wait to dispatch the given one of the plurality of instructions until the respective selected issue queue becomes available.

24. 18. The processor of claim 17, wherein the dispatch unit is further configured to: determine, for a given one of the plurality of instructions, the respective selected issue queue is busy; and, in response to determining the respective selected issue queue is busy, select a next issue queue based on the respective selected rotation order; and dispatch the given one of the plurality of instructions to the next issue queue.

25. The dispatch unit: receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive, the resource-intensive instructions being priority instructions and the non-resource-intensive instructions being non-priority instructions; dispatching each of the one or more instructions designated as resource intensive to a respective one of the plurality of issue queues according to the first rotation order; dispatching each of the one or more instructions designated as non-resource intensive to a respective one of the plurality of issue queues according to the second rotation order, the second rotation order being opposite to the first rotation order; 20. The processor of claim 17 configured to:

26. 26. The processor of claim 25, wherein the dispatch unit is further configured to track a position in the first rotation order and a position in the second rotation order for use in subsequent cycles.

27. the plurality of issue queues are divided into a first group and a second group that operates independently of the first group; 26. The processor of claim 25, wherein each of the first group and the second group is associated with both a respective first rotation order for resource-intensive instructions and a respective second rotation order for non-resource-intensive instructions.

28. at least two of the plurality of instructions are paired instructions; 26. The processor of claim 25, wherein the dispatch unit is further configured to dispatch the plurality of instructions in pairs such that each of the one or more instructions designated as resource-intensive is dispatched with another instruction of the plurality of instructions according to the first rotation order, and such that each of the one or more instructions designated as non-resource-intensive that is paired with another instruction designated as non-resource-intensive is dispatched according to the second rotation order.

29. 26. The processor of claim 25, wherein the instruction fetch unit is configured to dynamically determine on a cycle-by-cycle basis which instruction types are designated as resource-intensive.

30. a memory configured to store program code; a processor communicatively coupled to the memory and configured to execute the program code, the processor comprising: an instruction fetch unit; a dispatch unit communicatively connected to the instruction fetch unit; a plurality of issue queues communicatively connected to the dispatch unit; the processor, Equipped with The dispatch unit: receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource-intensive and one or more instructions designated as non-resource-intensive; dispatching each of the one or more instructions designated as resource intensive to a respective one of the plurality of issue queues according to a first rotation order; dispatching each of the one or more instructions designated as non-resource intensive to a respective one of the plurality of issue queues according to a second rotation order that is opposite to the first rotation order; A computer system configured to:

31. 31. The computer system of claim 30, wherein the dispatch unit is further configured to track a position in the first rotation order and a position in the second rotation order for use in subsequent cycles.

32. the plurality of issue queues are divided into a first group and a second group that operates independently of the first group; 31. The computer system of claim 30, wherein each of the first group and the second group is associated with both a respective first rotation order for resource-intensive instructions and a respective second rotation order for non-resource-intensive instructions.

33. at least two of the plurality of instructions are paired instructions; 31. The computer system of claim 30, wherein the dispatch unit is further configured to dispatch the plurality of instructions in pairs such that each of the one or more instructions designated as resource-intensive is dispatched with another instruction of the plurality of instructions according to the first rotation order, and such that each of the one or more instructions designated as non-resource-intensive that is paired with another instruction designated as non-resource-intensive is dispatched according to the second rotation order.

34. 31. The computer system of claim 30, wherein the instruction fetch unit is configured to dynamically determine on a cycle-by-cycle basis the instruction types designated as resource-intensive.

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