Electronic device and control method

Abstract

To control power-saving mode of a memory to be switched for each period of a predetermined time unit.SOLUTION: An electronic device includes: a memory; a plurality of bus masters which issues access requests to the memory; a memory controller which controls accesses to the memory in response to the access requests and operation mode of the memory; and mode control means which outputs, when the total amount of transfer to the memory using the bus masters in a period, the amount being calculated for each period of a predetermined unit time, is smaller than a threshold, a signal to switch the operation mode of the memory in the period to power-saving mode, to the memory controller.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electronic device and a control method. [Background technology]

[0002] Patent Document 1 describes a method for guaranteeing a predetermined amount of data transfer per unit time for each of multiple bus masters that share a memory. Patent Document 2 describes a method for reducing power consumption by setting a power-saving mode for a DRAM (Dynamic Random Access Memory) provided in an electronic device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-95966 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-133638 Summary of the Invention [Problem to be solved by the invention]

[0004] However, Patent Document 1 does not describe power saving mode control for memory. Patent Document 2 does not control switching of power saving mode for DRAM included in an electronic device for each processing period divided into predetermined time units.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to enable switching control of a power saving mode for a memory for each period divided into predetermined time units. [Means for solving the problem]

[0006] The electronic device of the present invention comprises a memory, a plurality of bus masters that make access requests to the memory, a memory controller that controls access to the memory in response to the access requests and the operating mode of the memory, and mode control means that, when the total amount of data transferred to the memory by the plurality of bus masters during a period calculated for each predetermined time unit is smaller than a threshold, outputs a signal to the memory controller to switch the operating mode of the memory during that period to a power saving mode. [Effects of the Invention]

[0007] According to the present invention, it is possible to control switching of the power saving mode for the memory for each period divided into predetermined time units. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating components of an electronic device according to a first embodiment. [Figure 2] FIG. 10 is a diagram illustrating command overhead. [Figure 3] FIG. 10 is a diagram illustrating overhead in a power saving mode. [Figure 4] FIG. 2 is a diagram for explaining slot control in the first embodiment. [Figure 5] 6 is a flowchart illustrating an example of a mode control process in the first embodiment. [Figure 6] FIG. 10 is a block diagram illustrating components of an electronic device according to a second embodiment. [Figure 7] FIG. 10 is a diagram illustrating data transfer in an encoding unit according to the second embodiment. [Figure 8] 10 is a flowchart illustrating an example of a process for generating a bandwidth control signal in the second embodiment. [Figure 9] 10 is a flowchart illustrating an example of a mode control process in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

[0010] [Embodiment 1] FIG. 1 is a block diagram illustrating components of an electronic device according to a first embodiment. The electronic device according to the first embodiment is, for example, an electronic device capable of operating as an imaging device. The electronic device according to the first embodiment includes an image sensor 100, a recording medium 101, an image processing unit 102, a development processing unit 103, an encoding unit 104, a slot information generating unit 105, and a synchronization signal generating unit 106. The electronic device according to the first embodiment also includes a slot control unit A 107, a slot control unit B 108, a slot control unit C 109, an arbitration unit 110, a mode control unit 111, a memory controller 112, a memory (DRAM) 113, and a CPU 114. The electronic device according to the first embodiment is not limited to the components shown in FIG. 1 and may include other components.

[0011] The image sensor 100 captures an optical image of a subject and generates image data. The image sensor 100 generates image data from the optical image of the subject by being driven based on a synchronization signal generated by a synchronization signal generator 106. The image processing unit 102 performs imaging processing such as defective pixel correction and shading processing on the image data generated by the image sensor 100. The image data captured and processed by the image processing unit 102 is recorded in memory 113 via a slot control unit A 107, an arbitration unit 110, and a memory controller 112.

[0012] The development processing unit 103 reads the image data after imaging processing that is recorded in the memory 113 via the memory controller 112, the arbitration unit 110, and the slot control unit B108, and performs development processing on the read image data. Development processing refers to pixel interpolation processing, filter processing, resizing processing such as reduction, and color conversion processing. Color conversion processing includes, for example, conversion to a YCbCr format, which is a format suitable for saving compressed image data. After processing, the image data developed by the development processing unit 103 is recorded in the memory 113 via the slot control unit B108, the arbitration unit 110, and the memory controller 112.

[0013] The encoding unit 104 reads the developed image data from the memory 113 via the memory controller 112, the arbitration unit 110, and the slot control unit C109, and performs compression and encoding processing such as H.264 on the read image data. The encoding unit 104 records the compressed and encoded image data on the recording medium 101, for example. The recording medium 101 is a recording medium such as an SD memory card (Secure Digital Memory Card). Note that, although the imaging processing unit 102, the development processing unit 103, and the encoding unit 104 are shown as examples of functional units that process image data in the first embodiment, the electronic device may also have other functional units that process image data.

[0014] A CPU (Central Processing Unit) 114 controls the components of the electronic device. The CPU 114 sets operating parameters and the like in the electronic device, for example, by executing a program. For example, the CPU 114 sets slot period information in the slot information generation unit 105. The CPU 114 also sets transfer rate upper limits for the imaging processing unit 102, development processing unit 103, and encoding unit 104, which are bus masters, in the slot information generation unit 105 for each slot period. Here, a slot refers to a period divided into fixed time units.

[0015] The slot information generation unit 105 generates slot periods that divide a processing period into predetermined time units based on the synchronization signal from the synchronization signal generation unit 106 and slot period information set by the CPU 114. The slot information generation unit 105 also generates a start signal for each slot period and outputs it to the mode control unit 111. The slot information generation unit 105 outputs an upper limit value for the transfer amount for each slot period to the imaging processing unit 102, development processing unit 103, and encoding unit 104, which are bus masters.

[0016] The slot control unit A107, slot control unit B108, and slot control unit C109 perform bandwidth control for the corresponding bus masters. Bandwidth control here refers to transmitting or stopping access requests from the corresponding bus masters to the arbitration unit 110. The slot control unit A107 performs bandwidth control for the imaging processing unit 102, which is the corresponding bus master, and the slot control unit B108 performs bandwidth control for the development processing unit 103, which is the corresponding bus master. The slot control unit C109 performs bandwidth control for the encoding unit 104, which is the corresponding bus master.

[0017] The slot control unit A107, slot control unit B108, and slot control unit C109 each receive a slot period and a transfer rate upper limit value (first transfer rate upper limit value) for each slot period from the slot information generation unit 105. Furthermore, the slot control unit A107, slot control unit B108, and slot control unit C109 calculate the transfer rates of the imaging processing unit 102, development processing unit 103, and encoding unit 104, which are their corresponding bus masters, for each slot period. When the calculated transfer rates reach the transfer rate upper limit value, the slot control unit A107, slot control unit B108, and slot control unit C109 perform bandwidth limitation control on the corresponding bus master.

[0018] The arbitration unit 110 arbitrates the access requests of the respective bus masters. The arbitration unit 110 arbitrates the requests from the corresponding bus masters transmitted from the slot control unit A 107, the slot control unit B 108, and the slot control unit C 109, and outputs the access requests to the memory controller 112.

[0019] The mode control unit 111 receives inputs of the slot period and the upper limit of the transfer rate of each bus master for each slot period from the slot information generation unit 105. Based on the information received from the slot information generation unit 105, the mode control unit 111 calculates the total transfer rate for each slot period, including command overhead. The mode control unit 111 also compares the total transfer rate for each slot period with the memory bandwidth, generates a switching signal for the operation mode of the memory 113, and outputs the switching signal to the memory controller 112. This switching signal is a signal for switching the operation mode of the memory 113 between a normal mode and a power-saving mode. Here, the power-saving mode of the memory 113 refers to, for example, Self Refresh Power Down, as defined by the Joint Electron Device Engineering Council (JEDEC). The memory bandwidth refers to the amount of data that the memory can process per unit time, and is expressed, for example, in bits per second (bps).

[0020] The memory controller 112 controls access to the memory 113. The memory controller 112 generates and issues a command to the memory 113 based on an access request from the arbitration unit 110. The memory controller 112 also inputs and outputs data to and from the memory 113 in accordance with the command issued to the memory 113. The memory controller 112 also controls the operation mode of the memory 113 based on a switching signal from the mode control unit 111, and switches between a normal mode and a power saving mode. The memory 113 is a memory that stores data, and is, for example, a DRAM (Dynamic Random Access Memory).

[0021] 2 and 3, a command overhead and a power saving mode overhead in accessing the memory 113 will be described below. The following description will be given assuming that the memory 113 is a DRAM.

[0022] 2 shows an example of commands, data, and memory states for memory 113 during normal data transfer. Generally, when transferring data to or from a DRAM, memory controller 112 issues to memory 113 an activate command (ACT) 201 that specifies a row address and activates a specific bank or row. Next, memory controller 112 issues to memory 113 a column command (WR / RD) 202 that specifies a column address. Thereafter, memory controller 112 transfers data to and from memory 113. Finally, after the transfer data is completed, memory controller 112 issues to memory 113 a precharge command (PRE) 203 that closes the bank or row that was activated by the activate command (ACT), thereby realizing the data transfer.

[0023] Here, when executing a data transfer, as shown in Figure 2, data transfer cannot be performed during the period when a command is issued to memory 113, and therefore the memory bandwidth cannot be used. This period is called command overhead, and a certain amount of time is required for the command overhead period when accessing memory. Therefore, the transfer time to memory 113 is the sum of the transfer data time during which data is being transferred and the command overhead time.

[0024] 3 shows an example of commands, data, memory states, and power saving periods for memory 113 when memory 113 is in power saving mode. When there is no data transfer request to memory 113, memory controller 112 issues a power saving mode entry command (command A) 301 to memory 113 to set the power saving mode of memory 113. Furthermore, when there is a data transfer request to memory 113 while memory 113 is in power saving mode, memory controller 112 issues a power saving mode release command (command B) 302 to memory 113 to release the power saving mode of memory 113.

[0025] When the memory 113 transitions between power saving modes, there is a period during which the memory device is inaccessible during the mode transition time. Therefore, the time it takes to enter and exit the power saving mode can also be considered command overhead, as shown in Figure 3. Data transfer to the memory 113 while the memory 113 is in the power saving mode requires additional command overhead time, equivalent to the time it takes to enter and exit the power saving mode, compared to normal data transfer, which impedes memory bandwidth.

[0026] As described above, in order to control the power saving mode of the memory 113 without causing a processing failure in various operation modes of the electronic device, it is necessary to take into consideration the command overhead caused by transition to the power saving mode.

[0027] Next, slot control of the electronic device in embodiment 1 will be described with reference to Fig. 4. Fig. 4 is a diagram showing an example of bandwidth control and setting of normal mode and power saving mode performed for each slot period in embodiment 1. Fig. 4 shows an example in which the processing period between synchronization signals (401) generated by the synchronization signal generating unit 106 is divided into five slot periods, slot period 1 to slot period 5, by dividing the processing period between synchronization signals (401) generated by the synchronization signal generating unit 106 into predetermined time units.

[0028] The slot transfer amount A (402) is the sum of the upper limit of the transfer amount per slot period (first upper limit of the transfer amount) of the image capture processing unit 102 and the transfer amount that can be transferred in the command overhead period. The value of the slot transfer amount A (402) shown in Fig. 4 indicates the ratio of the slot transfer amount A (402) when the memory bandwidth is 100%.

[0029] The slot transfer amount B (403) is the sum of the transfer amount upper limit (first transfer amount upper limit) for each slot period of the development processing unit 103 and the transfer amount that can be transferred in a command overhead period. The value of the slot transfer amount B (403) shown in Fig. 4 indicates the ratio of the slot transfer amount B (403) when the memory bandwidth is 100%.

[0030] The slot transfer amount C(404) is the sum of the upper limit of the transfer amount per slot period (first upper limit of the transfer amount) of the encoding unit 104 and the transfer amount that can be transferred in the command overhead period. The value of the slot transfer amount C(404) shown in Fig. 4 indicates the ratio of the slot transfer amount C(404) when the memory bandwidth is 100%.

[0031] The total transfer amount (405) indicates the sum of the slot transfer amount A (402), the slot transfer amount B (403), and the slot transfer amount C (404) in each slot period.

[0032] The power saving mode (406) determines whether the operating mode of the memory 113 is to be in the power saving mode (ON) or not (OFF, normal mode) based on the total transfer volume (405) for the slot period and a total transfer volume threshold. The total transfer volume threshold is the memory 113's limit bandwidth for each slot period, taking into account command overhead related to the transition to the power saving mode. The total transfer volume threshold is held in the mode control unit 111. In the first embodiment, the total transfer volume threshold is set to 80%. The mode control unit 111 determines to switch to the power saving mode (turn the power saving mode ON) if the total transfer volume (405) is less than 80%, and determines to switch to the normal mode (turn the power saving mode OFF) instead of the power saving mode if the total transfer volume (405) for the slot period is 80% or more.

[0033] Next, a mode control process for memory 113 in an electronic device will be described with reference to the flowchart of Fig. 5. Fig. 5 is a flowchart for explaining an example of a mode control process for memory 113 in an electronic device. The process of the flowchart shown in Fig. 5 is executed by mode control unit 111 for each slot period.

[0034] In step S501, mode control unit 111 is in a state of waiting to receive a slot period start signal from slot information generation unit 105. In step S501, when mode control unit 111 receives a slot period start signal from slot information generation unit 105 (YES in step S501), it proceeds to step S502.

[0035] In step S502, the mode control unit 111 calculates the total transfer amount for the current slot period (current slot period) including the command overhead based on the transfer amount upper limit value (first transfer amount upper limit value) of each bus master input from the slot information generation unit 105. After calculating the total transfer amount, the mode control unit 111 proceeds to step S503.

[0036] In step S503, the mode control unit 111 compares the total transfer amount calculated in step S502 with the total transfer amount threshold stored therein to determine whether the total transfer amount is smaller than the total transfer amount threshold. If it is determined that the total transfer amount is smaller than the total transfer amount threshold (YES in step S503), the mode control unit 111 proceeds to step S504. If it is determined that the total transfer amount is not smaller than the total transfer amount threshold (NO in step S503), the mode control unit 111 proceeds to step S505.

[0037] For example, if the total transfer volume threshold is 80%, then in slot period 1 shown in Fig. 4, the total transfer volume is 90%, which is equal to or greater than the total transfer volume threshold (NO in step S503), so the mode control unit 111 proceeds to step S505. Also, for example, in slot period 2 shown in Fig. 4, the total transfer volume is 70%, which is less than the total transfer volume threshold (YES in step S503), so the mode control unit 111 proceeds to step S504.

[0038] In step S504, the mode control unit 111 generates a switching signal to set the memory 113 to the power saving mode during the current slot period, and outputs the signal to the memory controller 112. Based on this switching signal, the memory controller 112 sets the operation mode of the memory 113 to the power saving mode during the current slot period, and ends the process.

[0039] In step S505, the mode control unit 111 generates a switching signal to set the memory 113 to the normal mode during the current slot period, and outputs the signal to the memory controller 112. Based on this switching signal, the memory controller 112 sets the operation mode of the memory 113 to the normal mode during the current slot period, and ends the process.

[0040] According to the first embodiment, the operation mode of the memory 113 is controlled based on the total transfer amount for each slot period, including command overhead, calculated based on the upper limit of the transfer amount of each bus master. This makes it possible to control switching of the power saving mode for the memory 113 for each slot period. Furthermore, it is possible to control the power saving mode of the memory 113 without causing a processing failure in each functional unit of the electronic device, thereby reducing the power consumption of the memory 113.

[0041] [Embodiment 2] In the first embodiment, the memory's operating mode is controlled to switch between normal mode and power-saving mode by comparing the total transfer amount during each slot period with a total transfer amount threshold that takes into account the overhead associated with transitioning to power-saving mode. However, in an electronic device capable of operating as an imaging device, the total transfer amount required varies depending on the captured image data, which can lead to a temporary increase in processing volume. One possible cause of this variation is the encoding process in the electronic device. In the first embodiment, bandwidth control is performed when the transfer amount of the encoding unit reaches the upper limit for the transfer amount during each slot period, which can lead to the device being unable to process the temporarily increased transfer amount. In consideration of this situation, the second embodiment controls the memory's operating mode in accordance with the varying processing.

[0042] FIG. 6 is a block diagram illustrating components of an electronic device according to a second embodiment. In FIG. 6, components identical to those described in FIG. 1 will not be described. The electronic device according to the second embodiment is, for example, an electronic device capable of operating as an imaging device. The electronic device according to the second embodiment includes an image sensor 100, a recording medium 101, an image processing unit 102, a development processing unit 103, an encoding unit 104, a slot information generating unit 105, and a synchronization signal generating unit 106. The electronic device according to the second embodiment also includes a slot control unit A 107, a slot control unit B 108, a slot control unit C 109, an arbitration unit 110, a mode control unit 111, a memory controller 112, a memory (DRAM) 113, and a CPU 114. The electronic device according to the second embodiment further includes a bandwidth control signal generating unit 600. The electronic device according to the second embodiment may include other components in addition to those shown in FIG. 6.

[0043] In the second embodiment, the slot control unit C109 outputs an upper limit reached signal to the bandwidth control signal generation unit 600. The upper limit reached signal is a signal indicating whether or not the transfer volume of the encoding unit 104 has exceeded a first transfer volume upper limit. The slot control unit C109 sets the upper limit reached signal to a high level when the transfer volume of the encoding unit 104 has reached the first transfer volume upper limit, and sets the upper limit reached signal to a low level when the transfer volume of the encoding unit 104 has not reached the first transfer volume upper limit.

[0044] The first upper limit of the transfer rate is a transfer rate upper limit of each bus master for each slot period, which is preset by the CPU 114 in the slot information generation unit 105. In the second embodiment, a second upper limit of the transfer rate is newly set in addition to the first upper limit of the transfer rate. The second upper limit of the transfer rate is preset by the CPU 114 in the slot information generation unit 105. The second upper limit of the transfer rate is a value greater than the first upper limit of the transfer rate and is a value obtained by adding the bandwidth that can be secured by setting the operating mode of the memory 113 to the normal mode to the first upper limit of the transfer rate. The second upper limit of the transfer rate is used for bandwidth control in the slot control unit C109 as a comparison value with the transfer rate of the encoding unit 104 in the slot period following the slot period in which the transfer rate of the encoding unit 104 reaches the first upper limit of the transfer rate. In the second embodiment, the second upper limit of the transfer rate is a value that does not exceed 100% of the total transfer rate, for example, 80 MB.

[0045] The bandwidth control signal generator 600 generates a bandwidth control signal that sets the operation mode of the memory 113 to the normal mode during the current slot period (current slot period) based on the upper limit reached signal input from the slot controller C109. The generated bandwidth control signal is output to the slot controller C109 and the mode controller 111. The bandwidth control signal is set to a high level when the operation mode of the memory 113 during the current slot period is set to the normal mode.

[0046] If the upper limit reached signal is at a high level in the slot period immediately preceding the current slot period (previous slot period), the bandwidth control signal generation unit 600 sets the bandwidth control signal to a high level and sends it to the slot control unit C109 and the mode control unit 111. If the bandwidth control signal from the bandwidth control signal generation unit 600 is at a high level, the slot control unit C109 switches the transfer rate upper limit value for that slot period from the first transfer rate upper limit value to the second transfer rate upper limit value, and performs bandwidth control based on the second transfer rate upper limit value. The mode control unit 111 also references the bandwidth control signal from the bandwidth control signal generation unit 600 to generate an operation mode switching signal for the memory 113 and outputs the signal to the memory controller 112.

[0047] 7A to 7C, the data transfer of the encoding unit 104 in the second embodiment will be described. In the following description, it is assumed that the first upper limit LV1 of the transfer volume in the encoding unit 104 is 30 MB and the second upper limit LV2 of the transfer volume is 80 MB. FIG. 7A shows the transfer volume of the encoding unit 104 when the transfer volume of the encoding process in the second embodiment temporarily increases. FIG. 7A shows an example in which transfer volumes of 0 MB, 60 MB, 70 MB, 20 MB, and 10 MB occur in slot periods 1 to 5, respectively. In slot periods 2 and 3, the transfer volume of the encoding unit 104 exceeds the first upper limit LV1 of the transfer volume.

[0048] 7(B) shows the transfer volume when bandwidth control is performed using only one upper limit value for transfer volume (first upper limit value for transfer volume LV1) for the transfer volume generated as shown in FIG. 7(A) as described in embodiment 1. It shows that transfer volumes of 0 MB, 30 MB, 30 MB, 30 MB, 30 MB, 30 MB, 30 MB, and 10 MB are processed in slot periods 1 to 7, respectively, so as not to exceed the first upper limit value for transfer volume LV1 in each slot period. As shown in FIG. 7(B), in a process such as encoding 104 where the transfer volume temporarily changes significantly, performing bandwidth control using only one upper limit value for transfer volume may result in an extended processing time.

[0049] 7(C) shows the data transfer rate when the data transfer rate during the current slot period reaches the first data transfer rate upper limit in the second embodiment, and the next slot period is processed in normal mode by removing the bandwidth restriction. In slot period 2, the data transfer rate of the encoding unit 104 reaches the first data transfer rate upper limit LV1 (30 MB). Therefore, in slot period 3, the slot control unit C109 performs bandwidth control using the second data transfer rate upper limit LV2. As a result, the data transfer rate of the encoding unit 104 in slot period 3 becomes 80 MB (20 MB), which is the second data transfer rate upper limit LV2. Furthermore, in slot periods 3 and 4, the data transfer rate of the encoding unit 104 reaches the first data transfer rate upper limit LV1. Therefore, in slot periods 4 and 5, the slot control unit C109 performs bandwidth control using the second data transfer rate upper limit LV2. In this way, in slot period 1 to slot period 5, transfer amounts of 0 MB, 30 MB, 80 MB, 40 MB, and 10 MB are processed, respectively.

[0050] As described above, in the second embodiment, a first upper limit value for the transfer amount used in the power saving mode and a second upper limit value for the transfer amount used in the normal mode are provided, which enables the electronic device to switch the operation mode of the memory 113 between the normal mode and the power saving mode without failure even when irregular changes in the transfer amount are required.

[0051] Next, the operation of the band control signal generating unit 600 will be described with reference to the flowchart in Fig. 8. Fig. 8 is a flowchart for explaining an example of the generation process of a band control signal in the band control signal generating unit 600. The process of the flowchart shown in Fig. 8 is executed by the band control signal generating unit 600 for each slot period.

[0052] In step S801, the band control signal generating unit 600 is in a state of waiting to receive a slot period start signal from the slot information generating unit 105. In step S801, when the band control signal generating unit 600 receives a slot period start signal from the slot information generating unit 105 (YES in step S801), the unit proceeds to step S802.

[0053] In step S802, the bandwidth control signal generation unit 600 determines whether the upper limit value reached signal from the slot control unit C109 was at a high level during the previous slot period. If it is determined that the upper limit value reached signal during the previous slot period was at a high level (YES in step S802), the bandwidth control signal generation unit 600 proceeds to step S803. If it is determined that the upper limit value reached signal during the previous slot period was not at a high level (NO in step S802), the bandwidth control signal generation unit 600 ends the process.

[0054] For example, in slot period 2 shown in FIG. 7A, the transfer amount has not reached the first transfer amount upper limit value in the previous slot period (slot period 1). Therefore, the upper limit reached signal in the previous slot period (slot period 1) is low level (NO in step S802), and the bandwidth control signal generation unit 600 ends the process. Also, for example, in slot period 3 shown in FIG. 7A, the transfer amount has reached the first transfer amount upper limit value in the previous slot period (slot period 2). Therefore, the upper limit reached signal in the previous slot period (slot period 2) is high level (YES in step S802), and the bandwidth control signal generation unit 600 proceeds to step S803.

[0055] In step S803, the bandwidth control signal generation unit 600 sets the bandwidth control signal to high level, outputs it to the slot control unit C109 and the mode control unit 111, and ends the process. For example, in slot period 3 shown in Figure 7(A), the transfer amount reached the first transfer amount upper limit value in the previous slot period (slot period 2), so the bandwidth control signal generation unit 600 sets the bandwidth control signal to high level and ends the process.

[0056] Next, a mode control process for memory 113 in an electronic device will be described with reference to the flowchart of Fig. 9. Fig. 9 is a flowchart for explaining an example of a mode control process for memory 113 in an electronic device. The process of the flowchart shown in Fig. 9 is executed by mode control unit 111 for each slot period.

[0057] In step S901, the mode control unit 111 is in a state of waiting to receive a slot period start signal from the slot information generation unit 105. In step S901, when the mode control unit 111 receives a slot period start signal from the slot information generation unit 105 (YES in step S901), the mode control unit 111 proceeds to step S902.

[0058] In step S902, the mode control unit 111 determines whether the bandwidth control signal from the bandwidth control signal generation unit 600 is at a high level. If it is determined that the bandwidth control signal is at a high level (YES in step S902), the mode control unit 111 proceeds to step S906. Note that if the bandwidth control signal is at a high level, the slot control unit C109 performs bandwidth control of the encoding unit 104 based on the second transfer amount upper limit value during this slot period. If it is determined that the bandwidth control signal is not at a high level (NO in step S902), the mode control unit 111 proceeds to step S903.

[0059] In step S903, the mode control unit 111 calculates the total transfer amount for the current slot period, including the command overhead, based on the first transfer amount upper limit value of each bus master input from the slot information generation unit 105. After calculating the total transfer amount, the mode control unit 111 proceeds to step S904.

[0060] In step S904, the mode control unit 111 compares the total transfer amount calculated in step S903 with the total transfer amount threshold stored therein, and determines whether the total transfer amount is smaller than the total transfer amount threshold. If it is determined that the total transfer amount is smaller than the total transfer amount threshold (YES in step S904), the mode control unit 111 proceeds to step S905. If it is determined that the total transfer amount is not smaller than the total transfer amount threshold (NO in step S904), the mode control unit 111 proceeds to step S906.

[0061] In step S905, the mode control unit 111 generates a switching signal to set the memory 113 to the power saving mode during the current slot period, and outputs the signal to the memory controller 112. Based on this switching signal, the memory controller 112 sets the operation mode of the memory 113 to the power saving mode during the current slot period, and ends the process.

[0062] In step S906, the mode control unit 111 generates a switching signal to set the memory 113 to the normal mode during the current slot period, and outputs the signal to the memory controller 112. Based on this switching signal, the memory controller 112 sets the operation mode of the memory 113 to the normal mode during the current slot period, and ends the process.

[0063] According to the second embodiment, as in the first embodiment, it is possible to control switching of the power saving mode for the memory 113 for each slot period. Furthermore, it is possible to control the power saving mode of the memory 113 without causing a processing failure in each functional unit of the electronic device, thereby reducing the power consumption of the memory 113. Furthermore, according to the second embodiment, when the transfer volume of the encoding unit 104 temporarily increases, the upper limit value of the transfer volume in the slot control unit C109 is increased to perform bandwidth control, and the operation mode of the memory 113 for that slot period is set to the normal mode. As a result, the electronic device according to the second embodiment can operate without failure even when the transfer volume of the encoding unit 104 temporarily increases.

[0064] In the above example, it is assumed that the transfer amount of the encoding unit 104 temporarily increases, but this is not limiting, and a similar mechanism may be provided in other processing units (imaging processing unit 102, development processing unit 103) that serve as bus masters. When the transfer amount of at least one bus master reaches the first transfer amount upper limit, the operation mode of the memory 113 may be switched to the normal mode and controlled in the same way as the encoding unit 104 described above.

[0065] [Embodiment 3] At least one of the various functions, processes, and methods described in the above embodiments can also be realized by a personal computer, a microcomputer, a CPU (Central Processing Unit), or a microprocessor executing a program. Hereinafter, in embodiment 3, the personal computer, microcomputer, CPU, or microprocessor will be referred to as "computer X." In embodiment 3, a program for controlling computer X and for realizing at least one of the various functions, processes, and methods described in the above embodiments will be referred to as "program Y."

[0066] At least one of the various functions, processes, and methods described in the above embodiments is realized by computer X executing program Y. In this case, program Y is supplied to computer X via a computer-readable storage medium. The computer-readable storage medium in embodiment 3 includes at least one of a hard disk drive, a magnetic storage device, an optical storage device, a magneto-optical storage device, a memory card, a volatile memory, a non-volatile memory, etc. The computer-readable storage medium in embodiment 3 is a non-transitory storage medium. [Explanation of symbols]

[0067] 100: Image sensor 102: Image processing unit 103: Development processing unit 107, 108, 109: Slot control unit 111: Mode control unit 112: Memory controller 113: Memory

Claims

1. Memory and a plurality of bus masters requesting access to the memory; a memory controller that controls access to the memory in response to the access request and an operation mode of the memory; mode control means for outputting a signal to switch the operation mode of the memory to a power saving mode during a period when a total amount of data transferred to the memory by the plurality of bus masters during the period is smaller than a threshold value, the signal being calculated for each period divided into predetermined time units; An electronic device comprising:

2. 2. The electronic device according to claim 1, wherein the mode control means calculates the total transfer amount of the plurality of bus masters based on a first upper limit value of the transfer amount of the plurality of bus masters that is set for each period.

3. 3. The electronic device according to claim 2, wherein the mode control means calculates the total transfer amount including command overhead based on a first upper limit value of transfer amount of the plurality of bus masters that is set for each period.

4. 4. The electronic device according to claim 1, further comprising a bandwidth control unit that calculates the transfer rate of each bus master to the memory and controls the transfer rate of each bus master based on the calculated transfer rate to the memory.

5. 5. The electronic device according to claim 4, wherein, when the transfer rate of at least one of the plurality of bus masters to the memory reaches a first transfer rate upper limit value during a first period, the bandwidth control means controls the transfer rate of the bus master to the memory using a second transfer rate upper limit value that is greater than the first transfer rate upper limit value during a second period following the first period.

6. The electronic device according to any one of claims 1 to 5, characterized in that the mode control means controls the operation mode of the memory during the calculated period to a power saving mode if the total transfer volume by the multiple bus masters during the calculated period is smaller than a threshold value, and controls the operation mode of the memory during the period to a normal mode if the total transfer volume is equal to or greater than the threshold value.

7. an imaging means for generating image data; 7. The electronic device according to claim 1, wherein the plurality of bus masters are processing means for performing predetermined processing on the image data.

8. 1. A control method for an electronic device having a memory, a plurality of bus masters that issue access requests to the memory, and a memory controller that controls access to the memory in response to the access requests and an operation mode of the memory, comprising: calculating a total amount of data transferred to the memory by the plurality of bus masters for each period divided into predetermined time units; if the calculated total transfer amount by the plurality of bus masters during the period is smaller than a threshold, outputting a signal to the memory controller to switch the operation mode of the memory during the period to a power saving mode; A control method comprising:

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