Receiving device and receiving method

Abstract

To receive data signals with high accuracy.SOLUTION: A receiving apparatus receives a data signal representing a data value 0 or 1. The receiving apparatus includes an equalizer circuit and a control circuit. The equalizer circuit outputs an output value representing a result obtained by comparing a voltage based on the received data signal with a first voltage as a reference, at each clock timing corresponding to the data signal. The control circuit is connected to the equalizer circuit. The control circuit changes, before the data signal is received, a tap coefficient related to characteristics of the equalizer circuit while a second voltage different from the first voltage is supplied, instead of the voltage of the data signal, to the equalizer circuit, to detect an inverted tap coefficient that is a tap coefficient at a boundary where a data value of the output value is inverted. The control circuit sets the inverted tap coefficient to the equalizer circuit at the time of receiving the data signal.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a receiving device and a receiving method. [Background technology]

[0002] In a memory system, data signals and strobe signals are transmitted and received between memory devices and a controller. For example, in a memory system in which each device is implemented using a package-on-package (PoP), the transmission line between the memory device and the controller is short, resulting in little insertion loss and reflection. However, as memory device capacities increase, the transmission line between the memory device and the controller becomes longer and more complex, making insertion loss and reflection more likely to occur. For this reason, as memory device capacities increase, it is considered to receive data signals using a decision feedback equalizer (DFE) to reduce the effects of insertion loss, reflection, and the like.

[0003] When the tap coefficients of a DFE are realized by the transconductance (gm) of a transistor, the transconductance varies greatly due to differences in PVT (process / voltage / temperature). Therefore, even if the tap coefficients are set in advance during design, differences in the PVT can cause differences in the characteristics of the tap coefficients. Therefore, when receiving data signals using such a DFE, it has been difficult to receive the data signals accurately. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-132239 [Patent Document 2] Japanese Patent Application Publication No. 5-235791 [Patent Document 3] Japanese Patent Application Publication No. 8-018492 [Non-patent literature]

[0005] [Non-Patent Document 1] Hyung-Joon Chi et al., “An 8.5Gb / s / pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process”, 2020 IEEE International Solid-State Circuits Conference / SESSION 22 / DRAM & HIGH-SPEED INTERFACES / 22.2, P332-P334, 2020 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment is to provide a receiving device and a receiving method that can receive a data signal with high accuracy. [Means for solving the problem]

[0007] According to one embodiment, there is provided a receiving device. The receiving device receives a data signal representing a data value of 0 or 1. The receiving device includes an equalizer circuit and a control circuit. The equalizer circuit outputs an output value representing a result of comparing a voltage based on the received data signal with a first reference voltage at each clock timing corresponding to the data signal. The control circuit is connected to the equalizer circuit. Before receiving the data signal, the control circuit supplies a second voltage different from the first voltage to the equalizer circuit instead of the voltage of the data signal, and changes tap coefficients related to the characteristics of the equalizer circuit in a state where the control circuit detects an inverted tap coefficient, which is the tap coefficient at the boundary where the data value of the output value is inverted. The control circuit sets the inverted tap coefficient for the equalizer circuit when receiving the data signal. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a memory system including a receiving device according to the embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of a receiving device according to the embodiment. [Figure 3] FIG. 3 is a diagram showing the configurations of the first decision feedback equalizer and the second decision feedback equalizer. [Figure 4] FIG. 4 is a diagram showing the circuit configuration of the amplifier circuit. [Figure 5] FIG. 5 is a diagram showing a circuit configuration of a latch circuit. [Figure 6] FIG. 6 is a flowchart showing the flow of processing by the control circuit. [Figure 7] FIG. 7 is a diagram showing the connection state by the switching circuit when a data signal is received. [Figure 8] FIG. 8 is a flowchart showing the process flow during offset adjustment. [Figure 9] FIG. 9 is a diagram showing a connection state by the switching circuit during offset adjustment. [Figure 10] FIG. 10 is a flowchart showing the flow of processing when adjusting tap coefficients. [Figure 11] FIG. 11 is a diagram showing the connection state by the switching circuit when adjusting the tap coefficients. [Figure 12] FIG. 12 is a diagram illustrating an example of the relationship between the tap coefficient and the correction voltage. [Figure 13] FIG. 13 is a flowchart showing the flow of processing when adjusting tap coefficients according to the first modification. [Figure 14] FIG. 14 is a flowchart showing the flow of processing when adjusting tap coefficients according to the second modification. [Figure 15] FIG. 15 is a diagram showing a connection state by the switching circuit when adjusting the positive-side tap coefficient in the second modified example. [Figure 16]FIG. 16 is a diagram showing a connection state by the switching circuit when adjusting the negative tap coefficient in the second modified example. [Figure 17] FIG. 17 is a diagram showing an example of the positive side correction voltage and the negative side correction voltage with respect to the tap coefficient. [Figure 18] FIG. 18 is a diagram showing an example of connections of N decision feedback equalizers according to the third modification. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, but the present invention is not limited to these embodiments.

[0010] 1 is a diagram showing the configurations of a memory system 200 and a host device 202. The memory system 200 is connected to the host device 202. The memory system 200 functions as a storage device for the host device 202. The host device 202 is an arithmetic processing circuit including a computer, a processor, or the like.

[0011] The memory system 200 is, for example, a solid state drive (SSD) or a universal flash storage (UFS) device. The memory system 200 includes a memory device 212 and a controller 214. The memory device 212 and the controller 214 are connected via a bus line 216.

[0012] The memory device 212 is one or more nonvolatile semiconductor memories, such as NAND flash memories, or may be one or more volatile semiconductor memories, such as DRAMs.

[0013] The controller 214 transmits and receives information to and from the host device 202. In response to a request from the host device 202, the controller 214 performs memory access to the memory device 212, such as writing and reading data.

[0014] The memory device 212 includes a memory-side memory interface 222. The controller 214 also includes a controller-side memory interface 224. The memory-side memory interface 222 includes a transmitting circuit and a receiving circuit. The controller-side memory interface 224 includes a transmitting circuit and a receiving circuit.

[0015] The memory-side memory interface 222 and the controller-side memory interface 224 transmit and receive signals between the memory device 212 and the controller 214 via the bus wiring 216. These signals include a data signal (DQ) and a strobe signal (DQS) that indicates the timing of the data signal (DQ). The data signal (DQ) is a signal that represents a data value (0 or 1) as a voltage. The memory-side memory interface 222 and the controller-side memory interface 224 may transmit and receive multiple data signals (DQ) to transmit and receive data in parallel.

[0016] The controller 214 also includes a host interface 226. The host interface 226 transmits and receives data to and from the host device 202 via a bus that complies with a predetermined interface standard.

[0017] FIG. 2 is a diagram showing a configuration of a receiving device 20 according to the embodiment.

[0018] The receiving device 20 according to this embodiment is included, for example, in both or one of the memory-side memory interface 222 and the controller-side memory interface 224 in the memory system 200 as part of a data signal receiving function. Note that the receiving device 20 is not limited to receiving data signals in the memory system 200, and may also be provided in another device as a receiving function for receiving serial data signals representing 0 or 1. The receiving device 20 may be included, for example, in the host interface 226 or the host device 202.

[0019] The receiving device 20 according to this embodiment receives a data signal and outputs an output value representing the value of the received data signal at each clock timing of the data signal.

[0020] The receiving device 20 includes a clock buffer 22, a first decision feedback equalizer 24 (first DFE), a second decision feedback equalizer 26 (second DFE), a first SR latch 27, a second SR latch 28, a first flip-flop 29, a second flip-flop 30, a switching circuit 32, and a control circuit 34.

[0021] The reference clock (CKP) and the inverted reference clock (CKN) are adjusted during a training period before data transmission / reception so that the received data can be sampled at the appropriate phase. The inverted reference clock (CKN) is a signal whose phase is inverted relative to the reference clock (CKP). The clock buffer 22 is a buffer that compensates for the circuit load of the subsequent first decision feedback equalizer 24 and second decision feedback equalizer 26, etc. In this embodiment, the clock buffer 22 receives the reference clock (CKP) and the inverted reference clock (CKN) and outputs an internal clock signal. The internal clock signal has a period twice that of the clock signal embedded in the data signal.

[0022] Each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 is a decision feedback equalizer circuit. When receiving a data signal, each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 outputs an output value representing the value of the data signal. In this embodiment, each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 outputs a differential output signal representing the output value.

[0023] When receiving a data signal, first decision feedback equalizer 24 receives an internal clock signal, synchronizes with the internal clock signal, obtains a value from the data signal, and generates an output value. Because the internal clock signal has twice the period of the data signal, first decision feedback equalizer 24 outputs an output value at every even-numbered clock timing of the data signal.

[0024] When receiving a data signal, second decision feedback equalizer 26 receives an inverted signal of the internal clock signal, synchronizes with the inverted signal of the internal clock signal, obtains a value from the data signal, and generates an output value. Because the internal clock signal has twice the period of the data signal, second decision feedback equalizer 26 outputs an output value at every odd-numbered clock timing of the data signal.

[0025] Each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 acquires a data signal, a reference voltage, and a past output value when receiving a data signal. The past output value is an output value output at a past clock timing. The past clock timing is, for example, the timing one sample earlier. Each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 then outputs an output value representing the result of comparing a voltage obtained by adding or subtracting a correction voltage to or from the voltage of the data signal with the reference voltage. The correction voltage is a voltage obtained by multiplying the past output value by a tap coefficient. The tap coefficient is a parameter related to the characteristics of the first decision feedback equalizer 24 and the second decision feedback equalizer 26.

[0026] In this embodiment, the first decision feedback equalizer 24 acquires, as the past output value, the output value output by the second decision feedback equalizer 26 in the immediately preceding sample. Also, in this embodiment, the second decision feedback equalizer 26 acquires, as the past output value, the output value output by the first decision feedback equalizer 24 in the immediately preceding sample.

[0027] Furthermore, each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 performs offset adjustment and tap coefficient correction before receiving the data signal, i.e., the offset adjustment and tap coefficient correction are performed prior to receiving the data signal.

[0028] During offset adjustment, a reference voltage is applied to each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 instead of a data signal. During offset adjustment, an inverted offset value is detected, which is the boundary state where the output value inverts from 0 to 1 or from 1 to 0. Then, when receiving a data signal, each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 is set with the inverted offset value as its offset value.

[0029] Furthermore, when adjusting the tap coefficients, a preset correction reference voltage is applied to each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 instead of a data signal. When adjusting the tap coefficients, an inverted tap coefficient is detected, which is a boundary state where the output value inverts from 0 to 1 or from 1 to 0. Then, when receiving a data signal, each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 is set with the inverted tap coefficient as its tap coefficient.

[0030] Here, the correction reference voltage is a voltage that removes the post-cursor in the single-bit response. The single-bit response is determined by the transmission path through which the data signal is transmitted and the voltage and frequency of the data signal. Therefore, the correction reference voltage can be determined in advance by measurement or simulation, etc., once the system in which the receiving device 20 is implemented is determined. Therefore, system designers can set the correction reference voltage in the receiving device 20 in advance of receiving the data signal.

[0031] For example, in the example of FIG. 2, the first decision feedback equalizer 24 and the second decision feedback equalizer 26 each have an INP terminal, an INN terminal, a P1 terminal, and an N1 terminal as input terminals. When a data signal is received, the INP terminal is supplied with a data signal. When a data signal is received, the INN terminal is supplied with a reference voltage. The P1 terminal receives the positive value of the output value of the immediately preceding sample. The N1 terminal receives the negative value of the output value of the immediately preceding sample. Here, the output value of the immediately preceding sample is the past output value.

[0032] 2, the first decision feedback equalizer 24 and the second decision feedback equalizer 26 each have an OUTP terminal and an OUTN terminal as output terminals. The OUTP terminal outputs the positive value of the differential output value. The OUTN terminal outputs the negative value of the differential output value.

[0033] The first SR latch 27 receives, at its set terminal, the positive value of the differential output value output from the OUTP terminal of the first decision feedback equalizer 24. The first SR latch 27 receives, at its reset terminal, the negative value of the differential output value output from the OUTN terminal of the first decision feedback equalizer 24. If the value of the set terminal becomes 1 while the value of the reset terminal is 0, the first SR latch 27 sets its output value to 1, and continues to hold the output value at 1 even if the set terminal subsequently becomes 0. Furthermore, if the value of the reset terminal becomes 1 while the value of the set terminal is 0, the first SR latch 27 sets its output value to 0, and continues to hold the output value at 0 even after the reset terminal subsequently becomes 0.

[0034] The second SR latch 28 receives, at its set terminal, the positive value of the differential output value output from the OUTP terminal of the second decision feedback equalizer 26. The second SR latch 28 receives, at its reset terminal, the negative value of the differential output value output from the OUTN terminal of the second decision feedback equalizer 26. The second SR latch 28 operates in the same manner as the first SR latch 27.

[0035] The first flip-flop 29 acquires and holds the output value of the first SR latch 27 in synchronization with the timing of the internal clock signal. The first flip-flop 29 then outputs the held value. Therefore, the first flip-flop 29 can output an output value at even-numbered clock timings of the data signal.

[0036] The second flip-flop 30 acquires and holds the output value of the second SR latch 28 in synchronization with the timing of the inverted signal of the internal clock signal. The second flip-flop 30 then outputs the held value. Therefore, the second flip-flop 30 can output the output value at the odd-numbered clock timings of the data signal.

[0037] When receiving a data signal, the switching circuit 32 supplies the data signal and the reference voltage to the first decision feedback equalizer 24 and the second decision feedback equalizer 26. In the example of Fig. 2, when receiving a data signal, the switching circuit 32 supplies the data signal to each INP terminal and the reference voltage to each INN terminal.

[0038] Furthermore, during offset adjustment, the switching circuit 32 supplies a reference voltage, instead of a data signal, to the first decision feedback equalizer 24 and the second decision feedback equalizer 26. In the example of Fig. 2, during offset adjustment, the switching circuit 32 supplies the reference voltage to both the INP terminal and the INN terminal.

[0039] Furthermore, when adjusting the tap coefficients, the switching circuit 32 supplies a correction reference voltage, instead of a data signal, to the first decision feedback equalizer 24 and the second decision feedback equalizer 26. In the example of Fig. 2, when adjusting the tap coefficients, the switching circuit 32 supplies the correction reference voltage to each INP terminal and the reference voltage to each INN terminal.

[0040] The control circuit 34 controls the switching of the switching circuit 32. Furthermore, the control circuit 34 sets offset values ​​and tap coefficients for the first decision feedback equalizer 24 and the second decision feedback equalizer 26 when receiving data.

[0041] Furthermore, before receiving the data signal, the control circuit 34 executes control for adjusting the offset and tap coefficients of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 individually.

[0042] During offset adjustment, the control circuit 34 controls the switching circuit 32 to supply a reference voltage, instead of the voltage of the data signal, to the first decision feedback equalizer 24 and the second decision feedback equalizer 26. During offset adjustment, the control circuit 34 changes the offset value for each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26. As a result, the control circuit 34 detects an inverted offset value, which is the offset value at the boundary where the output value is inverted. Then, when receiving a data signal, the control circuit 34 sets the detected inverted offset value as the offset value for each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26.

[0043] More specifically, the control circuit 34 detects a first inverted offset value by changing the offset value of the first decision feedback equalizer 24 during offset adjustment. The control circuit 34 sets the first inverted offset value as the offset value of the first decision feedback equalizer 24 during reception of a data signal. The control circuit 34 also detects a second inverted offset value by changing the offset value of the second decision feedback equalizer 26 during offset adjustment. The control circuit 34 sets the second inverted offset value as the offset value of the second decision feedback equalizer 26 during reception of a data signal. The control circuit 34 detects the first inverted offset value based on the output of the first SR latch 27. The control circuit 34 detects the second inverted offset value based on the output of the second SR latch 28.

[0044] During tap coefficient adjustment, the control circuit 34 controls the switching circuit 32 to supply a correction reference voltage, instead of the voltage of the data signal, to the first decision feedback equalizer 24 and the second decision feedback equalizer 26. During tap coefficient adjustment, the control circuit 34 changes the tap coefficients of each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26. As a result, the control circuit 34 detects an inverted tap coefficient, which is a tap coefficient at a boundary where the output value is inverted. Then, upon receiving a data signal, the control circuit 34 sets the detected inverted tap coefficient as the tap coefficient for each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26.

[0045] More specifically, the control circuit 34 detects a first inverted tap coefficient by changing the tap coefficient of the first decision feedback equalizer 24 when adjusting the tap coefficient. The control circuit 34 sets a first inverted tap coefficient as the tap coefficient of the first decision feedback equalizer 24 when receiving a data signal. Furthermore, the control circuit 34 detects a second inverted tap coefficient by changing the tap coefficient of the second decision feedback equalizer 26 when adjusting the tap coefficient. The control circuit 34 sets a second inverted tap coefficient as the tap coefficient of the second decision feedback equalizer 26 when receiving a data signal. The control circuit 34 detects the first inverted tap coefficient based on the output of the first SR latch 27. The control circuit 34 detects the second inverted tap coefficient based on the output of the second SR latch 28.

[0046] 2, the control circuit 34 provides signals TP, TN, FP, and FN to the first decision feedback equalizer 24 and the second decision feedback equalizer 26, respectively. The signal TP represents a signal for setting a tap coefficient of a positive value. The signal TN represents a signal for setting a tap coefficient of a negative value. The signal FP represents a signal for setting an offset value of a positive value. The signal FN represents a signal for setting an offset value of a negative value.

[0047] FIG. 3 is a diagram showing the configuration of the first decision feedback equalizer 24 and the second decision feedback equalizer 26. As shown in FIG.

[0048] The first decision feedback equalizer 24 and the second decision feedback equalizer 26 each have the same configuration, and include an amplifier circuit 42, a clock inversion circuit 44, and a latch circuit 46.

[0049] Each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 repeats a reset period and a comparison period in synchronization with a supplied clock signal. The first decision feedback equalizer 24 receives the internal clock signal as its clock signal, and operates during a reset period when the value of the internal clock signal is 1 (H level) and during a comparison period when the value of the internal clock signal is 0 (L level). The second decision feedback equalizer 26 receives the inverted signal of the internal clock signal as its clock signal, and operates during a reset period when the value of the inverted signal of the internal clock signal is 1 (H level) and during a hold period when the value of the inverted signal of the internal clock signal is 0 (L level).

[0050] During the reset period, the amplifier circuit 42 charges the parasitic capacitances of the OP1 terminal and the ON1 terminal. During the comparison period, the amplifier circuit 42 amplifies the difference between the reference voltage and the voltage obtained by adding or subtracting the correction voltage from the voltage of the data signal, and outputs the resulting amplified signal to the latch circuit 46.

[0051] In the example of FIG. 3, the amplifier circuit 42 receives an internal clock signal or its inverted signal at its CK terminal, a data signal at its INP terminal, and a reference voltage at its INN terminal. The amplifier circuit 42 receives the positive output value of the immediately preceding sample at its P1 terminal, and the negative output value of the immediately preceding sample at its N1 terminal. The positive output value input to the P1 terminal is the past output value, and the negative output value input to the N1 terminal is the inverted value of the past output value. Furthermore, in the example of FIG. 3, the amplifier circuit 42 outputs an amplified signal, which is the amplified voltage difference, from its OP1 terminal and ON1 terminal.

[0052] The amplifier circuit 42 also acquires signals TP, TN, FP, and FN for setting tap coefficients and offset values, and sets the tap coefficients and offset values ​​in accordance with the acquired signals TP, TN, FP, and FN.

[0053] The clock inversion circuit 44 receives a clock signal or its inverted signal, and outputs an inverted clock signal obtained by inverting the received signal.

[0054] During the comparison period, the latch circuit 46 holds the value of the amplified signal that is the output of the amplifier circuit 42 at the previous stage, and simultaneously outputs it.

[0055] 3, the latch circuit 46 receives an inverted clock signal at its CKB terminal, a positive amplified signal at its OP2 terminal, and a negative amplified signal at its ON2 terminal. Also, in the example of Fig. 3, the latch circuit 46 outputs the positive value of the differential output value from its OUTP terminal, and outputs the negative value of the differential output value from its OUTN terminal.

[0056] The first SR latch 27 receives the positive differential output value at its set terminal and the negative differential output value at its reset terminal from the latch circuit 46 of the first decision feedback equalizer 24. The second SR latch 28 receives the positive differential output value at its set terminal and the negative differential output value at its reset terminal from the latch circuit 46 of the second decision feedback equalizer 26. The first SR latch 27 and the second SR latch 28 hold the signals to be output during the reset period and pass the signals input to their set terminals during the comparison period.

[0057] 4 is a diagram showing the circuit configuration of the amplifier circuit 42. The amplifier circuit 42 includes, for example, a first FET 52, a second FET 54, a first switch 56, a second switch 58, a third switch 60, a positive tap coefficient circuit 62, a negative tap coefficient circuit 64, a positive offset circuit 66, and a negative offset circuit 68.

[0058] The gate of the first FET 52 is connected to the INP terminal, and the voltage of the data signal is applied to the gate of the first FET 52. The first FET 52 is, for example, a pMOSFET.

[0059] The second FET 54 has a gate connected to the INN terminal and a reference voltage applied to the gate. The second FET 54 is, for example, a pMOSFET.

[0060] The first switch 56 connects the source of the first FET 52 and the source of the second FET 54 to the power supply potential during the comparison period and disconnects them from the power supply potential during the reset period. The power supply potential is supplied to the amplifier circuit 42 and serves as a power source for operating the amplifier circuit 42. The first switch 56 is, for example, a pMOSFET. The gate of the first switch 56 is connected to the CK terminal, and the voltage of the clock signal is applied to the gate.

[0061] The second switch 58 connects the drain of the first FET 52 to ground potential during the reset period and disconnects it from ground potential during the comparison period. The ground potential is supplied to the amplifier circuit 42 and serves as a reference voltage for the operation of the amplifier circuit 42. The second switch 58 is, for example, an nMOSFET. The gate of the second switch 58 is connected to the CK terminal, and the voltage of the clock signal is applied to the gate.

[0062] The third switch 60 connects the drain of the second FET 54 to ground potential during the reset period and disconnects it from ground potential during the comparison period. The third switch 60 is, for example, an nMOSFET. The gate of the third switch 60 is connected to the CK terminal, and the voltage of the clock signal is applied to the gate.

[0063] The positive-side tap coefficient circuit 62 is connected in parallel to the drain and source of the second FET 54. When the past output value is 1 (in this embodiment, when the positive-side output value of the immediately preceding sample received from the P1 terminal is 1), the positive-side tap coefficient circuit 62 connects the drain and source of the second FET 54 with a resistance value according to the set tap coefficient. When the past output value is 0, the positive-side tap coefficient circuit 62 disconnects the drain and source of the second FET 54.

[0064] For example, the positive-side tap coefficient circuit 62 includes a third FET 72 and a fourth switch 74. The drain-source of the third FET 72 and the fourth switch 74 are connected in series. The third FET 72 is, for example, a pMOSFET. The fourth switch 74 is, for example, a pMOSFET. The gate of the fourth switch 74 is connected to the P1 terminal, and the positive-side output value of the immediately preceding sample is input thereto.

[0065] The third FET 72 has a gate to which the number of FETs corresponding to the positive-side tap coefficient is set by a signal TP from the control circuit 34. The third FET 72 includes a plurality of FET elements. The drain-source resistance value of the third FET 72 changes as the number of FET elements to be turned on is selected from the plurality of FET elements according to the number of FETs selected by the control circuit 34. The fourth switch 74 is short-circuited when the past output value is 1 (in this embodiment, when the positive-side output value of the immediately preceding sample received from the P1 terminal is 1), and is open when the past output value is 0.

[0066] 4, the drain of the third FET 72 is connected to the drain of the second FET 54. The fourth switch 74 shorts or disconnects the source of the third FET 72 and the source of the second FET 54.

[0067] The negative tap coefficient circuit 64 is connected in parallel to the drain and source of the first FET 52. When the past output value is 0 (in this embodiment, when the negative output value of the immediately preceding sample received from the N1 terminal is 1), the negative tap coefficient circuit 64 connects the drain and source of the first FET 52 with a resistance value according to the set tap coefficient. When the past output value is 1, the negative tap coefficient circuit 64 disconnects the drain and source of the first FET 52.

[0068] For example, the negative-side tap coefficient circuit 64 includes a fourth FET 76 and a fifth switch 78. The drain-source of the fourth FET 76 and the fifth switch 78 are connected in series. The fourth FET 76 is, for example, a pMOSFET. The fifth switch 78 is, for example, a pMOSFET. A gate of the fifth switch 78 is connected to the N1 terminal, and the negative-side past output value of the immediately preceding sample is input thereto.

[0069] The fourth FET 76 has a gate to which the number of FETs corresponding to the negative tap coefficient is set by a signal TN from the control circuit 34. The fourth FET 76 includes a plurality of FET elements. The drain-source resistance value of the fourth FET 76 changes as the number of FET elements to be turned on is selected from the plurality of FET elements according to the number of FETs selected by the control circuit 34. The fifth switch 78 is short-circuited when the past output value is 0 (in this embodiment, when the negative output value of the immediately preceding sample received from the N1 terminal is 1), and is open when the past output value is 1.

[0070] 4, the drain of the fourth FET 76 is connected to the drain of the first FET 52. In addition, the fifth switch 78 shorts or disconnects the source of the fourth FET 76 and the source of the first FET 52.

[0071] The positive-side offset circuit 66 is connected in parallel to the drain and source of the second FET 54. The positive-side offset circuit 66 connects between the drain and source of the second FET 54 with a resistance value according to the set offset value.

[0072] For example, the positive-side offset circuit 66 includes a plurality of fifth FETs 80, each with its source and drain connected in series. The plurality of fifth FETs 80 connected in series are connected in parallel to the drain and source of the second FET 54. Each of the plurality of fifth FETs 80 is, for example, a pMOSFET. The control circuit 34 sets the number of FETs at the gates of the plurality of fifth FETs 80 according to the positive-side offset value using a signal FP. Each of the plurality of fifth FETs 80 includes a plurality of FET elements. The drain-source resistance of each of the plurality of fifth FETs 80 changes as the number of FET elements to be turned on is selected from the plurality of FET elements according to the number of FETs selected by the control circuit 34.

[0073] Negative-side offset circuit 68 is connected in parallel to the drain and source of first FET 52. Negative-side offset circuit 68 connects between the drain and source of first FET 52 with a resistance value according to the set offset value.

[0074] For example, the negative-side offset circuit 68 includes a plurality of sixth FETs 82, each with its source and drain connected in series. The plurality of sixth FETs 82 connected in series are connected in parallel to the drain and source of the first FET 52. Each of the plurality of sixth FETs 82 is, for example, a pMOSFET. The control circuit 34 sets the number of FETs at the gates of the plurality of sixth FETs 82 according to the negative-side offset value using a signal FN. Each of the plurality of sixth FETs 82 includes a plurality of FET elements. The drain-source resistance value of each of the plurality of sixth FETs 82 changes as the number of FET elements to be turned on is selected from the plurality of FET elements according to the number of FETs selected by the control circuit 34.

[0075] The drain of the first FET 52 is connected to the ON1 terminal, and the drain of the second FET 54 is connected to the OP1 terminal. The amplifier circuit 42 configured as described above outputs a differential amplified signal from the OP1 terminal and the ON1 terminal.

[0076] The amplifier circuit 42 configured as described above includes the positive-side tap coefficient circuit 62 and the negative-side tap coefficient circuit 64, and can output a differential amplified signal that represents the result of comparing a voltage obtained by adding or subtracting a correction voltage (a voltage obtained by multiplying a past output value by a tap coefficient) to or from the voltage of the data signal with a reference voltage. Furthermore, the amplifier circuit 42 includes the positive-side offset circuit 66 and the negative-side offset circuit 68, and can also correct the offset of the voltage of the data signal.

[0077] FIG. 5 is a diagram showing the circuit configuration of the latch circuit 46. As shown in FIG.

[0078] The latch circuit 46 includes a seventh FET 84 , an eighth FET 86 , a ninth FET 88 , a tenth FET 90 , an eleventh FET 92 , a twelfth FET 94 , and a sixth switch 96 .

[0079] The seventh FET 84 has a gate connected to the OP2 terminal, and the voltage of the positive signal of the differential amplified signal output from the amplifier circuit 42 is applied to the gate. The seventh FET 84 has a source connected to a power supply potential, and a drain connected to the OUTN terminal. The seventh FET 84 is, for example, a pMOSFET. Here, the power supply potential is a voltage potential that is supplied to the latch circuit 46 and serves as a power source for operating the latch circuit 46. The power supply potential of the latch circuit 46 may be the same as or different from the power supply potential of the amplifier circuit 42.

[0080] The gate of the eighth FET 86 is connected to the ON2 terminal, and the voltage of the negative signal of the amplified differential signal output from the amplifier circuit 42 is applied to the gate. The source of the eighth FET 86 is connected to the power supply potential, and the drain is connected to the OUTP terminal. The seventh FET 84 is, for example, a pMOSFET.

[0081] The gate of the ninth FET 88 is connected to the OUTP terminal. The source of the ninth FET 88 is connected to the power supply potential, and the drain is connected to the OUTN terminal. The ninth FET 88 is, for example, a pMOSFET.

[0082] The gate of the tenth FET 90 is connected to the OUTP terminal. The source of the tenth FET 90 is connected to the ground potential via the sixth switch 96, and the drain is connected to the OUTN terminal. The tenth FET 90 is, for example, an nMOSFET. Here, the ground potential is a voltage potential that is supplied to the latch circuit 46 and serves as a reference for the operation of the latch circuit 46. The ground potential of the latch circuit 46 is the same as the ground potential of the amplifier circuit 42.

[0083] The gate of the eleventh FET 92 is connected to the OUTN terminal. The source of the eleventh FET 92 is connected to the power supply potential, and the drain is connected to the OUTP terminal. The eleventh FET 92 is, for example, a pMOSFET.

[0084] The gate of the twelfth FET 94 is connected to the OUTN terminal. The source of the twelfth FET 94 is connected to the ground potential via the sixth switch 96, and the drain is connected to the OUTP terminal. The twelfth FET 94 is, for example, an nMOSFET.

[0085] The sixth switch 96 disconnects the sources of the tenth FET 90 and the twelfth FET 94 from ground potential during the reset period and connects them to ground potential during the comparison period. The sixth switch 96 is, for example, an nMOSFET. The gate of the sixth switch 96 is connected to the CKB terminal, and the voltage of the inverted signal of the clock signal is applied to the gate.

[0086] Such a latch circuit 46 outputs a differential output value from the OUTP terminal and the OUTN terminal. The latch circuit 46 configured as described above sets the outputs of the cross-coupled inverters to the same potential (power supply voltage) during the reset period. The cross-coupled inverter is composed of a ninth FET 88, a tenth FET 90, an eleventh FET 92, and a twelfth FET 94. Then, during the comparison period, the latch circuit 46 holds and outputs the value of the amplified signal output by the amplifier circuit 42.

[0087] Fig. 6 is a flowchart showing the flow of processing by the control circuit 34. Fig. 7 is a diagram showing the connection state by the switching circuit 32 when a data signal is received.

[0088] Before receiving a data signal, the control circuit 34 performs an adjustment process for the offset value and the tap coefficient (S11).

[0089] In the adjustment process (S11), first, in S11-1, the control circuit 34 performs offset adjustment of the first decision feedback equalizer 24. Then, in S11-2, the control circuit 34 performs offset adjustment of the second decision feedback equalizer 26. Then, in S11-3, the control circuit 34 performs tap coefficient adjustment of the first decision feedback equalizer 24. Then, in S11-4, the control circuit 34 performs tap coefficient adjustment of the second decision feedback equalizer 26.

[0090] After the adjustment process (S11) is completed, the control circuit 34 starts receiving the data signal (S12). When receiving the data signal, the control circuit 34 controls the switching circuit 32 to input the data signal to the INP terminals of the first decision feedback equalizer 24 and the second decision feedback equalizer 26, and to input the reference voltage to the INN terminals of the first decision feedback equalizer 24 and the second decision feedback equalizer 26, as shown in FIG.

[0091] Fig. 8 is a flowchart showing the flow of processing during offset adjustment. Fig. 9 is a diagram showing the connection state by the switching circuit 32 during offset adjustment. During offset adjustment, the control circuit 34 executes processing for the first decision feedback equalizer 24 according to the flow shown in Fig. 8.

[0092] 9, the control circuit 34 controls the switching circuit 32 to short-circuit the INP terminal and the INN terminal of the first decision feedback equalizer 24, thereby supplying the reference voltage to the INP terminal and the INN terminal. This allows the control circuit 34 to supply the reference voltage to the first decision feedback equalizer 24 instead of the voltage of the data signal.

[0093] Next, in S22, the control circuit 34 detects a first inversion offset value, which is the offset value at the boundary where the output value is inverted, by changing the offset value of the first decision feedback equalizer 24. For example, the control circuit 34 changes the offset value by changing the number of FETs used to set the offset value.

[0094] Next, in S23, the control circuit 34 sets the first inverted offset value detected in S22 as the offset value for the first decision feedback equalizer 24. For example, the control circuit 34 sets the number of FETs at the boundary where the output value inverts, detected in S22, for the first decision feedback equalizer 24. Then, when the control circuit 34 finishes the process of S23, it ends the offset adjustment process.

[0095] Similarly, the control circuit 34 detects the second inverted offset value for the second decision feedback equalizer 26 and sets the second inverted offset value as the offset value.

[0096] Fig. 10 is a flowchart showing the flow of processing when adjusting tap coefficients. Fig. 11 is a diagram showing the connection state by the switching circuit 32 when adjusting tap coefficients. When adjusting tap coefficients, the control circuit 34 executes processing for the first decision feedback equalizer 24 according to the flow shown in Fig. 10.

[0097] 11, the control circuit 34 controls the switching circuit 32 to supply the corrected reference voltage to the INP terminal of the first decision feedback equalizer 24 and the reference voltage to the INN terminal of the first decision feedback equalizer 24. This allows the control circuit 34 to supply the corrected reference voltage to the first decision feedback equalizer 24 instead of the voltage of the data signal.

[0098] Next, in S32, the control circuit 34 detects a first inversion tap coefficient, which is a tap coefficient at a boundary where the output value is inverted, by changing the tap coefficient of the first decision feedback equalizer 24. For example, the control circuit 34 changes the tap coefficient by changing the number of FETs for setting the tap coefficient.

[0099] In this case, the control circuit 34 sets the past output value to 1 when changing the tap coefficient on the positive side, and sets the past output value to 0 when changing the tap coefficient on the negative side.

[0100] Next, in S33, the control circuit 34 sets the first inverted tap coefficients detected in S32 as tap coefficients for the first decision feedback equalizer 24. For example, the control circuit 34 sets the number of FETs at the boundary where the output value is inverted, detected in S32, for the first decision feedback equalizer 24. Then, when the control circuit 34 ends the process of S33, it ends the tap coefficient adjustment process.

[0101] Similarly, the control circuit 34 detects the second inverted tap coefficients of the second decision feedback equalizer 26 and sets the second inverted tap coefficients as the tap coefficients.

[0102] FIG. 12 is a diagram illustrating an example of the relationship between the tap coefficient and the correction voltage.

[0103] For example, when using the first decision feedback equalizer 24 and the second decision feedback equalizer 26 configured with MOSFETs as shown in Figures 4 and 5, the tap coefficients are realized by the transconductance (gm) of the third FET 72 and the fourth FET 76. For example, as shown in Figure 12, even when the same tap coefficients (number of FETs) are set, the value of the correction voltage added to or subtracted from the voltage of the data signal varies depending on the Vth voltage (threshold voltage) of the MOSFET due to PVT variations. For example, as shown in Figure 12, a difference may occur between when the Vth voltage of the transistor is low (fast) and when the Vth voltage of the transistor is high (slow).

[0104] In contrast, the receiving device 20 according to this embodiment detects an inverted tap coefficient at which the output value is inverted by changing the tap coefficients of each of the first decision feedback equalizer 24 and the second decision feedback equalizer 26 while supplying a correction reference voltage instead of the data signal voltage before receiving a data signal. Then, when receiving a data signal, the receiving device 20 sets the inverted tap coefficient as the tap coefficient for the first decision feedback equalizer 24 and the second decision feedback equalizer 26. This allows the receiving device 20 according to this embodiment to compare the voltage obtained by adding or subtracting an appropriate correction voltage to or from the data signal voltage with the reference voltage when receiving a data signal. Therefore, the receiving device 20 according to this embodiment can receive data signals with high accuracy.

[0105] FIG. 13 is a flowchart showing the flow of processing when adjusting tap coefficients according to the first modification.

[0106] 13 for the first decision feedback equalizer 24. In this case, the control circuit 34 also performs the same process for the second decision feedback equalizer 26.

[0107] First, in S41, the control circuit 34 controls the switching circuit 32 to supply the corrected reference voltage to the INP terminal of the first decision feedback equalizer 24 and the reference voltage to the INN terminal. S41 is the same as S31 in FIG.

[0108] Next, in S42, the control circuit 34 detects candidate values ​​of inverted tap coefficients, which are tap coefficients at boundaries where the output value is inverted, multiple times by changing the tap coefficients of the first decision feedback equalizer 24. For example, the control circuit 34 detects candidate values ​​of inverted tap coefficients x times (x is an integer equal to or greater than 2) (S42-1 to S42-x).

[0109] Next, in S43, the control circuit 34 calculates a statistically representative value of the plurality of candidate values ​​as the first inversion tap coefficient. For example, the control circuit 34 calculates an average value of the plurality of candidate values. Alternatively, the control circuit 34 may calculate a median or a mode of the plurality of candidate values.

[0110] Next, in S44, the control circuit 34 sets the first inverted tap coefficient (a statistical representative value of a plurality of candidate values) calculated in S43 as the tap coefficient for the first decision feedback equalizer 24. Then, when the control circuit 34 ends the process of S44, it ends the tap coefficient adjustment process.

[0111] By performing the tap coefficient adjustment according to the first modified example as described above, the control circuit 34 can reduce errors when detecting the inverted tap coefficients, and can receive the data signal with high accuracy.

[0112] Fig. 14 is a flowchart showing the flow of processing when adjusting tap coefficients according to the second modification. Fig. 15 is a diagram showing the connection state of the switching circuit 32 when adjusting the positive tap coefficients according to the second modification. Fig. 16 is a diagram showing the connection state of the switching circuit 32 when adjusting the negative tap coefficients according to the second modification.

[0113] 14 for the first decision feedback equalizer 24. In this case, the control circuit 34 also performs the same process for the second decision feedback equalizer 26.

[0114] First, in S51, as shown in Fig. 15, the control circuit 34 controls the switching circuit 32 to supply the corrected reference voltage to the INP terminal of the first decision feedback equalizer 24 and the reference voltage to the INN terminal. This enables the control circuit 34 to supply the corrected reference voltage, instead of the voltage of the data signal, to the first decision feedback equalizer 24. S51 is the same as S31 in Fig. 10.

[0115] Next, in S52, the control circuit 34 detects a positive-side inverting tap coefficient, which is a tap coefficient at a boundary where the output value is inverted, by changing the positive-side tap coefficient of the first decision feedback equalizer 24. For example, the control circuit 34 changes the number of FETs for setting the positive-side tap coefficient. In this case, the control circuit 34 sets the past output value to 1 in order to change the positive-side tap coefficient.

[0116] 16, the control circuit 34 controls the switching circuit 32 to supply the reference voltage to the INP terminal of the first decision feedback equalizer 24 and the corrected reference voltage to the INN terminal of the first decision feedback equalizer 24. This allows the control circuit 34 to supply the corrected reference voltage instead of the reference voltage and the reference voltage instead of the voltage of the data signal.

[0117] Next, in S54, the control circuit 34 detects a negative-side inverted tap coefficient, which is the negative-side tap coefficient at the boundary where the output value is inverted, for the first decision feedback equalizer 24 by changing the negative-side tap coefficient. For example, the control circuit 34 changes the number of FETs for setting the negative-side tap coefficient. In this case, the control circuit 34 sets the past output value to 0 in order to change the negative-side tap coefficient.

[0118] Next, in S55, the control circuit 34 sets the positive-side inverted tap coefficient detected in S52 as the positive-side tap coefficient for the first decision feedback equalizer 24. For example, the control circuit 34 sets the number of FETs at the boundary where the output value inverts, detected in S52, for the first decision feedback equalizer 24.

[0119] Next, in S56, the control circuit 34 sets the negative-side inverted tap coefficient detected in S54 as the negative-side tap coefficient for the first decision feedback equalizer 24. For example, the control circuit 34 sets the number of FETs at the boundary where the output value inverts, detected in S54, for the first decision feedback equalizer 24. Then, after completing the process of S56, the control circuit 34 ends the tap coefficient adjustment process.

[0120] FIG. 17 is a diagram showing an example of the positive side correction voltage and the negative side correction voltage with respect to the tap coefficient.

[0121] For example, when the first decision feedback equalizer 24 and the second decision feedback equalizer 26 are configured using MOSFETs as shown in FIGS. 4 and 5, the tap coefficients are determined by the transconductance (gm) of the third FET 72 and the fourth FET 76. The transconductance of the third FET 72 and the transconductance of the fourth FET 76 may differ. For example, as shown in FIG. 17, this difference may cause a difference between the absolute values ​​of the positive-side correction voltage and the negative-side correction voltage when the same tap coefficient (gate voltage) is set. That is, as shown in FIG. 17, the tap coefficients (gate voltages) at which the absolute values ​​of the positive-side correction voltage and the negative-side correction voltage are the same may differ between the positive and negative sides.

[0122] In contrast, the receiving device 20 according to the second modification detects the positive-side inverted tap coefficient and the negative-side inverted tap coefficient at which the output value is inverted by changing the tap coefficients separately for the positive and negative sides. Then, when receiving a data signal, the receiving device 20 sets the positive-side inverted tap coefficient as the positive-side tap coefficient and the negative-side inverted tap coefficient as the negative-side tap coefficient for the first decision feedback equalizer 24 and the second decision feedback equalizer 26. As a result, when receiving a data signal, the receiving device 20 according to the present embodiment can compare the voltage obtained by adding or subtracting an appropriate correction voltage from the voltage of the data signal with the reference voltage, regardless of whether the correction voltage is positive or negative. Therefore, the receiving device 20 according to the present embodiment can receive data signals with high accuracy.

[0123] FIG. 18 is a diagram showing an example of connections of N decision feedback equalizers 100 according to the third modification.

[0124] The receiving device 20 according to the third modification may include N decision feedback equalizers 100 (100-1 to 100-N) from the first to the Nth (N is an integer equal to or greater than 3) decision feedback equalizers 100 instead of the first decision feedback equalizer 24 and the second decision feedback equalizer 26. Each of the N decision feedback equalizers 100 has the same configuration as the first decision feedback equalizer 24 and the second decision feedback equalizer 26. Each of the N decision feedback equalizers 100 outputs an output value representing the result of comparing a voltage obtained by adding or subtracting a correction voltage to or from the voltage of the data signal with a reference voltage.

[0125] When N decision feedback equalizers 100 are provided, clock buffer 120 outputs N internal clock signals, numbered from first to Nth. Each of the N internal clock signals has a period N times the period of the clock signal embedded in the data signal. The N internal clock signals are phase-shifted by 1 / N period. The first decision feedback equalizer 100-1 receives the first internal clock signal as a clock signal. The second decision feedback equalizer 100-2 receives the second internal clock signal, which is phase-shifted by 1 / N period from the first internal clock signal, as a clock signal. The Nth decision feedback equalizer 100-N receives the Nth internal clock signal, which is phase-shifted by 1 / N period from the (N-1)th internal clock signal, as a clock signal.

[0126] Each of the N decision feedback equalizers 100 acquires, as a past output value, the output value output at the immediately preceding clock timing in the data signal. The nth (n is an integer between 1 and N) decision feedback equalizer 100-n of the N decision feedback equalizers 100 outputs an output value at each (R+1)th sampling timing (R is the remainder when the total number of samples is divided by N).

[0127] Before receiving a data signal, the control circuit 34 supplies a correction reference voltage to the nth decision feedback equalizer 100-n instead of the voltage of the data signal, and changes the tap coefficient to detect the nth inversion tap coefficient, which is the tap coefficient at the boundary where the output value is inverted. Then, when receiving the data signal, the control circuit 34 sets the nth inversion tap coefficient as the tap coefficient for the nth decision feedback equalizer 100-n.

[0128] The receiver 20 configured as described above can output output values ​​representing the values ​​of the data signals with high precision using the N decision feedback equalizers 100.

[0129] Note that receiving device 20 may include a single decision feedback equalizer 100 instead of first decision feedback equalizer 24 and second decision feedback equalizer 26. In this case, clock buffer 120 outputs an internal clock signal having the same period as the clock signal embedded in the data signal. Decision feedback equalizer 100 acquires, as a clock signal, the internal clock signal having the same period as the clock signal embedded in the data signal. In this case, decision feedback equalizer 100 acquires, as a past output value, the output value it output one sample before. Receiving device 20 configured in this way can also accurately output an output value representing the value of a data signal.

[0130] Each of the N decision feedback equalizers 100 is configured to acquire an output value one sample earlier, but may also acquire one or more output values ​​two or more samples earlier in addition to one sample earlier. Each of the N decision feedback equalizers 100 may then calculate a correction voltage by multiplying each of one or more output values ​​two or more samples earlier by an individually set tap coefficient, and further add or subtract the correction voltage from the voltage of the data signal.

[0131] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0132] (Addendum) The above-described embodiments can be summarized as the following technical proposals.

[0133] Technical proposal 1 1. A receiving device for receiving a data signal representing a data value of 0 or 1, comprising: an equalizer circuit that outputs an output value representing a result of comparing a voltage based on the received data signal with a first voltage serving as a reference at each clock timing corresponding to the data signal; a control circuit connected to the equalizer circuit; Equipped with The control circuit before receiving the data signal, a second voltage different from the first voltage is supplied to the equalizer circuit instead of the voltage of the data signal, and tap coefficients relating to characteristics of the equalizer circuit are changed to detect an inverted tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted; When receiving the data signal, the inverted tap coefficient is set for the equalizer circuit. Receiving device.

[0134] Technical proposal 2 The second voltage is a voltage obtained by adding an interference voltage that is applied to the data signal when the output value output at the previous clock timing is 1 to the first voltage. A receiving device according to Technical Proposal 1.

[0135] Technical proposal 3 The control circuit detecting candidate values ​​for the inverted tap coefficients a plurality of times before receiving the data signal; When receiving the data signal, a statistically representative value based on a plurality of candidate values ​​of the inverted tap coefficient is set for the equalizer circuit. A receiving device according to Technical Proposal 1.

[0136] Technical proposal 4 the equalizer circuit alternately repeats a reset period and a comparison period; The equalizer circuit an amplifier circuit that amplifies and outputs a voltage obtained by adding or subtracting a correction voltage from a voltage of the data signal and the first voltage during the comparison period, the correction voltage being a voltage obtained by multiplying a past output value, which is the output value output at a past clock timing, by the tap coefficient; a latch circuit that precharges a parasitic capacitance during the reset period and holds and outputs the value of the differential amplified signal during the comparison period; A receiving device according to any one of technical solutions 1 to 3, including:

[0137] Technical proposal 5 The amplifier circuit a first FET having a gate to which the voltage of the data signal is applied; a second FET having a gate to which the first voltage is applied; a first switch that connects the source of the first FET and the source of the second FET to a power supply potential during the comparison period and disconnects the source of the first FET and the source of the second FET from the power supply potential during the reset period; a second switch that connects the drain of the first FET to a ground potential during the reset period and disconnects the drain of the first FET from the ground potential during the comparison period; a third switch that connects the drain of the second FET to the ground potential during the reset period and disconnects the drain of the second FET from the ground potential during the comparison period; a positive-side tap coefficient circuit connected in parallel to the drain and source of the second FET; a negative tap coefficient circuit connected in parallel to the drain and source of the first FET; Equipped with the positive-side tap coefficient circuit connects the drain and source of the second FET with a resistance value according to the tap coefficient when the past output value is 1, and disconnects the drain and source of the second FET when the past output value is 0; The negative tap coefficient circuit connects the drain and source of the first FET with a resistance value according to the tap coefficient when the past output value is 0, and disconnects the drain and source of the first FET when the past output value is 1. A receiving device as described in Technical Proposal 4.

[0138] Technical proposal 6 The positive side tap coefficient circuit a third FET including a plurality of FET elements; A fourth switch; Including, the drain-source of the third FET and the fourth switch are connected in series; the fourth switch is short-circuited when the past output value is 1 and is disconnected when the past output value is 0; The third FET has a gate to which the number of FETs corresponding to the tap coefficient is set by the control circuit, and the number of FETs to be turned on among the plurality of FET elements is selected according to the number of FETs set by the control circuit, thereby changing the resistance value between the drain and source. A receiving device according to Technical Proposal 5.

[0139] Technical proposal 7 The negative tap coefficient circuit a fourth FET including a plurality of FET elements; The fifth switch, Including, the drain-source of the fourth FET and the fifth switch are connected in series; the fifth switch is short-circuited when the past output value is 0, and is disconnected when the past output value is 1; The fourth FET has a gate to which the number of FETs corresponding to the tap coefficient is set by the control circuit, and the number of FET elements to be turned on among the plurality of FET elements is selected according to the number of FETs set by the control circuit, thereby changing the resistance value between the drain and source. A receiving device according to Technical Proposal 6.

[0140] Technical proposal 8 The control circuit before receiving the data signal; detecting a positive-side inversion tap coefficient at a boundary where the data value of the output value is inverted by changing the tap coefficient while supplying the second voltage to the equalizer circuit instead of the voltage of the data signal; The second voltage is supplied to the equalizer circuit in place of the first voltage, and the first voltage is supplied in place of the voltage of the data signal, and the tap coefficient is changed to detect a negative side inversion tap coefficient at a boundary where the data value of the output value is inverted. Upon receiving the data signal, setting the positive-side inverted tap coefficient for the positive-side tap coefficient circuit; Setting the negative side inverted tap coefficient for the negative side tap coefficient circuit A receiving device according to any one of technical proposals 5 to 7.

[0141] Technical proposal 9 the equalizer circuit includes a first equalizer circuit and a second equalizer circuit; the first equalizer circuit outputs the output value at every even-numbered clock timing; the second equalizer circuit outputs the output value at every odd-numbered clock timing; The control circuit before receiving the data signal; detecting a first inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted, by changing the tap coefficient while supplying the second voltage to the first equalizer circuit instead of the voltage of the data signal; detecting a second inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted, by changing the tap coefficient while supplying the second voltage to the second equalizer circuit instead of the voltage of the data signal; When receiving the data signal, the first inverted tap coefficient is set for the first equalizer circuit, and the second inverted tap coefficient is set for the second equalizer circuit. A receiving device according to Technical Proposal 1.

[0142] Technical proposal 10 the equalizer circuit includes N equalizer circuits from 1st to Nth (N is an integer of 2 or more), The nth (n is an integer between 1 and N) decision feedback equalizer outputs the output value at each (R+1)th sampling timing (R is the remainder when the total number of samples is divided by N), The control circuit before receiving the data signal; detecting an n-th inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted, by changing the tap coefficient while supplying the second voltage to the n-th equalizer circuit instead of the voltage of the data signal; When receiving the data signal, the nth inverted tap coefficient is set for the nth equalizer circuit. A receiving device according to Technical Proposal 1.

[0143] Technical proposal 11 1. A method of receiving a data signal representing a data value of 0 or 1, comprising: an equalizer circuit outputs an output value representing a result of comparing a voltage based on the received data signal with a first voltage serving as a reference at each clock timing corresponding to the data signal; a control circuit connected to the equalizer circuit, before receiving the data signal, supplies a second voltage different from the first voltage to the equalizer circuit instead of the voltage of the data signal, and changes tap coefficients related to characteristics of the equalizer circuit to detect an inverted tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted; The control circuit sets the inverted tap coefficients for the equalizer circuit when the data signal is received. Receiving method. [Explanation of symbols]

[0144] 20 Receiving device 22 Clock Buffer 24 1st decision feedback equalizer 26 Second decision feedback equalizer 27 1st SR latch 28 Second SR latch 29 First Flip-Flop 30 Second Flip-Flop 32 Switching circuit 34 Control circuit 42 Amplification circuit 44 Clock Inverter 46 Latch Circuit 52 1st FET 54 2nd FET 56 First Switch 58 Second Switch 60 Third Switch 62 Positive tap coefficient circuit 64 Negative tap coefficient circuit 66 Positive offset circuit 68 Negative offset circuit 72 3rd FET 74 4th Switch 76 4th FET 78 5th Switch 80 5th FET 82 6th FET 84 7th FET 86 8th FET 88 9th FET 90 10th FET 92 11th FET 94 12th FET 96 6th Switch

Claims

1. 1. A receiving device for receiving a data signal representing a data value of 0 or 1, comprising: an equalizer circuit that outputs an output value representing a result of comparing a voltage based on the received data signal with a first voltage serving as a reference at each clock timing corresponding to the data signal; a control circuit connected to the equalizer circuit; Equipped with The control circuit before receiving the data signal, a second voltage different from the first voltage is supplied to the equalizer circuit instead of the voltage of the data signal, and tap coefficients relating to characteristics of the equalizer circuit are changed to detect an inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted; When receiving the data signal, the inverted tap coefficient is set for the equalizer circuit. Receiving device.

2. The second voltage is a voltage obtained by adding an interference voltage that is applied to the data signal when the output value output at the previous clock timing is 1 to the first voltage.

2. The receiving device according to claim 1.

3. The control circuit detecting candidate values ​​for the inverted tap coefficients a plurality of times before receiving the data signal; When receiving the data signal, a statistically representative value based on a plurality of candidate values ​​of the inverted tap coefficient is set for the equalizer circuit.

2. The receiving device according to claim 1.

4. the equalizer circuit alternately repeats a reset period and a comparison period; The equalizer circuit an amplifier circuit that amplifies and outputs a voltage obtained by adding or subtracting a correction voltage from a voltage of the data signal during the comparison period and the first voltage, the correction voltage being a voltage obtained by multiplying a past output value, which is the output value output at a past clock timing, by the tap coefficient; a latch circuit that precharges a parasitic capacitance during the reset period and holds and outputs the value of the differential amplified signal during the comparison period; 4. The receiving device according to claim 1, further comprising:

5. The amplifier circuit a first FET having a gate to which the voltage of the data signal is applied; a second FET having a gate to which the first voltage is applied; a first switch that connects a source of the first FET and a source of the second FET to a power supply potential during the comparison period and disconnects the source of the first FET and the source of the second FET from the power supply potential during the reset period; a second switch that connects the drain of the first FET to a ground potential during the reset period and disconnects the drain of the first FET from the ground potential during the comparison period; a third switch that connects the drain of the second FET to the ground potential during the reset period and disconnects the drain of the second FET from the ground potential during the comparison period; a positive-side tap coefficient circuit connected in parallel to the drain and source of the second FET; a negative tap coefficient circuit connected in parallel to the drain and source of the first FET; Equipped with the positive-side tap coefficient circuit connects the drain and source of the second FET with a resistance value according to the tap coefficient when the past output value is 1, and disconnects the drain and source of the second FET when the past output value is 0; The negative tap coefficient circuit connects the drain and source of the first FET with a resistance value according to the tap coefficient when the past output value is 0, and disconnects the drain and source of the first FET when the past output value is 1.

5. The receiving device according to claim 4.

6. the equalizer circuit includes a first equalizer circuit and a second equalizer circuit; the first equalizer circuit outputs the output value at every even-numbered clock timing; the second equalizer circuit outputs the output value at every odd-numbered clock timing; The control circuit before receiving the data signal; detecting a first inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted, by changing the tap coefficient while supplying the second voltage to the first equalizer circuit instead of the voltage of the data signal; detecting a second inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted, by changing the tap coefficient while supplying the second voltage to the second equalizer circuit instead of the voltage of the data signal; When receiving the data signal, the first inverted tap coefficient is set for the first equalizer circuit, and the second inverted tap coefficient is set for the second equalizer circuit.

2. The receiving device according to claim 1.

7. the equalizer circuit includes N equalizer circuits from 1st to Nth (N is an integer of 2 or more), the n-th (n is an integer between 1 and N) decision feedback equalizer outputs the output value at each (R+1)-th sampling timing (R is the remainder when the total number of samples is divided by N); The control circuit before receiving the data signal; detecting an n-th inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted, by changing the tap coefficient while supplying the second voltage to the n-th equalizer circuit instead of the voltage of the data signal; When receiving the data signal, the nth inverted tap coefficient is set for the nth equalizer circuit.

2. The receiving device according to claim 1.

8. 1. A method of receiving a data signal representing a data value of 0 or 1, comprising the steps of: an equalizer circuit outputs an output value representing a result of comparing a voltage based on the received data signal with a first voltage serving as a reference at each clock timing corresponding to the data signal; before receiving the data signal, a second voltage different from the first voltage is supplied to the equalizer circuit instead of the voltage of the data signal, and tap coefficients relating to characteristics of the equalizer circuit are changed to detect an inversion tap coefficient, which is the tap coefficient at a boundary where the data value of the output value is inverted; When receiving the data signal, the inverted tap coefficient is set for the equalizer circuit. Receiving method.

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