Equalizer

Abstract

This equalizer comprises: a delay device (1) that delays a reception signal by a unit time; a delay device (2) that delays an output signal from the delay device (1) by the unit time; a slicer (3) that binarizes the reception signal; a multiplier (4) that multiplies a square wave outputted from the slicer (3) by a negative first tap coefficient; a multiplier (5) that multiplies the output signal from the delay device (1) by a positive second tap coefficient; a slicer (6) that binarizes an output signal from the delay device (2); a multiplier (7) that multiplies a square wave outputted from the slicer (6) by a negative third tap coefficient; and an adder (8) that adds output signals from the multipliers (4, 5, 7).

Description

equalizer

[0001] The present invention relates to a technique for improving waveform distortion caused by high-speed electrical signal transmission through signal compensation.

[0002] In high-speed serial electrical signal transmission, signal waveform distortion, mainly due to the attenuation characteristics of the transmission line in the high frequency band, is a problem. Equalizers are used as a technology for compensating for waveform distortion. Equalizers are used in USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express), among others. Equalizers are designed to achieve frequency characteristics that are the inverse of those of the transmission line in order to improve distortion caused by the transmission line characteristics. FIG. 10A shows an example of the waveform of an electrical signal with waveform distortion, and FIG. 10B shows an example of the waveform of an electrical signal improved by signal compensation using an equalizer.

[0003] There are several types of equalizers, including FFE (Feed Forward Equalizer), CTLE (Continuous Time Linear Equalizer), DFE (Decision Feedback Equalizer), etc. Among them, DFE is a technology that performs signal compensation by feeding back a rectangular wave from a slicer in a receiver (see Non-Patent Documents 1, 2, and 3).

[0004] 11 is a block diagram showing the configuration of a DFE. The DFE is composed of adder 100, which adds a received signal and a rectangular wave, slicer 101, which binarizes the output of adder 100 to 0 or 1, delayer 102, which delays the rectangular wave output from slicer 101 by unit time ΔT, delayer 103, which delays the output signal of delayer 102 by unit time ΔT, delayer 104, which delays the output signal of delayer 103 by unit time ΔT, multiplier 105, which multiplies the output signal of delayer 102 by a predetermined negative tap coefficient a1, multiplier 106, which multiplies the output signal of delayer 103 by a predetermined negative tap coefficient a2, multiplier 107, which multiplies the output signal of delayer 104 by a predetermined negative tap coefficient a3, and adder 108, which outputs a waveform obtained by adding the outputs of multipliers 105 to 107 to adder 100.

[0005] The operation of waveform compensation by the DFE is shown in Fig. 12. In Fig. 12, 200 denotes the received signal input to adder 100, 201 denotes the square wave output from multiplier 105, 202 denotes the square wave output from multiplier 106, and 203 denotes the square wave output from multiplier 107. Because the DFE uses the square wave from slicer 101, distortion is not added to the received signal, making it possible to compensate the signal without being affected by waveform distortion.

[0006] However, since the DFE uses a feedback signal from slicer 101, it cannot compensate for distortion before the arrival of the received signal (pre-cursor), but only compensates for distortion after the arrival of the received signal (post-cursor). Also, the DFE has a problem in that it is difficult to handle high-speed signals because the signal processing delay of the feedback section consisting of delay devices 102 to 104, multipliers 105 to 107, and adder 108 must be completed within one clock.

[0007] Sam Palermo, "ECEN720: High-Speed Links Circuits and Systems, Lecture 8: RX FIR, CTLE, DFE, & Adaptive Eq.", Texas A&M University, 2023, <https: / / people.engr.tamu.edu / spalermo / ecen689 / lecture8_ee720_rx_adaptive_eq.pdf> "PCIe 5.0 SerDes Test Methods", Anritsu Corporation, 2021, <https: / / pages.anritsu-jpresponse.com / rs / 408-MNE-052 / images / mp1900a-pcie-jr1101.pdf> Mohammad Hekmat, et al., "23.3 A 6Gb / s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm / 0.18μm CMOS for next-generation 8K displays", 2016 IEEE International Conference on Solid-State Circuits (ISSCC), 2016, <https: / / ieeexplore.ieee.org / document / <7418077>

[0008] The present invention has been made to solve the above problems, and an object thereof is to provide an equalizer that can easily handle high-speed signals and can compensate for precursor signals.

[0009] The equalizer of the present invention is characterized by comprising: a first delay device configured to give a delay of a unit time to a received signal; a second delay device configured to give a delay of the unit time to an output signal of the first delay device; a first slicer configured to binarize the received signal; a first multiplier configured to multiply a square wave output from the first slicer by a negative first tap coefficient; a second multiplier configured to multiply an output signal of the first delay device by a positive second tap coefficient; a second slicer configured to binarize an output signal of the second delay device; a third multiplier configured to multiply a square wave output from the second slicer by a negative third tap coefficient; and an adder configured to add output signals of the first, second, and third multipliers.

[0010] According to the present invention, since square waves from the first and second slicers are used, distortion is not added to the received signal, and signal compensation can be performed without the influence of waveform distortion. In the present invention, precursor signal compensation is possible by adding the square wave via the first slicer to the received signal delayed by the first delay device. Furthermore, in the present invention, the configuration of feeding back from the slicer to the received signal is eliminated, so that operation is not hindered even if processing in the first, second, and third multipliers and adders exceeds one clock, making it easier to support high-speed signals.

[0011] FIG. 1 is a block diagram showing the configuration of an equalizer according to a first embodiment of the present invention. FIG. 2 is a diagram explaining the operation of waveform compensation by the equalizer according to the first embodiment of the present invention. FIG. 3A is a diagram showing an example of a received signal in which waveform distortion has occurred. FIG. 3B is a diagram showing an example of an output signal of the equalizer according to the first embodiment of the present invention. FIG. 4A is a diagram showing an example of an output signal of a DFE. FIG. 4B is a diagram showing an example of an output signal of the equalizer according to the first embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of an FFE. FIG. 6 is a diagram explaining the operation of waveform compensation by the FFE. FIG. 7 is a block diagram showing the configuration of an equalizer according to a second embodiment of the present invention. FIG. 8 is a block diagram showing another configuration of the equalizer according to the first embodiment of the present invention. FIG. 9 is a block diagram showing another configuration of the equalizer according to the second embodiment of the present invention. FIG. 10A is a diagram showing an example of an electrical signal in which waveform distortion has occurred. FIG. 10B is a diagram showing an example of an electrical signal improved by signal compensation by the equalizer. FIG. 11 is a block diagram showing the configuration of a DFE. FIG. 12 is a diagram explaining the operation of waveform compensation by the DFE.

[0012] [First Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of an equalizer according to a first embodiment of the present invention. The equalizer includes a delay unit 1 that delays a received signal by a unit time ΔT, a delay unit 2 that delays an output signal of the delay unit 1 by a unit time ΔT, a slicer 3 that binarizes the received signal to 0 or 1, a multiplier 4 that multiplies the rectangular wave output from the slicer 3 by a predetermined negative tap coefficient b1, a multiplier 5 that multiplies the output signal of the delay unit 1 by a predetermined positive tap coefficient b2, a slicer 6 that binarizes the output signal of the delay unit 2 to 0 or 1, a multiplier 7 that multiplies the rectangular wave output from the slicer 6 by a predetermined negative tap coefficient b3, and an adder 8 that adds the output signals of the multipliers 4, 5, and 7.

[0013] The operation of waveform compensation according to this embodiment is shown in Fig. 2. In Fig. 2, 300 denotes a signal output from multiplier 5, 301 denotes a square wave output from multiplier 4, and 302 denotes a square wave output from multiplier 7.

[0014] 3A shows the simulation results of a received signal with waveform distortion, and FIG. 3B shows the simulation results of the output signal of the equalizer of this embodiment. The tap coefficients b1, b2, and b3 can be adjusted so that the eye opening is appropriate while observing the output signal of the equalizer.

[0015] 4A shows the simulation results of the output signal of the conventional DFE, and FIG. 4B shows the simulation results of the output signal of the equalizer of this embodiment. With the DFE, the eye opening of the output signal waveform was 62.4 ps wide and 158.4 mV high. On the other hand, with this embodiment, the eye opening was 71.5 ps wide and 200.6 mV high. It was confirmed that this embodiment can obtain a wider eye opening than the conventional DFE.

[0016] As described above, in this embodiment, as with the DFE, the rectangular waves from the slicers 3 and 6 are used, so distortion is not added to the received signal, and signal compensation can be performed without the influence of waveform distortion. In this embodiment, precursor signal compensation is possible by adding the rectangular wave via the slicer 3 to the received signal delayed by the delay device 1. Furthermore, in this embodiment, the configuration of feeding back from the slicer to the received signal is eliminated, so that operation is not hindered even if processing in the multipliers 4, 5, and 7 and the adder 8 exceeds one clock, making it easier to support high-speed signals.

[0017] 5 shows the configuration of an FFE, a technology similar to this embodiment. The FFE is composed of a multiplier 400 that multiplies the received signal by a predetermined negative tap coefficient c1, a delay unit 401 that delays the received signal by unit time ΔT, a multiplier 402 that multiplies the output signal of delay unit 401 by a predetermined positive tap coefficient c2, a delay unit 403 that delays the output signal of delay unit 401 by unit time ΔT, a multiplier 404 that multiplies the output signal of delay unit 403 by a predetermined negative tap coefficient c3, and an adder 405 that adds the output signals of multipliers 400, 402, and 404.

[0018] The operation of waveform compensation by the FFE is shown in Figure 6. In Figure 6, 500 is the signal output from multiplier 402, 501 is the signal output from multiplier 400, and 502 is the signal output from multiplier 404. The FFE is configured to compensate for distortion using the received signal rather than a square wave. In the FFE, if the received signal contains waveform distortion, the distortion is also added during the compensation process. As shown in Figures 5 and 6, it can be seen that the equalizer of this embodiment is different from conventional FFEs.

[0019] 7 is a block diagram showing the configuration of an equalizer according to a second embodiment of the present invention. The equalizer of this embodiment includes a delay unit 11 that delays the received signal by a unit time ΔT, a slicer 12 that binarizes the received signal to 0 or 1, a delay unit 13 that delays the output signal of slicer 12 by 2ΔT, a multiplier 14 that multiplies the rectangular wave output from slicer 12 by a predetermined negative tap coefficient b1, a multiplier 15 that multiplies the output signal of delay unit 11 by a predetermined positive tap coefficient b2, a multiplier 16 that multiplies the rectangular wave output from delay unit 13 by a predetermined negative tap coefficient b3, and an adder 17 that adds the output signals of multipliers 14 to 16.

[0020] This embodiment achieves the same effect as the first embodiment with a single slicer, and is configured to branch the output of the slicer 12 according to the number of taps for signal compensation. Since this embodiment uses only one slicer, it is possible to simplify the circuit and reduce costs compared to the first embodiment.

[0021] [Third Embodiment] In the first and second embodiments, the number of taps is set to 3, but the number of taps may be set to N (N is an integer greater than 3). The greater the number of taps, the more precise the compensation for the front and rear of the waveform. FIG. 8 shows a configuration in which the equalizer of the first embodiment has N taps. The equalizer of FIG. 8 includes n (n is an integer greater than or equal to 2) cascaded delay devices 1-1 to 1-n that delay the received signal by a unit time ΔT, m (m is an integer greater than or equal to 2) cascaded delay devices 2-1 to 2-m that delay the output signal of the delay device 1-n in the final stage by a unit time ΔT, a slicer 3-1 that binarizes the received signal to 0 or 1, (n-1) slicers 3-2 to 3-n that binarize the output signals of the delay devices 1-1 to 1-(n-1) in the first to (n-1)th stages to 0 or 1, respectively, and a rectangular wave output from the slicers 3-1 to 3-n. The system is composed of n multipliers 4-1 to 4-n, each multiplying by a predetermined negative tap coefficient b1_1 to b1_n, a multiplier 5 multiplying the output signal of the final-stage delay device 1-n by a predetermined positive tap coefficient b2, m slicers 6-1 to 6-m binarizing the output signals of the delay devices 2-1 to 2-m to 0 or 1, m multipliers 7-1 to 7-m multiplying the rectangular waves output from the slicers 6-1 to 6-m by a predetermined negative tap coefficient b3_1 to b3_m, and an adder 8 adding the output signals of the multipliers 4-1 to 4-n, 5, 7-1 to 7-m.

[0022] The configuration of the equalizer of the second embodiment when it is an N-tap is shown in Fig. 9. The equalizer of Fig. 9 includes n delay devices 11-1 to 11-n connected in cascade to give a delay of unit time ΔT to the received signal, a slicer 12-1 that binarizes the received signal to 0 or 1, (n-1) slicers 12-2 to 12-n that binarize the output signals of the delay devices 11-1 to 11-(n-1) in the first to (n-1)th stages to 0 or 1, a delay device 13-1 that gives a delay of (n+1)ΔT to the output signal of the slicer 12-1, and (m-1) delay devices 13-2 that give a delay of unit time ΔT to the output signal of the delay device 13-1. to 13-m, n multipliers 14-1 to 14-n that multiply the rectangular waves output from slicers 12-1 to 12-n by predetermined negative tap coefficients b1_1 to b1_n, respectively, a multiplier 15 that multiplies the output signal of delay device 11-n in the final stage by a predetermined positive tap coefficient b2, m multipliers 16-1 to 16-m that multiply the rectangular waves output from delay devices 13-1 to 13-m by predetermined negative tap coefficients b3_1 to b3_m, respectively, and an adder 17 that adds up the output signals of multipliers 14-1 to 14-n, 15, 16-1 to 16-m.

[0023] In the configurations of Figures 8 and 9, the number of taps N = n + m + 1. In the configurations of Figures 8 and 9, the tap coefficients b1_1 to b1_n may be the same value or different values. Similarly, the tap coefficients b3_1 to b3_m may be the same value or different values. As in the first embodiment, the tap coefficients b1_1 to b1_n, b2, and b3_1 to b3_m may be adjusted so that the eye opening of the output signal of the equalizer is appropriate.

[0024] 1 and 8, it is assumed that the delay of slicers 3, 3-1 to 3-n, 6, 6-1 to 6-m is negligibly small compared to the delay amount of delay devices 1, 1-1 to 1-n, 2, 2-1 to 2-m. On the other hand, in the configurations of Figures 7 and 9, slicers 12, 12-1 to 12-n can be operated as an equalizer even if the delay exceeds the delay amount of delay devices 11, 11-1 to 11-n, 13, 13-1 to 13-m.

[0025] In the first to third embodiments, examples have been described in which electrical signals are transmitted by wire, but the present invention can also be applied in the same way to cases in which optical communication or wireless communication sections exist within the transmission line.

[0026] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0027] (Supplementary Note 1) The equalizer of the present invention comprises a first delay device configured to give a delay of a unit time to a received signal, a second delay device configured to give a delay of the unit time to an output signal of the first delay device, a first slicer configured to binarize the received signal, a first multiplier configured to multiply a square wave output from the first slicer by a negative first tap coefficient, a second multiplier configured to multiply an output signal of the first delay device by a positive second tap coefficient, a second slicer configured to binarize an output signal of the second delay device, a third multiplier configured to multiply a square wave output from the second slicer by a negative third tap coefficient, and an adder configured to add output signals of the first, second, and third multipliers.

[0028] (Supplementary Note 2) The equalizer of the present invention comprises a first delay device configured to give a delay of a unit time to a received signal, a slicer configured to binarize the received signal, a second delay device configured to give a delay of twice the unit time to an output signal of the slicer, a first multiplier configured to multiply a square wave output from the slicer by a negative first tap coefficient, a second multiplier configured to multiply an output signal of the first delay device by a positive second tap coefficient, a third multiplier configured to multiply a square wave output from the second delay device by a negative third tap coefficient, and an adder configured to add output signals of the first, second, and third multipliers.

[0029] (Supplementary Note 3) The equalizer of the present invention comprises n (n is an integer of 2 or more) first delay devices cascaded to give a delay of unit time to a received signal, m (m is an integer of 2 or more) second delay devices cascaded to give a delay of unit time to an output signal of the first delay device in the final stage, a first slicer configured to binarize the received signal, (n-1) second slicers configured to binarize output signals of the first to (n-1)th stages of the first delay devices, respectively, and a signal output from the first and second slicers. The input / output amplifier comprises n first multipliers configured to multiply a rectangular wave by a negative first tap coefficient, a second multiplier configured to multiply an output signal of the first delay device in the final stage by a positive second tap coefficient, m third slicers configured to binarize the output signals of the second delay devices, m third multipliers configured to multiply the rectangular wave output from the third slicers by a negative third tap coefficient, and an adder configured to add the output signals of the first, second, and third multipliers.

[0030] (Supplementary Note 4) The equalizer of the present invention comprises n (n is an integer of 2 or more) first delay devices cascade-connected to give a delay of a unit time to a received signal, a first slicer configured to binarize the received signal, (n-1) second slicers configured to binarize output signals of the first delay devices from the first stage to the (n-1)th stage, respectively, a second delay device configured to give a delay of (n+1) times the unit time to the output signal of the first slicer, and a second delay device configured to give a delay of the unit time to the output signal of the second delay device. The multiplier comprises (m-1) cascaded third delay devices, n first multipliers configured to multiply the rectangular waves output from the first and second slicers by negative first tap coefficients, a second multiplier configured to multiply the output signal of the first delay device in the final stage by a positive second tap coefficient, m third multipliers configured to multiply the rectangular waves output from the second and third delay devices by negative third tap coefficients, and an adder configured to add the output signals of the first, second, and third multipliers.

[0031] The present invention can be applied to signal compensation techniques.

[0032] 1, 1-1 to 1-n, 2, 2-1 to 2-m, 11, 11-1 to 11-n, 13, 13-1 to 13-m... delay devices, 3, 3-1 to 3-n, 6, 6-1 to 6-m, 12, 12-1 to 12-n... slicers, 4, 4-1 to 4-n, 5, 7, 7-1 to 7-m, 14, 14-1 to 14-n, 16, 16-1 to 16-m... multipliers, 8, 17... adder.

Claims

1. An equalizer comprising: a first delay device configured to delay a received signal by a unit time; a second delay device configured to delay an output signal of the first delay device by the unit time; a first slicer configured to digitize the received signal; a first multiplier configured to multiply a square wave output from the first slicer by a negative first tap coefficient; a second multiplier configured to multiply an output signal of the first delay device by a positive second tap coefficient; a second slicer configured to digitize an output signal of the second delay device; a third multiplier configured to multiply a square wave output from the second slicer by a negative third tap coefficient; and an adder configured to add output signals of the first, second, and third multipliers.

2. An equalizer comprising: a first delay device configured to delay a received signal by a unit time; a slicer configured to binarize the received signal; a second delay device configured to delay an output signal of the slicer by twice the unit time; a first multiplier configured to multiply a rectangular wave output from the slicer by a negative first tap coefficient; a second multiplier configured to multiply an output signal of the first delay device by a positive second tap coefficient; a third multiplier configured to multiply a rectangular wave output from the second delay device by a negative third tap coefficient; and an adder configured to add the output signals of the first, second, and third multipliers.

3. n (n is an integer of 2 or more) first delay devices cascaded to give a delay of a unit time to a received signal; m (m is an integer of 2 or more) second delay devices cascaded to give a delay of the unit time to an output signal of the first delay device in the final stage; a first slicer configured to binarize the received signal; (n-1) second slicers configured to binarize output signals of the first delay devices in the first to (n-1)th stages, respectively; n first multipliers configured to multiply rectangular waves output from the first and second slicers by a negative first tap coefficient, respectively; a second multiplier configured to multiply an output signal of the first delay device in the final stage by a positive second tap coefficient; and m third slicers configured to binarize output signals of the second delay devices, respectively. an equalizer comprising: m third multipliers configured to multiply the rectangular waves output from the third slicer by negative third tap coefficients, respectively; and an adder configured to add the output signals of the first, second, and third multipliers.

4. n (n is an integer of 2 or more) first delay devices cascaded to give a delay of a unit time to a received signal; a first slicer configured to binarize the received signal; (n-1) second slicers configured to binarize output signals of the first delay devices from the first stage to the (n-1)th stage, respectively; a second delay device configured to give a delay of (n+1) times the unit time to the output signal of the first slicer; (m-1) third delay devices cascaded to give a delay of the unit time to the output signal of the second delay device; n first multipliers configured to multiply the rectangular waves output from the first and second slicers by a negative first tap coefficient, respectively; and a second multiplier configured to multiply the output signal of the first delay device in the final stage by a positive second tap coefficient. an equalizer comprising: m third multipliers configured to multiply the rectangular waves output from the second and third delay devices by negative third tap coefficients, respectively; and an adder configured to add the output signals of the first, second, and third multipliers.

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