Data stream processing method and apparatus

Abstract

To provide a method and an apparatus for recovering a data stream even when the number of physical lanes of a receiving end is not 2n.SOLUTION: In a data stream processing method, a first chip acquires a first data stream. The acquired first data stream includes a first alignment marker. The first chip periodically inserts a second alignment marker into the first data stream in order to obtain a second data stream, and sends the second data stream through a plurality of physical lanes. A second chip receives a plurality of second data sub-streams from the first chip, each of the plurality of second data sub-streams including a second alignment sub-marker. The second chip aligns the plurality of second data sub-streams based on the second alignment sub-markers in the plurality of second data sub-streams and converts the plurality of second data sub-streams to the first data stream.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] This application is This is a divisional application of Japanese Patent Application No. 2022-534296 filed on September 29, 2020. December 6, 2019 Out Prayed Tanaka Priority is claimed from National Patent Application No. 201911243779.9 The disclosures of the aforementioned applications are incorporated by reference in their entireties. It is incorporated here.

[0002] The present application relates to the field of communications, and in particular to a method and apparatus for processing data streams. [Background technology]

[0003] A data stream may be transmitted via multiple physical lanes (PL) to achieve high-speed transmission of the data stream over an Ethernet interface. The transmitting end may convert one data stream into multiple data substreams and simultaneously transmit the multiple data substreams to a receiving end via the multiple physical lanes. During the process of transmitting the data stream from the transmitting end to the receiving end, different delays may occur for different physical lanes. As a result, the multiple data substreams arrive at the receiving end at different times. Currently, a frequently used method is to insert alignment markers (AM) into the data stream, so that the receiving end can restore the multiple data substreams into a data stream. In this way, the receiving end can align the data substreams based on the alignment markers in the multiple data substreams to restore the aligned data stream.

[0004] However, this method requires a network with two physical lanes. n (n is a positive integer) and the number of physical lanes is 2. n If not, the receiving end will not be able to recover the data stream using the methods described above. Summary of the Invention [Means for solving the problem]

[0005] In the embodiment of the present application, the receiving end has two physical lanes. n To provide a data stream processing method and apparatus so that the data stream can be restored even when it is not.

[0006] According to a first aspect, an embodiment of the present application provides a data stream processing method. The method can be applied to a first chip. The first chip can be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a central processing unit (CPU) chip, or a programmable logic device (PLD), etc. This is not particularly limited in the present application. The method includes the following steps: First, the first chip acquires a first data stream, where the first data stream includes a first alignment marker. The first data stream is a data stream acquired by a conventional method, and the period and size of the first data stream are each 2. n Second, the first chip periodically inserts a second alignment marker into the first data stream to obtain the second data stream. Finally, the first chip transmits the second data stream over multiple physical lanes, and the number of the multiple physical lanes is 2. n and n is a positive integer. nTo transmit the first data stream over physical lanes that are not identical, the insertion period of the second alignment markers and the size of each second alignment marker are determined based on a first condition or a second condition, where the first condition is the number of physical lanes, and the second condition is the ratio of the number of physical lanes and the rate of the second data stream to the rate of the first data stream. The common part of the first condition and the second condition is that the insertion period of the second alignment markers and the size of each second alignment marker are each an integer multiple of the number of physical lanes. Therefore, the second alignment markers can be evenly allocated to all physical lanes. In this way, a receiving end receiving the second data stream can align the second data substream based on the second alignment markers and restore the first data stream based on the aligned second data substream. Therefore, the number of physical lanes can be increased by two while ensuring that the insertion period and size of the first alignment markers are not changed. n In addition, the second condition further includes a ratio of the rate of the second data stream to the rate of the first data stream, where the rate of the second data stream is equal to or greater than the rate of the first data stream, and the traffic per unit time corresponding to the rate of the second data stream is an integer multiple of the number of physical lanes. n To transmit a data stream over physical lanes that are not aligned, the second alignment markers may be evenly allocated to all physical lanes while ensuring that the entire second data stream can be evenly allocated to all physical lanes.

[0007] In this embodiment of the present application, the second alignment marker can be inserted into the first data stream in two possible implementations.

[0008] OneIn one possible implementation, the first chip first converts the first data stream into multiple first data substreams and then inserts a second alignment submarker into each first data substream. Specifically, the second alignment marker includes multiple second alignment submarkers, the number of the multiple second alignment submarkers equals the number of physical lanes, and the size of each second alignment submarker is the number m of data blocks, where m is a ratio of the size of the second alignment marker to the number of physical lanes, and m is a positive integer. First, the first chip converts the first data stream into multiple first data substreams based on the number of physical lanes, each of the multiple first data substreams corresponding to one physical lane. Next, the first chip periodically inserts second alignment submarkers into each first data substream to obtain multiple second data substreams. Finally, the first chip transmits the multiple second data substreams over the multiple physical lanes.

[0009] In another embodiment, the first chip first inserts a second alignment marker into the first data stream to obtain a second data stream, then converts the second data stream into multiple second data substreams, and distributes the multiple second data substreams over multiple physical lanes.

[0010] In this embodiment of the present application, the position of the second alignment marker may be associated with the position of the first alignment marker. Specifically, the first chip may first determine the insertion position of the second alignment marker based on the position of the first alignment marker in the first data stream and a preset distance. Then, the first chip periodically inserts the second alignment marker into the first data stream based on the insertion position of the second alignment marker, and the insertion period of the second alignment marker is equal to or greater than a common multiple of the insertion period of the first alignment marker and the number of physical lanes. When the position of the second alignment marker is associated with the position of the first alignment marker, the receiving end may identify the position of the first alignment marker based on the position of the second alignment marker for subsequent processing. Alternatively, when the second data stream does not include the first alignment marker, the receiving end may restore the first alignment marker based on the position of the second alignment marker to restore the first data stream.

[0011] In this embodiment of the present application, when the rate of the second data stream is greater than the rate of the first data stream, the method further includes the first chip inserting padding data into the first data stream, where the padding data is, for example, a random sequence. To distribute the second data stream to multiple physical lanes, the padding data is inserted into the first data stream so that the traffic of the second data stream per unit time can be accurately divided by the number of physical lanes. Optionally, the first chip may insert the padding data into the first data stream periodically or non-periodically, which is not particularly limited in this embodiment of the present application.

[0012] In this embodiment of the present application, when the rate of the second data stream is equal to the rate of the first data stream, a second alignment marker is inserted, and therefore the first alignment marker needs to be correspondingly deleted.

[0013] In a possible implementation, the first chip may delete the first alignment marker before inserting the second alignment marker. Specifically, the first chip first deletes the first alignment marker from the first data stream to obtain the third data stream. Then, the first chip periodically inserts the second alignment marker into the third data stream to obtain the second data stream. Correspondingly, the product of the size of the second alignment marker and the period of the second alignment marker is equal to the product of the size of the first alignment marker and the period of the first alignment marker, thereby ensuring that the rate of the second data stream is equal to the rate of the first data stream.

[0014] In another possible implementation, the first chip may first insert the second alignment marker and then delete the first alignment marker. Specifically, the first chip may first delete the first alignment marker from the second data stream to obtain a fourth data stream. Then, the first chip may transmit the fourth data stream over multiple physical lanes. Similarly, the product of the size of the second alignment marker and the period of the second alignment marker is equal to the product of the size of the first alignment marker and the period of the first alignment marker, thereby ensuring that the rate of the second data stream is equal to the rate of the first data stream.

[0015] According to a second aspect, an embodiment of the present application provides a data stream processing method. The method may be applied to a second chip. The specific implementation of the second chip is similar to that of the first chip. For details, please refer to the above description. The details will not be described again here. The method may include the following steps: First, the second chip receives a plurality of second data substreams, each of which includes a second alignment submarker. Next, the second chip aligns the plurality of second data substreams based on the second alignment submarkers in the plurality of second data substreams. Finally, the second chip converts the plurality of second data substreams into a first data stream, where the first data stream does not include the second alignment submarker. In this embodiment of the present application, since the second alignment submarkers are aligned within the plurality of second data substreams, the second data substreams can be aligned based on the second alignment submarkers. In addition, the size and period of the second alignment sub-marker are 2 n This does not conform to existing standards for alignment markers in data streams, so the second alignment submarker must be removed to restore a standard-compliant first data stream.

[0016] In this embodiment of the present application, the second chip can convert the multiple second data substreams into the first data stream in two possible implementations.

[0017] In one possible embodiment, the second chip may first remove the second alignment sub-markers from the second data sub-streams and then combine them to obtain one data stream. Specifically, the second chip may first remove the second alignment sub-markers from the second data sub-streams to obtain the first data sub-streams. Then, the second chip may combine the first data sub-streams to obtain the first data stream.

[0018] In another possible implementation, the second chip may first combine the second data substreams into one data stream and then remove the second alignment markers from the data stream. Specifically, the second chip may first combine multiple second data substreams into a second data stream and then remove the multiple alignment markers from the data stream. Second The second chip combines the second alignment sub-markers in the data sub-streams into a second alignment marker, and then removes the second alignment marker from the second data stream to obtain the first data stream.

[0019] In this embodiment of the present application, when the second data substream further includes padding data, the second chip needs to further remove the padding data to restore the standard first data stream. Similar to removing the second alignment marker, the padding data can also be removed in two implementations.

[0020] In one possible implementation, the second chip first removes padding data from multiple second data substreams to obtain first data substreams, and then combines the first data substreams into the first data stream.

[0021] If the position of the second alignment submarker is associated with the position of the padding data, the second chip deletes the padding data from the plurality of second data substreams based on the position of the second alignment submarker and the first preset positional relationship. The first preset positional relationship is the positional relationship between the second alignment submarker and the padding data. The second chip can quickly find the padding data using the above-described method to delete the padding data.

[0022] In another possible implementation, the second chip first combines multiple second data substreams into a second data stream to obtain the first data stream, and then removes the padding data from the second data stream.

[0023] If the position of the second alignment sub-marker is associated with the position of the padding data, the second chip deletes the padding data from the plurality of second data streams based on the position of the second alignment marker and the second preset positional relationship. The second preset positional relationship is the positional relationship between the second alignment marker and the padding data. The second chip can quickly find the padding data using the above-described method to delete the padding data.

[0024] In this embodiment of the present application, the second data sub-stream may not include the first alignment marker, in which case the first alignment marker needs to be restored.

[0025] In a possible embodiment, the second chip may first delete the second alignment sub-markers and then restore the first alignment markers. Specifically, to obtain the first data sub-streams, the second chip deletes the second alignment sub-markers from the second data sub-streams and inserts the first alignment sub-markers into the second data sub-streams based on the positions of the second alignment sub-markers and a third preset positional relationship. The third preset positional relationship is the relationship between the insertion positions of the first alignment sub-markers and the positions of the second alignment sub-markers.

[0026] In another possible implementation, the second chip may first restore the first alignment marker and then delete the second alignment sub-marker. Specifically, to obtain the first data stream, the second chip deletes the second alignment marker from the second data stream and inserts the first alignment marker into the second data stream based on the position of the second alignment marker and a fourth preset positional relationship. The fourth preset positional relationship is the relationship between the insertion position of the first alignment marker and the position of the second alignment marker.

[0027] According to a third aspect, an embodiment of the present application provides a data stream processing device. The device is applied to a first chip. The device includes an acquisition unit, an insertion unit, and a transmission unit. The acquisition unit is configured to acquire a first data stream, where the first data stream includes a first alignment marker. The insertion unit is configured to periodically insert a second alignment marker into the first data stream to acquire a second data stream. The transmission unit transmits the second data stream via a plurality of physical lanes, where the number of the plurality of physical lanes is two. n and n is a positive integer. The insertion period of the second alignment markers and the size of each second alignment marker are determined based on a first condition or a second condition. The first condition is the number of the plurality of physical lanes, and the second condition is the number of the plurality of physical lanes and the ratio of the rate of the second data stream to the rate of the first data stream. The insertion period of the second alignment markers and the size of each second alignment marker are each an integer multiple of the number of the plurality of physical lanes. The rate of the second data stream is equal to or greater than the rate of the first data stream, and the traffic per unit time corresponding to the rate of the second data stream is an integer multiple of the number of physical lanes.

[0028] Optionally, the second alignment marker includes a plurality of second alignment sub-markers, the number of the plurality of second alignment sub-markers being equal to the number of the plurality of physical lanes, and a size of each second alignment sub-marker being equal to the number m of data blocks, where m is a ratio of the size of the second alignment marker to the number of the plurality of physical lanes, and m is a positive integer. The insertion unit is configured to convert the first data stream into a plurality of first data sub-streams based on the number of the plurality of physical lanes, each of the plurality of first data sub-streams corresponding to one physical lane, and to periodically insert the second alignment sub-marker into each first data sub-stream to obtain a plurality of second data sub-streams. The transmission unit is configured to transmit the plurality of second data sub-streams via the plurality of physical lanes.

[0029] Optionally, the apparatus further includes a determining unit configured to determine insertion positions of second alignment markers based on positions of the first alignment markers in the first data stream and the predetermined distance, and the inserting unit is configured to periodically insert the second alignment markers into the first data stream based on the insertion positions of the second alignment markers, wherein the insertion period of the second alignment markers is greater than or equal to a common multiple of the insertion period of the first alignment markers and the number of the plurality of physical lanes.

[0030] Optionally, the insertion unit is further configured to insert padding data into the first data stream when the rate of the second data stream is greater than the rate of the first data stream.

[0031] Optionally, the insertion unit is configured to periodically insert padding data into the first data stream.

[0032] Optionally, the padding data is a random sequence.

[0033] Optionally, when the rate of the second data stream is equal to the rate of the first data stream, the insertion unit is configured to delete the first alignment markers from the first data stream to obtain the third data stream, and periodically insert the second alignment markers into the third data stream to obtain the second data stream, wherein the product of the size of the second alignment markers and the period of the second alignment markers is equal to the product of the size of the first alignment markers and the period of the first alignment markers.

[0034] Optionally, when the rate of the second data stream is equal to the rate of the first data stream, the transmitting unit is configured to remove the first alignment marker from the second data stream to obtain a fourth data stream, and transmit the fourth data stream via the plurality of physical lanes, wherein a product of a size of the second alignment marker and a period of the second alignment marker is equal to a product of a size of the first alignment marker and a period of the first alignment marker.

[0035] According to a fourth aspect, an embodiment of the present application provides a data stream processing device. The device is applied to a second chip. The device includes a receiving unit, an alignment unit, and a conversion unit. The receiving unit is configured to receive a plurality of second data substreams, each of the plurality of second data substreams including a second alignment submarker. The alignment unit is configured to align the plurality of second data substreams based on the second alignment submarkers in the plurality of second data substreams. The conversion unit is configured to convert the plurality of second data substreams into a first data stream, the first data stream not including the second alignment submarker.

[0036] Optionally, the conversion unit is configured to remove the second alignment sub-markers from the plurality of second data sub-streams to obtain the plurality of first data sub-streams, and combine the plurality of first data sub-streams into the first data stream.

[0037] Optionally, the conversion unit combines the plurality of second data sub-streams into a second data stream, and converts the plurality of Second The method is configured to combine the second alignment sub-markers in the data sub-streams into a second alignment marker and remove the second alignment marker from the second data stream to obtain the first data stream.

[0038] Optionally, the second data substreams further include padding data. The conversion unit is configured to remove the padding data from the plurality of second data substreams to obtain the first data substreams and combine the first data substreams into the first data stream.

[0039] Optionally, the conversion unit is configured to remove padding data from the plurality of second data sub-streams based on positions of the second alignment sub-markers and a first preset positional relationship, where the first preset positional relationship is a positional relationship between the second alignment sub-markers and the padding data.

[0040] Optionally, the second data substreams further include padding data. The conversion unit is configured to combine the plurality of second data substreams into a second data stream and remove the padding data from the second data stream to obtain the first data stream.

[0041] Optionally, removing the padding data from the second data streams includes removing the padding data from the plurality of second data streams based on positions of the second alignment markers and a second preset positional relationship, wherein the second preset positional relationship is a positional relationship between the second alignment markers and the padding data.

[0042] Optionally, deleting the second alignment sub-markers from the plurality of second data sub-streams to obtain the first data sub-streams includes deleting the second alignment sub-markers from the plurality of second data sub-streams to obtain the first data sub-streams, and inserting the first alignment sub-markers into the second data sub-streams based on positions of the second alignment sub-markers and a third preset positional relationship, wherein the third preset positional relationship is a relationship between insertion positions of the first alignment sub-markers and positions of the second alignment sub-markers.

[0043] Optionally, deleting the second alignment marker from the second data stream to obtain the first data stream includes deleting the second alignment marker from the second data stream to obtain the first data stream, and inserting the first alignment marker into the second data stream based on a position of the second alignment marker and a fourth preset positional relationship, wherein the fourth preset positional relationship is a relationship between an insertion position of the first alignment marker and a position of the second alignment marker.

[0044] According to a fifth aspect, an embodiment of the present application provides a computer-readable storage medium containing a computer program, which, when run on a computer, enables the computer to perform the data stream processing method described above.

[0045] According to a sixth aspect, an embodiment of the present application provides a network device including the aforementioned data stream processing device applied in a first chip and / or the aforementioned data stream processing device applied in a second chip. [Brief explanation of the drawings]

[0046] [Figure 1] FIG. 2 is a schematic diagram of one data stream according to an embodiment of the present application. [Figure 2] 2 is a schematic diagram of any two of the 16 data sub-streams obtained by transforming the data stream of FIG. 1 according to an embodiment of the present application; [Figure 3] 2 is a schematic diagram of any three of the twelve data sub-streams obtained by transforming the data stream of FIG. 1 according to an embodiment of the present application. [Figure 4] 1 is a schematic diagram of a network device 100 according to an embodiment of the present application. [Figure 5] 1 is a flowchart of a data stream processing method according to an embodiment of the present application; [Figure 6] FIG. 10 is a schematic diagram of inserting a second alignment sub-marker into a second data sub-stream according to an embodiment of the present application; [Figure 7] FIG. 10 is a schematic diagram of the insertion position of the second alignment marker and the position of the first alignment marker according to an embodiment of the present application. [Figure 8] FIG. 2 is a schematic diagram of inserting padding data and a second alignment marker into a first data sub-stream according to an embodiment of the present application; [Figure 9] 1 is a block diagram of the structure of a data stream processing device according to an embodiment of the present application; [Figure 10] FIG. 2 is a block diagram of the structure of another data stream processing apparatus according to an embodiment of the present application; [Figure 11] 1 is a schematic diagram of a data stream processing device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0047] For ease of understanding, a data stream can be considered to include multiple consecutive data blocks, and the size of each data block is the traffic of the data stream per unit time. For example, the size of one data block is 1 bit, 8 bits, or 10 bits. When the data stream is delivered to a physical lane, the data stream may be delivered in data blocks or 1 bit.

[0048] In conventional methods, the size and period of alignment markers in the data stream are set to the number of physical lanes, i.e., 2 nFor example, when the number of physical lanes is 16, the period of the alignment marker is 16t (t is a positive integer). In other words, one alignment marker is inserted into the data stream at an interval of 16t data blocks. The size of each alignment marker is the number of data blocks, 16w (w is a positive integer). (For ease of explanation, the size of the alignment markers described below will be expressed in terms of the number of data blocks.) FIG. 1 is a schematic diagram of one data stream. In this diagram, the white blocks represent data blocks in the data stream, and the black blocks represent alignment markers. FIG. 2 is a schematic diagram of any two of the 16 data substreams obtained by converting the data stream. From FIG. 2, it can be seen that since the size of the alignment marker is the number of data blocks, 16w, all alignment markers can be allocated evenly to all data substreams. In addition, since the period of the alignment marker is an integer multiple of the number of physical lanes, the positions of the alignment markers in all data substreams are the same. Specifically, the alignment markers of the two data substreams are aligned. When receiving the 16 data substreams shown in Figure 2, the receiving end can align the 16 data substreams based on the alignment markers in the 16 data substreams to restore the data stream shown in Figure 1.

[0049] However, the number of physical lanes is 2 n If not, the size and period of the alignment markers are still 2 n When the data stream is converted into multiple data substreams, the alignment markers in the data substreams are not aligned, so that after receiving the multiple data substreams, the receiving end cannot restore the original data stream based on the alignment markers.

[0050] Assume that the number of physical lanes is 12, the period of the alignment marker still includes 16t (where t is a positive integer) data blocks, and the size of the alignment marker still is 16w. In this case, after the data stream is converted into 12 data substreams, the alignment markers cannot be allocated evenly to all data substreams, and the positions of the alignment markers in all data substreams are also different. Figure 3 is a schematic diagram of three data substreams. It can be seen that the alignment markers in the three data substreams are not aligned. Therefore, the receiving end cannot restore the data stream of Figure 1 based on the alignment markers in the three data substreams.

[0051] To solve the technical problem, the embodiment of the present application is directed to a receiving end that has two physical lanes. n To provide a data stream processing method and apparatus so that the data stream can be restored even when it is not.

[0052] For ease of understanding, the application scenario in the embodiment of this application is first described.

[0053] 4 is a schematic diagram of a network device 100. The network device 100 may be a router, a switch, or the like. The network device 100 includes a chip 101 and a chip 102. The chip 101 and the chip 102 may be connected via a backbone, a parallel bus, or the like.

[0054] The chip 101 includes at least one interface, which may be, for example, an Ethernet interface. Each interface may include multiple physical lanes, which are configured to transmit data streams. Each physical lane may correspond to a serializer and a deserializer, which are simply called SerDes.

[0055] The chip 102 includes at least one interface, which may be, for example, an Ethernet interface. Each interface may include multiple physical lanes, which are configured to receive data streams. Each physical lane may correspond to a pair of SerDes.

[0056] Each of chip 101 and chip 102 may be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a central processing unit (CPU) chip, or a programmable logic device (PLD), etc., which is not particularly limited in this application.

[0057] 4 does not constitute a limitation on the technical solution of the present application. Those skilled in the art can design the application scenario based on a specific situation. For example, the chip 101 and the chip 102 are distributed in different network devices.

[0058] FIG. 5 is a flowchart of a data stream processing method according to an embodiment of the present application.

[0059] The following describes the data stream processing method provided in this embodiment of the present application with reference to FIGS.

[0060] S101: A first chip acquires a first data stream, where the first data stream includes a first alignment marker.

[0061] In this embodiment of the present application, for example, the first chip may be chip 101 in the embodiment shown in Figure 4. The first chip acquires a first data stream. The period of the first alignment marker included in the first data stream is S*2 n , i.e., S2 n The size of the first alignment marker is L*2 n , i.e., L2 n The first data stream is a data stream obtained in a conventional manner. In this embodiment of the present application, the number of physical lanes is 2 n where n is a positive integer. Therefore, the first data stream cannot be recovered at the receiving end by using only the first alignment marker.

[0062] In addition, in this embodiment of the present application, the number of physical lanes may alternatively be, for example, the number of SerDeses. For example, if the 400G interface of the first chip uses 6 pairs of SerDeses to transmit data, the number of physical lanes of the interface is 6.

[0063] S102: The first chip periodically inserts a second alignment marker into the first data stream to obtain a second data stream.

[0064] In this embodiment of the present application, the second alignment marker may be the same as or different from the first alignment marker. For details, see the description below. If the second alignment marker is different from the first alignment marker, the second alignment marker must satisfy the condition that the second alignment marker can be identified from the second data stream and distinguished from the first alignment marker.

[0065] S103: The first chip transmits a second data stream to the second chip via multiple physical lanes.

[0066] In order to enable the receiving end to recover the first data stream, in this embodiment of the present application, the first chip periodically inserts a second alignment marker into the first data stream to obtain the second data stream.

[0067] The insertion period of the second alignment markers is an integer multiple of the number of the plurality of physical lanes. In addition, the size of each second alignment marker is also an integer multiple of the number of the plurality of physical lanes. In this embodiment of the present application, the size of the second alignment marker is the number of data blocks included in the second alignment marker. The data blocks included in the second alignment marker can be evenly allocated to and aligned among the plurality of physical lanes.

[0068] For example, if the number of physical lanes is 12 and the period of the first alignment marker includes 16 data blocks, the period of the second alignment marker may include, for example, 48 data blocks, 96 data blocks, or 144 data blocks. If the period of the second alignment marker includes 48 data blocks, this indicates that one second alignment marker may be inserted at intervals of 48 data blocks. Note that 48 data blocks include a first alignment marker.

[0069] In another example, the insertion period of the second alignment marker may be specifically obtained according to a common multiple of the period of the first alignment marker and the number of physical lanes, the number of symbols having a size of 10 bits in a forward error correction (FEC) codeword in the first data stream, and the rate of the first data stream. For details, see the following formula.

[0070] T'=h*T*Z*x / N=h*T*Z / 2 n

[0071] T' is the insertion period of the second alignment marker, T is the period of the first alignment marker, h and Z are coefficients, h is a positive integer, and Z = xy / z, where x is related to the number of physical lanes, and the number of physical lanes is N = x * 2 n x may be expressed as: x = 17; y = 17; y = 17; y = 17; y = 17; y = 17; z ...

[0072] For example, the period T of the first alignment markers is as follows: In the first data stream, one first alignment marker is inserted every 5440*4096 bits of data. If the number of physical lanes is 12, the period T' of the second alignment markers is as follows: One second alignment marker is inserted every 5440*4096*18 / 17*3 bits of data.

[0073] In this embodiment of the present application, the first chip may insert the second alignment marker in two possible implementations.

[0074] In one possible implementation, each second alignment marker includes a plurality of second alignment sub-markers, the number of the plurality of second alignment sub-markers being the number of physical lanes, and the size of each second alignment sub-marker being the ratio of the size of the second alignment marker to the number of the plurality of physical lanes. For example, the size of each second alignment marker is the number of data blocks (12*12). If the number of physical lanes is 12, each second alignment marker can be considered to include 12 alignment sub-markers, and the size of each second alignment sub-marker is the number of data blocks (12).

[0075] Correspondingly, S102 and S103 may be specifically as follows: the first chip converts the first data stream into a plurality of first data sub-streams according to the number of the plurality of physical lanes, and each of the plurality of first data sub-streams corresponds to one physical lane. In this embodiment of the present application, when the number of the plurality of physical lanes is 2, n Since the first alignment markers in the multiple first data substreams are not aligned, for example, the black blocks in FIG. 3 are not aligned. Therefore, to align the multiple first data substreams, in this embodiment of the present application, the first chip periodically inserts second alignment submarkers into each first data substream to obtain multiple second data substreams. The insertion period of the second alignment submarkers is the ratio of the insertion period of the second alignment markers to the number of the multiple physical lanes.

[0076] After the first chip inserts the second alignment sub-markers into each of the first data sub-streams at the same period, the second alignment sub-markers are aligned. Finally, the first chip transmits the second data sub-streams via the plurality of physical lanes.

[0077] FIG. 6 is a schematic diagram of inserting a second alignment submarker into a second data substream. The shaded blocks represent second alignment submarkers. The positions of the second alignment submarkers in the second data substream are the same. Specifically, the second alignment submarkers are aligned within the second data substream. In this way, after receiving the second data substream, the receiving end can restore the first data stream based on the second alignment submarkers in the second data substream.

[0078] In some embodiments of the present application, the insertion position of the second alignment submarker may be determined based on the position of the first alignment submarker in the first data substream that forms the first alignment marker, or may be unrelated to the position of the first alignment submarker. If the insertion position of the second alignment submarker is determined based on the position of the first alignment submarker in the first data substream that forms the first alignment marker, the receiving end may find the first alignment submarker based on the positional relationship between the second alignment submarker and the first alignment submarker, and restore the first data stream based on the position of the first alignment submarker. Specifically, the first chip determines the insertion position of the second alignment submarker based on the position of the first alignment submarker in the first data stream and the preset distance, and then periodically inserts the second alignment submarker into the first data stream based on the insertion position of the second alignment submarker. If the insertion position of the second alignment submarker is not related to the position of the first alignment submarker, the receiving end needs to detect the first alignment submarker and then restore the first data stream based on the detected first alignment submarker. For details, please refer to the description below. This will not be described in detail here.

[0079] In the embodiment shown in Figure 6, the data substream in the first row is assumed to be data substream A. The positional relationship between the first alignment submarker and the second alignment submarker in data substream A is as follows: the next alignment submarker adjacent to the second alignment submarker is the first alignment submarker (the order of transmitting data blocks is assumed to be from right to left), i.e., the preset distance includes one data block. The data substream in the second row is assumed to be data substream B. The first alignment submarker in data substream B Sub Marker and Secondary Alignment Sub The positional relationship with the marker is as follows: the wth data block after the second alignment sub-marker is the first alignment sub-marker, i.e., the preset distance includes w data blocks. The value of w can be determined based on specific circumstances, and details will not be described here.

[0080] In another possible implementation, S102 and S103 may be specifically as follows: after the first chip periodically inserts second alignment markers into the first data stream to obtain the second data stream, the first chip converts the second data stream into multiple second data substreams, and then the first chip transmits the second data substreams to the second chip via multiple physical lanes.

[0081] The insertion position of the second alignment marker may or may not be related to the insertion position of the first alignment marker. If the insertion position of the second alignment marker is related to the insertion position of the first alignment marker, the second chip may determine the position of the first alignment marker based on the insertion position of the second alignment marker. For example, see FIG. 7. The second alignment marker is followed by the first alignment marker (the flow direction of the data stream is from left to right). In this case, the insertion period of the second alignment marker is equal to or greater than a common multiple of the insertion period of the first alignment marker and the number of physical lanes. When the rate of the second data stream is equal to the rate of the first data stream, the insertion period of the second alignment marker is equal to the common multiple of the insertion period of the first alignment marker and the number of physical lanes, and when the rate of the second data stream is greater than the rate of the first data stream, the insertion period of the second alignment marker is greater than the common multiple of the insertion period of the first alignment marker and the number of physical lanes.

[0082] It is understood that the above two embodiments do not constitute limitations on the technical solutions of the present application, and those skilled in the art may design embodiments based on specific situations.

[0083] In this embodiment of the present application, the second data stream may or may not include a first alignment marker. When the rate of the second data stream is equal to the rate of the first data stream, the second data stream does not include the first alignment marker. The first chip may delete the first alignment marker from the first data stream and insert the second alignment marker to obtain the second data stream. That is, the first alignment marker is "replaced" with the second alignment marker. The product of the size and period of the second alignment marker is equal to the product of the size and period of the first alignment marker. With respect to the receiving end, if the second data stream does not include the first alignment marker, the receiving end needs to restore the first alignment marker to obtain the first data stream.

[0084] Specifically, the first chip can delete the first alignment marker in two ways. In one possible implementation, S102 can be as follows: the first chip deletes the first alignment marker from the first data stream to obtain a third data stream, and then the first chip periodically inserts a second alignment marker into the third data stream to obtain a second data stream. In another possible implementation, S103 can be as follows: the first chip deletes the first alignment marker from the second data stream to obtain a fourth data stream, and then the first chip transmits the fourth data stream via multiple physical lanes. In other words, in the former implementation, the first alignment marker is deleted and then the second alignment marker is inserted, while in the latter implementation, the second alignment marker is inserted and then the first alignment marker is deleted.

[0085] In addition, the number of physical lanes is 2. n Therefore, the traffic of the first data stream (including the first alignment marker) per unit time acquired by the first chip is 2n When the number of physical lanes is an integer multiple of , the data streams can be evenly allocated to all physical lanes. For example, the traffic of the first data stream is 4*106.25 Gbps. When the number of physical lanes is 4, the traffic corresponding to each physical lane is 106.25 Gbps. However, in the embodiment of the present application, when the number of physical lanes is 2, n Therefore, the ratio of the traffic of the first data stream per unit time to the number of physical lanes may or may not be an integer. For example, if the traffic of the first data stream is 450 Gbps and the number of physical lanes is 6, 450 Gbps can be divided exactly by 6. Therefore, the first data stream can be evenly allocated to the six physical lanes. If the traffic of the first data stream is 4*106.25 ... 12 , then 4*106.25Gbps cannot be divided exactly by 12. Therefore, the first data stream cannot be allocated evenly to the 12 physical lanes.

[0086] If the ratio of the traffic of the first data stream per unit time to the number of physical lanes is not an integer, the data stream needs to be "expanded" so that the traffic of the data stream per unit time can be exactly divided by the number of physical lanes.

[0087] In this embodiment of the present application, the rate of the second data stream can be determined first, which must satisfy the following two conditions: the rate of the second data stream is equal to or greater than the rate of the first data stream, and the traffic per unit time corresponding to the rate of the second data stream is an integer multiple of the number of physical lanes.

[0088] For example, if the rate of the first data stream is 4*106.25 Gbps and the number of physical lanes is 6, the rate of the second data stream may be 450 Gbps.

[0089] Optionally, in this embodiment of the present application, the rate of the second data stream may be equal to the product of the rate of the first data stream and a factor Z, where Z=xy / z, where x is related to the number of physical lanes, and the number of physical lanes is N=x*2 n x may be expressed as: x = j * l where l is a coefficient and l is a positive integer. For example, if the number of physical lanes is 12, x may be 3. y is a coefficient and the value of y is a positive integer. z is related to the interface type, and z = j * l, where l is a coefficient and the value of l is a positive integer. j is a common divisor between the number of symbols having a size of 10 bits in an FEC codeword in the first data stream and the rate of the first data stream.

[0090] In this embodiment of the present application, in a possible implementation, the size and period of the second alignment marker may be determined based on the ratio of the rate of the second data stream to the rate of the first data stream, so that the total rate of the data substreams delivered to each physical lane is the rate of the second data stream.

[0091] For example, assume that the rate of the second data stream is 450 Gbps and the rate of the first data stream is 4*106.25 Gbps, in which case the ratio of the rate of the first data stream to the rate of the second data stream is 17 / 18.

[0092] In another possible implementation, in addition to inserting the second alignment marker into the first data stream, padding data may be further inserted into the first data stream. The padding data may be data, such as random data or pseudo-random data, that can be distinguished from the service data in the first data stream. The size of the padding data is determined based on the ratio of the rate of the second data stream to the rate of the first data stream and the size and period of the second alignment marker.

[0093] For example, if there are 12 physical lanes, there are 8,570,880 data blocks between two second alignment markers, the corresponding first data stream has 80,947,200 data blocks, and the size of the second alignment markers is 96 data blocks, the size of the padding data between the two second alignment markers may be 476,064 data blocks.

[0094] In this embodiment of the present application, the padding data may be inserted into the first data stream periodically or randomly every unit time, which is not particularly limited in the present application.

[0095] In addition, padding data may be inserted into the first data stream first, and then the first data stream may be converted into multiple data substreams, or the first data stream may be converted into multiple first data substreams first, and then padding data may be inserted into the first data substream. Figure 8 is a schematic diagram of inserting padding data and second alignment markers into the first data substream according to an embodiment of the present application. Blocks filled with black dots represent padding data.

[0096] When the rate of the second data stream is not equal to the rate of the first data stream, the insertion period of the second alignment marker is determined based on the product of a first value and a second value, where the first value is a common multiple of the insertion period of the first alignment marker and the number of the plurality of physical lanes, and the second value is a ratio of the rate of the second data stream to the rate of the first data stream.

[0097] Additionally, it should be noted that the second alignment marker and padding data may be inserted before or after the second data stream is delivered to the physical lanes.

[0098] It should be further noted that the total rate of the data substreams delivered to each physical lane must be within the rate range supported by each data substream of each physical lane. For example, assuming that the rate ranges supported by the data substreams of a physical lane are 45 Gbps to 55 Gbps and 70 Gbps to 80 Gbps, the total rate of the data substreams delivered to each physical lane must be within one of the two ranges mentioned above, but cannot be within 55 Gbps to 70 Gbps. Therefore, the rate of the second data stream of multiple physical lanes must be within the range of the product of the rate range supported by the data substream of each physical lane and the number of physical lanes.

[0099] S104: The second chip receives a plurality of second data substreams from the first chip, where each of the plurality of second data substreams includes a second alignment sub-marker.

[0100] As the receiving end of the second data substream, the second chip may be, for example, chip 102 in the embodiment shown in FIG.

[0101] S105: The second chip aligns the multiple second data substreams based on the second alignment sub-markers in the multiple second data substreams.

[0102] Because the second alignment sub-marker was aligned when the second data sub-stream was transmitted, after receiving the second data sub-stream, the second chip can align the second data sub-stream based on the second alignment sub-marker so that the reception time at which the second chip received the second data sub-stream is the same.

[0103] S106: The second chip converts the plurality of second data sub-streams into the first data stream.

[0104] In this embodiment of the present application, the second chip may remove the second alignment sub-markers from the multiple second data sub-streams and then recover the first data stream. Alternatively, the second chip may combine the multiple second data sub-streams into one data stream to obtain the first data stream, and then remove the second alignment markers from the data stream.

[0105] Specifically, in a possible embodiment, S106 is specifically as follows: first, the second chip removes second alignment sub-markers from the multiple second data sub-streams to obtain first data sub-streams, and then the second chip combines the first data sub-streams into the first data stream.

[0106] In another possible embodiment, S106 is specifically as follows: first, the second chip combines a plurality of second data sub-streams into a second data stream, and Second The second chip combines the second alignment sub-markers in the data sub-streams into a second alignment marker, and then removes the second alignment marker from the second data stream to obtain the first data stream.

[0107] If the second data substream further includes padding data, the second chip needs to delete the padding data. Specifically, if the position of the padding data is not associated with the position of the second alignment marker, the second chip may find the padding data based on the characteristics of the padding data and delete the padding data. If the position of the padding data is associated with the position of the second alignment marker, for example, if the position of the padding data in the second data substream and the position of the second alignment marker in the data substream satisfy a first preset positional relationship, the second chip may first find the second alignment marker, then find the position of the padding data based on the first preset positional relationship and the position of the second alignment marker, and delete the padding data based on the position of the padding data.

[0108] The time when the second chip deletes the padding data is the same as the time when the second chip deletes the second alignment sub-marker or the second alignment marker.

[0109] In a possible implementation, when the second data substreams further include padding data, the second chip converting the multiple second data substreams into the first data stream further includes the second chip removing the padding data from the multiple second data substreams to obtain the first data substreams, and the second chip combining the first data substreams into the first data stream.

[0110] If the positions of the second alignment sub-markers are associated with the positions of the padding data, the second chip deletes the padding data from the plurality of second data sub-streams based on the positions of the second alignment sub-markers and the first preset positional relationship, where the first preset positional relationship is the positional relationship between the second alignment sub-markers and the padding data.

[0111] In another possible implementation, when the second data substreams further include padding data, the second chip converting the multiple second data substreams into the first data stream further includes the second chip combining the multiple second data substreams into the second data stream, and the second chip removing the padding data from the second data stream to obtain the first data stream.

[0112] When the position of the second alignment marker is associated with the position of the padding data, the second chip deletes the padding data from the plurality of second data streams based on the position of the second alignment marker and the second preset positional relationship, where the second preset positional relationship is the positional relationship between the second alignment marker and the padding data.

[0113] As described above, if the second data substream includes a first alignment marker, when the first chip inserts the second alignment marker, the second alignment marker needs to be distinguished from the first alignment marker. Specifically, the second alignment marker is different from the first alignment marker so that the second chip can identify the second alignment marker and further delete the second alignment marker. If the position of the second alignment marker is related to the position of the first alignment marker, the second chip can identify the position of the first alignment marker based on the position of the second alignment marker.

[0114] If the second data substream does not include the first alignment marker, the second chip may insert the first alignment marker into the second data substream to restore the first data stream. In this case, the second alignment marker may be the same as the first alignment marker.

[0115] When the second chip first deletes the second alignment sub-markers and then obtains the converted first data stream, the second chip may alternatively first insert the first alignment markers and then obtain the merged second data stream. Specifically, to obtain the first data sub-streams, the second chip deletes the second alignment sub-markers from the second data sub-streams and inserts the first alignment sub-markers into the second data sub-streams based on the positions of the second alignment sub-markers and a third preset positional relationship. The third preset positional relationship is the relationship between the insertion positions of the first alignment sub-markers and the positions of the second alignment sub-markers.

[0116] When the second chip first acquires the merged second data stream and then deletes the second alignment marker, the second chip may alternatively first acquire the merged second data stream and then insert the first alignment marker. Specifically, to acquire the first data stream, the second chip deletes the second alignment marker from the second data stream and inserts the first alignment marker into the second data stream based on the position of the second alignment marker and a fourth preset positional relationship. The fourth preset positional relationship is the relationship between the insertion position of the first alignment marker and the position of the second alignment marker.

[0117] In practical applications, the second chip may first insert the first alignment marker and then delete the second alignment marker, or may first delete the second alignment marker and then insert the first alignment marker.

[0118] When the second chip first deletes the second alignment marker and then inserts the first alignment marker, the second chip needs to insert a marker at the position of the second alignment marker after deleting the second alignment marker, and the marker is used to indicate that the position is the position of the second alignment marker. When the first alignment marker is inserted, the first alignment marker is inserted into the marker and Fourth The insertion can be based on a preset positional relationship.

[0119] In conclusion, in this embodiment of the present application, the first chip inserts second alignment markers into the first data stream to obtain a second data stream, and the number of the second alignment markers is 2. n The second data stream is transmitted over a plurality of physical lanes that are not equal to 1. The insertion period and the size of the second alignment marker are each an integer multiple of the number of physical lanes, so that the second alignment markers in the second data substreams corresponding to the physical lanes are Sub The markers are aligned. In this way, the second chip can align the received second data substream based on the second alignment marker and restore the first data stream based on the aligned second data substream. Therefore, the number of physical lanes can be increased by two while ensuring that the insertion period and size of the first alignment markers are not changed. n This allows for improved flexibility in transmitting data streams.

[0120] Correspondingly, please refer to Figure 9. An embodiment of the present application further provides a data stream processing device 900. The device 900 is applied to a first chip, and the first chip may perform the function of the first chip in the embodiment shown in Figure 5.

[0121] The data stream processing device 900 includes an acquiring unit 901, an inserting unit 902, and a sending unit 903. The acquiring unit 901 is configured to acquire a first data stream, where the first data stream includes a first alignment marker.

[0122] The insertion unit 902 is configured to periodically insert second alignment markers into the first data stream to obtain a second data stream.

[0123] The transmitting unit 903 transmits the second data stream through a plurality of physical lanes, and the number of the plurality of physical lanes is two. n where n is a positive integer, the insertion period of the second alignment markers and the size of each of the second alignment markers are determined based on a first condition or a second condition, the first condition being the number of the plurality of physical lanes, the second condition being the ratio of the number of the plurality of physical lanes and the rate of the second data stream to the rate of the first data stream, the insertion period of the second alignment markers and the size of each of the second alignment markers being an integer multiple of the number of the plurality of physical lanes, the rate of the second data stream being equal to or greater than the rate of the first data stream, and the traffic per unit time corresponding to the rate of the second data stream being an integer multiple of the number of physical lanes.

[0124] For the relevant description of the data stream processing device 900, please refer to the description of the first chip in the embodiment shown in Figure 5. The details will not be described again here.

[0125] Please refer to Fig. 10. One embodiment of the present application provides a data stream processing device 1000. The device 1000 is applied to a second chip, and the second chip may perform the functions of the second chip in the embodiment shown in Fig. 5.

[0126] The data stream processing device 1000 includes a receiving unit 1001, an alignment unit 1002, and a conversion unit 1003. The receiving unit 1001 is configured to receive a plurality of second data sub-streams, each of the plurality of second data sub-streams including a second alignment sub-marker.

[0127] The alignment unit 1002 is configured to align the plurality of second data sub-streams based on second alignment sub-markers in the plurality of second data sub-streams.

[0128] The conversion unit 1003 is configured to convert the plurality of second data sub-streams into a first data stream, where the first data stream does not include the second alignment sub-marker.

[0129] For a related description of the data stream processing device 1000, see the embodiment shown in FIG. Second Please refer to the chip description, the details will not be repeated here.

[0130] Correspondingly, an embodiment of the present application further provides a data stream processing device corresponding to the data stream processing apparatus 900 and a data stream processing device corresponding to the data stream processing apparatus 1000. Each of the aforementioned devices includes a processor and a memory. The memory is configured to store instructions. The processor is configured to execute the instructions in the memory to perform the data stream processing method provided in the aforementioned method embodiment, which is performed by the first chip and the second chip.

[0131] It should be noted that the hardware structures of a data stream processing device corresponding to the data stream processing device 900 and a data stream processing device corresponding to the data stream processing device 1000 may be the configurations shown in Fig. 11. Fig. 11 shows a configuration of a data stream processing device according to an embodiment of the present application. Data Stream Processing FIG. 1 is a schematic diagram of the structure of the device.

[0132] See Figure 11. The device 1100 includes a processor 1110, a communication interface 1120, and a memory 1130. The device 1100 may include one or more processors 1110. In Figure 11, one processor is used as an example. In this embodiment of the present application, the processor 1110, the communication interface 1120, and the memory 1130 may be connected via a bus system or in another manner. In Figure 11, for example, a bus system 1140 is used for connection.

[0133] The processor 1110 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 1110 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0134] The memory 1130 may include a volatile memory, such as a random-access memory (RAM). Alternatively, the memory 1130 may include a non-volatile memory, such as a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD). Alternatively, the memory 1130 may include a combination of the aforementioned types of memory.

[0135] Optionally, the memory 1130 stores an operating system and programs, executable modules, or data structures, or a subset or extended set thereof. The programs may include various operating instructions used to perform various operations. The operating system may include various system programs for performing various basic services and handling hardware-based tasks. The processor 1110 may include a processor, such as a microprocessor, a microcontroller, a microcomputer, a microcomputer system, or a microcomputer system. Data Stream Processing A program in memory 1130 may be read to implement the method.

[0136] The bus system 1140 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 1140 may be categorized into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used to represent a bus in Figure 11, but this does not mean that there is only one bus or only one type of bus.

[0137] An embodiment of the present application provides a computer-readable storage medium containing a computer program, which, when run on a computer, enables the computer to perform the data stream processing method described above.

[0138] An embodiment of the present application provides a network device, including the aforementioned data stream processing device applied in a first chip and the aforementioned data stream processing device applied in a second chip.

[0139] In the specification, claims, and accompanying drawings of this application, the terms "first," "second," "third," and "fourth," etc. (where available) are intended to distinguish between similar objects, but not necessarily in any particular order or sequence. References in this manner are interchangeable where appropriate, and thus it should be understood that the embodiments of the invention described herein may be performed in sequences other than those illustrated or described herein. Furthermore, the terms "comprise," "contain," and any other variants are intended to include non-exclusive inclusions; for example, a process, method, system, product, or device that includes a list of steps or units is not necessarily limited to those explicitly listed steps or units, but may include other steps or units not explicitly listed or inherent to such process, method, system, product, or device.

[0140] For the sake of convenience, it can be clearly understood by those skilled in the art that the detailed operation processes of the aforementioned systems, devices and units are to be referred to the corresponding processes in the aforementioned method embodiments, and the details will not be described again here.

[0141] In some embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the described device embodiments are merely examples. For example, the division into units is merely a logical modular division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some functions may be ignored or not performed. In addition, the shown or described mutual couplings or direct couplings or communication connections may be implemented via some interfaces. Indirect couplings or communication connections between devices or units may be implemented in electrical, mechanical, or other forms.

[0142] Units described as separate parts may or may not be physically separated, and parts presented as units may or may not be physical units, i.e., located in one location or distributed across multiple network units. Some or all of the units may be obtained according to the actual requirements for implementing the objectives of the solutions in the embodiments.

[0143] In addition, the module units in the embodiments of the present application may be integrated into one processing unit. Alternatively, each unit may exist physically alone, or at least two units may be integrated into one unit. The integrated unit may be implemented in the form of hardware or in the form of a software module unit.

[0144] When the integrated unit is implemented in the form of a software module unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or a portion contributing to the prior art, or all or a portion of the technical solution, may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or a portion of the steps of the method described in the embodiments of the present application. The storage medium includes any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0145] In one or more of the foregoing examples, those skilled in the art will understand that the functions described herein may be implemented by hardware, software, firmware, or any combination thereof. When the functions are implemented by software, the functions may be stored on a computer-readable medium or transmitted as one or more instructions or code within the computer-readable medium. Computer-readable media include computer storage media and communication media. Communication media include any medium that facilitates the transmission of a computer program from one place to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer.

[0146] In the above specific embodiments, the objectives, technical solutions and beneficial effects of the present invention are further explained in detail. It should be understood that the above descriptions are only specific embodiments of the present invention.

[0147] Finally, the above embodiments are only intended to illustrate the technical solutions of the present application, and are not intended to limit the present application. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that, without departing from the scope of the technical solutions of the embodiments of the present application, they may further modify the technical solutions described in the above embodiments, or make equivalent substitutions for some technical features thereof. [Explanation of symbols]

[0148] 100 network devices 101 chips 102 chips 900 Data Stream Processing Device 901 Acquired Units 902 Insertion Unit 903 Transmitting Unit 1000 Data Stream Processing Device 1001 receiving unit 1002 Alignment Unit 1003 Conversion Unit 1100 devices 1110 processor 1120 Communication Interface 1130 memory 1140 Bus System

Claims

1. 1. A method for processing a data stream, comprising: acquiring, by a first chip, a first data stream, the first data stream including a first alignment marker; periodically inserting, by the first chip, second alignment markers into the first data stream to obtain a second data stream; transmitting, by the first chip, the second data stream over a plurality of physical lanes, wherein an insertion period of the second alignment markers and a size of each of the second alignment markers are determined based on the number of the plurality of physical lanes and based on a ratio of a rate of the second data stream to a rate of the first data stream, the insertion period of the second alignment markers and the size of each of the second alignment markers are each an integer multiple of the number of the plurality of physical lanes, the rate of the second data stream is equal to or greater than the rate of the first data stream, and traffic per unit time corresponding to the rate of the second data stream is an integer multiple of the number of physical lanes; A data stream processing method comprising:

2. the second alignment marker includes a plurality of second alignment sub-markers, the number of the plurality of second alignment sub-markers is the number of the plurality of physical lanes, the size of each of the second alignment sub-markers is represented by the number of data blocks when the first data stream is treated as a plurality of consecutive data blocks, the number of the data blocks is m, m is a ratio of the size of the second alignment marker to the number of the plurality of physical lanes, and m is a positive integer; the step of periodically inserting, by the first chip, second alignment markers into the first data stream to obtain a second data stream includes: converting, by the first chip, the first data stream into a plurality of first data substreams based on the number of the plurality of physical lanes, each of the plurality of first data substreams corresponding to one physical lane; periodically inserting, by the first chip, second alignment sub-markers into each of the first data sub-streams to obtain a plurality of second data sub-streams; and wherein the step of transmitting, by the first chip, the second data stream over a plurality of physical lanes comprises: transmitting, by the first chip, the plurality of second data substreams over the plurality of physical lanes; 2. The method of claim 1, comprising:

3. determining, by the first chip, an insertion position of the second alignment marker based on a position of the first alignment marker in the first data stream and a preset distance; the step of periodically inserting second alignment markers into the first data stream by the first chip comprises: periodically inserting, by the first chip, the second alignment marker into the first data stream based on the insertion position of the second alignment marker, wherein the insertion period of the second alignment marker is equal to or greater than a common multiple of the insertion period of the first alignment marker and the number of the plurality of physical lanes.

2. The method of claim 1, comprising:

4. 4. The method of claim 1, further comprising inserting, by the first chip, padding data into the first data stream when the rate of the second data stream is greater than the rate of the first data stream.

5. 5. The method of claim 4, wherein the step of inserting padding data into the first data stream by the first chip comprises inserting the padding data into the first data stream periodically by the first chip.

6. The method of claim 5 , wherein the padding data is a random sequence.

7. the step of periodically inserting, by the first chip, a second alignment marker into the first data stream to obtain a second data stream when the rate of the second data stream is equal to the rate of the first data stream, comprises: removing, by the first chip, the first alignment marker from the first data stream to obtain a third data stream; periodically inserting, by the first chip, the second alignment marker into the third data stream to obtain the second data stream, wherein the product of the size of the second alignment marker and the period of the second alignment marker is equal to the product of the size of the first alignment marker and the period of the first alignment marker; 4. The method of claim 1, comprising:

8. transmitting, by the first chip, the second data stream over a plurality of physical lanes when the rate of the second data stream is equal to the rate of the first data stream; removing, by the first chip, the first alignment marker from the second data stream to obtain a fourth data stream; transmitting, by the first chip, the fourth data stream in place of the second data stream over the plurality of physical lanes, wherein the product of the size of the second alignment marker and the period of the second alignment marker is equal to the product of the size of the first alignment marker and the period of the first alignment marker; 4. The method of claim 1, comprising:

9. 1. A method for processing a data stream, comprising: receiving, by a second chip, a plurality of second data substreams, each of the plurality of second data substreams including a second alignment sub-marker; aligning, by the second chip, the plurality of second data substreams based on the second alignment sub-markers in the plurality of second data substreams; converting, by the second chip, the plurality of second data sub-streams into a first data stream, the first data stream not including the second alignment sub-marker; Including, The step of converting the plurality of second data substreams into a first data stream by the second chip includes: a step of deleting, by the second chip, the second alignment sub-markers from the plurality of second data sub-streams to obtain a plurality of first data sub-streams; and a step of inserting, by the second chip, a first alignment sub-marker into the second data sub-streams based on a position of the second alignment sub-marker and a third preset positional relationship, wherein the third preset positional relationship is a relationship between an insertion position of the first alignment sub-marker and a position of the second alignment sub-marker.

10. The step of converting the plurality of second data substreams into a first data stream by the second chip includes: combining, by the second chip, the plurality of first data substreams into the first data stream.

10. The method of claim 9, further comprising:

11. the second data sub-stream further includes padding data; The step of converting the plurality of second data substreams into a first data stream by the second chip includes: removing, by the second chip, padding data from the plurality of second data substreams to obtain first data substreams; combining, by the second chip, the first data substreams into the first data stream; 10. The method of claim 9, further comprising:

12. 12. The method of claim 11, wherein the step of removing padding data from the plurality of second data substreams by the second chip includes a step of removing, by the second chip, the padding data from the plurality of second data substreams based on positions of the second alignment submarkers and a first preset positional relationship, wherein the first preset positional relationship is a positional relationship between the second alignment submarkers and the padding data.

13. A data stream processing method comprising: receiving, by a second chip, a plurality of second data substreams, each of the plurality of second data substreams including a second alignment sub-marker; aligning, by the second chip, the plurality of second data substreams based on the second alignment sub-markers in the plurality of second data substreams; converting, by the second chip, the plurality of second data sub-streams into a first data stream, the first data stream not including the second alignment sub-marker; Including, The step of converting the plurality of second data substreams into a first data stream by the second chip includes: combining, by the second chip, the plurality of second data substreams into a second data stream and combining the second alignment submarkers in the plurality of second data substreams into a second alignment marker; removing, by the second chip, the second alignment marker from the second data stream to obtain the first data stream; A method for processing a data stream, comprising:

14. the second data sub-stream further includes padding data; The step of converting the plurality of second data substreams into a first data stream by the second chip includes: removing, by the second chip, padding data from the second data stream to obtain the first data stream.

14. The method of claim 13, further comprising:

15. 15. The method of claim 14, wherein the step of removing padding data from the second data streams by the second chip includes a step of removing padding data from the plurality of second data streams by the second chip based on positions of second alignment markers and a second preset positional relationship, wherein the second preset positional relationship is a positional relationship between the second alignment markers and the padding data.

16. 14. The method of claim 13, wherein the step of deleting, by the second chip, the second alignment marker from the second data stream to obtain the first data stream comprises: deleting, by the second chip, the second alignment marker from the second data stream to obtain the first data stream; and inserting a first alignment marker into the second data stream based on a position of the second alignment marker and a fourth preset positional relationship, wherein the fourth preset positional relationship is a relationship between an insertion position of the first alignment marker and a position of the second alignment marker.

17. A data stream processing device applied to a first chip, comprising: an acquisition unit configured to acquire a first data stream, the first data stream including a first alignment marker; an insertion unit configured to periodically insert second alignment markers into the first data stream to obtain a second data stream; a transmitting unit configured to transmit the second data stream via a plurality of physical lanes, wherein an insertion period of the second alignment markers and a size of each of the second alignment markers are determined based on the number of the plurality of physical lanes and based on a ratio of a rate of the second data stream to a rate of the first data stream, the insertion period of the second alignment markers and the size of each of the second alignment markers are each an integer multiple of the number of the plurality of physical lanes, the rate of the second data stream is equal to or greater than the rate of the first data stream, and traffic per unit time corresponding to the rate of the second data stream is an integer multiple of the number of the physical lanes; A data stream processing device comprising:

18. the second alignment marker includes a plurality of second alignment sub-markers, the number of the plurality of second alignment sub-markers is the number of the plurality of physical lanes, the size of each of the second alignment sub-markers is represented by the number of data blocks when the first data stream is treated as a plurality of consecutive data blocks, the number of the data blocks is m, m is a ratio of the size of the second alignment marker to the number of the plurality of physical lanes, and m is a positive integer; the insertion unit is configured to convert the first data stream into a plurality of first data substreams based on the number of the plurality of physical lanes, each of the plurality of first data substreams corresponding to one physical lane, and to periodically insert second alignment sub-markers into each of the first data substreams to obtain a plurality of second data substreams; 20. The apparatus of claim 17, wherein the transmitting unit is configured to transmit the second plurality of data substreams over the physical lanes.

19. a determining unit configured to determine an insertion position of the second alignment marker based on a position of the first alignment marker in the first data stream and a predetermined distance; Furthermore, 18. The apparatus of claim 17, wherein the insertion unit is configured to periodically insert the second alignment marker into the first data stream based on the insertion position of the second alignment marker, and wherein the insertion period of the second alignment marker is greater than or equal to a common multiple of the insertion period of the first alignment marker and the number of the plurality of physical lanes.

20. 20. The apparatus of claim 17, wherein the insertion unit is further configured to insert padding data into the first data stream when the rate of the second data stream is greater than the rate of the first data stream.

21. the insertion unit is configured to periodically insert the padding data into the first data stream.

21. The apparatus of claim 20.

22. The apparatus of claim 21 , wherein the padding data is a random sequence.

23. when the rate of the second data stream is equal to the rate of the first data stream, the insertion unit is configured to delete the first alignment marker from the first data stream to obtain a third data stream, and periodically insert the second alignment marker into the third data stream to obtain the second data stream, and a product of the size of the second alignment marker and a period of the second alignment marker is equal to a product of the size of the first alignment marker and a period of the first alignment marker.

20. Apparatus according to any one of claims 17 to 19.

24. when the rate of the second data stream is equal to the rate of the first data stream, the transmitting unit is configured to remove the first alignment marker from the second data stream to obtain a fourth data stream, and transmit the fourth data stream instead of the second data stream via the plurality of physical lanes, and a product of the size of the second alignment marker and a period of the second alignment marker is equal to a product of the size of the first alignment marker and a period of the first alignment marker.

20. Apparatus according to any one of claims 17 to 19.

25. A data stream processing device applied to a second chip, comprising: a receiving unit configured to receive a plurality of second data substreams, each of the plurality of second data substreams including a second alignment sub-marker; an alignment unit configured to align the plurality of second data substreams based on the second alignment sub-markers in the plurality of second data substreams; a conversion unit configured to convert the plurality of second data sub-streams into a first data stream, the first data stream not including the second alignment sub-markers; Equipped with the conversion unit is further configured to: remove the second alignment sub-markers from the plurality of second data sub-streams to obtain a plurality of first data sub-streams; and insert first alignment sub-markers into the second data sub-streams based on positions of the second alignment sub-markers and a third preset positional relationship to obtain a plurality of first data sub-streams, wherein the third preset positional relationship is a relationship between an insertion position of the first alignment sub-marker and a position of the second alignment sub-marker. Data stream processing device.

26. the conversion unit is further configured to combine the plurality of first data substreams into the first data stream.

26. The apparatus of claim 25.

27. the second data sub-stream further includes padding data; 26. The apparatus of claim 25, wherein the conversion unit is further configured to remove padding data from the plurality of second data substreams to obtain first data substreams and combine the first data substreams into the first data stream.

28. the conversion unit is configured to remove the padding data from the plurality of second data sub-streams based on positions of the second alignment sub-markers and a first preset positional relationship, the first preset positional relationship being a positional relationship between the second alignment sub-markers and the padding data.

28. The apparatus of claim 27.

29. A data stream processing device applied to a second chip, comprising: a receiving unit configured to receive a plurality of second data substreams, each of the plurality of second data substreams including a second alignment sub-marker; an alignment unit configured to align the plurality of second data substreams based on the second alignment sub-markers in the plurality of second data substreams; a conversion unit configured to convert the plurality of second data sub-streams into a first data stream, the first data stream not including the second alignment sub-markers; Equipped with the conversion unit is further configured to combine the plurality of second data sub-streams into a second data stream, combine the second alignment sub-markers in the plurality of second data sub-streams into a second alignment marker, and remove the second alignment marker from the second data stream to obtain the first data stream. Data stream processing device.

30. the second data sub-stream further includes padding data; 30. The apparatus of claim 29, wherein the conversion unit is further configured to remove padding data from the second data stream to obtain the first data stream.

31. Removing padding data from the second data stream includes:

31. The apparatus of claim 30, further comprising removing the padding data from a plurality of second data streams based on a position of a second alignment marker and a second preset positional relationship, the second preset positional relationship being a positional relationship between the second alignment marker and the padding data.

32. Removing the second alignment marker from the second data stream to obtain the first data stream includes:

30. The apparatus of claim 29, further comprising: deleting the second alignment marker from the second data stream to obtain the first data stream; and inserting a first alignment marker into the second data stream based on a position of the second alignment marker and a fourth preset positional relationship, wherein the fourth preset positional relationship is a relationship between an insertion position of the first alignment marker and a position of the second alignment marker.

33. 14. A computer-readable storage medium storing a computer program, the computer program being capable of causing the computer to carry out the method of claim 1, 9 or 13 when executed on the computer.

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